machfb.c revision 1.45
1 /* $NetBSD: machfb.c,v 1.45 2006/05/10 21:53:16 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, 36 "$NetBSD: machfb.c,v 1.45 2006/05/10 21:53:16 mrg Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/callout.h> 44 45 #ifdef __sparc__ 46 #include <machine/promlib.h> 47 #endif 48 49 #ifdef __powerpc__ 50 #include <dev/ofw/openfirm.h> 51 #include <dev/ofw/ofw_pci.h> 52 #endif 53 54 #include <dev/videomode/videomode.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcidevs.h> 59 #include <dev/pci/pciio.h> 60 #include <dev/pci/machfbreg.h> 61 62 #ifdef __sparc__ 63 #include <dev/sun/fbio.h> 64 #include <dev/sun/fbvar.h> 65 #include <sys/conf.h> 66 #else 67 #include <dev/wscons/wsdisplayvar.h> 68 #endif 69 70 #include <dev/wscons/wsconsio.h> 71 #include <dev/wsfont/wsfont.h> 72 #include <dev/rasops/rasops.h> 73 74 #include <dev/wscons/wsdisplay_vconsvar.h> 75 76 #define MACH64_REG_SIZE 1024 77 #define MACH64_REG_OFF 0x7ffc00 78 79 #define NBARS 3 /* number of Mach64 PCI BARs */ 80 81 struct vga_bar { 82 bus_addr_t vb_base; 83 pcireg_t vb_busaddr; 84 bus_size_t vb_size; 85 pcireg_t vb_type; 86 int vb_flags; 87 }; 88 89 struct mach64_softc { 90 struct device sc_dev; 91 #ifdef __sparc__ 92 struct fbdevice sc_fb; 93 #endif 94 pci_chipset_tag_t sc_pc; 95 pcitag_t sc_pcitag; 96 97 struct vga_bar sc_bars[NBARS]; 98 struct vga_bar sc_rom; 99 100 #define sc_aperbase sc_bars[0].vb_base 101 #define sc_apersize sc_bars[0].vb_size 102 #define sc_aperphys sc_bars[0].vb_busaddr 103 104 #define sc_iobase sc_bars[1].vb_base 105 #define sc_iosize sc_bars[1].vb_size 106 107 #define sc_regbase sc_bars[2].vb_base 108 #define sc_regsize sc_bars[2].vb_size 109 #define sc_regphys sc_bars[2].vb_busaddr 110 111 bus_space_tag_t sc_regt; 112 bus_space_tag_t sc_memt; 113 bus_space_handle_t sc_regh; 114 bus_space_handle_t sc_memh; 115 caddr_t sc_aperture; /* mapped aperture vaddr */ 116 caddr_t sc_registers; /* mapped registers vaddr */ 117 118 uint32_t sc_nbus, sc_ndev, sc_nfunc; 119 size_t memsize; 120 int memtype; 121 122 int sc_mode; 123 int sc_bg; 124 int sc_locked; 125 126 int has_dsp; 127 int bits_per_pixel; 128 int max_x; 129 int max_y; 130 int virt_x; 131 int virt_y; 132 int color_depth; 133 134 int mem_freq; 135 int ramdac_freq; 136 int ref_freq; 137 138 int ref_div; 139 int log2_vclk_post_div; 140 int vclk_post_div; 141 int vclk_fb_div; 142 int mclk_post_div; 143 int mclk_fb_div; 144 145 struct videomode *sc_my_mode; 146 u_char sc_cmap_red[256]; 147 u_char sc_cmap_green[256]; 148 u_char sc_cmap_blue[256]; 149 int sc_dacw, sc_blanked, sc_console; 150 struct vcons_data vd; 151 }; 152 153 struct mach64_crtcregs { 154 uint32_t h_total_disp; 155 uint32_t h_sync_strt_wid; 156 uint32_t v_total_disp; 157 uint32_t v_sync_strt_wid; 158 uint32_t gen_cntl; 159 uint32_t clock_cntl; 160 uint32_t color_depth; 161 uint32_t dot_clock; 162 }; 163 164 struct { 165 uint16_t chip_id; 166 uint32_t ramdac_freq; 167 } static const mach64_info[] = { 168 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 169 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 170 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 171 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 172 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 173 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 174 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 175 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 176 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 177 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 178 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 185 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 186 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 188 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 189 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 190 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 191 }; 192 193 static int mach64_chip_id, mach64_chip_rev; 194 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; 195 196 static const char *mach64_memtype_names[] = { 197 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 198 "(unknown type)" 199 }; 200 201 static struct videomode mach64_modes[] = { 202 /* 640x400 @ 70 Hz, 31.5 kHz */ 203 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0 }, 204 /* 640x480 @ 72 Hz, 36.5 kHz */ 205 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0 }, 206 /* 800x600 @ 72 Hz, 48.0 kHz */ 207 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 208 VID_PHSYNC | VID_PVSYNC }, 209 /* 1024x768 @ 70 Hz, 56.5 kHz */ 210 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 211 VID_NHSYNC | VID_NVSYNC }, 212 /* 1152x864 @ 70 Hz, 62.4 kHz */ 213 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0 }, 214 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 215 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 216 VID_NHSYNC | VID_NVSYNC } 217 }; 218 219 extern const u_char rasops_cmap[768]; 220 221 static int mach64_match(struct device *, struct cfdata *, void *); 222 static void mach64_attach(struct device *, struct device *, void *); 223 224 CFATTACH_DECL(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 225 NULL, NULL); 226 227 static void mach64_init(struct mach64_softc *); 228 static int mach64_get_memsize(struct mach64_softc *); 229 static int mach64_get_max_ramdac(struct mach64_softc *); 230 231 #if defined(__sparc__) || defined(__powerpc__) 232 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 233 #endif 234 235 static int mach64_calc_crtcregs(struct mach64_softc *, 236 struct mach64_crtcregs *, 237 struct videomode *); 238 static void mach64_set_crtcregs(struct mach64_softc *, 239 struct mach64_crtcregs *); 240 241 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 242 static void mach64_set_dsp(struct mach64_softc *); 243 static void mach64_set_pll(struct mach64_softc *, int); 244 static void mach64_reset_engine(struct mach64_softc *); 245 static void mach64_init_engine(struct mach64_softc *); 246 #if 0 247 static void mach64_adjust_frame(struct mach64_softc *, int, int); 248 #endif 249 static void mach64_init_lut(struct mach64_softc *); 250 251 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 252 static int mach64_set_screentype(struct mach64_softc *, 253 const struct wsscreen_descr *); 254 static int mach64_is_console(struct pci_attach_args *); 255 256 static void mach64_cursor(void *, int, int, int); 257 #if 0 258 static int mach64_mapchar(void *, int, u_int *); 259 #endif 260 static void mach64_putchar(void *, int, int, u_int, long); 261 static void mach64_copycols(void *, int, int, int, int); 262 static void mach64_erasecols(void *, int, int, int, long); 263 static void mach64_copyrows(void *, int, int, int); 264 static void mach64_eraserows(void *, int, int, long); 265 static int mach64_allocattr(void *, int, int, int, long *); 266 static void mach64_clearscreen(struct mach64_softc *); 267 268 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 269 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 270 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 271 uint8_t, uint8_t); 272 static void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, 273 int, int, int) ; 274 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 275 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 276 uint32_t, uint32_t); 277 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 278 #if 0 279 static void mach64_showpal(struct mach64_softc *); 280 #endif 281 282 static void set_address(struct rasops_info *, caddr_t); 283 static void machfb_blank(struct mach64_softc *, int); 284 285 #if 0 286 static const struct wsdisplay_emulops mach64_emulops = { 287 mach64_cursor, 288 mach64_mapchar, 289 mach64_putchar, 290 mach64_copycols, 291 mach64_erasecols, 292 mach64_copyrows, 293 mach64_eraserows, 294 mach64_allocattr, 295 }; 296 #endif 297 298 static struct wsscreen_descr mach64_defaultscreen = { 299 "default", 300 80, 30, 301 NULL, 302 8, 16, 303 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 304 &default_mode 305 }, mach64_80x25_screen = { 306 "80x25", 80, 25, 307 NULL, 308 8, 16, 309 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 310 &mach64_modes[0] 311 }, mach64_80x30_screen = { 312 "80x30", 80, 30, 313 NULL, 314 8, 16, 315 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 316 &mach64_modes[1] 317 }, mach64_80x40_screen = { 318 "80x40", 80, 40, 319 NULL, 320 8, 10, 321 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 322 &mach64_modes[0] 323 }, mach64_80x50_screen = { 324 "80x50", 80, 50, 325 NULL, 326 8, 8, 327 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 328 &mach64_modes[0] 329 }, mach64_100x37_screen = { 330 "100x37", 100, 37, 331 NULL, 332 8, 16, 333 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 334 &mach64_modes[2] 335 }, mach64_128x48_screen = { 336 "128x48", 128, 48, 337 NULL, 338 8, 16, 339 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 340 &mach64_modes[3] 341 }, mach64_144x54_screen = { 342 "144x54", 144, 54, 343 NULL, 344 8, 16, 345 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 346 &mach64_modes[4] 347 }, mach64_160x64_screen = { 348 "160x54", 160, 64, 349 NULL, 350 8, 16, 351 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 352 &mach64_modes[5] 353 }; 354 355 static const struct wsscreen_descr *_mach64_scrlist[] = { 356 &mach64_defaultscreen, 357 &mach64_80x25_screen, 358 &mach64_80x30_screen, 359 &mach64_80x40_screen, 360 &mach64_80x50_screen, 361 &mach64_100x37_screen, 362 &mach64_128x48_screen, 363 &mach64_144x54_screen, 364 &mach64_160x64_screen 365 }; 366 367 static struct wsscreen_list mach64_screenlist = { 368 sizeof(_mach64_scrlist) / sizeof(struct wsscreen_descr *), 369 _mach64_scrlist 370 }; 371 372 static int mach64_ioctl(void *, void *, u_long, caddr_t, int, 373 struct lwp *); 374 static paddr_t mach64_mmap(void *, void *, off_t, int); 375 376 #if 0 377 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 378 #endif 379 380 static struct wsdisplay_accessops mach64_accessops = { 381 mach64_ioctl, 382 mach64_mmap, 383 NULL, /* vcons_alloc_screen */ 384 NULL, /* vcons_free_screen */ 385 NULL, /* vcons_show_screen */ 386 NULL, /* load_font */ 387 NULL, /* polls */ 388 NULL, /* scroll */ 389 }; 390 391 static struct vcons_screen mach64_console_screen; 392 393 /* framebuffer device, SPARC-only so far */ 394 #ifdef __sparc__ 395 396 static void machfb_unblank(struct device *); 397 static void machfb_fbattach(struct mach64_softc *); 398 399 extern struct cfdriver machfb_cd; 400 401 dev_type_open(machfb_fbopen); 402 dev_type_close(machfb_fbclose); 403 dev_type_ioctl(machfb_fbioctl); 404 dev_type_mmap(machfb_fbmmap); 405 406 /* frame buffer generic driver */ 407 static struct fbdriver machfb_fbdriver = { 408 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 409 machfb_fbmmap, nokqfilter 410 }; 411 412 #endif /* __sparc__ */ 413 414 /* 415 * Inline functions for getting access to register aperture. 416 */ 417 418 static inline uint32_t 419 regr(struct mach64_softc *sc, uint32_t index) 420 { 421 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 422 } 423 424 static inline uint8_t 425 regrb(struct mach64_softc *sc, uint32_t index) 426 { 427 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 428 } 429 430 static inline void 431 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 432 { 433 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 434 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 435 BUS_SPACE_BARRIER_WRITE); 436 } 437 438 static inline void 439 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 440 { 441 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 442 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 443 BUS_SPACE_BARRIER_WRITE); 444 } 445 446 static inline void 447 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 448 { 449 regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); 450 regwb(sc, CLOCK_CNTL + 2, data); 451 regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); 452 } 453 454 static inline void 455 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 456 { 457 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 458 continue; 459 } 460 461 static inline void 462 wait_for_idle(struct mach64_softc *sc) 463 { 464 wait_for_fifo(sc, 16); 465 while ((regr(sc, GUI_STAT) & 1) != 0) 466 continue; 467 } 468 469 static int 470 mach64_match(struct device *parent, struct cfdata *match, void *aux) 471 { 472 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 473 int i; 474 475 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 476 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 477 return 0; 478 479 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 480 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 481 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 482 mach64_chip_rev = PCI_REVISION(pa->pa_class); 483 return 100; 484 } 485 486 return 0; 487 } 488 489 static void 490 mach64_attach(struct device *parent, struct device *self, void *aux) 491 { 492 struct mach64_softc *sc = (void *)self; 493 struct pci_attach_args *pa = aux; 494 struct rasops_info *ri; 495 char devinfo[256]; 496 int bar, reg, id; 497 struct wsemuldisplaydev_attach_args aa; 498 long defattr; 499 int setmode; 500 pcireg_t screg; 501 502 sc->sc_pc = pa->pa_pc; 503 sc->sc_pcitag = pa->pa_tag; 504 sc->sc_dacw = -1; 505 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 506 sc->sc_nbus = pa->pa_bus; 507 sc->sc_ndev = pa->pa_device; 508 sc->sc_nfunc = pa->pa_function; 509 sc->sc_locked = 0; 510 511 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 512 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 513 514 /* enable memory and IO access */ 515 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 516 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 517 pci_conf_write(sc->sc_pc, sc->sc_pcitag,PCI_COMMAND_STATUS_REG,screg); 518 519 for (bar = 0; bar < NBARS; bar++) { 520 reg = PCI_MAPREG_START + (bar * 4); 521 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 522 sc->sc_pcitag, reg); 523 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 524 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 525 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 526 sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc, 527 sc->sc_pcitag, reg)&0xfffffff0; 528 } 529 sc->sc_memt = pa->pa_memt; 530 531 mach64_init(sc); 532 533 printf("%s: %d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 534 sc->sc_dev.dv_xname, (u_int)(sc->sc_apersize / (1024 * 1024)), 535 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 536 (u_int)sc->sc_regphys); 537 538 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 539 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 540 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 541 (mach64_chip_rev & 0x07) == 0)) 542 sc->has_dsp = 0; 543 else 544 sc->has_dsp = 1; 545 546 sc->memsize = mach64_get_memsize(sc); 547 if (sc->memsize == 8192) 548 /* The last page is used as register aperture. */ 549 sc->memsize -= 4; 550 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 551 552 /* XXX is there any way to calculate reference frequency from 553 known values? */ 554 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 555 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 556 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 557 printf("%s: ref_freq=29.498MHz\n", sc->sc_dev.dv_xname); 558 sc->ref_freq = 29498; 559 } else 560 sc->ref_freq = 14318; 561 562 regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); 563 sc->ref_div = regrb(sc, CLOCK_CNTL + 2); 564 regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); 565 sc->mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); 566 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 567 (sc->ref_div * 2); 568 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 569 (sc->mem_freq * sc->ref_div); 570 sc->ramdac_freq = mach64_get_max_ramdac(sc); 571 printf("%s: %ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 572 sc->sc_dev.dv_xname, (u_long)sc->memsize, 573 mach64_memtype_names[sc->memtype], 574 sc->mem_freq / 1000, sc->mem_freq % 1000, 575 sc->ramdac_freq / 1000); 576 577 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 578 if (id != mach64_chip_id) { 579 printf("%s: chip ID mismatch, 0x%x != 0x%x\n", 580 sc->sc_dev.dv_xname, id, mach64_chip_id); 581 return; 582 } 583 584 sc->sc_console = mach64_is_console(pa); 585 #ifdef DIAGNOSTIC 586 printf("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 587 #endif 588 #if defined(__sparc__) || defined(__powerpc__) 589 if (sc->sc_console) { 590 mach64_get_mode(sc, &default_mode); 591 setmode = 0; 592 sc->sc_my_mode = &default_mode; 593 } else { 594 /* fill in default_mode if it's empty */ 595 mach64_get_mode(sc, &default_mode); 596 if (default_mode.dot_clock == 0) { 597 memcpy(&default_mode, &mach64_modes[4], 598 sizeof(default_mode)); 599 } 600 sc->sc_my_mode = &default_mode; 601 setmode = 1; 602 } 603 #else 604 if (default_mode.dot_clock == 0) { 605 memcpy(&default_mode, &mach64_modes[0], 606 sizeof(default_mode)); 607 } 608 sc->sc_my_mode = &mach64_modes[0]; 609 setmode = 1; 610 #endif 611 612 sc->bits_per_pixel = 8; 613 sc->virt_x = sc->sc_my_mode->hdisplay; 614 sc->virt_y = sc->sc_my_mode->vdisplay; 615 sc->max_x = sc->virt_x - 1; 616 sc->max_y = (sc->memsize * 1024) / 617 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 618 619 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 620 621 mach64_init_engine(sc); 622 #if 0 623 mach64_adjust_frame(0, 0); 624 if (sc->bits_per_pixel == 8) 625 mach64_init_lut(sc); 626 #endif 627 628 printf("%s: initial resolution %dx%d at %d bpp\n", sc->sc_dev.dv_xname, 629 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 630 sc->bits_per_pixel); 631 632 #ifdef __sparc__ 633 machfb_fbattach(sc); 634 #endif 635 636 wsfont_init(); 637 638 sc->sc_bg = WS_DEFAULT_BG; 639 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &mach64_accessops); 640 sc->vd.init_screen = mach64_init_screen; 641 642 if (sc->sc_console) { 643 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 644 &defattr); 645 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 646 647 ri = &mach64_console_screen.scr_ri; 648 mach64_defaultscreen.textops = &ri->ri_ops; 649 mach64_defaultscreen.capabilities = ri->ri_caps; 650 mach64_defaultscreen.nrows = ri->ri_rows; 651 mach64_defaultscreen.ncols = ri->ri_cols; 652 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 653 } else { 654 /* 655 * since we're not the console we can postpone the rest 656 * until someone actually allocates a screen for us 657 */ 658 mach64_modeswitch(sc, sc->sc_my_mode); 659 } 660 661 mach64_init_lut(sc); 662 mach64_clearscreen(sc); 663 machfb_blank(sc, 0); /* unblank the screen */ 664 665 aa.console = sc->sc_console; 666 aa.scrdata = &mach64_screenlist; 667 aa.accessops = &mach64_accessops; 668 aa.accesscookie = &sc->vd; 669 670 config_found(self, &aa, wsemuldisplaydevprint); 671 } 672 673 static void 674 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 675 long *defattr) 676 { 677 struct mach64_softc *sc = cookie; 678 struct rasops_info *ri = &scr->scr_ri; 679 680 /* XXX for now */ 681 #define setmode 0 682 683 ri->ri_depth = sc->bits_per_pixel; 684 ri->ri_width = sc->sc_my_mode->hdisplay; 685 ri->ri_height = sc->sc_my_mode->vdisplay; 686 ri->ri_stride = ri->ri_width; 687 ri->ri_flg = RI_CENTER; 688 set_address(ri, sc->sc_aperture); 689 690 if (existing) { 691 ri->ri_flg |= RI_CLEAR; 692 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 693 panic("%s: failed to switch video mode", 694 sc->sc_dev.dv_xname); 695 } 696 } 697 698 rasops_init(ri, sc->sc_my_mode->vdisplay/8, 699 sc->sc_my_mode->hdisplay/8); 700 ri->ri_caps = WSSCREEN_WSCOLORS; 701 702 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 703 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 704 705 /* enable acceleration */ 706 ri->ri_hw = scr; 707 ri->ri_ops.copyrows = mach64_copyrows; 708 ri->ri_ops.copycols = mach64_copycols; 709 ri->ri_ops.eraserows = mach64_eraserows; 710 ri->ri_ops.erasecols = mach64_erasecols; 711 ri->ri_ops.cursor = mach64_cursor; 712 ri->ri_ops.putchar = mach64_putchar; 713 ri->ri_ops.allocattr = mach64_allocattr; 714 } 715 716 static void 717 mach64_init(struct mach64_softc *sc) 718 { 719 uint32_t *p32, saved_value; 720 uint8_t *p; 721 int need_swap; 722 723 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 724 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 725 panic("%s: failed to map aperture", sc->sc_dev.dv_xname); 726 } 727 sc->sc_aperture = (caddr_t)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 728 729 sc->sc_regt = sc->sc_memt; 730 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 731 sc->sc_regsize, &sc->sc_regh); 732 sc->sc_registers = sc->sc_aperture + 0x7ffc00; 733 734 /* 735 * Test wether the aperture is byte swapped or not 736 */ 737 p32 = (uint32_t*)sc->sc_aperture; 738 saved_value = *p32; 739 p = (uint8_t*)(u_long)sc->sc_aperture; 740 *p32 = 0x12345678; 741 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 742 need_swap = 0; 743 else 744 need_swap = 1; 745 if (need_swap) { 746 sc->sc_aperture += 0x800000; 747 sc->sc_aperbase += 0x800000; 748 sc->sc_apersize -= 0x800000; 749 } 750 *p32 = saved_value; 751 752 sc->sc_blanked = 0; 753 } 754 755 static int 756 mach64_get_memsize(struct mach64_softc *sc) 757 { 758 int tmp, memsize; 759 int mem_tab[] = { 760 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 761 }; 762 tmp = regr(sc, MEM_CNTL); 763 #ifdef DIAGNOSTIC 764 printf("%s: memctl %08x\n", sc->sc_dev.dv_xname, tmp); 765 #endif 766 if (sc->has_dsp) { 767 tmp &= 0x0000000f; 768 if (tmp < 8) 769 memsize = (tmp + 1) * 512; 770 else if (tmp < 12) 771 memsize = (tmp - 3) * 1024; 772 else 773 memsize = (tmp - 7) * 2048; 774 } else { 775 memsize = mem_tab[tmp & 0x07]; 776 } 777 778 return memsize; 779 } 780 781 static int 782 mach64_get_max_ramdac(struct mach64_softc *sc) 783 { 784 int i; 785 786 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 787 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 788 (mach64_chip_rev & 0x07)) 789 return 170000; 790 791 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 792 if (mach64_chip_id == mach64_info[i].chip_id) 793 return mach64_info[i].ramdac_freq; 794 795 if (sc->bits_per_pixel == 8) 796 return 135000; 797 else 798 return 80000; 799 } 800 801 #if defined(__sparc__) || defined(__powerpc__) 802 static void 803 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 804 { 805 struct mach64_crtcregs crtc; 806 807 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 808 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 809 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 810 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 811 812 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 813 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 814 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 815 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 816 mode->hsync_start; 817 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 818 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 819 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 820 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 821 822 #ifndef DEBUG_MACHFB 823 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 824 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 825 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 826 #endif 827 } 828 #endif 829 830 static int 831 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 832 struct videomode *mode) 833 { 834 835 if (mode->dot_clock > sc->ramdac_freq) 836 /* Clock too high. */ 837 return 1; 838 839 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 840 ((mode->htotal >> 3) - 1); 841 crtc->h_sync_strt_wid = 842 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 843 ((mode->hsync_start >> 3) - 1); 844 845 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 846 (mode->vtotal - 1); 847 crtc->v_sync_strt_wid = 848 ((mode->vsync_end - mode->vsync_start) << 16) | 849 (mode->vsync_start - 1); 850 851 if (mode->flags & VID_NVSYNC) 852 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 853 854 switch (sc->bits_per_pixel) { 855 case 8: 856 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 857 break; 858 case 16: 859 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 860 break; 861 case 32: 862 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 863 break; 864 } 865 866 crtc->gen_cntl = 0; 867 if (mode->flags & VID_INTERLACE) 868 crtc->gen_cntl |= CRTC_INTERLACE_EN; 869 870 if (mode->flags & VID_CSYNC) 871 crtc->gen_cntl |= CRTC_CSYNC_EN; 872 873 crtc->dot_clock = mode->dot_clock; 874 875 return 0; 876 } 877 878 static void 879 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 880 { 881 882 mach64_set_pll(sc, crtc->dot_clock); 883 884 if (sc->has_dsp) 885 mach64_set_dsp(sc); 886 887 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 888 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 889 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 890 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 891 892 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 893 894 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 895 896 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 897 /* XXX this unconditionally enables composite sync on SPARC */ 898 #ifdef __sparc__ 899 CRTC_CSYNC_EN | 900 #endif 901 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 902 } 903 904 static int 905 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 906 { 907 struct mach64_crtcregs crtc; 908 909 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 910 911 if (mach64_calc_crtcregs(sc, &crtc, mode)) 912 return 1; 913 914 mach64_set_crtcregs(sc, &crtc); 915 return 0; 916 } 917 918 static void 919 mach64_reset_engine(struct mach64_softc *sc) 920 { 921 922 /* Reset engine.*/ 923 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 924 925 /* Enable engine. */ 926 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 927 928 /* Ensure engine is not locked up by clearing any FIFO or 929 host errors. */ 930 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 931 BUS_FIFO_ERR_ACK); 932 } 933 934 static void 935 mach64_init_engine(struct mach64_softc *sc) 936 { 937 uint32_t pitch_value; 938 939 pitch_value = sc->virt_x; 940 941 if (sc->bits_per_pixel == 24) 942 pitch_value *= 3; 943 944 mach64_reset_engine(sc); 945 946 wait_for_fifo(sc, 14); 947 948 regw(sc, CONTEXT_MASK, 0xffffffff); 949 950 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 951 952 regw(sc, DST_Y_X, 0); 953 regw(sc, DST_HEIGHT, 0); 954 regw(sc, DST_BRES_ERR, 0); 955 regw(sc, DST_BRES_INC, 0); 956 regw(sc, DST_BRES_DEC, 0); 957 958 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 959 DST_Y_TOP_TO_BOTTOM); 960 961 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 962 963 regw(sc, SRC_Y_X, 0); 964 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 965 regw(sc, SRC_Y_X_START, 0); 966 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 967 968 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 969 970 wait_for_fifo(sc, 13); 971 regw(sc, HOST_CNTL, 0); 972 973 regw(sc, PAT_REG0, 0); 974 regw(sc, PAT_REG1, 0); 975 regw(sc, PAT_CNTL, 0); 976 977 regw(sc, SC_LEFT, 0); 978 regw(sc, SC_TOP, 0); 979 regw(sc, SC_BOTTOM, sc->sc_my_mode->vdisplay - 1); 980 regw(sc, SC_RIGHT, pitch_value - 1); 981 982 regw(sc, DP_BKGD_CLR, 0); 983 regw(sc, DP_FRGD_CLR, 0xffffffff); 984 regw(sc, DP_WRITE_MASK, 0xffffffff); 985 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 986 987 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 988 989 wait_for_fifo(sc, 3); 990 regw(sc, CLR_CMP_CLR, 0); 991 regw(sc, CLR_CMP_MASK, 0xffffffff); 992 regw(sc, CLR_CMP_CNTL, 0); 993 994 wait_for_fifo(sc, 2); 995 switch (sc->bits_per_pixel) { 996 case 8: 997 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 998 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 999 /* We want 8 bit per channel */ 1000 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1001 break; 1002 #if 0 1003 case 32: 1004 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 1005 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1006 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1007 break; 1008 #endif 1009 } 1010 1011 wait_for_fifo(sc, 5); 1012 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1013 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1014 1015 wait_for_idle(sc); 1016 } 1017 1018 #if 0 1019 static void 1020 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1021 { 1022 int offset; 1023 1024 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1025 1026 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1027 offset); 1028 } 1029 #endif 1030 1031 static void 1032 mach64_set_dsp(struct mach64_softc *sc) 1033 { 1034 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1035 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1036 uint32_t xclks_per_qw, y; 1037 uint32_t fifo_off, fifo_on; 1038 1039 printf("%s: initializing the DSP\n", sc->sc_dev.dv_xname); 1040 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1041 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1042 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1043 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1044 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1045 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1046 dsp_loop_latency = 0; 1047 fifo_depth = 24; 1048 } else { 1049 dsp_loop_latency = 2; 1050 fifo_depth = 32; 1051 } 1052 1053 dsp_precision = 0; 1054 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1055 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1056 y = (xclks_per_qw * fifo_depth) >> 11; 1057 while (y) { 1058 y >>= 1; 1059 dsp_precision++; 1060 } 1061 dsp_precision -= 5; 1062 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1063 1064 switch (sc->memtype) { 1065 case DRAM: 1066 case EDO_DRAM: 1067 case PSEUDO_EDO: 1068 if (sc->memsize > 1024) { 1069 page_size = 9; 1070 dsp_loop_latency += 6; 1071 } else { 1072 page_size = 10; 1073 if (sc->memtype == DRAM) 1074 dsp_loop_latency += 8; 1075 else 1076 dsp_loop_latency += 7; 1077 } 1078 break; 1079 case SDRAM: 1080 case SGRAM: 1081 if (sc->memsize > 1024) { 1082 page_size = 8; 1083 dsp_loop_latency += 8; 1084 } else { 1085 page_size = 10; 1086 dsp_loop_latency += 9; 1087 } 1088 break; 1089 default: 1090 page_size = 10; 1091 dsp_loop_latency += 9; 1092 break; 1093 } 1094 1095 if (xclks_per_qw >= (page_size << 11)) 1096 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1097 else 1098 fifo_on = (3 * page_size + 2) << 6; 1099 1100 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1101 dsp_on = fifo_on >> dsp_precision; 1102 dsp_off = fifo_off >> dsp_precision; 1103 1104 #ifdef DEBUG_MACHFB 1105 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1106 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1107 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1108 "mclk_post_div = %d, vclk_post_div = %d\n", 1109 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1110 sc->mclk_fb_div, sc->vclk_fb_div, 1111 sc->mclk_post_div, sc->vclk_post_div); 1112 #endif 1113 1114 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1115 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1116 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1117 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1118 } 1119 1120 static void 1121 mach64_set_pll(struct mach64_softc *sc, int clock) 1122 { 1123 int q; 1124 1125 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1126 #ifdef DEBUG_MACHFB 1127 printf("q = %d\n", q); 1128 #endif 1129 if (q > 25500) { 1130 printf("Warning: q > 25500\n"); 1131 q = 25500; 1132 sc->vclk_post_div = 1; 1133 sc->log2_vclk_post_div = 0; 1134 } else if (q > 12750) { 1135 sc->vclk_post_div = 1; 1136 sc->log2_vclk_post_div = 0; 1137 } else if (q > 6350) { 1138 sc->vclk_post_div = 2; 1139 sc->log2_vclk_post_div = 1; 1140 } else if (q > 3150) { 1141 sc->vclk_post_div = 4; 1142 sc->log2_vclk_post_div = 2; 1143 } else if (q >= 1600) { 1144 sc->vclk_post_div = 8; 1145 sc->log2_vclk_post_div = 3; 1146 } else { 1147 printf("Warning: q < 1600\n"); 1148 sc->vclk_post_div = 8; 1149 sc->log2_vclk_post_div = 3; 1150 } 1151 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1152 1153 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1154 regwb_pll(sc, VCLK_POST_DIV, sc->log2_vclk_post_div); 1155 regwb_pll(sc, VCLK0_FB_DIV, sc->vclk_fb_div); 1156 } 1157 1158 static void 1159 mach64_init_lut(struct mach64_softc *sc) 1160 { 1161 int i, idx; 1162 1163 idx = 0; 1164 for (i = 0; i < 256; i++) { 1165 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1], 1166 rasops_cmap[idx + 2]); 1167 idx += 3; 1168 } 1169 } 1170 1171 static int 1172 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1173 uint8_t b) 1174 { 1175 sc->sc_cmap_red[index] = r; 1176 sc->sc_cmap_green[index] = g; 1177 sc->sc_cmap_blue[index] = b; 1178 /* 1179 * writing the dac index takes a while, in theory we can poll some 1180 * register to see when it's ready - but we better avoid writing it 1181 * unnecessarily 1182 */ 1183 if (index != sc->sc_dacw) { 1184 regwb(sc, DAC_MASK, 0xff); 1185 regwb(sc, DAC_WINDEX, index); 1186 } 1187 sc->sc_dacw = index + 1; 1188 regwb(sc, DAC_DATA, r); 1189 regwb(sc, DAC_DATA, g); 1190 regwb(sc, DAC_DATA, b); 1191 return 0; 1192 } 1193 1194 static int 1195 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1196 { 1197 uint index = cm->index; 1198 uint count = cm->count; 1199 int i, error; 1200 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1201 uint8_t *r, *g, *b; 1202 1203 if (cm->index >= 256 || cm->count > 256 || 1204 (cm->index + cm->count) > 256) 1205 return EINVAL; 1206 error = copyin(cm->red, &rbuf[index], count); 1207 if (error) 1208 return error; 1209 error = copyin(cm->green, &gbuf[index], count); 1210 if (error) 1211 return error; 1212 error = copyin(cm->blue, &bbuf[index], count); 1213 if (error) 1214 return error; 1215 1216 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1217 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1218 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1219 1220 r = &sc->sc_cmap_red[index]; 1221 g = &sc->sc_cmap_green[index]; 1222 b = &sc->sc_cmap_blue[index]; 1223 1224 for (i = 0; i < count; i++) { 1225 mach64_putpalreg(sc, index, *r, *g, *b); 1226 index++; 1227 r++, g++, b++; 1228 } 1229 return 0; 1230 } 1231 1232 static int 1233 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1234 { 1235 u_int index = cm->index; 1236 u_int count = cm->count; 1237 int error; 1238 1239 if (index >= 255 || count > 256 || index + count > 256) 1240 return EINVAL; 1241 1242 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1243 if (error) 1244 return error; 1245 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1246 if (error) 1247 return error; 1248 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1249 if (error) 1250 return error; 1251 1252 return 0; 1253 } 1254 1255 static int 1256 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1257 { 1258 struct mach64_crtcregs regs; 1259 1260 if (mach64_calc_crtcregs(sc, ®s, 1261 (struct videomode *)des->modecookie)) 1262 return 1; 1263 1264 mach64_set_crtcregs(sc, ®s); 1265 return 0; 1266 } 1267 1268 static int 1269 mach64_is_console(struct pci_attach_args *pa) 1270 { 1271 #ifdef __sparc__ 1272 int node; 1273 1274 node = PCITAG_NODE(pa->pa_tag); 1275 if (node == -1) 1276 return 0; 1277 1278 return (node == prom_instance_to_package(prom_stdout())); 1279 #elif defined(__powerpc__) 1280 /* check if we're the /chosen console device */ 1281 int chosen, stdout, node, us; 1282 1283 us = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 1284 chosen = OF_finddevice("/chosen"); 1285 OF_getprop(chosen, "stdout", &stdout, 4); 1286 node = OF_instance_to_package(stdout); 1287 return (us == node); 1288 #else 1289 return 1; 1290 #endif 1291 } 1292 1293 /* 1294 * wsdisplay_emulops 1295 */ 1296 1297 static void 1298 mach64_cursor(void *cookie, int on, int row, int col) 1299 { 1300 struct rasops_info *ri = cookie; 1301 struct vcons_screen *scr = ri->ri_hw; 1302 struct mach64_softc *sc = scr->scr_cookie; 1303 int x, y, wi, he; 1304 1305 wi = ri->ri_font->fontwidth; 1306 he = ri->ri_font->fontheight; 1307 1308 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1309 x = ri->ri_ccol * wi + ri->ri_xorigin; 1310 y = ri->ri_crow * he + ri->ri_yorigin; 1311 if (ri->ri_flg & RI_CURSOR) { 1312 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1313 0xff); 1314 ri->ri_flg &= ~RI_CURSOR; 1315 } 1316 ri->ri_crow = row; 1317 ri->ri_ccol = col; 1318 if (on) { 1319 x = ri->ri_ccol * wi + ri->ri_xorigin; 1320 y = ri->ri_crow * he + ri->ri_yorigin; 1321 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1322 0xff); 1323 ri->ri_flg |= RI_CURSOR;; 1324 } 1325 } else { 1326 scr->scr_ri.ri_crow = row; 1327 scr->scr_ri.ri_ccol = col; 1328 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1329 } 1330 } 1331 1332 #if 0 1333 static int 1334 mach64_mapchar(void *cookie, int uni, u_int *index) 1335 { 1336 return 0; 1337 } 1338 #endif 1339 1340 static void 1341 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1342 { 1343 struct rasops_info *ri = cookie; 1344 struct vcons_screen *scr = ri->ri_hw; 1345 struct mach64_softc *sc = scr->scr_cookie; 1346 1347 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1348 int fg, bg, uc; 1349 uint8_t *data; 1350 int x, y, wi, he; 1351 wi = ri->ri_font->fontwidth; 1352 he = ri->ri_font->fontheight; 1353 1354 if (!CHAR_IN_FONT(c, ri->ri_font)) 1355 return; 1356 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0xf]; 1357 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0xf]; 1358 x = ri->ri_xorigin + col * wi; 1359 y = ri->ri_yorigin + row * he; 1360 if (c == 0x20) { 1361 mach64_rectfill(sc, x, y, wi, he, bg); 1362 } else { 1363 uc = c-ri->ri_font->firstchar; 1364 data = (uint8_t *)ri->ri_font->data + uc * 1365 ri->ri_fontscale; 1366 1367 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1368 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1369 } 1370 } 1371 } 1372 1373 1374 static void 1375 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1376 { 1377 struct rasops_info *ri = cookie; 1378 struct vcons_screen *scr = ri->ri_hw; 1379 struct mach64_softc *sc = scr->scr_cookie; 1380 int32_t xs, xd, y, width, height; 1381 1382 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1383 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1384 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1385 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1386 width = ri->ri_font->fontwidth * ncols; 1387 height = ri->ri_font->fontheight; 1388 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff); 1389 } 1390 } 1391 1392 static void 1393 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1394 { 1395 struct rasops_info *ri = cookie; 1396 struct vcons_screen *scr = ri->ri_hw; 1397 struct mach64_softc *sc = scr->scr_cookie; 1398 int32_t x, y, width, height, fg, bg, ul; 1399 1400 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1401 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1402 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1403 width = ri->ri_font->fontwidth * ncols; 1404 height = ri->ri_font->fontheight; 1405 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1406 1407 mach64_rectfill(sc, x, y, width, height, bg); 1408 } 1409 } 1410 1411 static void 1412 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1413 { 1414 struct rasops_info *ri = cookie; 1415 struct vcons_screen *scr = ri->ri_hw; 1416 struct mach64_softc *sc = scr->scr_cookie; 1417 int32_t x, ys, yd, width, height; 1418 1419 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1420 x = ri->ri_xorigin; 1421 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1422 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1423 width = ri->ri_emuwidth; 1424 height = ri->ri_font->fontheight*nrows; 1425 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff); 1426 } 1427 } 1428 1429 static void 1430 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1431 { 1432 struct rasops_info *ri = cookie; 1433 struct vcons_screen *scr = ri->ri_hw; 1434 struct mach64_softc *sc = scr->scr_cookie; 1435 int32_t x, y, width, height, fg, bg, ul; 1436 1437 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1438 x = ri->ri_xorigin; 1439 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1440 width = ri->ri_emuwidth; 1441 height = ri->ri_font->fontheight * nrows; 1442 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1443 1444 mach64_rectfill(sc, x, y, width, height, bg); 1445 } 1446 } 1447 1448 static void 1449 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1450 { 1451 uint32_t dest_ctl = 0; 1452 1453 wait_for_idle(sc); 1454 regw(sc, DP_WRITE_MASK, mask); /* XXX only good for 8 bit */ 1455 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1456 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1457 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1458 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1459 if (yd < ys) { 1460 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1461 } else { 1462 ys += height - 1; 1463 yd += height - 1; 1464 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1465 } 1466 if (xd < xs) { 1467 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1468 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1469 } else { 1470 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1471 xs += width - 1; 1472 xd += width - 1; 1473 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1474 } 1475 regw(sc, DST_CNTL, dest_ctl); 1476 1477 regw(sc, SRC_Y_X, (xs << 16) | ys); 1478 regw(sc, SRC_WIDTH1, width); 1479 regw(sc, DST_Y_X, (xd << 16) | yd); 1480 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1481 } 1482 1483 static void 1484 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1485 int height, uint32_t fg, uint32_t bg) 1486 { 1487 wait_for_idle(sc); 1488 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1489 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1490 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1491 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1492 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1493 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1494 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1495 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1496 regw(sc, DP_BKGD_CLR, bg); 1497 regw(sc, DP_FRGD_CLR, fg); 1498 regw(sc, SRC_Y_X, 0); 1499 regw(sc, SRC_WIDTH1, width); 1500 regw(sc, DST_Y_X, (xd << 16) | yd); 1501 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1502 /* now feed the data into the chip */ 1503 } 1504 1505 static void 1506 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1507 { 1508 int i; 1509 uint32_t latch = 0, bork; 1510 int shift = 0; 1511 int reg = 0; 1512 1513 for (i=0;i<count;i++) { 1514 bork = data[i]; 1515 latch |= (bork << shift); 1516 if (shift == 24) { 1517 regw(sc, HOST_DATA0 + reg, latch); 1518 latch = 0; 1519 shift = 0; 1520 reg = (reg + 4) & 0x3c; 1521 } else 1522 shift += 8; 1523 } 1524 if (shift != 0) /* 24 */ 1525 regw(sc, HOST_DATA0 + reg, latch); 1526 } 1527 1528 1529 static void 1530 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1531 int colour) 1532 { 1533 wait_for_idle(sc); 1534 regw(sc, DP_WRITE_MASK, 0xff); 1535 regw(sc, DP_FRGD_CLR, colour); 1536 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1537 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1538 regw(sc, DP_MIX, MIX_SRC << 16); 1539 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1540 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1541 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1542 1543 regw(sc, SRC_Y_X, (x << 16) | y); 1544 regw(sc, SRC_WIDTH1, width); 1545 regw(sc, DST_Y_X, (x << 16) | y); 1546 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1547 } 1548 1549 static void 1550 mach64_clearscreen(struct mach64_softc *sc) 1551 { 1552 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1553 } 1554 1555 1556 #if 0 1557 static void 1558 mach64_showpal(struct mach64_softc *sc) 1559 { 1560 int i, x = 0; 1561 1562 for (i = 0; i < 16; i++) { 1563 mach64_rectfill(sc, x, 0, 64, 64, i); 1564 x += 64; 1565 } 1566 } 1567 #endif 1568 1569 static int 1570 mach64_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1571 { 1572 if ((fg == 0) && (bg == 0)) 1573 { 1574 fg = WS_DEFAULT_FG; 1575 bg = WS_DEFAULT_BG; 1576 } 1577 *attrp = (fg & 0xf) << 24 | (bg & 0xf) << 16 | (flags & 0xff) << 8; 1578 return 0; 1579 } 1580 1581 /* 1582 * wsdisplay_accessops 1583 */ 1584 1585 static int 1586 mach64_ioctl(void *v, void *vs, u_long cmd, caddr_t data, int flag, 1587 struct lwp *l) 1588 { 1589 struct vcons_data *vd = v; 1590 struct mach64_softc *sc = vd->cookie; 1591 struct wsdisplay_fbinfo *wdf; 1592 struct vcons_screen *ms = vd->active; 1593 1594 switch (cmd) { 1595 case WSDISPLAYIO_GTYPE: 1596 /* XXX is this the right type to return? */ 1597 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1598 return 0; 1599 1600 case WSDISPLAYIO_GINFO: 1601 wdf = (void *)data; 1602 wdf->height = sc->virt_y; 1603 wdf->width = sc->virt_x; 1604 wdf->depth = sc->color_depth; 1605 wdf->cmsize = 256; 1606 return 0; 1607 1608 case WSDISPLAYIO_GETCMAP: 1609 return mach64_getcmap(sc, 1610 (struct wsdisplay_cmap *)data); 1611 1612 case WSDISPLAYIO_PUTCMAP: 1613 return mach64_putcmap(sc, 1614 (struct wsdisplay_cmap *)data); 1615 1616 /* PCI config read/write passthrough. */ 1617 case PCI_IOC_CFGREAD: 1618 case PCI_IOC_CFGWRITE: 1619 return (pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1620 cmd, data, flag, l)); 1621 1622 case WSDISPLAYIO_SMODE: 1623 { 1624 int new_mode = *(int*)data; 1625 1626 if (new_mode != sc->sc_mode) 1627 { 1628 sc->sc_mode = new_mode; 1629 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1630 && (ms != NULL)) 1631 { 1632 vcons_redraw_screen(ms); 1633 } 1634 } 1635 } 1636 return 0; 1637 1638 } 1639 return EPASSTHROUGH; 1640 } 1641 1642 static paddr_t 1643 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1644 { 1645 struct vcons_data *vd = v; 1646 struct mach64_softc *sc = vd->cookie; 1647 paddr_t pa; 1648 pcireg_t reg; 1649 1650 #ifndef __sparc64__ 1651 /* 1652 *'regular' framebuffer mmap()ing 1653 * disabled on sparc64 because some ATI firmware likes to map some PCI 1654 * resources to addresses that would collide with this ( like some Rage 1655 * IIc which uses 0x2000 for the 2nd register block ) 1656 * Other 64bit architectures might run into similar problems. 1657 */ 1658 if (offset<sc->sc_apersize) { 1659 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, offset, 1660 prot, BUS_SPACE_MAP_LINEAR); 1661 return pa; 1662 } 1663 #endif 1664 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1665 if (reg != sc->sc_regphys) { 1666 #ifdef DIAGNOSTIC 1667 printf("%s: BAR 0x18 changed! (%x %x)\n", 1668 sc->sc_dev.dv_xname, (uint32_t)sc->sc_regphys, 1669 (uint32_t)reg); 1670 #endif 1671 sc->sc_regphys = reg; 1672 } 1673 1674 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1675 if (reg != sc->sc_aperphys) { 1676 #ifdef DIAGNOSTIC 1677 printf("%s: BAR 0x10 changed! (%x %x)\n", 1678 sc->sc_dev.dv_xname, (uint32_t)sc->sc_aperphys, 1679 (uint32_t)reg); 1680 #endif 1681 sc->sc_aperphys = reg; 1682 } 1683 1684 #if 0 1685 /* evil hack to allow mmap()ing other devices as well */ 1686 if ((offset > 0x80000000) && (offset <= 0xffffffff)) { 1687 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1688 BUS_SPACE_MAP_LINEAR); 1689 return pa; 1690 } 1691 #endif 1692 1693 if ((offset >= sc->sc_aperphys) && 1694 (offset < (sc->sc_aperphys + sc->sc_apersize))) { 1695 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1696 BUS_SPACE_MAP_LINEAR); 1697 return pa; 1698 } 1699 1700 if ((offset >= sc->sc_regphys) && 1701 (offset < (sc->sc_regphys + sc->sc_regsize))) { 1702 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1703 BUS_SPACE_MAP_LINEAR); 1704 return pa; 1705 } 1706 1707 return -1; 1708 } 1709 1710 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1711 static void 1712 set_address(struct rasops_info *ri, caddr_t fb) 1713 { 1714 #ifdef notdef 1715 printf(" %d %d %d\n", ri->ri_xorigin, ri->ri_yorigin, ri->ri_stride); 1716 #endif 1717 ri->ri_bits = (void *)(fb + ri->ri_stride * ri->ri_yorigin + 1718 ri->ri_xorigin); 1719 } 1720 1721 #if 0 1722 static int 1723 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1724 { 1725 1726 return 0; 1727 } 1728 #endif 1729 1730 void 1731 machfb_blank(struct mach64_softc *sc, int blank) 1732 { 1733 uint32_t reg; 1734 1735 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1736 1737 switch (blank) 1738 { 1739 case 0: 1740 reg = regr(sc, CRTC_GEN_CNTL); 1741 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1742 sc->sc_blanked = 0; 1743 break; 1744 case 1: 1745 reg = regr(sc, CRTC_GEN_CNTL); 1746 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1747 sc->sc_blanked = 1; 1748 break; 1749 default: 1750 break; 1751 } 1752 } 1753 1754 /* framebuffer device support */ 1755 #ifdef __sparc__ 1756 1757 static void 1758 machfb_unblank(struct device *dev) 1759 { 1760 struct mach64_softc *sc = (struct mach64_softc *)dev; 1761 1762 machfb_blank(sc, 0); 1763 } 1764 1765 static void 1766 machfb_fbattach(struct mach64_softc *sc) 1767 { 1768 struct fbdevice *fb = &sc->sc_fb; 1769 1770 fb->fb_device = &sc->sc_dev; 1771 fb->fb_driver = &machfb_fbdriver; 1772 1773 fb->fb_type.fb_cmsize = 256; 1774 fb->fb_type.fb_size = sc->memsize; 1775 1776 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 1777 fb->fb_flags = sc->sc_dev.dv_cfdata->cf_flags & FB_USERMASK; 1778 fb->fb_type.fb_depth = sc->bits_per_pixel; 1779 fb->fb_type.fb_width = sc->virt_x; 1780 fb->fb_type.fb_height = sc->virt_y; 1781 1782 fb->fb_pixels = sc->sc_aperture; 1783 fb_attach(fb, sc->sc_console); 1784 } 1785 1786 int 1787 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 1788 { 1789 struct mach64_softc *sc; 1790 int unit = minor(dev); 1791 1792 sc = machfb_cd.cd_devs[unit]; 1793 sc->sc_locked = 1; 1794 1795 #ifdef DEBUG_MACHFB 1796 printf("machfb_fbopen(%d)\n", unit); 1797 #endif 1798 if (unit > machfb_cd.cd_ndevs || machfb_cd.cd_devs[unit] == NULL) 1799 return ENXIO; 1800 return 0; 1801 } 1802 1803 int 1804 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 1805 { 1806 struct mach64_softc *sc = machfb_cd.cd_devs[minor(dev)]; 1807 1808 #ifdef DEBUG_MACHFB 1809 printf("machfb_fbclose()\n"); 1810 #endif 1811 mach64_init_engine(sc); 1812 mach64_init_lut(sc); 1813 sc->sc_locked = 0; 1814 return 0; 1815 } 1816 1817 int 1818 machfb_fbioctl(dev_t dev, u_long cmd, caddr_t data, int flags, struct lwp *l) 1819 { 1820 struct mach64_softc *sc = machfb_cd.cd_devs[minor(dev)]; 1821 1822 #ifdef DEBUG_MACHFB 1823 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 1824 #endif 1825 switch (cmd) { 1826 case FBIOGTYPE: 1827 *(struct fbtype *)data = sc->sc_fb.fb_type; 1828 break; 1829 1830 case FBIOGATTR: 1831 #define fba ((struct fbgattr *)data) 1832 fba->real_type = sc->sc_fb.fb_type.fb_type; 1833 fba->owner = 0; /* XXX ??? */ 1834 fba->fbtype = sc->sc_fb.fb_type; 1835 fba->sattr.flags = 0; 1836 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 1837 fba->sattr.dev_specific[0] = sc->sc_nbus; 1838 fba->sattr.dev_specific[1] = sc->sc_ndev; 1839 fba->sattr.dev_specific[2] = sc->sc_nfunc; 1840 fba->sattr.dev_specific[3] = -1; 1841 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 1842 fba->emu_types[1] = -1; 1843 #undef fba 1844 break; 1845 1846 #if 0 1847 case FBIOGETCMAP: 1848 #define p ((struct fbcmap *)data) 1849 return (bt_getcmap(p, &sc->sc_cmap, 256, 1)); 1850 1851 case FBIOPUTCMAP: 1852 /* copy to software map */ 1853 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 1854 if (error) 1855 return error; 1856 /* now blast them into the chip */ 1857 /* XXX should use retrace interrupt */ 1858 cg6_loadcmap(sc, p->index, p->count); 1859 #undef p 1860 break; 1861 #endif 1862 case FBIOGVIDEO: 1863 *(int *)data = sc->sc_blanked; 1864 break; 1865 1866 case FBIOSVIDEO: 1867 machfb_blank(sc, *(int *)data); 1868 break; 1869 1870 #if 0 1871 case FBIOGCURSOR: 1872 break; 1873 1874 case FBIOSCURSOR: 1875 break; 1876 1877 case FBIOGCURPOS: 1878 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 1879 break; 1880 1881 case FBIOSCURPOS: 1882 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 1883 break; 1884 1885 case FBIOGCURMAX: 1886 /* max cursor size is 32x32 */ 1887 ((struct fbcurpos *)data)->x = 32; 1888 ((struct fbcurpos *)data)->y = 32; 1889 break; 1890 #endif 1891 case PCI_IOC_CFGREAD: 1892 case PCI_IOC_CFGWRITE: 1893 { 1894 int ret; 1895 1896 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1897 cmd, data, flags, l); 1898 1899 #ifdef DEBUG_MACHFB 1900 printf("pci_devioctl: %d\n", ret); 1901 #endif 1902 return ret; 1903 } 1904 default: 1905 #ifdef DEBUG_MACHFB 1906 log(LOG_NOTICE, "machfb_fbioctl(0x%lx) (%s[%d])\n", cmd, 1907 p->p_comm, p->p_pid); 1908 #endif 1909 return ENOTTY; 1910 } 1911 #ifdef DEBUG_MACHFB 1912 printf("machfb_fbioctl done\n"); 1913 #endif 1914 return 0; 1915 } 1916 1917 paddr_t 1918 machfb_fbmmap(dev_t dev, off_t off, int prot) 1919 { 1920 struct mach64_softc *sc = machfb_cd.cd_devs[minor(dev)]; 1921 1922 if (sc != NULL) 1923 return mach64_mmap(&sc->vd, NULL, off, prot); 1924 1925 return 0; 1926 } 1927 1928 #endif /* __sparc__ */ 1929
Indexes created Thu Oct 02 14:10:14 GMT 2025