machfb.c revision 1.48.2.2
1 /* $NetBSD: machfb.c,v 1.48.2.2 2008/03/24 20:53:54 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, 36 "$NetBSD: machfb.c,v 1.48.2.2 2008/03/24 20:53:54 bouyer Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/callout.h> 44 #include <sys/kauth.h> 45 46 #ifdef __sparc__ 47 #include <machine/promlib.h> 48 #endif 49 50 #ifdef __powerpc__ 51 #include <dev/ofw/openfirm.h> 52 #include <dev/ofw/ofw_pci.h> 53 #endif 54 55 #include <dev/videomode/videomode.h> 56 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcidevs.h> 60 #include <dev/pci/pciio.h> 61 #include <dev/pci/machfbreg.h> 62 63 #ifdef __sparc__ 64 #include <dev/sun/fbio.h> 65 #include <dev/sun/fbvar.h> 66 #include <sys/conf.h> 67 #else 68 #include <dev/wscons/wsdisplayvar.h> 69 #endif 70 71 #include <dev/wscons/wsconsio.h> 72 #include <dev/wsfont/wsfont.h> 73 #include <dev/rasops/rasops.h> 74 75 #include <dev/wscons/wsdisplay_vconsvar.h> 76 77 #define MACH64_REG_SIZE 1024 78 #define MACH64_REG_OFF 0x7ffc00 79 80 #define NBARS 3 /* number of Mach64 PCI BARs */ 81 82 struct vga_bar { 83 bus_addr_t vb_base; 84 pcireg_t vb_busaddr; 85 bus_size_t vb_size; 86 pcireg_t vb_type; 87 int vb_flags; 88 }; 89 90 struct mach64_softc { 91 struct device sc_dev; 92 #ifdef __sparc__ 93 struct fbdevice sc_fb; 94 #endif 95 pci_chipset_tag_t sc_pc; 96 pcitag_t sc_pcitag; 97 98 struct vga_bar sc_bars[NBARS]; 99 struct vga_bar sc_rom; 100 101 #define sc_aperbase sc_bars[0].vb_base 102 #define sc_apersize sc_bars[0].vb_size 103 #define sc_aperphys sc_bars[0].vb_busaddr 104 105 #define sc_iobase sc_bars[1].vb_base 106 #define sc_iosize sc_bars[1].vb_size 107 108 #define sc_regbase sc_bars[2].vb_base 109 #define sc_regsize sc_bars[2].vb_size 110 #define sc_regphys sc_bars[2].vb_busaddr 111 112 bus_space_tag_t sc_regt; 113 bus_space_tag_t sc_memt; 114 bus_space_handle_t sc_regh; 115 bus_space_handle_t sc_memh; 116 caddr_t sc_aperture; /* mapped aperture vaddr */ 117 caddr_t sc_registers; /* mapped registers vaddr */ 118 119 uint32_t sc_nbus, sc_ndev, sc_nfunc; 120 size_t memsize; 121 int memtype; 122 123 int sc_mode; 124 int sc_bg; 125 int sc_locked; 126 127 int has_dsp; 128 int bits_per_pixel; 129 int max_x; 130 int max_y; 131 int virt_x; 132 int virt_y; 133 int color_depth; 134 135 int mem_freq; 136 int ramdac_freq; 137 int ref_freq; 138 139 int ref_div; 140 int log2_vclk_post_div; 141 int vclk_post_div; 142 int vclk_fb_div; 143 int mclk_post_div; 144 int mclk_fb_div; 145 146 struct videomode *sc_my_mode; 147 u_char sc_cmap_red[256]; 148 u_char sc_cmap_green[256]; 149 u_char sc_cmap_blue[256]; 150 int sc_dacw, sc_blanked, sc_console; 151 struct vcons_data vd; 152 }; 153 154 struct mach64_crtcregs { 155 uint32_t h_total_disp; 156 uint32_t h_sync_strt_wid; 157 uint32_t v_total_disp; 158 uint32_t v_sync_strt_wid; 159 uint32_t gen_cntl; 160 uint32_t clock_cntl; 161 uint32_t color_depth; 162 uint32_t dot_clock; 163 }; 164 165 static struct { 166 uint16_t chip_id; 167 uint32_t ramdac_freq; 168 } const mach64_info[] = { 169 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 170 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 171 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 172 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 173 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 174 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 175 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 176 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 178 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 179 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 182 #if 0 183 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 185 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 186 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 189 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 190 #endif 191 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 192 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 193 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 194 }; 195 196 static int mach64_chip_id, mach64_chip_rev; 197 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 198 199 static const char *mach64_memtype_names[] = { 200 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 201 "(unknown type)" 202 }; 203 204 static struct videomode mach64_modes[] = { 205 /* 640x400 @ 70 Hz, 31.5 kHz */ 206 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0, NULL, }, 207 /* 640x480 @ 72 Hz, 36.5 kHz */ 208 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0, NULL, }, 209 /* 800x600 @ 72 Hz, 48.0 kHz */ 210 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 211 VID_PHSYNC | VID_PVSYNC, NULL, }, 212 /* 1024x768 @ 70 Hz, 56.5 kHz */ 213 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 214 VID_NHSYNC | VID_NVSYNC, NULL, }, 215 /* 1152x864 @ 70 Hz, 62.4 kHz */ 216 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0, NULL, }, 217 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 218 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 219 VID_NHSYNC | VID_NVSYNC, NULL, } 220 }; 221 222 extern const u_char rasops_cmap[768]; 223 224 static int mach64_match(struct device *, struct cfdata *, void *); 225 static void mach64_attach(struct device *, struct device *, void *); 226 227 CFATTACH_DECL(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 228 NULL, NULL); 229 230 static void mach64_init(struct mach64_softc *); 231 static int mach64_get_memsize(struct mach64_softc *); 232 static int mach64_get_max_ramdac(struct mach64_softc *); 233 234 #if defined(__sparc__) || defined(__powerpc__) 235 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 236 #endif 237 238 static int mach64_calc_crtcregs(struct mach64_softc *, 239 struct mach64_crtcregs *, 240 struct videomode *); 241 static void mach64_set_crtcregs(struct mach64_softc *, 242 struct mach64_crtcregs *); 243 244 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 245 static void mach64_set_dsp(struct mach64_softc *); 246 static void mach64_set_pll(struct mach64_softc *, int); 247 static void mach64_reset_engine(struct mach64_softc *); 248 static void mach64_init_engine(struct mach64_softc *); 249 #if 0 250 static void mach64_adjust_frame(struct mach64_softc *, int, int); 251 #endif 252 static void mach64_init_lut(struct mach64_softc *); 253 254 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 255 static int mach64_set_screentype(struct mach64_softc *, 256 const struct wsscreen_descr *); 257 static int mach64_is_console(struct pci_attach_args *); 258 259 static void mach64_cursor(void *, int, int, int); 260 #if 0 261 static int mach64_mapchar(void *, int, u_int *); 262 #endif 263 static void mach64_putchar(void *, int, int, u_int, long); 264 static void mach64_copycols(void *, int, int, int, int); 265 static void mach64_erasecols(void *, int, int, int, long); 266 static void mach64_copyrows(void *, int, int, int); 267 static void mach64_eraserows(void *, int, int, long); 268 static int mach64_allocattr(void *, int, int, int, long *); 269 static void mach64_clearscreen(struct mach64_softc *); 270 271 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 272 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 273 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 274 uint8_t, uint8_t); 275 static void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, 276 int, int, int) ; 277 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 278 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 279 uint32_t, uint32_t); 280 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 281 #if 0 282 static void mach64_showpal(struct mach64_softc *); 283 #endif 284 285 static void set_address(struct rasops_info *, caddr_t); 286 static void machfb_blank(struct mach64_softc *, int); 287 288 #if 0 289 static const struct wsdisplay_emulops mach64_emulops = { 290 mach64_cursor, 291 mach64_mapchar, 292 mach64_putchar, 293 mach64_copycols, 294 mach64_erasecols, 295 mach64_copyrows, 296 mach64_eraserows, 297 mach64_allocattr, 298 }; 299 #endif 300 301 static struct wsscreen_descr mach64_defaultscreen = { 302 "default", 303 80, 30, 304 NULL, 305 8, 16, 306 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 307 &default_mode 308 }, mach64_80x25_screen = { 309 "80x25", 80, 25, 310 NULL, 311 8, 16, 312 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 313 &mach64_modes[0] 314 }, mach64_80x30_screen = { 315 "80x30", 80, 30, 316 NULL, 317 8, 16, 318 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 319 &mach64_modes[1] 320 }, mach64_80x40_screen = { 321 "80x40", 80, 40, 322 NULL, 323 8, 10, 324 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 325 &mach64_modes[0] 326 }, mach64_80x50_screen = { 327 "80x50", 80, 50, 328 NULL, 329 8, 8, 330 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 331 &mach64_modes[0] 332 }, mach64_100x37_screen = { 333 "100x37", 100, 37, 334 NULL, 335 8, 16, 336 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 337 &mach64_modes[2] 338 }, mach64_128x48_screen = { 339 "128x48", 128, 48, 340 NULL, 341 8, 16, 342 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 343 &mach64_modes[3] 344 }, mach64_144x54_screen = { 345 "144x54", 144, 54, 346 NULL, 347 8, 16, 348 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 349 &mach64_modes[4] 350 }, mach64_160x64_screen = { 351 "160x54", 160, 64, 352 NULL, 353 8, 16, 354 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 355 &mach64_modes[5] 356 }; 357 358 static const struct wsscreen_descr *_mach64_scrlist[] = { 359 &mach64_defaultscreen, 360 &mach64_80x25_screen, 361 &mach64_80x30_screen, 362 &mach64_80x40_screen, 363 &mach64_80x50_screen, 364 &mach64_100x37_screen, 365 &mach64_128x48_screen, 366 &mach64_144x54_screen, 367 &mach64_160x64_screen 368 }; 369 370 static struct wsscreen_list mach64_screenlist = { 371 sizeof(_mach64_scrlist) / sizeof(struct wsscreen_descr *), 372 _mach64_scrlist 373 }; 374 375 static int mach64_ioctl(void *, void *, u_long, caddr_t, int, 376 struct lwp *); 377 static paddr_t mach64_mmap(void *, void *, off_t, int); 378 379 #if 0 380 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 381 #endif 382 383 static struct wsdisplay_accessops mach64_accessops = { 384 mach64_ioctl, 385 mach64_mmap, 386 NULL, /* vcons_alloc_screen */ 387 NULL, /* vcons_free_screen */ 388 NULL, /* vcons_show_screen */ 389 NULL, /* load_font */ 390 NULL, /* polls */ 391 NULL, /* scroll */ 392 }; 393 394 static struct vcons_screen mach64_console_screen; 395 396 /* framebuffer device, SPARC-only so far */ 397 #ifdef __sparc__ 398 399 static void machfb_unblank(struct device *); 400 static void machfb_fbattach(struct mach64_softc *); 401 402 extern struct cfdriver machfb_cd; 403 404 dev_type_open(machfb_fbopen); 405 dev_type_close(machfb_fbclose); 406 dev_type_ioctl(machfb_fbioctl); 407 dev_type_mmap(machfb_fbmmap); 408 409 /* frame buffer generic driver */ 410 static struct fbdriver machfb_fbdriver = { 411 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 412 machfb_fbmmap, nokqfilter 413 }; 414 415 #endif /* __sparc__ */ 416 417 /* 418 * Inline functions for getting access to register aperture. 419 */ 420 421 static inline uint32_t 422 regr(struct mach64_softc *sc, uint32_t index) 423 { 424 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 425 } 426 427 static inline uint8_t 428 regrb(struct mach64_softc *sc, uint32_t index) 429 { 430 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 431 } 432 433 static inline void 434 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 435 { 436 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 437 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 438 BUS_SPACE_BARRIER_WRITE); 439 } 440 441 static inline void 442 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 443 { 444 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 445 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 446 BUS_SPACE_BARRIER_WRITE); 447 } 448 449 static inline void 450 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 451 { 452 regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); 453 regwb(sc, CLOCK_CNTL + 2, data); 454 regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); 455 } 456 457 static inline void 458 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 459 { 460 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 461 continue; 462 } 463 464 static inline void 465 wait_for_idle(struct mach64_softc *sc) 466 { 467 wait_for_fifo(sc, 16); 468 while ((regr(sc, GUI_STAT) & 1) != 0) 469 continue; 470 } 471 472 static int 473 mach64_match(struct device *parent, struct cfdata *match, 474 void *aux) 475 { 476 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 477 int i; 478 479 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 480 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 481 return 0; 482 483 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 484 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 485 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 486 mach64_chip_rev = PCI_REVISION(pa->pa_class); 487 return 100; 488 } 489 490 return 0; 491 } 492 493 static void 494 mach64_attach(struct device *parent, struct device *self, void *aux) 495 { 496 struct mach64_softc *sc = (void *)self; 497 struct pci_attach_args *pa = aux; 498 struct rasops_info *ri; 499 char devinfo[256]; 500 int bar, reg, id; 501 struct wsemuldisplaydev_attach_args aa; 502 long defattr; 503 int setmode; 504 pcireg_t screg; 505 506 sc->sc_pc = pa->pa_pc; 507 sc->sc_pcitag = pa->pa_tag; 508 sc->sc_dacw = -1; 509 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 510 sc->sc_nbus = pa->pa_bus; 511 sc->sc_ndev = pa->pa_device; 512 sc->sc_nfunc = pa->pa_function; 513 sc->sc_locked = 0; 514 515 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 516 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 517 518 /* enable memory and IO access */ 519 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 520 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 521 pci_conf_write(sc->sc_pc, sc->sc_pcitag,PCI_COMMAND_STATUS_REG,screg); 522 523 for (bar = 0; bar < NBARS; bar++) { 524 reg = PCI_MAPREG_START + (bar * 4); 525 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 526 sc->sc_pcitag, reg); 527 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 528 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 529 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 530 sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc, 531 sc->sc_pcitag, reg)&0xfffffff0; 532 } 533 sc->sc_memt = pa->pa_memt; 534 535 mach64_init(sc); 536 537 printf("%s: %d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 538 sc->sc_dev.dv_xname, (u_int)(sc->sc_apersize / (1024 * 1024)), 539 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 540 (u_int)sc->sc_regphys); 541 542 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 543 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 544 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 545 (mach64_chip_rev & 0x07) == 0)) 546 sc->has_dsp = 0; 547 else 548 sc->has_dsp = 1; 549 550 sc->memsize = mach64_get_memsize(sc); 551 if (sc->memsize == 8192) 552 /* The last page is used as register aperture. */ 553 sc->memsize -= 4; 554 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 555 556 /* XXX is there any way to calculate reference frequency from 557 known values? */ 558 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 559 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 560 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 561 printf("%s: ref_freq=29.498MHz\n", sc->sc_dev.dv_xname); 562 sc->ref_freq = 29498; 563 } else 564 sc->ref_freq = 14318; 565 566 regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); 567 sc->ref_div = regrb(sc, CLOCK_CNTL + 2); 568 regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); 569 sc->mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); 570 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 571 (sc->ref_div * 2); 572 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 573 (sc->mem_freq * sc->ref_div); 574 sc->ramdac_freq = mach64_get_max_ramdac(sc); 575 printf("%s: %ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 576 sc->sc_dev.dv_xname, (u_long)sc->memsize, 577 mach64_memtype_names[sc->memtype], 578 sc->mem_freq / 1000, sc->mem_freq % 1000, 579 sc->ramdac_freq / 1000); 580 581 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 582 if (id != mach64_chip_id) { 583 printf("%s: chip ID mismatch, 0x%x != 0x%x\n", 584 sc->sc_dev.dv_xname, id, mach64_chip_id); 585 return; 586 } 587 588 sc->sc_console = mach64_is_console(pa); 589 #ifdef DIAGNOSTIC 590 printf("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 591 #endif 592 #if defined(__sparc__) || defined(__powerpc__) 593 if (sc->sc_console) { 594 mach64_get_mode(sc, &default_mode); 595 setmode = 0; 596 sc->sc_my_mode = &default_mode; 597 } else { 598 /* fill in default_mode if it's empty */ 599 mach64_get_mode(sc, &default_mode); 600 if (default_mode.dot_clock == 0) { 601 memcpy(&default_mode, &mach64_modes[4], 602 sizeof(default_mode)); 603 } 604 sc->sc_my_mode = &default_mode; 605 setmode = 1; 606 } 607 #else 608 if (default_mode.dot_clock == 0) { 609 memcpy(&default_mode, &mach64_modes[0], 610 sizeof(default_mode)); 611 } 612 sc->sc_my_mode = &mach64_modes[0]; 613 setmode = 1; 614 #endif 615 616 sc->bits_per_pixel = 8; 617 sc->virt_x = sc->sc_my_mode->hdisplay; 618 sc->virt_y = sc->sc_my_mode->vdisplay; 619 sc->max_x = sc->virt_x - 1; 620 sc->max_y = (sc->memsize * 1024) / 621 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 622 623 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 624 625 mach64_init_engine(sc); 626 #if 0 627 mach64_adjust_frame(0, 0); 628 if (sc->bits_per_pixel == 8) 629 mach64_init_lut(sc); 630 #endif 631 632 printf("%s: initial resolution %dx%d at %d bpp\n", sc->sc_dev.dv_xname, 633 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 634 sc->bits_per_pixel); 635 636 #ifdef __sparc__ 637 machfb_fbattach(sc); 638 #endif 639 640 wsfont_init(); 641 642 sc->sc_bg = WS_DEFAULT_BG; 643 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &mach64_accessops); 644 sc->vd.init_screen = mach64_init_screen; 645 646 if (sc->sc_console) { 647 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 648 &defattr); 649 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 650 651 ri = &mach64_console_screen.scr_ri; 652 mach64_defaultscreen.textops = &ri->ri_ops; 653 mach64_defaultscreen.capabilities = ri->ri_caps; 654 mach64_defaultscreen.nrows = ri->ri_rows; 655 mach64_defaultscreen.ncols = ri->ri_cols; 656 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 657 } else { 658 /* 659 * since we're not the console we can postpone the rest 660 * until someone actually allocates a screen for us 661 */ 662 mach64_modeswitch(sc, sc->sc_my_mode); 663 } 664 665 mach64_init_lut(sc); 666 mach64_clearscreen(sc); 667 machfb_blank(sc, 0); /* unblank the screen */ 668 669 aa.console = sc->sc_console; 670 aa.scrdata = &mach64_screenlist; 671 aa.accessops = &mach64_accessops; 672 aa.accesscookie = &sc->vd; 673 674 config_found(self, &aa, wsemuldisplaydevprint); 675 } 676 677 static void 678 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 679 long *defattr) 680 { 681 struct mach64_softc *sc = cookie; 682 struct rasops_info *ri = &scr->scr_ri; 683 684 /* XXX for now */ 685 #define setmode 0 686 687 ri->ri_depth = sc->bits_per_pixel; 688 ri->ri_width = sc->sc_my_mode->hdisplay; 689 ri->ri_height = sc->sc_my_mode->vdisplay; 690 ri->ri_stride = ri->ri_width; 691 ri->ri_flg = RI_CENTER; 692 set_address(ri, sc->sc_aperture); 693 694 if (existing) { 695 ri->ri_flg |= RI_CLEAR; 696 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 697 panic("%s: failed to switch video mode", 698 sc->sc_dev.dv_xname); 699 } 700 } 701 702 rasops_init(ri, sc->sc_my_mode->vdisplay/8, 703 sc->sc_my_mode->hdisplay/8); 704 ri->ri_caps = WSSCREEN_WSCOLORS; 705 706 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 707 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 708 709 /* enable acceleration */ 710 ri->ri_hw = scr; 711 ri->ri_ops.copyrows = mach64_copyrows; 712 ri->ri_ops.copycols = mach64_copycols; 713 ri->ri_ops.eraserows = mach64_eraserows; 714 ri->ri_ops.erasecols = mach64_erasecols; 715 ri->ri_ops.cursor = mach64_cursor; 716 ri->ri_ops.putchar = mach64_putchar; 717 ri->ri_ops.allocattr = mach64_allocattr; 718 } 719 720 static void 721 mach64_init(struct mach64_softc *sc) 722 { 723 uint32_t *p32, saved_value; 724 uint8_t *p; 725 int need_swap; 726 727 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 728 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 729 panic("%s: failed to map aperture", sc->sc_dev.dv_xname); 730 } 731 sc->sc_aperture = (caddr_t)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 732 733 sc->sc_regt = sc->sc_memt; 734 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 735 sc->sc_regsize, &sc->sc_regh); 736 sc->sc_registers = sc->sc_aperture + 0x7ffc00; 737 738 /* 739 * Test wether the aperture is byte swapped or not 740 */ 741 p32 = (uint32_t*)sc->sc_aperture; 742 saved_value = *p32; 743 p = (uint8_t*)(u_long)sc->sc_aperture; 744 *p32 = 0x12345678; 745 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 746 need_swap = 0; 747 else 748 need_swap = 1; 749 if (need_swap) { 750 sc->sc_aperture += 0x800000; 751 sc->sc_aperbase += 0x800000; 752 sc->sc_apersize -= 0x800000; 753 } 754 *p32 = saved_value; 755 756 sc->sc_blanked = 0; 757 } 758 759 static int 760 mach64_get_memsize(struct mach64_softc *sc) 761 { 762 int tmp, memsize; 763 int mem_tab[] = { 764 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 765 }; 766 tmp = regr(sc, MEM_CNTL); 767 #ifdef DIAGNOSTIC 768 printf("%s: memctl %08x\n", sc->sc_dev.dv_xname, tmp); 769 #endif 770 if (sc->has_dsp) { 771 tmp &= 0x0000000f; 772 if (tmp < 8) 773 memsize = (tmp + 1) * 512; 774 else if (tmp < 12) 775 memsize = (tmp - 3) * 1024; 776 else 777 memsize = (tmp - 7) * 2048; 778 } else { 779 memsize = mem_tab[tmp & 0x07]; 780 } 781 782 return memsize; 783 } 784 785 static int 786 mach64_get_max_ramdac(struct mach64_softc *sc) 787 { 788 int i; 789 790 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 791 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 792 (mach64_chip_rev & 0x07)) 793 return 170000; 794 795 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 796 if (mach64_chip_id == mach64_info[i].chip_id) 797 return mach64_info[i].ramdac_freq; 798 799 if (sc->bits_per_pixel == 8) 800 return 135000; 801 else 802 return 80000; 803 } 804 805 #if defined(__sparc__) || defined(__powerpc__) 806 static void 807 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 808 { 809 struct mach64_crtcregs crtc; 810 811 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 812 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 813 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 814 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 815 816 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 817 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 818 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 819 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 820 mode->hsync_start; 821 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 822 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 823 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 824 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 825 826 #ifndef DEBUG_MACHFB 827 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 828 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 829 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 830 #endif 831 } 832 #endif 833 834 static int 835 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 836 struct videomode *mode) 837 { 838 839 if (mode->dot_clock > sc->ramdac_freq) 840 /* Clock too high. */ 841 return 1; 842 843 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 844 ((mode->htotal >> 3) - 1); 845 crtc->h_sync_strt_wid = 846 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 847 ((mode->hsync_start >> 3) - 1); 848 849 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 850 (mode->vtotal - 1); 851 crtc->v_sync_strt_wid = 852 ((mode->vsync_end - mode->vsync_start) << 16) | 853 (mode->vsync_start - 1); 854 855 if (mode->flags & VID_NVSYNC) 856 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 857 858 switch (sc->bits_per_pixel) { 859 case 8: 860 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 861 break; 862 case 16: 863 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 864 break; 865 case 32: 866 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 867 break; 868 } 869 870 crtc->gen_cntl = 0; 871 if (mode->flags & VID_INTERLACE) 872 crtc->gen_cntl |= CRTC_INTERLACE_EN; 873 874 if (mode->flags & VID_CSYNC) 875 crtc->gen_cntl |= CRTC_CSYNC_EN; 876 877 crtc->dot_clock = mode->dot_clock; 878 879 return 0; 880 } 881 882 static void 883 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 884 { 885 886 mach64_set_pll(sc, crtc->dot_clock); 887 888 if (sc->has_dsp) 889 mach64_set_dsp(sc); 890 891 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 892 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 893 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 894 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 895 896 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 897 898 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 899 900 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 901 /* XXX this unconditionally enables composite sync on SPARC */ 902 #ifdef __sparc__ 903 CRTC_CSYNC_EN | 904 #endif 905 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 906 } 907 908 static int 909 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 910 { 911 struct mach64_crtcregs crtc; 912 913 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 914 915 if (mach64_calc_crtcregs(sc, &crtc, mode)) 916 return 1; 917 918 mach64_set_crtcregs(sc, &crtc); 919 return 0; 920 } 921 922 static void 923 mach64_reset_engine(struct mach64_softc *sc) 924 { 925 926 /* Reset engine.*/ 927 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 928 929 /* Enable engine. */ 930 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 931 932 /* Ensure engine is not locked up by clearing any FIFO or 933 host errors. */ 934 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 935 BUS_FIFO_ERR_ACK); 936 } 937 938 static void 939 mach64_init_engine(struct mach64_softc *sc) 940 { 941 uint32_t pitch_value; 942 943 pitch_value = sc->virt_x; 944 945 if (sc->bits_per_pixel == 24) 946 pitch_value *= 3; 947 948 mach64_reset_engine(sc); 949 950 wait_for_fifo(sc, 14); 951 952 regw(sc, CONTEXT_MASK, 0xffffffff); 953 954 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 955 956 regw(sc, DST_Y_X, 0); 957 regw(sc, DST_HEIGHT, 0); 958 regw(sc, DST_BRES_ERR, 0); 959 regw(sc, DST_BRES_INC, 0); 960 regw(sc, DST_BRES_DEC, 0); 961 962 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 963 DST_Y_TOP_TO_BOTTOM); 964 965 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 966 967 regw(sc, SRC_Y_X, 0); 968 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 969 regw(sc, SRC_Y_X_START, 0); 970 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 971 972 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 973 974 wait_for_fifo(sc, 13); 975 regw(sc, HOST_CNTL, 0); 976 977 regw(sc, PAT_REG0, 0); 978 regw(sc, PAT_REG1, 0); 979 regw(sc, PAT_CNTL, 0); 980 981 regw(sc, SC_LEFT, 0); 982 regw(sc, SC_TOP, 0); 983 regw(sc, SC_BOTTOM, sc->sc_my_mode->vdisplay - 1); 984 regw(sc, SC_RIGHT, pitch_value - 1); 985 986 regw(sc, DP_BKGD_CLR, 0); 987 regw(sc, DP_FRGD_CLR, 0xffffffff); 988 regw(sc, DP_WRITE_MASK, 0xffffffff); 989 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 990 991 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 992 993 wait_for_fifo(sc, 3); 994 regw(sc, CLR_CMP_CLR, 0); 995 regw(sc, CLR_CMP_MASK, 0xffffffff); 996 regw(sc, CLR_CMP_CNTL, 0); 997 998 wait_for_fifo(sc, 2); 999 switch (sc->bits_per_pixel) { 1000 case 8: 1001 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 1002 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1003 /* We want 8 bit per channel */ 1004 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1005 break; 1006 #if 0 1007 case 32: 1008 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 1009 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1010 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1011 break; 1012 #endif 1013 } 1014 1015 wait_for_fifo(sc, 5); 1016 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1017 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1018 1019 wait_for_idle(sc); 1020 } 1021 1022 #if 0 1023 static void 1024 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1025 { 1026 int offset; 1027 1028 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1029 1030 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1031 offset); 1032 } 1033 #endif 1034 1035 static void 1036 mach64_set_dsp(struct mach64_softc *sc) 1037 { 1038 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1039 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1040 uint32_t xclks_per_qw, y; 1041 uint32_t fifo_off, fifo_on; 1042 1043 printf("%s: initializing the DSP\n", sc->sc_dev.dv_xname); 1044 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1045 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1046 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1047 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1048 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1049 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1050 dsp_loop_latency = 0; 1051 fifo_depth = 24; 1052 } else { 1053 dsp_loop_latency = 2; 1054 fifo_depth = 32; 1055 } 1056 1057 dsp_precision = 0; 1058 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1059 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1060 y = (xclks_per_qw * fifo_depth) >> 11; 1061 while (y) { 1062 y >>= 1; 1063 dsp_precision++; 1064 } 1065 dsp_precision -= 5; 1066 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1067 1068 switch (sc->memtype) { 1069 case DRAM: 1070 case EDO_DRAM: 1071 case PSEUDO_EDO: 1072 if (sc->memsize > 1024) { 1073 page_size = 9; 1074 dsp_loop_latency += 6; 1075 } else { 1076 page_size = 10; 1077 if (sc->memtype == DRAM) 1078 dsp_loop_latency += 8; 1079 else 1080 dsp_loop_latency += 7; 1081 } 1082 break; 1083 case SDRAM: 1084 case SGRAM: 1085 if (sc->memsize > 1024) { 1086 page_size = 8; 1087 dsp_loop_latency += 8; 1088 } else { 1089 page_size = 10; 1090 dsp_loop_latency += 9; 1091 } 1092 break; 1093 default: 1094 page_size = 10; 1095 dsp_loop_latency += 9; 1096 break; 1097 } 1098 1099 if (xclks_per_qw >= (page_size << 11)) 1100 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1101 else 1102 fifo_on = (3 * page_size + 2) << 6; 1103 1104 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1105 dsp_on = fifo_on >> dsp_precision; 1106 dsp_off = fifo_off >> dsp_precision; 1107 1108 #ifdef DEBUG_MACHFB 1109 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1110 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1111 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1112 "mclk_post_div = %d, vclk_post_div = %d\n", 1113 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1114 sc->mclk_fb_div, sc->vclk_fb_div, 1115 sc->mclk_post_div, sc->vclk_post_div); 1116 #endif 1117 1118 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1119 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1120 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1121 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1122 } 1123 1124 static void 1125 mach64_set_pll(struct mach64_softc *sc, int clock) 1126 { 1127 int q; 1128 1129 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1130 #ifdef DEBUG_MACHFB 1131 printf("q = %d\n", q); 1132 #endif 1133 if (q > 25500) { 1134 printf("Warning: q > 25500\n"); 1135 q = 25500; 1136 sc->vclk_post_div = 1; 1137 sc->log2_vclk_post_div = 0; 1138 } else if (q > 12750) { 1139 sc->vclk_post_div = 1; 1140 sc->log2_vclk_post_div = 0; 1141 } else if (q > 6350) { 1142 sc->vclk_post_div = 2; 1143 sc->log2_vclk_post_div = 1; 1144 } else if (q > 3150) { 1145 sc->vclk_post_div = 4; 1146 sc->log2_vclk_post_div = 2; 1147 } else if (q >= 1600) { 1148 sc->vclk_post_div = 8; 1149 sc->log2_vclk_post_div = 3; 1150 } else { 1151 printf("Warning: q < 1600\n"); 1152 sc->vclk_post_div = 8; 1153 sc->log2_vclk_post_div = 3; 1154 } 1155 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1156 1157 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1158 regwb_pll(sc, VCLK_POST_DIV, sc->log2_vclk_post_div); 1159 regwb_pll(sc, VCLK0_FB_DIV, sc->vclk_fb_div); 1160 } 1161 1162 static void 1163 mach64_init_lut(struct mach64_softc *sc) 1164 { 1165 int i, idx; 1166 1167 idx = 0; 1168 for (i = 0; i < 256; i++) { 1169 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1], 1170 rasops_cmap[idx + 2]); 1171 idx += 3; 1172 } 1173 } 1174 1175 static int 1176 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1177 uint8_t b) 1178 { 1179 sc->sc_cmap_red[index] = r; 1180 sc->sc_cmap_green[index] = g; 1181 sc->sc_cmap_blue[index] = b; 1182 /* 1183 * writing the dac index takes a while, in theory we can poll some 1184 * register to see when it's ready - but we better avoid writing it 1185 * unnecessarily 1186 */ 1187 if (index != sc->sc_dacw) { 1188 regwb(sc, DAC_MASK, 0xff); 1189 regwb(sc, DAC_WINDEX, index); 1190 } 1191 sc->sc_dacw = index + 1; 1192 regwb(sc, DAC_DATA, r); 1193 regwb(sc, DAC_DATA, g); 1194 regwb(sc, DAC_DATA, b); 1195 return 0; 1196 } 1197 1198 static int 1199 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1200 { 1201 uint index = cm->index; 1202 uint count = cm->count; 1203 int i, error; 1204 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1205 uint8_t *r, *g, *b; 1206 1207 if (cm->index >= 256 || cm->count > 256 || 1208 (cm->index + cm->count) > 256) 1209 return EINVAL; 1210 error = copyin(cm->red, &rbuf[index], count); 1211 if (error) 1212 return error; 1213 error = copyin(cm->green, &gbuf[index], count); 1214 if (error) 1215 return error; 1216 error = copyin(cm->blue, &bbuf[index], count); 1217 if (error) 1218 return error; 1219 1220 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1221 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1222 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1223 1224 r = &sc->sc_cmap_red[index]; 1225 g = &sc->sc_cmap_green[index]; 1226 b = &sc->sc_cmap_blue[index]; 1227 1228 for (i = 0; i < count; i++) { 1229 mach64_putpalreg(sc, index, *r, *g, *b); 1230 index++; 1231 r++, g++, b++; 1232 } 1233 return 0; 1234 } 1235 1236 static int 1237 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1238 { 1239 u_int index = cm->index; 1240 u_int count = cm->count; 1241 int error; 1242 1243 if (index >= 255 || count > 256 || index + count > 256) 1244 return EINVAL; 1245 1246 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1247 if (error) 1248 return error; 1249 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1250 if (error) 1251 return error; 1252 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1253 if (error) 1254 return error; 1255 1256 return 0; 1257 } 1258 1259 static int 1260 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1261 { 1262 struct mach64_crtcregs regs; 1263 1264 if (mach64_calc_crtcregs(sc, ®s, 1265 (struct videomode *)des->modecookie)) 1266 return 1; 1267 1268 mach64_set_crtcregs(sc, ®s); 1269 return 0; 1270 } 1271 1272 static int 1273 mach64_is_console(struct pci_attach_args *pa) 1274 { 1275 #ifdef __sparc__ 1276 int node; 1277 1278 node = PCITAG_NODE(pa->pa_tag); 1279 if (node == -1) 1280 return 0; 1281 1282 return (node == prom_instance_to_package(prom_stdout())); 1283 #elif defined(__powerpc__) 1284 /* check if we're the /chosen console device */ 1285 int chosen, stdout, node, us; 1286 1287 us = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 1288 chosen = OF_finddevice("/chosen"); 1289 OF_getprop(chosen, "stdout", &stdout, 4); 1290 node = OF_instance_to_package(stdout); 1291 return (us == node); 1292 #else 1293 return 1; 1294 #endif 1295 } 1296 1297 /* 1298 * wsdisplay_emulops 1299 */ 1300 1301 static void 1302 mach64_cursor(void *cookie, int on, int row, int col) 1303 { 1304 struct rasops_info *ri = cookie; 1305 struct vcons_screen *scr = ri->ri_hw; 1306 struct mach64_softc *sc = scr->scr_cookie; 1307 int x, y, wi, he; 1308 1309 wi = ri->ri_font->fontwidth; 1310 he = ri->ri_font->fontheight; 1311 1312 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1313 x = ri->ri_ccol * wi + ri->ri_xorigin; 1314 y = ri->ri_crow * he + ri->ri_yorigin; 1315 if (ri->ri_flg & RI_CURSOR) { 1316 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1317 0xff); 1318 ri->ri_flg &= ~RI_CURSOR; 1319 } 1320 ri->ri_crow = row; 1321 ri->ri_ccol = col; 1322 if (on) { 1323 x = ri->ri_ccol * wi + ri->ri_xorigin; 1324 y = ri->ri_crow * he + ri->ri_yorigin; 1325 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1326 0xff); 1327 ri->ri_flg |= RI_CURSOR;; 1328 } 1329 } else { 1330 scr->scr_ri.ri_crow = row; 1331 scr->scr_ri.ri_ccol = col; 1332 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1333 } 1334 } 1335 1336 #if 0 1337 static int 1338 mach64_mapchar(void *cookie, int uni, u_int *index) 1339 { 1340 return 0; 1341 } 1342 #endif 1343 1344 static void 1345 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1346 { 1347 struct rasops_info *ri = cookie; 1348 struct vcons_screen *scr = ri->ri_hw; 1349 struct mach64_softc *sc = scr->scr_cookie; 1350 1351 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1352 int fg, bg, uc; 1353 uint8_t *data; 1354 int x, y, wi, he; 1355 wi = ri->ri_font->fontwidth; 1356 he = ri->ri_font->fontheight; 1357 1358 if (!CHAR_IN_FONT(c, ri->ri_font)) 1359 return; 1360 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0xf]; 1361 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0xf]; 1362 x = ri->ri_xorigin + col * wi; 1363 y = ri->ri_yorigin + row * he; 1364 if (c == 0x20) { 1365 mach64_rectfill(sc, x, y, wi, he, bg); 1366 } else { 1367 uc = c-ri->ri_font->firstchar; 1368 data = (uint8_t *)ri->ri_font->data + uc * 1369 ri->ri_fontscale; 1370 1371 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1372 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1373 } 1374 } 1375 } 1376 1377 1378 static void 1379 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1380 { 1381 struct rasops_info *ri = cookie; 1382 struct vcons_screen *scr = ri->ri_hw; 1383 struct mach64_softc *sc = scr->scr_cookie; 1384 int32_t xs, xd, y, width, height; 1385 1386 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1387 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1388 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1389 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1390 width = ri->ri_font->fontwidth * ncols; 1391 height = ri->ri_font->fontheight; 1392 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff); 1393 } 1394 } 1395 1396 static void 1397 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1398 { 1399 struct rasops_info *ri = cookie; 1400 struct vcons_screen *scr = ri->ri_hw; 1401 struct mach64_softc *sc = scr->scr_cookie; 1402 int32_t x, y, width, height, fg, bg, ul; 1403 1404 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1405 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1406 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1407 width = ri->ri_font->fontwidth * ncols; 1408 height = ri->ri_font->fontheight; 1409 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1410 1411 mach64_rectfill(sc, x, y, width, height, bg); 1412 } 1413 } 1414 1415 static void 1416 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1417 { 1418 struct rasops_info *ri = cookie; 1419 struct vcons_screen *scr = ri->ri_hw; 1420 struct mach64_softc *sc = scr->scr_cookie; 1421 int32_t x, ys, yd, width, height; 1422 1423 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1424 x = ri->ri_xorigin; 1425 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1426 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1427 width = ri->ri_emuwidth; 1428 height = ri->ri_font->fontheight*nrows; 1429 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff); 1430 } 1431 } 1432 1433 static void 1434 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1435 { 1436 struct rasops_info *ri = cookie; 1437 struct vcons_screen *scr = ri->ri_hw; 1438 struct mach64_softc *sc = scr->scr_cookie; 1439 int32_t x, y, width, height, fg, bg, ul; 1440 1441 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1442 x = ri->ri_xorigin; 1443 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1444 width = ri->ri_emuwidth; 1445 height = ri->ri_font->fontheight * nrows; 1446 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1447 1448 mach64_rectfill(sc, x, y, width, height, bg); 1449 } 1450 } 1451 1452 static void 1453 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1454 { 1455 uint32_t dest_ctl = 0; 1456 1457 wait_for_idle(sc); 1458 regw(sc, DP_WRITE_MASK, mask); /* XXX only good for 8 bit */ 1459 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1460 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1461 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1462 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1463 if (yd < ys) { 1464 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1465 } else { 1466 ys += height - 1; 1467 yd += height - 1; 1468 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1469 } 1470 if (xd < xs) { 1471 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1472 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1473 } else { 1474 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1475 xs += width - 1; 1476 xd += width - 1; 1477 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1478 } 1479 regw(sc, DST_CNTL, dest_ctl); 1480 1481 regw(sc, SRC_Y_X, (xs << 16) | ys); 1482 regw(sc, SRC_WIDTH1, width); 1483 regw(sc, DST_Y_X, (xd << 16) | yd); 1484 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1485 } 1486 1487 static void 1488 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1489 int height, uint32_t fg, uint32_t bg) 1490 { 1491 wait_for_idle(sc); 1492 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1493 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1494 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1495 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1496 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1497 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1498 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1499 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1500 regw(sc, DP_BKGD_CLR, bg); 1501 regw(sc, DP_FRGD_CLR, fg); 1502 regw(sc, SRC_Y_X, 0); 1503 regw(sc, SRC_WIDTH1, width); 1504 regw(sc, DST_Y_X, (xd << 16) | yd); 1505 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1506 /* now feed the data into the chip */ 1507 } 1508 1509 static void 1510 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1511 { 1512 int i; 1513 uint32_t latch = 0, bork; 1514 int shift = 0; 1515 int reg = 0; 1516 1517 for (i=0;i<count;i++) { 1518 bork = data[i]; 1519 latch |= (bork << shift); 1520 if (shift == 24) { 1521 regw(sc, HOST_DATA0 + reg, latch); 1522 latch = 0; 1523 shift = 0; 1524 reg = (reg + 4) & 0x3c; 1525 } else 1526 shift += 8; 1527 } 1528 if (shift != 0) /* 24 */ 1529 regw(sc, HOST_DATA0 + reg, latch); 1530 } 1531 1532 1533 static void 1534 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1535 int colour) 1536 { 1537 wait_for_idle(sc); 1538 regw(sc, DP_WRITE_MASK, 0xff); 1539 regw(sc, DP_FRGD_CLR, colour); 1540 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1541 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1542 regw(sc, DP_MIX, MIX_SRC << 16); 1543 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1544 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1545 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1546 1547 regw(sc, SRC_Y_X, (x << 16) | y); 1548 regw(sc, SRC_WIDTH1, width); 1549 regw(sc, DST_Y_X, (x << 16) | y); 1550 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1551 } 1552 1553 static void 1554 mach64_clearscreen(struct mach64_softc *sc) 1555 { 1556 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1557 } 1558 1559 1560 #if 0 1561 static void 1562 mach64_showpal(struct mach64_softc *sc) 1563 { 1564 int i, x = 0; 1565 1566 for (i = 0; i < 16; i++) { 1567 mach64_rectfill(sc, x, 0, 64, 64, i); 1568 x += 64; 1569 } 1570 } 1571 #endif 1572 1573 static int 1574 mach64_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1575 { 1576 if ((fg == 0) && (bg == 0)) 1577 { 1578 fg = WS_DEFAULT_FG; 1579 bg = WS_DEFAULT_BG; 1580 } 1581 *attrp = (fg & 0xf) << 24 | (bg & 0xf) << 16 | (flags & 0xff) << 8; 1582 return 0; 1583 } 1584 1585 /* 1586 * wsdisplay_accessops 1587 */ 1588 1589 static int 1590 mach64_ioctl(void *v, void *vs, u_long cmd, caddr_t data, int flag, 1591 struct lwp *l) 1592 { 1593 struct vcons_data *vd = v; 1594 struct mach64_softc *sc = vd->cookie; 1595 struct wsdisplay_fbinfo *wdf; 1596 struct vcons_screen *ms = vd->active; 1597 1598 switch (cmd) { 1599 case WSDISPLAYIO_GTYPE: 1600 /* XXX is this the right type to return? */ 1601 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1602 return 0; 1603 1604 case WSDISPLAYIO_GINFO: 1605 wdf = (void *)data; 1606 wdf->height = sc->virt_y; 1607 wdf->width = sc->virt_x; 1608 wdf->depth = sc->color_depth; 1609 wdf->cmsize = 256; 1610 return 0; 1611 1612 case WSDISPLAYIO_GETCMAP: 1613 return mach64_getcmap(sc, 1614 (struct wsdisplay_cmap *)data); 1615 1616 case WSDISPLAYIO_PUTCMAP: 1617 return mach64_putcmap(sc, 1618 (struct wsdisplay_cmap *)data); 1619 1620 /* PCI config read/write passthrough. */ 1621 case PCI_IOC_CFGREAD: 1622 case PCI_IOC_CFGWRITE: 1623 return (pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1624 cmd, data, flag, l)); 1625 1626 case WSDISPLAYIO_SMODE: 1627 { 1628 int new_mode = *(int*)data; 1629 1630 if (new_mode != sc->sc_mode) 1631 { 1632 sc->sc_mode = new_mode; 1633 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1634 && (ms != NULL)) 1635 { 1636 vcons_redraw_screen(ms); 1637 } 1638 } 1639 } 1640 return 0; 1641 1642 } 1643 return EPASSTHROUGH; 1644 } 1645 1646 static paddr_t 1647 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1648 { 1649 struct vcons_data *vd = v; 1650 struct mach64_softc *sc = vd->cookie; 1651 paddr_t pa; 1652 pcireg_t reg; 1653 1654 #ifndef __sparc64__ 1655 /* 1656 *'regular' framebuffer mmap()ing 1657 * disabled on sparc64 because some ATI firmware likes to map some PCI 1658 * resources to addresses that would collide with this ( like some Rage 1659 * IIc which uses 0x2000 for the 2nd register block ) 1660 * Other 64bit architectures might run into similar problems. 1661 */ 1662 if (offset<sc->sc_apersize) { 1663 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, offset, 1664 prot, BUS_SPACE_MAP_LINEAR); 1665 return pa; 1666 } 1667 #endif 1668 1669 /* 1670 * restrict all other mappings to processes with superuser privileges 1671 * or the kernel itself 1672 */ 1673 if (curlwp != NULL) { 1674 if (kauth_authorize_generic(kauth_cred_get(), 1675 KAUTH_GENERIC_ISSUSER, NULL) != 0) { 1676 printf("%s: mmap() rejected.\n", sc->sc_dev.dv_xname); 1677 return -1; 1678 } 1679 } 1680 1681 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1682 if (reg != sc->sc_regphys) { 1683 #ifdef DIAGNOSTIC 1684 printf("%s: BAR 0x18 changed! (%x %x)\n", 1685 sc->sc_dev.dv_xname, (uint32_t)sc->sc_regphys, 1686 (uint32_t)reg); 1687 #endif 1688 sc->sc_regphys = reg; 1689 } 1690 1691 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1692 if (reg != sc->sc_aperphys) { 1693 #ifdef DIAGNOSTIC 1694 printf("%s: BAR 0x10 changed! (%x %x)\n", 1695 sc->sc_dev.dv_xname, (uint32_t)sc->sc_aperphys, 1696 (uint32_t)reg); 1697 #endif 1698 sc->sc_aperphys = reg; 1699 } 1700 1701 #if 0 1702 /* evil hack to allow mmap()ing other devices as well */ 1703 if ((offset > 0x80000000) && (offset <= 0xffffffff)) { 1704 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1705 BUS_SPACE_MAP_LINEAR); 1706 return pa; 1707 } 1708 #endif 1709 1710 if ((offset >= sc->sc_aperphys) && 1711 (offset < (sc->sc_aperphys + sc->sc_apersize))) { 1712 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1713 BUS_SPACE_MAP_LINEAR); 1714 return pa; 1715 } 1716 1717 if ((offset >= sc->sc_regphys) && 1718 (offset < (sc->sc_regphys + sc->sc_regsize))) { 1719 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1720 BUS_SPACE_MAP_LINEAR); 1721 return pa; 1722 } 1723 1724 return -1; 1725 } 1726 1727 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1728 static void 1729 set_address(struct rasops_info *ri, caddr_t fb) 1730 { 1731 #ifdef notdef 1732 printf(" %d %d %d\n", ri->ri_xorigin, ri->ri_yorigin, ri->ri_stride); 1733 #endif 1734 ri->ri_bits = (void *)(fb + ri->ri_stride * ri->ri_yorigin + 1735 ri->ri_xorigin); 1736 } 1737 1738 #if 0 1739 static int 1740 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1741 { 1742 1743 return 0; 1744 } 1745 #endif 1746 1747 void 1748 machfb_blank(struct mach64_softc *sc, int blank) 1749 { 1750 uint32_t reg; 1751 1752 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1753 1754 switch (blank) 1755 { 1756 case 0: 1757 reg = regr(sc, CRTC_GEN_CNTL); 1758 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1759 sc->sc_blanked = 0; 1760 break; 1761 case 1: 1762 reg = regr(sc, CRTC_GEN_CNTL); 1763 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1764 sc->sc_blanked = 1; 1765 break; 1766 default: 1767 break; 1768 } 1769 } 1770 1771 /* framebuffer device support */ 1772 #ifdef __sparc__ 1773 1774 static void 1775 machfb_unblank(struct device *dev) 1776 { 1777 struct mach64_softc *sc = (struct mach64_softc *)dev; 1778 1779 machfb_blank(sc, 0); 1780 } 1781 1782 static void 1783 machfb_fbattach(struct mach64_softc *sc) 1784 { 1785 struct fbdevice *fb = &sc->sc_fb; 1786 1787 fb->fb_device = &sc->sc_dev; 1788 fb->fb_driver = &machfb_fbdriver; 1789 1790 fb->fb_type.fb_cmsize = 256; 1791 fb->fb_type.fb_size = sc->memsize; 1792 1793 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 1794 fb->fb_flags = sc->sc_dev.dv_cfdata->cf_flags & FB_USERMASK; 1795 fb->fb_type.fb_depth = sc->bits_per_pixel; 1796 fb->fb_type.fb_width = sc->virt_x; 1797 fb->fb_type.fb_height = sc->virt_y; 1798 1799 fb->fb_pixels = sc->sc_aperture; 1800 fb_attach(fb, sc->sc_console); 1801 } 1802 1803 int 1804 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 1805 { 1806 struct mach64_softc *sc; 1807 int unit = minor(dev); 1808 1809 sc = machfb_cd.cd_devs[unit]; 1810 sc->sc_locked = 1; 1811 1812 #ifdef DEBUG_MACHFB 1813 printf("machfb_fbopen(%d)\n", unit); 1814 #endif 1815 if (unit > machfb_cd.cd_ndevs || machfb_cd.cd_devs[unit] == NULL) 1816 return ENXIO; 1817 return 0; 1818 } 1819 1820 int 1821 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 1822 { 1823 struct mach64_softc *sc = machfb_cd.cd_devs[minor(dev)]; 1824 1825 #ifdef DEBUG_MACHFB 1826 printf("machfb_fbclose()\n"); 1827 #endif 1828 mach64_init_engine(sc); 1829 mach64_init_lut(sc); 1830 sc->sc_locked = 0; 1831 return 0; 1832 } 1833 1834 int 1835 machfb_fbioctl(dev_t dev, u_long cmd, caddr_t data, int flags, struct lwp *l) 1836 { 1837 struct mach64_softc *sc = machfb_cd.cd_devs[minor(dev)]; 1838 1839 #ifdef DEBUG_MACHFB 1840 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 1841 #endif 1842 switch (cmd) { 1843 case FBIOGTYPE: 1844 *(struct fbtype *)data = sc->sc_fb.fb_type; 1845 break; 1846 1847 case FBIOGATTR: 1848 #define fba ((struct fbgattr *)data) 1849 fba->real_type = sc->sc_fb.fb_type.fb_type; 1850 fba->owner = 0; /* XXX ??? */ 1851 fba->fbtype = sc->sc_fb.fb_type; 1852 fba->sattr.flags = 0; 1853 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 1854 fba->sattr.dev_specific[0] = sc->sc_nbus; 1855 fba->sattr.dev_specific[1] = sc->sc_ndev; 1856 fba->sattr.dev_specific[2] = sc->sc_nfunc; 1857 fba->sattr.dev_specific[3] = -1; 1858 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 1859 fba->emu_types[1] = -1; 1860 #undef fba 1861 break; 1862 1863 #if 0 1864 case FBIOGETCMAP: 1865 #define p ((struct fbcmap *)data) 1866 return (bt_getcmap(p, &sc->sc_cmap, 256, 1)); 1867 1868 case FBIOPUTCMAP: 1869 /* copy to software map */ 1870 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 1871 if (error) 1872 return error; 1873 /* now blast them into the chip */ 1874 /* XXX should use retrace interrupt */ 1875 cg6_loadcmap(sc, p->index, p->count); 1876 #undef p 1877 break; 1878 #endif 1879 case FBIOGVIDEO: 1880 *(int *)data = sc->sc_blanked; 1881 break; 1882 1883 case FBIOSVIDEO: 1884 machfb_blank(sc, *(int *)data); 1885 break; 1886 1887 #if 0 1888 case FBIOGCURSOR: 1889 break; 1890 1891 case FBIOSCURSOR: 1892 break; 1893 1894 case FBIOGCURPOS: 1895 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 1896 break; 1897 1898 case FBIOSCURPOS: 1899 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 1900 break; 1901 1902 case FBIOGCURMAX: 1903 /* max cursor size is 32x32 */ 1904 ((struct fbcurpos *)data)->x = 32; 1905 ((struct fbcurpos *)data)->y = 32; 1906 break; 1907 #endif 1908 case PCI_IOC_CFGREAD: 1909 case PCI_IOC_CFGWRITE: 1910 { 1911 int ret; 1912 1913 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1914 cmd, data, flags, l); 1915 1916 #ifdef DEBUG_MACHFB 1917 printf("pci_devioctl: %d\n", ret); 1918 #endif 1919 return ret; 1920 } 1921 default: 1922 #ifdef DEBUG_MACHFB 1923 log(LOG_NOTICE, "machfb_fbioctl(0x%lx) (%s[%d])\n", cmd, 1924 p->p_comm, p->p_pid); 1925 #endif 1926 return ENOTTY; 1927 } 1928 #ifdef DEBUG_MACHFB 1929 printf("machfb_fbioctl done\n"); 1930 #endif 1931 return 0; 1932 } 1933 1934 paddr_t 1935 machfb_fbmmap(dev_t dev, off_t off, int prot) 1936 { 1937 struct mach64_softc *sc = machfb_cd.cd_devs[minor(dev)]; 1938 1939 if (sc != NULL) 1940 return mach64_mmap(&sc->vd, NULL, off, prot); 1941 1942 return 0; 1943 } 1944 1945 #endif /* __sparc__ */ 1946
Indexes created Thu Oct 02 14:10:14 GMT 2025