machfb.c revision 1.5
1 /* $NetBSD: machfb.c,v 1.5 2002/10/29 13:50:11 junyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 32 */ 33 34 #include <sys/cdefs.h> 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/callout.h> 42 43 #ifdef __sparc__ 44 #include <machine/openfirm.h> 45 #endif 46 47 #include <dev/ic/videomode.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcidevs.h> 52 #include <dev/pci/pciio.h> 53 #include <dev/pci/machfbreg.h> 54 55 #include <dev/wscons/wsdisplayvar.h> 56 #include <dev/wscons/wsconsio.h> 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/rasops/rasops.h> 59 60 #define MACH64_REG_SIZE 1024 61 #define MACH64_REG_OFF 0x7ffc00 62 63 #define NBARS 3 /* number of Mach64 PCI BARs */ 64 65 struct vga_bar { 66 bus_addr_t vb_base; 67 bus_size_t vb_size; 68 pcireg_t vb_type; 69 int vb_flags; 70 }; 71 72 struct mach64_softc { 73 struct device sc_dev; 74 pci_chipset_tag_t sc_pc; 75 pcitag_t sc_pcitag; 76 77 struct vga_bar sc_bars[NBARS]; 78 struct vga_bar sc_rom; 79 80 #define sc_aperbase sc_bars[0].vb_base 81 #define sc_apersize sc_bars[0].vb_size 82 83 #define sc_iobase sc_bars[1].vb_base 84 #define sc_iosize sc_bars[1].vb_size 85 86 #define sc_regbase sc_bars[2].vb_base 87 #define sc_regsize sc_bars[2].vb_size 88 89 bus_space_tag_t sc_regt; 90 bus_space_tag_t sc_memt; 91 bus_space_handle_t sc_regh; 92 bus_space_handle_t sc_memh; 93 94 size_t memsize; 95 int memtype; 96 97 int has_dsp; 98 int bits_per_pixel; 99 int max_x, max_y; 100 int virt_x, virt_y; 101 int color_depth; 102 103 int mem_freq; 104 int ramdac_freq; 105 int ref_freq; 106 107 int ref_div; 108 int log2_vclk_post_div; 109 int vclk_post_div; 110 int vclk_fb_div; 111 int mclk_post_div; 112 int mclk_fb_div; 113 114 struct mach64screen *wanted; 115 struct mach64screen *active; 116 void (*switchcb)(void *, int, int); 117 void *switchcbarg; 118 struct callout switch_callout; 119 int nscreens; 120 LIST_HEAD(, mach64screen) screens; 121 const struct wsscreen_descr *currenttype; 122 }; 123 124 struct mach64screen { 125 LIST_ENTRY(mach64screen) next; 126 struct mach64_softc *sc; 127 const struct wsscreen_descr *type; 128 int active; 129 u_int16_t *mem; 130 int dispoffset; 131 int mindispoffset; 132 int maxdispoffset; 133 134 int cursoron; 135 int cursorcol; 136 int cursorrow; 137 u_int16_t cursortmp; 138 }; 139 140 struct mach64_crtcregs { 141 u_int32_t h_total_disp; 142 u_int32_t h_sync_strt_wid; 143 u_int32_t v_total_disp; 144 u_int32_t v_sync_strt_wid; 145 u_int32_t gen_cntl; 146 u_int32_t clock_cntl; 147 u_int32_t color_depth; 148 u_int32_t dot_clock; 149 }; 150 151 struct { 152 u_int16_t chip_id; 153 u_int32_t ramdac_freq; 154 } mach64_info[] = { 155 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 156 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 157 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 158 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 159 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 160 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 161 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 162 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 163 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 164 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 165 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 166 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 167 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 168 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 169 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 170 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 171 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 172 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 173 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 174 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 175 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 176 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 177 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 178 }; 179 180 static int mach64_chip_id, mach64_chip_rev; 181 static struct videomode default_mode; 182 struct rasops_info mach64_rasops_info; 183 static struct mach64screen mach64_console_screen; 184 185 static char *mach64_memtype_names[] = { 186 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 187 "(unknown type)" 188 }; 189 190 struct videomode mach64_modes[] = { 191 /* 640x400 @ 70 Hz, 31.5 kHz */ 192 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0 }, 193 /* 640x480 @ 72 Hz, 36.5 kHz */ 194 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0 }, 195 /* 800x600 @ 72 Hz, 48.0 kHz */ 196 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 197 VID_PHSYNC | VID_PVSYNC }, 198 /* 1024x768 @ 70 Hz, 56.5 kHz */ 199 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 200 VID_NHSYNC | VID_NVSYNC }, 201 /* 1152x864 @ 70 Hz, 62.4 kHz */ 202 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0 }, 203 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 204 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 205 VID_NHSYNC | VID_NVSYNC } 206 }; 207 208 /* FIXME values are wrong! */ 209 const u_char mach64_cmap[16 * 3] = { 210 0x00, 0x00, 0x00, /* black */ 211 0x7f, 0x00, 0x00, /* red */ 212 0x00, 0x7f, 0x00, /* green */ 213 0x7f, 0x7f, 0x00, /* brown */ 214 0x00, 0x00, 0x7f, /* blue */ 215 0x7f, 0x00, 0x7f, /* magenta */ 216 0x00, 0x7f, 0x7f, /* cyan */ 217 0xff, 0xff, 0xff, /* white */ 218 219 0x7f, 0x7f, 0x7f, /* black */ 220 0xff, 0x00, 0x00, /* red */ 221 0x00, 0xff, 0x00, /* green */ 222 0xff, 0xff, 0x00, /* brown */ 223 0x00, 0x00, 0xff, /* blue */ 224 0xff, 0x00, 0xff, /* magenta */ 225 0x00, 0xff, 0xff, /* cyan */ 226 0xff, 0xff, 0xff, /* white */ 227 }; 228 229 int mach64_match(struct device *, struct cfdata *, void *); 230 void mach64_attach(struct device *, struct device *, void *); 231 232 CFATTACH_DECL(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 233 NULL, NULL); 234 235 void mach64_init(struct mach64_softc *); 236 int mach64_get_memsize(struct mach64_softc *); 237 int mach64_get_max_ramdac(struct mach64_softc *); 238 void mach64_get_mode(struct mach64_softc *, struct videomode *); 239 int mach64_calc_crtcregs(struct mach64_softc *, struct mach64_crtcregs *, 240 struct videomode *); 241 void mach64_set_crtcregs(struct mach64_softc *, struct mach64_crtcregs *); 242 int mach64_modeswitch(struct mach64_softc *, struct videomode *); 243 void mach64_set_dsp(struct mach64_softc *); 244 void mach64_set_pll(struct mach64_softc *, int); 245 void mach64_reset_engine(struct mach64_softc *); 246 void mach64_init_engine(struct mach64_softc *); 247 void mach64_adjust_frame(struct mach64_softc *, int, int); 248 void mach64_init_lut(struct mach64_softc *); 249 void mach64_switch_screen(struct mach64_softc *); 250 void mach64_init_screen(struct mach64_softc *, struct mach64screen *, 251 const struct wsscreen_descr *, int, long *); 252 void mach64_restore_screen(struct mach64screen *, 253 const struct wsscreen_descr *, u_int16_t *); 254 void mach64_set_screentype(struct mach64_softc *, 255 const struct wsscreen_descr *); 256 int mach64_is_console(struct pci_attach_args *); 257 258 void mach64_cursor(void *, int, int, int); 259 int mach64_mapchar(void *, int, u_int *); 260 void mach64_putchar(void *, int, int, u_int, long); 261 void mach64_copycols(void *, int, int, int, int); 262 void mach64_erasecols(void *, int, int, int, long); 263 void mach64_copyrows(void *, int, int, int); 264 void mach64_eraserows(void *, int, int, long); 265 int mach64_allocattr(void *, int, int, int, long *); 266 267 const struct wsdisplay_emulops mach64_emulops = { 268 mach64_cursor, 269 mach64_mapchar, 270 mach64_putchar, 271 mach64_copycols, 272 mach64_erasecols, 273 mach64_copyrows, 274 mach64_eraserows, 275 mach64_allocattr, 276 }; 277 278 struct wsscreen_descr mach64_defaultscreen = { 279 "default", 280 0, 0, 281 &mach64_rasops_info.ri_ops, 282 8, 16, 283 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 284 &default_mode 285 }, mach64_80x25_screen = { 286 "80x25", 80, 25, 287 &mach64_rasops_info.ri_ops, 288 8, 16, 289 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 290 &mach64_modes[0] 291 }, mach64_80x30_screen = { 292 "80x30", 80, 30, 293 &mach64_rasops_info.ri_ops, 294 8, 16, 295 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 296 &mach64_modes[1] 297 }, mach64_80x40_screen = { 298 "80x40", 80, 40, 299 &mach64_rasops_info.ri_ops, 300 8, 10, 301 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 302 &mach64_modes[0] 303 }, mach64_80x50_screen = { 304 "80x50", 80, 50, 305 &mach64_rasops_info.ri_ops, 306 8, 8, 307 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 308 &mach64_modes[0] 309 }, mach64_100x37_screen = { 310 "100x37", 100, 37, 311 &mach64_rasops_info.ri_ops, 312 8, 16, 313 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 314 &mach64_modes[2] 315 }, mach64_128x48_screen = { 316 "128x48", 128, 48, 317 &mach64_rasops_info.ri_ops, 318 8, 16, 319 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 320 &mach64_modes[3] 321 }, mach64_144x54_screen = { 322 "144x54", 144, 54, 323 &mach64_rasops_info.ri_ops, 324 8, 16, 325 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 326 &mach64_modes[4] 327 }, mach64_160x64_screen = { 328 "160x54", 160, 64, 329 &mach64_rasops_info.ri_ops, 330 8, 16, 331 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 332 &mach64_modes[5] 333 }; 334 335 const struct wsscreen_descr *_mach64_scrlist[] = { 336 &mach64_defaultscreen, 337 &mach64_80x25_screen, 338 &mach64_80x30_screen, 339 &mach64_80x40_screen, 340 &mach64_80x50_screen, 341 &mach64_100x37_screen, 342 &mach64_128x48_screen, 343 &mach64_144x54_screen, 344 &mach64_160x64_screen 345 }; 346 347 struct wsscreen_list mach64_screenlist = { 348 sizeof(_mach64_scrlist) / sizeof(struct wsscreen_descr *), 349 _mach64_scrlist 350 }; 351 352 int mach64_ioctl(void *, u_long, caddr_t, int, struct proc *); 353 paddr_t mach64_mmap(void *, off_t, int); 354 int mach64_alloc_screen(void *, const struct wsscreen_descr *, void **, 355 int *, int *, long *); 356 void mach64_free_screen(void *, void *); 357 int mach64_show_screen(void *, void *, int, void (*)(void *, int, int), 358 void *); 359 int mach64_load_font(void *, void *, struct wsdisplay_font *); 360 361 struct wsdisplay_accessops mach64_accessops = { 362 mach64_ioctl, 363 mach64_mmap, 364 mach64_alloc_screen, 365 mach64_free_screen, 366 mach64_show_screen, 367 NULL 368 }; 369 370 /* 371 * Inline functions for getting access to register aperture. 372 */ 373 static inline u_int32_t regr(struct mach64_softc *, u_int32_t); 374 static inline u_int8_t regrb(struct mach64_softc *, u_int32_t); 375 static inline void regw(struct mach64_softc *, u_int32_t, u_int32_t); 376 static inline void regwb(struct mach64_softc *, u_int32_t, u_int8_t); 377 static inline void regwb_pll(struct mach64_softc *, u_int32_t, u_int8_t); 378 379 static inline u_int32_t 380 regr(struct mach64_softc *sc, u_int32_t index) 381 { 382 383 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 384 } 385 386 static inline u_int8_t 387 regrb(struct mach64_softc *sc, u_int32_t index) 388 { 389 390 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 391 } 392 393 static inline void 394 regw(struct mach64_softc *sc, u_int32_t index, u_int32_t data) 395 { 396 397 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 398 } 399 400 static inline void 401 regwb(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 402 { 403 404 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 405 } 406 407 static inline void 408 regwb_pll(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 409 { 410 411 regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); 412 regwb(sc, CLOCK_CNTL + 2, data); 413 regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); 414 } 415 416 static inline void 417 wait_for_fifo(struct mach64_softc *sc, u_int8_t v) 418 { 419 420 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 421 ; 422 } 423 424 static inline void 425 wait_for_idle(struct mach64_softc *sc) 426 { 427 428 wait_for_fifo(sc, 16); 429 while ((regr(sc, GUI_STAT) & 1) != 0) 430 ; 431 } 432 433 int 434 mach64_match(struct device *parent, struct cfdata *match, void *aux) 435 { 436 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 437 int i; 438 439 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 440 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 441 return 0; 442 443 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 444 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 445 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 446 mach64_chip_rev = PCI_REVISION(pa->pa_class); 447 return 1; 448 } 449 450 return 0; 451 } 452 453 void 454 mach64_attach(struct device *parent, struct device *self, void *aux) 455 { 456 struct mach64_softc *sc = (void *)self; 457 struct pci_attach_args *pa = aux; 458 char devinfo[256]; 459 int bar, reg, id; 460 struct wsemuldisplaydev_attach_args aa; 461 int console; 462 long defattr; 463 464 sc->sc_pc = pa->pa_pc; 465 sc->sc_pcitag = pa->pa_tag; 466 467 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 468 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 469 470 for (bar = 0; bar < NBARS; bar++) { 471 reg = PCI_MAPREG_START + (bar * 4); 472 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 473 sc->sc_pcitag, reg); 474 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 475 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 476 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 477 } 478 sc->sc_memt = pa->pa_memt; 479 480 mach64_init(sc); 481 482 printf("%s: %d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 483 sc->sc_dev.dv_xname, (u_int)(sc->sc_apersize / (1024 * 1024)), 484 (u_int)sc->sc_aperbase, (u_int)(sc->sc_regsize / 1024), 485 (u_int)sc->sc_regbase); 486 487 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 488 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 489 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 490 (mach64_chip_rev & 0x07) == 0)) 491 sc->has_dsp = 0; 492 else 493 sc->has_dsp = 1; 494 495 sc->memsize = mach64_get_memsize(sc); 496 if (sc->memsize == 8192) 497 /* The last page is used as register aperture. */ 498 sc->memsize -= 4; 499 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 500 501 /* XXX is there any way to calculate reference frequency from 502 known values? */ 503 if (mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) 504 sc->ref_freq = 29498; 505 else 506 sc->ref_freq = 14318; 507 508 regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); 509 sc->ref_div = regrb(sc, CLOCK_CNTL + 2); 510 regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); 511 sc->mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); 512 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 513 (sc->ref_div * 2); 514 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 515 (sc->mem_freq * sc->ref_div); 516 sc->ramdac_freq = mach64_get_max_ramdac(sc); 517 printf("%s: %ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 518 sc->sc_dev.dv_xname, (u_long)sc->memsize, 519 mach64_memtype_names[sc->memtype], 520 sc->mem_freq / 1000, sc->mem_freq % 1000, 521 sc->ramdac_freq / 1000); 522 523 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 524 if (id != mach64_chip_id) { 525 printf("%s: chip ID mismatch, 0x%x != 0x%x\n", 526 sc->sc_dev.dv_xname, id, mach64_chip_id); 527 return; 528 } 529 530 #ifdef __sparc__ 531 mach64_get_mode(sc, &default_mode); 532 #else 533 memcpy(&default_mode, &mach64_modes[0], sizeof(struct videomode)) ; 534 #endif 535 536 sc->bits_per_pixel = 8; 537 sc->virt_x = default_mode.hdisplay; 538 sc->virt_y = default_mode.vdisplay; 539 sc->max_x = sc->virt_x - 1; 540 sc->max_y = (sc->memsize * 1024) / 541 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 542 543 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 544 545 mach64_init_engine(sc); 546 #if 0 547 mach64_adjust_frame(0, 0); 548 if (sc->bits_per_pixel == 8) 549 mach64_init_lut(sc); 550 #endif 551 552 printf("%s: initial resolution %dx%d at %d bpp\n", sc->sc_dev.dv_xname, 553 default_mode.hdisplay, default_mode.vdisplay, 554 sc->bits_per_pixel); 555 556 mach64_rasops_info.ri_depth = sc->bits_per_pixel; 557 mach64_rasops_info.ri_bits = (void *)sc->sc_aperbase; 558 mach64_rasops_info.ri_width = default_mode.hdisplay; 559 mach64_rasops_info.ri_height = default_mode.vdisplay; 560 mach64_rasops_info.ri_stride = mach64_rasops_info.ri_width; 561 mach64_rasops_info.ri_flg = RI_CLEAR; 562 563 rasops_init(&mach64_rasops_info, mach64_rasops_info.ri_height / 16, 564 mach64_rasops_info.ri_width / 8); 565 566 mach64_defaultscreen.nrows = mach64_rasops_info.ri_rows; 567 mach64_defaultscreen.ncols = mach64_rasops_info.ri_cols; 568 569 mach64_init_screen(sc, &mach64_console_screen, 570 &mach64_defaultscreen, 1, &defattr); 571 572 mach64_rasops_info.ri_ops.allocattr(&mach64_rasops_info, 0, 0, 0, 573 &defattr); 574 575 console = mach64_is_console(pa); 576 if (console) 577 wsdisplay_cnattach(&mach64_defaultscreen, &mach64_rasops_info, 578 0, 0, defattr); 579 580 aa.console = console; 581 aa.scrdata = &mach64_screenlist; 582 aa.accessops = &mach64_accessops; 583 aa.accesscookie = sc; 584 585 config_found(self, &aa, wsemuldisplaydevprint); 586 } 587 588 void 589 mach64_init_screen(struct mach64_softc *sc, struct mach64screen *scr, 590 const struct wsscreen_descr *type, int existing, long *attrp) 591 { 592 #if !defined(__sparc__) 593 struct videomode *mode = (struct videomode *)type->modecookie; 594 #endif 595 596 scr->sc = sc; 597 scr->type = type; 598 scr->mindispoffset = 0; 599 scr->maxdispoffset = sc->memsize * 1024; 600 scr->dispoffset = 0; 601 scr->cursorcol = 0; 602 scr->cursorrow = 0; 603 604 if (existing) { 605 scr->mem = (u_int16_t *)malloc(type->nrows * type->ncols * 2, 606 M_DEVBUF, M_WAITOK); 607 scr->active = 1; 608 609 #if !defined(__sparc__) 610 if (mach64_modeswitch(sc, mode)) { 611 panic("%s: failed to switch video mode", 612 sc->sc_dev.dv_xname); 613 } 614 #endif 615 } else { 616 scr->active = 0; 617 scr->mem = NULL; 618 } 619 620 wsfont_init(); 621 622 sc->nscreens++; 623 LIST_INSERT_HEAD(&sc->screens, scr, next); 624 } 625 626 void 627 mach64_init(struct mach64_softc *sc) 628 { 629 630 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 631 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 632 panic("%s: failed to map aperture", sc->sc_dev.dv_xname); 633 } 634 sc->sc_aperbase = (vaddr_t)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 635 636 sc->sc_regt = sc->sc_memt; 637 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 638 sc->sc_regsize, &sc->sc_regh); 639 sc->sc_regbase = sc->sc_aperbase + 0x7ffc00; 640 641 #if _BYTE_ORDER == _BIG_ENDIAN 642 sc->sc_aperbase += 0x800000; 643 sc->sc_apersize -= 0x800000; 644 #endif 645 646 sc->nscreens = 0; 647 LIST_INIT(&sc->screens); 648 sc->active = NULL; 649 sc->currenttype = &mach64_defaultscreen; 650 callout_init(&sc->switch_callout); 651 } 652 653 int 654 mach64_get_memsize(struct mach64_softc *sc) 655 { 656 int tmp, memsize; 657 int mem_tab[] = { 658 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 659 }; 660 661 tmp = regr(sc, MEM_CNTL); 662 if (sc->has_dsp) { 663 tmp &= 0x0000000f; 664 if (tmp < 8) 665 memsize = (tmp + 1) * 512; 666 else if (tmp < 12) 667 memsize = (tmp - 3) * 1024; 668 else 669 memsize = (tmp - 7) * 2048; 670 } else { 671 memsize = mem_tab[tmp & 0x07]; 672 } 673 674 return memsize; 675 } 676 677 int 678 mach64_get_max_ramdac(struct mach64_softc *sc) 679 { 680 int i; 681 682 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 683 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 684 (mach64_chip_rev & 0x07)) 685 return 170000; 686 687 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 688 if (mach64_chip_id == mach64_info[i].chip_id) 689 return mach64_info[i].ramdac_freq; 690 691 if (sc->bits_per_pixel == 8) 692 return 135000; 693 else 694 return 80000; 695 } 696 697 void 698 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 699 { 700 struct mach64_crtcregs crtc; 701 702 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 703 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 704 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 705 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 706 707 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 708 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 709 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 710 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 711 mode->hsync_start; 712 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 713 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 714 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 715 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 716 717 #ifdef MACH64_DEBUG 718 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 719 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 720 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 721 #endif 722 } 723 724 int 725 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 726 struct videomode *mode) 727 { 728 729 if (mode->dot_clock > sc->ramdac_freq) 730 /* Clock too high. */ 731 return 1; 732 733 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 734 ((mode->htotal >> 3) - 1); 735 crtc->h_sync_strt_wid = 736 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 737 ((mode->hsync_start >> 3) - 1); 738 739 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 740 (mode->vtotal - 1); 741 crtc->v_sync_strt_wid = 742 ((mode->vsync_end - mode->vsync_start) << 16) | 743 (mode->vsync_start - 1); 744 745 if (mode->flags & VID_NVSYNC) 746 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 747 748 switch (sc->bits_per_pixel) { 749 case 8: 750 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 751 break; 752 case 16: 753 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 754 break; 755 case 32: 756 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 757 break; 758 } 759 760 crtc->gen_cntl = 0; 761 if (mode->flags & VID_INTERLACE) 762 crtc->gen_cntl |= CRTC_INTERLACE_EN; 763 if (mode->flags & VID_CSYNC) 764 crtc->gen_cntl |= CRTC_CSYNC_EN; 765 766 crtc->dot_clock = mode->dot_clock; 767 768 return 0; 769 } 770 771 void 772 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 773 { 774 775 mach64_set_pll(sc, crtc->dot_clock); 776 777 if (sc->has_dsp) 778 mach64_set_dsp(sc); 779 780 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 781 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 782 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 783 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 784 785 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 786 787 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 788 789 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 790 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 791 } 792 793 int 794 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 795 { 796 struct mach64_crtcregs crtc; 797 798 if (mach64_calc_crtcregs(sc, &crtc, mode)) 799 return 1; 800 801 mach64_set_crtcregs(sc, &crtc); 802 return 0; 803 } 804 805 void 806 mach64_reset_engine(struct mach64_softc *sc) 807 { 808 809 /* Reset engine.*/ 810 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 811 812 /* Enable engine. */ 813 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 814 815 /* Ensure engine is not locked up by clearing any FIFO or 816 host errors. */ 817 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 818 BUS_FIFO_ERR_ACK); 819 } 820 821 void 822 mach64_init_engine(struct mach64_softc *sc) 823 { 824 u_int32_t pitch_value; 825 826 pitch_value = sc->virt_x; 827 828 if (sc->bits_per_pixel == 24) 829 pitch_value *= 3; 830 831 mach64_reset_engine(sc); 832 833 wait_for_fifo(sc, 14); 834 835 regw(sc, CONTEXT_MASK, 0xffffffff); 836 837 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 838 839 regw(sc, DST_Y_X, 0); 840 regw(sc, DST_HEIGHT, 0); 841 regw(sc, DST_BRES_ERR, 0); 842 regw(sc, DST_BRES_INC, 0); 843 regw(sc, DST_BRES_DEC, 0); 844 845 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 846 DST_Y_TOP_TO_BOTTOM); 847 848 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 849 850 regw(sc, SRC_Y_X, 0); 851 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 852 regw(sc, SRC_Y_X_START, 0); 853 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 854 855 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 856 857 wait_for_fifo(sc, 13); 858 regw(sc, HOST_CNTL, 0); 859 860 regw(sc, PAT_REG0, 0); 861 regw(sc, PAT_REG1, 0); 862 regw(sc, PAT_CNTL, 0); 863 864 regw(sc, SC_LEFT, 0); 865 regw(sc, SC_TOP, 0); 866 regw(sc, SC_BOTTOM, default_mode.vdisplay - 1); 867 regw(sc, SC_RIGHT, pitch_value - 1); 868 869 regw(sc, DP_BKGD_CLR, 0); 870 regw(sc, DP_FRGD_CLR, 0xffffffff); 871 regw(sc, DP_WRITE_MASK, 0xffffffff); 872 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 873 874 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 875 876 wait_for_fifo(sc, 3); 877 regw(sc, CLR_CMP_CLR, 0); 878 regw(sc, CLR_CMP_MASK, 0xffffffff); 879 regw(sc, CLR_CMP_CNTL, 0); 880 881 wait_for_fifo(sc, 2); 882 switch (sc->bits_per_pixel) { 883 case 8: 884 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 885 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 886 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) & ~DAC_8BIT_EN); 887 break; 888 #if 0 889 case 32: 890 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 891 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 892 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 893 break; 894 #endif 895 } 896 897 wait_for_fifo(sc, 5); 898 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 899 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 900 901 wait_for_idle(sc); 902 } 903 904 void 905 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 906 { 907 int offset; 908 909 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 910 911 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 912 offset); 913 } 914 915 void 916 mach64_set_dsp(struct mach64_softc *sc) 917 { 918 u_int32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 919 u_int32_t dsp_off, dsp_on, dsp_xclks_per_qw; 920 u_int32_t xclks_per_qw, y; 921 u_int32_t fifo_off, fifo_on; 922 923 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 924 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 925 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 926 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 927 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 928 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 929 dsp_loop_latency = 0; 930 fifo_depth = 24; 931 } else { 932 dsp_loop_latency = 2; 933 fifo_depth = 32; 934 } 935 936 dsp_precision = 0; 937 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 938 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 939 y = (xclks_per_qw * fifo_depth) >> 11; 940 while (y) { 941 y >>= 1; 942 dsp_precision++; 943 } 944 dsp_precision -= 5; 945 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 946 947 switch (sc->memtype) { 948 case DRAM: 949 case EDO_DRAM: 950 case PSEUDO_EDO: 951 if (sc->memsize > 1024) { 952 page_size = 9; 953 dsp_loop_latency += 6; 954 } else { 955 page_size = 10; 956 if (sc->memtype == DRAM) 957 dsp_loop_latency += 8; 958 else 959 dsp_loop_latency += 7; 960 } 961 break; 962 case SDRAM: 963 case SGRAM: 964 if (sc->memsize > 1024) { 965 page_size = 8; 966 dsp_loop_latency += 8; 967 } else { 968 page_size = 10; 969 dsp_loop_latency += 9; 970 } 971 break; 972 default: 973 page_size = 10; 974 dsp_loop_latency += 9; 975 break; 976 } 977 978 if (xclks_per_qw >= (page_size << 11)) 979 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 980 else 981 fifo_on = (3 * page_size + 2) << 6; 982 983 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 984 dsp_on = fifo_on >> dsp_precision; 985 dsp_off = fifo_off >> dsp_precision; 986 987 #ifdef MACH64_DEBUG 988 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 989 "dsp_precision = %d, dsp_loop_latency = %d,\n" 990 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 991 "mclk_post_div = %d, vclk_post_div = %d\n", 992 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 993 sc->mclk_fb_div, sc->vclk_fb_div, 994 sc->mclk_post_div, sc->vclk_post_div); 995 #endif 996 997 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 998 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 999 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1000 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1001 } 1002 1003 void 1004 mach64_set_pll(struct mach64_softc *sc, int clock) 1005 { 1006 int q; 1007 1008 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1009 #ifdef MACH64_DEBUG 1010 printf("q = %d\n", q); 1011 #endif 1012 if (q > 25500) { 1013 printf("Warning: q > 25500\n"); 1014 q = 25500; 1015 sc->vclk_post_div = 1; 1016 sc->log2_vclk_post_div = 0; 1017 } else if (q > 12750) { 1018 sc->vclk_post_div = 1; 1019 sc->log2_vclk_post_div = 0; 1020 } else if (q > 6350) { 1021 sc->vclk_post_div = 2; 1022 sc->log2_vclk_post_div = 1; 1023 } else if (q > 3150) { 1024 sc->vclk_post_div = 4; 1025 sc->log2_vclk_post_div = 2; 1026 } else if (q >= 1600) { 1027 sc->vclk_post_div = 8; 1028 sc->log2_vclk_post_div = 3; 1029 } else { 1030 printf("Warning: q < 1600\n"); 1031 sc->vclk_post_div = 8; 1032 sc->log2_vclk_post_div = 3; 1033 } 1034 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1035 1036 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1037 regwb_pll(sc, VCLK_POST_DIV, sc->log2_vclk_post_div); 1038 regwb_pll(sc, VCLK0_FB_DIV, sc->vclk_fb_div); 1039 } 1040 1041 void 1042 mach64_init_lut(struct mach64_softc *sc) 1043 { 1044 int i; 1045 1046 regwb(sc, DAC_REGS, 0); 1047 1048 for (i = 0; i < 16; i++) { 1049 regwb(sc, DAC_REGS + 1, mach64_cmap[i * 3]); 1050 regwb(sc, DAC_REGS + 1, mach64_cmap[i * 3 + 1]); 1051 regwb(sc, DAC_REGS + 1, mach64_cmap[i + 3 + 2]); 1052 } 1053 } 1054 1055 void 1056 mach64_switch_screen(struct mach64_softc *sc) 1057 { 1058 struct mach64screen *scr, *oldscr; 1059 const struct wsscreen_descr *type; 1060 1061 scr = sc->wanted; 1062 if (!scr) { 1063 printf("mach64_switch_screen: disappeared\n"); 1064 (*sc->switchcb)(sc->switchcbarg, EIO, 0); 1065 return; 1066 } 1067 type = scr->type; 1068 oldscr = sc->active; /* can be NULL! */ 1069 #ifdef DIAGNOSTIC 1070 if (oldscr) { 1071 if (!oldscr->active) 1072 panic("mach64_switch_screen: not active"); 1073 if (oldscr->type != vc->currenttype) 1074 panic("mach64_switch_screen: bad type"); 1075 } 1076 #endif 1077 if (scr == oldscr) 1078 return; 1079 1080 #ifdef DIAGNOSTIC 1081 if (scr->active) 1082 panic("mach64_switch_screen: active"); 1083 #endif 1084 1085 if (oldscr) 1086 oldscr->active = 0; 1087 1088 if (sc->currenttype != type) { 1089 mach64_set_screentype(sc, type); 1090 sc->currenttype = type; 1091 } 1092 1093 scr->dispoffset = scr->mindispoffset; 1094 1095 if (!oldscr || (scr->dispoffset != oldscr->dispoffset)) { 1096 1097 } 1098 1099 /* Clear the entire screen. */ 1100 1101 scr->active = 1; 1102 mach64_restore_screen(scr, type, scr->mem); 1103 1104 sc->active = scr; 1105 1106 mach64_cursor(scr, scr->cursoron, scr->cursorrow, scr->cursorcol); 1107 1108 sc->wanted = 0; 1109 if (sc->switchcb) 1110 (*sc->switchcb)(sc->switchcbarg, 0, 0); 1111 } 1112 1113 void 1114 mach64_restore_screen(struct mach64screen *scr, 1115 const struct wsscreen_descr *type, u_int16_t *mem) 1116 { 1117 1118 } 1119 1120 void 1121 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1122 { 1123 1124 } 1125 1126 int 1127 mach64_is_console(struct pci_attach_args *pa) 1128 { 1129 #ifdef __sparc__ 1130 int node; 1131 1132 node = PCITAG_NODE(pa->pa_tag); 1133 if (node == -1) 1134 return 0; 1135 1136 return (node == OF_instance_to_package(OF_stdout())); 1137 #else 1138 return 1; 1139 #endif 1140 } 1141 1142 /* 1143 * wsdisplay_emulops 1144 */ 1145 1146 void 1147 mach64_cursor(void *cookie, int on, int row, int col) 1148 { 1149 1150 } 1151 1152 int 1153 mach64_mapchar(void *cookie, int uni, u_int *index) 1154 { 1155 1156 return 0; 1157 } 1158 1159 void 1160 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1161 { 1162 1163 } 1164 1165 void 1166 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1167 { 1168 1169 } 1170 1171 void 1172 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1173 { 1174 1175 } 1176 1177 void 1178 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1179 { 1180 1181 } 1182 1183 void 1184 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1185 { 1186 1187 } 1188 1189 int 1190 mach64_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1191 { 1192 1193 return 0; 1194 } 1195 1196 /* 1197 * wsdisplay_accessops 1198 */ 1199 1200 int 1201 mach64_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 1202 { 1203 1204 return ENOTTY; 1205 } 1206 1207 paddr_t 1208 mach64_mmap(void *v, off_t offset, int prot) 1209 { 1210 1211 return -1; 1212 } 1213 1214 int 1215 mach64_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, 1216 int *curxp, int *curyp, long *defattrp) 1217 { 1218 struct mach64_softc *sc = v; 1219 struct mach64screen *scr; 1220 1221 if (sc->nscreens == 1) 1222 sc->screens.lh_first->mem = scr->mem; 1223 1224 scr = malloc(sizeof(struct mach64screen), M_DEVBUF, M_WAITOK); 1225 mach64_init_screen(sc, scr, type, 0, defattrp); 1226 1227 if (sc->nscreens == 1) { 1228 scr->active = 1; 1229 sc->active = scr; 1230 sc->currenttype = type; 1231 } else { 1232 scr->mem = malloc(type->ncols * type->nrows * 2, M_DEVBUF, 1233 M_WAITOK); 1234 mach64_eraserows(sc, 0, type->nrows, *defattrp); 1235 } 1236 1237 *cookiep = scr; 1238 *curxp = scr->cursorcol; 1239 *curyp = scr->cursorrow; 1240 1241 return 0; 1242 } 1243 1244 void 1245 mach64_free_screen(void *v, void *cookie) 1246 { 1247 struct mach64_softc *sc = v; 1248 struct mach64screen *scr = cookie; 1249 1250 LIST_REMOVE(scr, next); 1251 if (scr != &mach64_console_screen) 1252 free(scr, M_DEVBUF); 1253 else 1254 panic("mach64_free_screen: console"); 1255 1256 if (sc->active == scr) 1257 sc->active = 0; 1258 } 1259 1260 int 1261 mach64_show_screen(void *v, void *cookie, int waitok, 1262 void (*cb)(void *, int, int), void *cbarg) 1263 { 1264 struct mach64_softc *sc = v; 1265 struct mach64screen *scr, *oldscr; 1266 1267 scr = cookie; 1268 oldscr = sc->active; 1269 if (scr == oldscr) 1270 return 0; 1271 1272 sc->wanted = scr; 1273 sc->switchcb = cb; 1274 sc->switchcbarg = cbarg; 1275 if (cb) { 1276 callout_reset(&sc->switch_callout, 0, 1277 (void(*)(void *))mach64_switch_screen, sc); 1278 return EAGAIN; 1279 } 1280 1281 mach64_switch_screen(sc); 1282 1283 return 0; 1284 } 1285 1286 int 1287 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1288 { 1289 1290 return 0; 1291 } 1292
Indexes created Thu Oct 02 14:10:14 GMT 2025