machfb.c revision 1.54
1 /* $NetBSD: machfb.c,v 1.54 2008/07/01 23:19:48 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, 36 "$NetBSD: machfb.c,v 1.54 2008/07/01 23:19:48 dyoung Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/callout.h> 44 #include <sys/kauth.h> 45 46 #ifdef __sparc__ 47 #include <machine/promlib.h> 48 #endif 49 50 #ifdef __powerpc__ 51 #include <dev/ofw/openfirm.h> 52 #include <dev/ofw/ofw_pci.h> 53 #endif 54 55 #include <dev/videomode/videomode.h> 56 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcidevs.h> 60 #include <dev/pci/pciio.h> 61 #include <dev/pci/machfbreg.h> 62 63 #ifdef __sparc__ 64 #include <dev/sun/fbio.h> 65 #include <dev/sun/fbvar.h> 66 #include <sys/conf.h> 67 #else 68 #include <dev/wscons/wsdisplayvar.h> 69 #endif 70 71 #include <dev/wscons/wsconsio.h> 72 #include <dev/wsfont/wsfont.h> 73 #include <dev/rasops/rasops.h> 74 75 #include <dev/wscons/wsdisplay_vconsvar.h> 76 77 #define MACH64_REG_SIZE 1024 78 #define MACH64_REG_OFF 0x7ffc00 79 80 #define NBARS 3 /* number of Mach64 PCI BARs */ 81 82 struct vga_bar { 83 bus_addr_t vb_base; 84 pcireg_t vb_busaddr; 85 bus_size_t vb_size; 86 pcireg_t vb_type; 87 int vb_flags; 88 }; 89 90 struct mach64_softc { 91 struct device sc_dev; 92 #ifdef __sparc__ 93 struct fbdevice sc_fb; 94 #endif 95 pci_chipset_tag_t sc_pc; 96 pcitag_t sc_pcitag; 97 98 struct vga_bar sc_bars[NBARS]; 99 struct vga_bar sc_rom; 100 101 #define sc_aperbase sc_bars[0].vb_base 102 #define sc_apersize sc_bars[0].vb_size 103 #define sc_aperphys sc_bars[0].vb_busaddr 104 105 #define sc_iobase sc_bars[1].vb_base 106 #define sc_iosize sc_bars[1].vb_size 107 108 #define sc_regbase sc_bars[2].vb_base 109 #define sc_regsize sc_bars[2].vb_size 110 #define sc_regphys sc_bars[2].vb_busaddr 111 112 bus_space_tag_t sc_regt; 113 bus_space_tag_t sc_memt; 114 bus_space_handle_t sc_regh; 115 bus_space_handle_t sc_memh; 116 void *sc_aperture; /* mapped aperture vaddr */ 117 void *sc_registers; /* mapped registers vaddr */ 118 119 uint32_t sc_nbus, sc_ndev, sc_nfunc; 120 size_t memsize; 121 int memtype; 122 123 int sc_mode; 124 int sc_bg; 125 int sc_locked; 126 127 int has_dsp; 128 int bits_per_pixel; 129 int max_x; 130 int max_y; 131 int virt_x; 132 int virt_y; 133 int color_depth; 134 135 int mem_freq; 136 int ramdac_freq; 137 int ref_freq; 138 139 int ref_div; 140 int log2_vclk_post_div; 141 int vclk_post_div; 142 int vclk_fb_div; 143 int mclk_post_div; 144 int mclk_fb_div; 145 146 struct videomode *sc_my_mode; 147 u_char sc_cmap_red[256]; 148 u_char sc_cmap_green[256]; 149 u_char sc_cmap_blue[256]; 150 int sc_dacw, sc_blanked, sc_console; 151 struct vcons_data vd; 152 }; 153 154 struct mach64_crtcregs { 155 uint32_t h_total_disp; 156 uint32_t h_sync_strt_wid; 157 uint32_t v_total_disp; 158 uint32_t v_sync_strt_wid; 159 uint32_t gen_cntl; 160 uint32_t clock_cntl; 161 uint32_t color_depth; 162 uint32_t dot_clock; 163 }; 164 165 static struct { 166 uint16_t chip_id; 167 uint32_t ramdac_freq; 168 } const mach64_info[] = { 169 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 170 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 171 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 172 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 173 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 174 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 175 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 176 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 178 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 179 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 185 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 186 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 189 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 190 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 191 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 192 }; 193 194 static int mach64_chip_id, mach64_chip_rev; 195 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 196 197 static const char *mach64_memtype_names[] = { 198 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 199 "(unknown type)" 200 }; 201 202 static struct videomode mach64_modes[] = { 203 /* 640x400 @ 70 Hz, 31.5 kHz */ 204 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0, NULL, }, 205 /* 640x480 @ 72 Hz, 36.5 kHz */ 206 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0, NULL, }, 207 /* 800x600 @ 72 Hz, 48.0 kHz */ 208 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 209 VID_PHSYNC | VID_PVSYNC, NULL, }, 210 /* 1024x768 @ 70 Hz, 56.5 kHz */ 211 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 212 VID_NHSYNC | VID_NVSYNC, NULL, }, 213 /* 1152x864 @ 70 Hz, 62.4 kHz */ 214 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0, NULL, }, 215 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 216 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 217 VID_NHSYNC | VID_NVSYNC, NULL, } 218 }; 219 220 extern const u_char rasops_cmap[768]; 221 222 static int mach64_match(device_t, cfdata_t, void *); 223 static void mach64_attach(device_t, device_t, void *); 224 225 CFATTACH_DECL(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 226 NULL, NULL); 227 228 static void mach64_init(struct mach64_softc *); 229 static int mach64_get_memsize(struct mach64_softc *); 230 static int mach64_get_max_ramdac(struct mach64_softc *); 231 232 #if defined(__sparc__) || defined(__powerpc__) 233 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 234 #endif 235 236 static int mach64_calc_crtcregs(struct mach64_softc *, 237 struct mach64_crtcregs *, 238 struct videomode *); 239 static void mach64_set_crtcregs(struct mach64_softc *, 240 struct mach64_crtcregs *); 241 242 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 243 static void mach64_set_dsp(struct mach64_softc *); 244 static void mach64_set_pll(struct mach64_softc *, int); 245 static void mach64_reset_engine(struct mach64_softc *); 246 static void mach64_init_engine(struct mach64_softc *); 247 #if 0 248 static void mach64_adjust_frame(struct mach64_softc *, int, int); 249 #endif 250 static void mach64_init_lut(struct mach64_softc *); 251 252 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 253 static int mach64_set_screentype(struct mach64_softc *, 254 const struct wsscreen_descr *); 255 static int mach64_is_console(struct pci_attach_args *); 256 257 static void mach64_cursor(void *, int, int, int); 258 #if 0 259 static int mach64_mapchar(void *, int, u_int *); 260 #endif 261 static void mach64_putchar(void *, int, int, u_int, long); 262 static void mach64_copycols(void *, int, int, int, int); 263 static void mach64_erasecols(void *, int, int, int, long); 264 static void mach64_copyrows(void *, int, int, int); 265 static void mach64_eraserows(void *, int, int, long); 266 static int mach64_allocattr(void *, int, int, int, long *); 267 static void mach64_clearscreen(struct mach64_softc *); 268 269 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 270 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 271 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 272 uint8_t, uint8_t); 273 static void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, 274 int, int, int) ; 275 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 276 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 277 uint32_t, uint32_t); 278 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 279 #if 0 280 static void mach64_showpal(struct mach64_softc *); 281 #endif 282 283 static void set_address(struct rasops_info *, void *); 284 static void machfb_blank(struct mach64_softc *, int); 285 286 #if 0 287 static const struct wsdisplay_emulops mach64_emulops = { 288 mach64_cursor, 289 mach64_mapchar, 290 mach64_putchar, 291 mach64_copycols, 292 mach64_erasecols, 293 mach64_copyrows, 294 mach64_eraserows, 295 mach64_allocattr, 296 }; 297 #endif 298 299 static struct wsscreen_descr mach64_defaultscreen = { 300 "default", 301 80, 30, 302 NULL, 303 8, 16, 304 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 305 &default_mode 306 }, mach64_80x25_screen = { 307 "80x25", 80, 25, 308 NULL, 309 8, 16, 310 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 311 &mach64_modes[0] 312 }, mach64_80x30_screen = { 313 "80x30", 80, 30, 314 NULL, 315 8, 16, 316 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 317 &mach64_modes[1] 318 }, mach64_80x40_screen = { 319 "80x40", 80, 40, 320 NULL, 321 8, 10, 322 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 323 &mach64_modes[0] 324 }, mach64_80x50_screen = { 325 "80x50", 80, 50, 326 NULL, 327 8, 8, 328 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 329 &mach64_modes[0] 330 }, mach64_100x37_screen = { 331 "100x37", 100, 37, 332 NULL, 333 8, 16, 334 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 335 &mach64_modes[2] 336 }, mach64_128x48_screen = { 337 "128x48", 128, 48, 338 NULL, 339 8, 16, 340 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 341 &mach64_modes[3] 342 }, mach64_144x54_screen = { 343 "144x54", 144, 54, 344 NULL, 345 8, 16, 346 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 347 &mach64_modes[4] 348 }, mach64_160x64_screen = { 349 "160x54", 160, 64, 350 NULL, 351 8, 16, 352 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 353 &mach64_modes[5] 354 }; 355 356 static const struct wsscreen_descr *_mach64_scrlist[] = { 357 &mach64_defaultscreen, 358 &mach64_80x25_screen, 359 &mach64_80x30_screen, 360 &mach64_80x40_screen, 361 &mach64_80x50_screen, 362 &mach64_100x37_screen, 363 &mach64_128x48_screen, 364 &mach64_144x54_screen, 365 &mach64_160x64_screen 366 }; 367 368 static struct wsscreen_list mach64_screenlist = { 369 __arraycount(_mach64_scrlist), 370 _mach64_scrlist 371 }; 372 373 static int mach64_ioctl(void *, void *, u_long, void *, int, 374 struct lwp *); 375 static paddr_t mach64_mmap(void *, void *, off_t, int); 376 377 #if 0 378 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 379 #endif 380 381 static struct wsdisplay_accessops mach64_accessops = { 382 mach64_ioctl, 383 mach64_mmap, 384 NULL, /* vcons_alloc_screen */ 385 NULL, /* vcons_free_screen */ 386 NULL, /* vcons_show_screen */ 387 NULL, /* load_font */ 388 NULL, /* polls */ 389 NULL, /* scroll */ 390 }; 391 392 static struct vcons_screen mach64_console_screen; 393 394 /* framebuffer device, SPARC-only so far */ 395 #ifdef __sparc__ 396 397 static void machfb_unblank(device_t); 398 static void machfb_fbattach(struct mach64_softc *); 399 400 extern struct cfdriver machfb_cd; 401 402 dev_type_open(machfb_fbopen); 403 dev_type_close(machfb_fbclose); 404 dev_type_ioctl(machfb_fbioctl); 405 dev_type_mmap(machfb_fbmmap); 406 407 /* frame buffer generic driver */ 408 static struct fbdriver machfb_fbdriver = { 409 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 410 machfb_fbmmap, nokqfilter 411 }; 412 413 #endif /* __sparc__ */ 414 415 /* 416 * Inline functions for getting access to register aperture. 417 */ 418 419 static inline uint32_t 420 regr(struct mach64_softc *sc, uint32_t index) 421 { 422 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 423 } 424 425 static inline uint8_t 426 regrb(struct mach64_softc *sc, uint32_t index) 427 { 428 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 429 } 430 431 static inline void 432 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 433 { 434 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 435 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 436 BUS_SPACE_BARRIER_WRITE); 437 } 438 439 static inline void 440 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 441 { 442 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 443 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 444 BUS_SPACE_BARRIER_WRITE); 445 } 446 447 static inline void 448 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 449 { 450 regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); 451 regwb(sc, CLOCK_CNTL + 2, data); 452 regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); 453 } 454 455 static inline void 456 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 457 { 458 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 459 continue; 460 } 461 462 static inline void 463 wait_for_idle(struct mach64_softc *sc) 464 { 465 wait_for_fifo(sc, 16); 466 while ((regr(sc, GUI_STAT) & 1) != 0) 467 continue; 468 } 469 470 static int 471 mach64_match(device_t parent, cfdata_t match, void *aux) 472 { 473 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 474 int i; 475 476 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 477 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 478 return 0; 479 480 for (i = 0; i < __arraycount(mach64_info); i++) 481 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 482 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 483 mach64_chip_rev = PCI_REVISION(pa->pa_class); 484 return 100; 485 } 486 487 return 0; 488 } 489 490 static void 491 mach64_attach(device_t parent, device_t self, void *aux) 492 { 493 struct mach64_softc *sc = device_private(self); 494 struct pci_attach_args *pa = aux; 495 struct rasops_info *ri; 496 char devinfo[256]; 497 int bar, reg, id; 498 struct wsemuldisplaydev_attach_args aa; 499 long defattr; 500 int setmode; 501 pcireg_t screg; 502 503 sc->sc_pc = pa->pa_pc; 504 sc->sc_pcitag = pa->pa_tag; 505 sc->sc_dacw = -1; 506 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 507 sc->sc_nbus = pa->pa_bus; 508 sc->sc_ndev = pa->pa_device; 509 sc->sc_nfunc = pa->pa_function; 510 sc->sc_locked = 0; 511 512 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 513 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 514 515 /* enable memory and IO access */ 516 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 517 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 518 pci_conf_write(sc->sc_pc, sc->sc_pcitag,PCI_COMMAND_STATUS_REG,screg); 519 520 for (bar = 0; bar < NBARS; bar++) { 521 reg = PCI_MAPREG_START + (bar * 4); 522 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 523 sc->sc_pcitag, reg); 524 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 525 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 526 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 527 sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc, 528 sc->sc_pcitag, reg)&0xfffffff0; 529 } 530 sc->sc_memt = pa->pa_memt; 531 532 mach64_init(sc); 533 534 printf("%s: %d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 535 device_xname(&sc->sc_dev), (u_int)(sc->sc_apersize / (1024 * 1024)), 536 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 537 (u_int)sc->sc_regphys); 538 539 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 540 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 541 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 542 (mach64_chip_rev & 0x07) == 0)) 543 sc->has_dsp = 0; 544 else 545 sc->has_dsp = 1; 546 547 sc->memsize = mach64_get_memsize(sc); 548 if (sc->memsize == 8192) 549 /* The last page is used as register aperture. */ 550 sc->memsize -= 4; 551 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 552 553 /* XXX is there any way to calculate reference frequency from 554 known values? */ 555 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 556 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 557 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 558 printf("%s: ref_freq=29.498MHz\n", device_xname(&sc->sc_dev)); 559 sc->ref_freq = 29498; 560 } else 561 sc->ref_freq = 14318; 562 563 regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); 564 sc->ref_div = regrb(sc, CLOCK_CNTL + 2); 565 regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); 566 sc->mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); 567 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 568 (sc->ref_div * 2); 569 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 570 (sc->mem_freq * sc->ref_div); 571 sc->ramdac_freq = mach64_get_max_ramdac(sc); 572 printf("%s: %ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 573 device_xname(&sc->sc_dev), (u_long)sc->memsize, 574 mach64_memtype_names[sc->memtype], 575 sc->mem_freq / 1000, sc->mem_freq % 1000, 576 sc->ramdac_freq / 1000); 577 578 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 579 if (id != mach64_chip_id) { 580 printf("%s: chip ID mismatch, 0x%x != 0x%x\n", 581 device_xname(&sc->sc_dev), id, mach64_chip_id); 582 return; 583 } 584 585 sc->sc_console = mach64_is_console(pa); 586 #ifdef DIAGNOSTIC 587 printf("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 588 #endif 589 #if defined(__sparc__) || defined(__powerpc__) 590 if (sc->sc_console) { 591 mach64_get_mode(sc, &default_mode); 592 setmode = 0; 593 sc->sc_my_mode = &default_mode; 594 } else { 595 /* fill in default_mode if it's empty */ 596 mach64_get_mode(sc, &default_mode); 597 if (default_mode.dot_clock == 0) { 598 memcpy(&default_mode, &mach64_modes[4], 599 sizeof(default_mode)); 600 } 601 sc->sc_my_mode = &default_mode; 602 setmode = 1; 603 } 604 #else 605 if (default_mode.dot_clock == 0) { 606 memcpy(&default_mode, &mach64_modes[0], 607 sizeof(default_mode)); 608 } 609 sc->sc_my_mode = &mach64_modes[0]; 610 setmode = 1; 611 #endif 612 613 sc->bits_per_pixel = 8; 614 sc->virt_x = sc->sc_my_mode->hdisplay; 615 sc->virt_y = sc->sc_my_mode->vdisplay; 616 sc->max_x = sc->virt_x - 1; 617 sc->max_y = (sc->memsize * 1024) / 618 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 619 620 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 621 622 mach64_init_engine(sc); 623 #if 0 624 mach64_adjust_frame(0, 0); 625 if (sc->bits_per_pixel == 8) 626 mach64_init_lut(sc); 627 #endif 628 629 printf("%s: initial resolution %dx%d at %d bpp\n", device_xname(&sc->sc_dev), 630 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 631 sc->bits_per_pixel); 632 633 #ifdef __sparc__ 634 machfb_fbattach(sc); 635 #endif 636 637 wsfont_init(); 638 639 sc->sc_bg = WS_DEFAULT_BG; 640 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &mach64_accessops); 641 sc->vd.init_screen = mach64_init_screen; 642 643 if (sc->sc_console) { 644 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 645 &defattr); 646 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 647 648 ri = &mach64_console_screen.scr_ri; 649 mach64_defaultscreen.textops = &ri->ri_ops; 650 mach64_defaultscreen.capabilities = ri->ri_caps; 651 mach64_defaultscreen.nrows = ri->ri_rows; 652 mach64_defaultscreen.ncols = ri->ri_cols; 653 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 654 } else { 655 /* 656 * since we're not the console we can postpone the rest 657 * until someone actually allocates a screen for us 658 */ 659 mach64_modeswitch(sc, sc->sc_my_mode); 660 } 661 662 mach64_init_lut(sc); 663 mach64_clearscreen(sc); 664 machfb_blank(sc, 0); /* unblank the screen */ 665 666 aa.console = sc->sc_console; 667 aa.scrdata = &mach64_screenlist; 668 aa.accessops = &mach64_accessops; 669 aa.accesscookie = &sc->vd; 670 671 config_found(self, &aa, wsemuldisplaydevprint); 672 } 673 674 static void 675 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 676 long *defattr) 677 { 678 struct mach64_softc *sc = cookie; 679 struct rasops_info *ri = &scr->scr_ri; 680 681 /* XXX for now */ 682 #define setmode 0 683 684 ri->ri_depth = sc->bits_per_pixel; 685 ri->ri_width = sc->sc_my_mode->hdisplay; 686 ri->ri_height = sc->sc_my_mode->vdisplay; 687 ri->ri_stride = ri->ri_width; 688 ri->ri_flg = RI_CENTER; 689 set_address(ri, sc->sc_aperture); 690 691 if (existing) { 692 ri->ri_flg |= RI_CLEAR; 693 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 694 panic("%s: failed to switch video mode", 695 device_xname(&sc->sc_dev)); 696 } 697 } 698 699 rasops_init(ri, sc->sc_my_mode->vdisplay/8, 700 sc->sc_my_mode->hdisplay/8); 701 ri->ri_caps = WSSCREEN_WSCOLORS; 702 703 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 704 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 705 706 /* enable acceleration */ 707 ri->ri_hw = scr; 708 ri->ri_ops.copyrows = mach64_copyrows; 709 ri->ri_ops.copycols = mach64_copycols; 710 ri->ri_ops.eraserows = mach64_eraserows; 711 ri->ri_ops.erasecols = mach64_erasecols; 712 ri->ri_ops.cursor = mach64_cursor; 713 ri->ri_ops.putchar = mach64_putchar; 714 ri->ri_ops.allocattr = mach64_allocattr; 715 } 716 717 static void 718 mach64_init(struct mach64_softc *sc) 719 { 720 uint32_t *p32, saved_value; 721 uint8_t *p; 722 int need_swap; 723 724 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 725 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 726 panic("%s: failed to map aperture", device_xname(&sc->sc_dev)); 727 } 728 sc->sc_aperture = (void *)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 729 730 sc->sc_regt = sc->sc_memt; 731 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 732 sc->sc_regsize, &sc->sc_regh); 733 sc->sc_registers = (char *)sc->sc_aperture + 0x7ffc00; 734 735 /* 736 * Test wether the aperture is byte swapped or not 737 */ 738 p32 = (uint32_t*)sc->sc_aperture; 739 saved_value = *p32; 740 p = (uint8_t*)(u_long)sc->sc_aperture; 741 *p32 = 0x12345678; 742 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 743 need_swap = 0; 744 else 745 need_swap = 1; 746 if (need_swap) { 747 sc->sc_aperture = (char *)sc->sc_aperture + 0x800000; 748 sc->sc_aperbase += 0x800000; 749 sc->sc_apersize -= 0x800000; 750 } 751 *p32 = saved_value; 752 753 sc->sc_blanked = 0; 754 } 755 756 static int 757 mach64_get_memsize(struct mach64_softc *sc) 758 { 759 int tmp, memsize; 760 int mem_tab[] = { 761 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 762 }; 763 tmp = regr(sc, MEM_CNTL); 764 #ifdef DIAGNOSTIC 765 printf("%s: memctl %08x\n", device_xname(&sc->sc_dev), tmp); 766 #endif 767 if (sc->has_dsp) { 768 tmp &= 0x0000000f; 769 if (tmp < 8) 770 memsize = (tmp + 1) * 512; 771 else if (tmp < 12) 772 memsize = (tmp - 3) * 1024; 773 else 774 memsize = (tmp - 7) * 2048; 775 } else { 776 memsize = mem_tab[tmp & 0x07]; 777 } 778 779 return memsize; 780 } 781 782 static int 783 mach64_get_max_ramdac(struct mach64_softc *sc) 784 { 785 int i; 786 787 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 788 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 789 (mach64_chip_rev & 0x07)) 790 return 170000; 791 792 for (i = 0; i < __arraycount(mach64_info); i++) 793 if (mach64_chip_id == mach64_info[i].chip_id) 794 return mach64_info[i].ramdac_freq; 795 796 if (sc->bits_per_pixel == 8) 797 return 135000; 798 else 799 return 80000; 800 } 801 802 #if defined(__sparc__) || defined(__powerpc__) 803 static void 804 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 805 { 806 struct mach64_crtcregs crtc; 807 808 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 809 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 810 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 811 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 812 813 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 814 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 815 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 816 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 817 mode->hsync_start; 818 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 819 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 820 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 821 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 822 823 #ifndef DEBUG_MACHFB 824 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 825 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 826 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 827 #endif 828 } 829 #endif 830 831 static int 832 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 833 struct videomode *mode) 834 { 835 836 if (mode->dot_clock > sc->ramdac_freq) 837 /* Clock too high. */ 838 return 1; 839 840 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 841 ((mode->htotal >> 3) - 1); 842 crtc->h_sync_strt_wid = 843 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 844 ((mode->hsync_start >> 3) - 1); 845 846 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 847 (mode->vtotal - 1); 848 crtc->v_sync_strt_wid = 849 ((mode->vsync_end - mode->vsync_start) << 16) | 850 (mode->vsync_start - 1); 851 852 if (mode->flags & VID_NVSYNC) 853 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 854 855 switch (sc->bits_per_pixel) { 856 case 8: 857 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 858 break; 859 case 16: 860 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 861 break; 862 case 32: 863 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 864 break; 865 } 866 867 crtc->gen_cntl = 0; 868 if (mode->flags & VID_INTERLACE) 869 crtc->gen_cntl |= CRTC_INTERLACE_EN; 870 871 if (mode->flags & VID_CSYNC) 872 crtc->gen_cntl |= CRTC_CSYNC_EN; 873 874 crtc->dot_clock = mode->dot_clock; 875 876 return 0; 877 } 878 879 static void 880 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 881 { 882 883 mach64_set_pll(sc, crtc->dot_clock); 884 885 if (sc->has_dsp) 886 mach64_set_dsp(sc); 887 888 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 889 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 890 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 891 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 892 893 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 894 895 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 896 897 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 898 /* XXX this unconditionally enables composite sync on SPARC */ 899 #ifdef __sparc__ 900 CRTC_CSYNC_EN | 901 #endif 902 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 903 } 904 905 static int 906 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 907 { 908 struct mach64_crtcregs crtc; 909 910 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 911 912 if (mach64_calc_crtcregs(sc, &crtc, mode)) 913 return 1; 914 915 mach64_set_crtcregs(sc, &crtc); 916 return 0; 917 } 918 919 static void 920 mach64_reset_engine(struct mach64_softc *sc) 921 { 922 923 /* Reset engine.*/ 924 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 925 926 /* Enable engine. */ 927 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 928 929 /* Ensure engine is not locked up by clearing any FIFO or 930 host errors. */ 931 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 932 BUS_FIFO_ERR_ACK); 933 } 934 935 static void 936 mach64_init_engine(struct mach64_softc *sc) 937 { 938 uint32_t pitch_value; 939 940 pitch_value = sc->virt_x; 941 942 if (sc->bits_per_pixel == 24) 943 pitch_value *= 3; 944 945 mach64_reset_engine(sc); 946 947 wait_for_fifo(sc, 14); 948 949 regw(sc, CONTEXT_MASK, 0xffffffff); 950 951 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 952 953 regw(sc, DST_Y_X, 0); 954 regw(sc, DST_HEIGHT, 0); 955 regw(sc, DST_BRES_ERR, 0); 956 regw(sc, DST_BRES_INC, 0); 957 regw(sc, DST_BRES_DEC, 0); 958 959 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 960 DST_Y_TOP_TO_BOTTOM); 961 962 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 963 964 regw(sc, SRC_Y_X, 0); 965 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 966 regw(sc, SRC_Y_X_START, 0); 967 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 968 969 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 970 971 wait_for_fifo(sc, 13); 972 regw(sc, HOST_CNTL, 0); 973 974 regw(sc, PAT_REG0, 0); 975 regw(sc, PAT_REG1, 0); 976 regw(sc, PAT_CNTL, 0); 977 978 regw(sc, SC_LEFT, 0); 979 regw(sc, SC_TOP, 0); 980 regw(sc, SC_BOTTOM, sc->sc_my_mode->vdisplay - 1); 981 regw(sc, SC_RIGHT, pitch_value - 1); 982 983 regw(sc, DP_BKGD_CLR, 0); 984 regw(sc, DP_FRGD_CLR, 0xffffffff); 985 regw(sc, DP_WRITE_MASK, 0xffffffff); 986 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 987 988 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 989 990 wait_for_fifo(sc, 3); 991 regw(sc, CLR_CMP_CLR, 0); 992 regw(sc, CLR_CMP_MASK, 0xffffffff); 993 regw(sc, CLR_CMP_CNTL, 0); 994 995 wait_for_fifo(sc, 2); 996 switch (sc->bits_per_pixel) { 997 case 8: 998 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 999 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1000 /* We want 8 bit per channel */ 1001 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1002 break; 1003 #if 0 1004 case 32: 1005 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 1006 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1007 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1008 break; 1009 #endif 1010 } 1011 1012 wait_for_fifo(sc, 5); 1013 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1014 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1015 1016 wait_for_idle(sc); 1017 } 1018 1019 #if 0 1020 static void 1021 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1022 { 1023 int offset; 1024 1025 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1026 1027 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1028 offset); 1029 } 1030 #endif 1031 1032 static void 1033 mach64_set_dsp(struct mach64_softc *sc) 1034 { 1035 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1036 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1037 uint32_t xclks_per_qw, y; 1038 uint32_t fifo_off, fifo_on; 1039 1040 printf("%s: initializing the DSP\n", device_xname(&sc->sc_dev)); 1041 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1042 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1043 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1044 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1045 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1046 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1047 dsp_loop_latency = 0; 1048 fifo_depth = 24; 1049 } else { 1050 dsp_loop_latency = 2; 1051 fifo_depth = 32; 1052 } 1053 1054 dsp_precision = 0; 1055 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1056 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1057 y = (xclks_per_qw * fifo_depth) >> 11; 1058 while (y) { 1059 y >>= 1; 1060 dsp_precision++; 1061 } 1062 dsp_precision -= 5; 1063 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1064 1065 switch (sc->memtype) { 1066 case DRAM: 1067 case EDO_DRAM: 1068 case PSEUDO_EDO: 1069 if (sc->memsize > 1024) { 1070 page_size = 9; 1071 dsp_loop_latency += 6; 1072 } else { 1073 page_size = 10; 1074 if (sc->memtype == DRAM) 1075 dsp_loop_latency += 8; 1076 else 1077 dsp_loop_latency += 7; 1078 } 1079 break; 1080 case SDRAM: 1081 case SGRAM: 1082 if (sc->memsize > 1024) { 1083 page_size = 8; 1084 dsp_loop_latency += 8; 1085 } else { 1086 page_size = 10; 1087 dsp_loop_latency += 9; 1088 } 1089 break; 1090 default: 1091 page_size = 10; 1092 dsp_loop_latency += 9; 1093 break; 1094 } 1095 1096 if (xclks_per_qw >= (page_size << 11)) 1097 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1098 else 1099 fifo_on = (3 * page_size + 2) << 6; 1100 1101 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1102 dsp_on = fifo_on >> dsp_precision; 1103 dsp_off = fifo_off >> dsp_precision; 1104 1105 #ifdef DEBUG_MACHFB 1106 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1107 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1108 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1109 "mclk_post_div = %d, vclk_post_div = %d\n", 1110 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1111 sc->mclk_fb_div, sc->vclk_fb_div, 1112 sc->mclk_post_div, sc->vclk_post_div); 1113 #endif 1114 1115 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1116 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1117 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1118 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1119 } 1120 1121 static void 1122 mach64_set_pll(struct mach64_softc *sc, int clock) 1123 { 1124 int q; 1125 1126 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1127 #ifdef DEBUG_MACHFB 1128 printf("q = %d\n", q); 1129 #endif 1130 if (q > 25500) { 1131 printf("Warning: q > 25500\n"); 1132 q = 25500; 1133 sc->vclk_post_div = 1; 1134 sc->log2_vclk_post_div = 0; 1135 } else if (q > 12750) { 1136 sc->vclk_post_div = 1; 1137 sc->log2_vclk_post_div = 0; 1138 } else if (q > 6350) { 1139 sc->vclk_post_div = 2; 1140 sc->log2_vclk_post_div = 1; 1141 } else if (q > 3150) { 1142 sc->vclk_post_div = 4; 1143 sc->log2_vclk_post_div = 2; 1144 } else if (q >= 1600) { 1145 sc->vclk_post_div = 8; 1146 sc->log2_vclk_post_div = 3; 1147 } else { 1148 printf("Warning: q < 1600\n"); 1149 sc->vclk_post_div = 8; 1150 sc->log2_vclk_post_div = 3; 1151 } 1152 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1153 1154 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1155 regwb_pll(sc, VCLK_POST_DIV, sc->log2_vclk_post_div); 1156 regwb_pll(sc, VCLK0_FB_DIV, sc->vclk_fb_div); 1157 } 1158 1159 static void 1160 mach64_init_lut(struct mach64_softc *sc) 1161 { 1162 int i, idx; 1163 1164 idx = 0; 1165 for (i = 0; i < 256; i++) { 1166 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1], 1167 rasops_cmap[idx + 2]); 1168 idx += 3; 1169 } 1170 } 1171 1172 static int 1173 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1174 uint8_t b) 1175 { 1176 sc->sc_cmap_red[index] = r; 1177 sc->sc_cmap_green[index] = g; 1178 sc->sc_cmap_blue[index] = b; 1179 /* 1180 * writing the dac index takes a while, in theory we can poll some 1181 * register to see when it's ready - but we better avoid writing it 1182 * unnecessarily 1183 */ 1184 if (index != sc->sc_dacw) { 1185 regwb(sc, DAC_MASK, 0xff); 1186 regwb(sc, DAC_WINDEX, index); 1187 } 1188 sc->sc_dacw = index + 1; 1189 regwb(sc, DAC_DATA, r); 1190 regwb(sc, DAC_DATA, g); 1191 regwb(sc, DAC_DATA, b); 1192 return 0; 1193 } 1194 1195 static int 1196 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1197 { 1198 uint index = cm->index; 1199 uint count = cm->count; 1200 int i, error; 1201 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1202 uint8_t *r, *g, *b; 1203 1204 if (cm->index >= 256 || cm->count > 256 || 1205 (cm->index + cm->count) > 256) 1206 return EINVAL; 1207 error = copyin(cm->red, &rbuf[index], count); 1208 if (error) 1209 return error; 1210 error = copyin(cm->green, &gbuf[index], count); 1211 if (error) 1212 return error; 1213 error = copyin(cm->blue, &bbuf[index], count); 1214 if (error) 1215 return error; 1216 1217 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1218 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1219 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1220 1221 r = &sc->sc_cmap_red[index]; 1222 g = &sc->sc_cmap_green[index]; 1223 b = &sc->sc_cmap_blue[index]; 1224 1225 for (i = 0; i < count; i++) { 1226 mach64_putpalreg(sc, index, *r, *g, *b); 1227 index++; 1228 r++, g++, b++; 1229 } 1230 return 0; 1231 } 1232 1233 static int 1234 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1235 { 1236 u_int index = cm->index; 1237 u_int count = cm->count; 1238 int error; 1239 1240 if (index >= 255 || count > 256 || index + count > 256) 1241 return EINVAL; 1242 1243 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1244 if (error) 1245 return error; 1246 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1247 if (error) 1248 return error; 1249 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1250 if (error) 1251 return error; 1252 1253 return 0; 1254 } 1255 1256 static int 1257 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1258 { 1259 struct mach64_crtcregs regs; 1260 1261 if (mach64_calc_crtcregs(sc, ®s, 1262 (struct videomode *)des->modecookie)) 1263 return 1; 1264 1265 mach64_set_crtcregs(sc, ®s); 1266 return 0; 1267 } 1268 1269 static int 1270 mach64_is_console(struct pci_attach_args *pa) 1271 { 1272 #ifdef __sparc__ 1273 int node; 1274 1275 node = PCITAG_NODE(pa->pa_tag); 1276 if (node == -1) 1277 return 0; 1278 1279 return (node == prom_instance_to_package(prom_stdout())); 1280 #elif defined(__powerpc__) 1281 /* check if we're the /chosen console device */ 1282 int chosen, stdout, node, us; 1283 1284 us = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 1285 chosen = OF_finddevice("/chosen"); 1286 OF_getprop(chosen, "stdout", &stdout, 4); 1287 node = OF_instance_to_package(stdout); 1288 return (us == node); 1289 #else 1290 return 1; 1291 #endif 1292 } 1293 1294 /* 1295 * wsdisplay_emulops 1296 */ 1297 1298 static void 1299 mach64_cursor(void *cookie, int on, int row, int col) 1300 { 1301 struct rasops_info *ri = cookie; 1302 struct vcons_screen *scr = ri->ri_hw; 1303 struct mach64_softc *sc = scr->scr_cookie; 1304 int x, y, wi, he; 1305 1306 wi = ri->ri_font->fontwidth; 1307 he = ri->ri_font->fontheight; 1308 1309 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1310 x = ri->ri_ccol * wi + ri->ri_xorigin; 1311 y = ri->ri_crow * he + ri->ri_yorigin; 1312 if (ri->ri_flg & RI_CURSOR) { 1313 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1314 0xff); 1315 ri->ri_flg &= ~RI_CURSOR; 1316 } 1317 ri->ri_crow = row; 1318 ri->ri_ccol = col; 1319 if (on) { 1320 x = ri->ri_ccol * wi + ri->ri_xorigin; 1321 y = ri->ri_crow * he + ri->ri_yorigin; 1322 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1323 0xff); 1324 ri->ri_flg |= RI_CURSOR;; 1325 } 1326 } else { 1327 scr->scr_ri.ri_crow = row; 1328 scr->scr_ri.ri_ccol = col; 1329 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1330 } 1331 } 1332 1333 #if 0 1334 static int 1335 mach64_mapchar(void *cookie, int uni, u_int *index) 1336 { 1337 return 0; 1338 } 1339 #endif 1340 1341 static void 1342 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1343 { 1344 struct rasops_info *ri = cookie; 1345 struct vcons_screen *scr = ri->ri_hw; 1346 struct mach64_softc *sc = scr->scr_cookie; 1347 1348 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1349 int fg, bg, uc; 1350 uint8_t *data; 1351 int x, y, wi, he; 1352 wi = ri->ri_font->fontwidth; 1353 he = ri->ri_font->fontheight; 1354 1355 if (!CHAR_IN_FONT(c, ri->ri_font)) 1356 return; 1357 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0xf]; 1358 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0xf]; 1359 x = ri->ri_xorigin + col * wi; 1360 y = ri->ri_yorigin + row * he; 1361 if (c == 0x20) { 1362 mach64_rectfill(sc, x, y, wi, he, bg); 1363 } else { 1364 uc = c-ri->ri_font->firstchar; 1365 data = (uint8_t *)ri->ri_font->data + uc * 1366 ri->ri_fontscale; 1367 1368 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1369 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1370 } 1371 } 1372 } 1373 1374 1375 static void 1376 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1377 { 1378 struct rasops_info *ri = cookie; 1379 struct vcons_screen *scr = ri->ri_hw; 1380 struct mach64_softc *sc = scr->scr_cookie; 1381 int32_t xs, xd, y, width, height; 1382 1383 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1384 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1385 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1386 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1387 width = ri->ri_font->fontwidth * ncols; 1388 height = ri->ri_font->fontheight; 1389 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff); 1390 } 1391 } 1392 1393 static void 1394 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1395 { 1396 struct rasops_info *ri = cookie; 1397 struct vcons_screen *scr = ri->ri_hw; 1398 struct mach64_softc *sc = scr->scr_cookie; 1399 int32_t x, y, width, height, fg, bg, ul; 1400 1401 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1402 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1403 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1404 width = ri->ri_font->fontwidth * ncols; 1405 height = ri->ri_font->fontheight; 1406 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1407 1408 mach64_rectfill(sc, x, y, width, height, bg); 1409 } 1410 } 1411 1412 static void 1413 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1414 { 1415 struct rasops_info *ri = cookie; 1416 struct vcons_screen *scr = ri->ri_hw; 1417 struct mach64_softc *sc = scr->scr_cookie; 1418 int32_t x, ys, yd, width, height; 1419 1420 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1421 x = ri->ri_xorigin; 1422 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1423 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1424 width = ri->ri_emuwidth; 1425 height = ri->ri_font->fontheight*nrows; 1426 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff); 1427 } 1428 } 1429 1430 static void 1431 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1432 { 1433 struct rasops_info *ri = cookie; 1434 struct vcons_screen *scr = ri->ri_hw; 1435 struct mach64_softc *sc = scr->scr_cookie; 1436 int32_t x, y, width, height, fg, bg, ul; 1437 1438 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1439 x = ri->ri_xorigin; 1440 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1441 width = ri->ri_emuwidth; 1442 height = ri->ri_font->fontheight * nrows; 1443 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1444 1445 mach64_rectfill(sc, x, y, width, height, bg); 1446 } 1447 } 1448 1449 static void 1450 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1451 { 1452 uint32_t dest_ctl = 0; 1453 1454 wait_for_idle(sc); 1455 regw(sc, DP_WRITE_MASK, mask); /* XXX only good for 8 bit */ 1456 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1457 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1458 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1459 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1460 if (yd < ys) { 1461 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1462 } else { 1463 ys += height - 1; 1464 yd += height - 1; 1465 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1466 } 1467 if (xd < xs) { 1468 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1469 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1470 } else { 1471 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1472 xs += width - 1; 1473 xd += width - 1; 1474 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1475 } 1476 regw(sc, DST_CNTL, dest_ctl); 1477 1478 regw(sc, SRC_Y_X, (xs << 16) | ys); 1479 regw(sc, SRC_WIDTH1, width); 1480 regw(sc, DST_Y_X, (xd << 16) | yd); 1481 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1482 } 1483 1484 static void 1485 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1486 int height, uint32_t fg, uint32_t bg) 1487 { 1488 wait_for_idle(sc); 1489 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1490 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1491 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1492 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1493 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1494 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1495 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1496 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1497 regw(sc, DP_BKGD_CLR, bg); 1498 regw(sc, DP_FRGD_CLR, fg); 1499 regw(sc, SRC_Y_X, 0); 1500 regw(sc, SRC_WIDTH1, width); 1501 regw(sc, DST_Y_X, (xd << 16) | yd); 1502 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1503 /* now feed the data into the chip */ 1504 } 1505 1506 static void 1507 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1508 { 1509 int i; 1510 uint32_t latch = 0, bork; 1511 int shift = 0; 1512 int reg = 0; 1513 1514 for (i=0;i<count;i++) { 1515 bork = data[i]; 1516 latch |= (bork << shift); 1517 if (shift == 24) { 1518 regw(sc, HOST_DATA0 + reg, latch); 1519 latch = 0; 1520 shift = 0; 1521 reg = (reg + 4) & 0x3c; 1522 } else 1523 shift += 8; 1524 } 1525 if (shift != 0) /* 24 */ 1526 regw(sc, HOST_DATA0 + reg, latch); 1527 } 1528 1529 1530 static void 1531 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1532 int colour) 1533 { 1534 wait_for_idle(sc); 1535 regw(sc, DP_WRITE_MASK, 0xff); 1536 regw(sc, DP_FRGD_CLR, colour); 1537 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1538 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1539 regw(sc, DP_MIX, MIX_SRC << 16); 1540 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1541 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1542 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1543 1544 regw(sc, SRC_Y_X, (x << 16) | y); 1545 regw(sc, SRC_WIDTH1, width); 1546 regw(sc, DST_Y_X, (x << 16) | y); 1547 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1548 } 1549 1550 static void 1551 mach64_clearscreen(struct mach64_softc *sc) 1552 { 1553 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1554 } 1555 1556 1557 #if 0 1558 static void 1559 mach64_showpal(struct mach64_softc *sc) 1560 { 1561 int i, x = 0; 1562 1563 for (i = 0; i < 16; i++) { 1564 mach64_rectfill(sc, x, 0, 64, 64, i); 1565 x += 64; 1566 } 1567 } 1568 #endif 1569 1570 static int 1571 mach64_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1572 { 1573 if ((fg == 0) && (bg == 0)) 1574 { 1575 fg = WS_DEFAULT_FG; 1576 bg = WS_DEFAULT_BG; 1577 } 1578 *attrp = (fg & 0xf) << 24 | (bg & 0xf) << 16 | (flags & 0xff) << 8; 1579 return 0; 1580 } 1581 1582 /* 1583 * wsdisplay_accessops 1584 */ 1585 1586 static int 1587 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1588 struct lwp *l) 1589 { 1590 struct vcons_data *vd = v; 1591 struct mach64_softc *sc = vd->cookie; 1592 struct wsdisplay_fbinfo *wdf; 1593 struct vcons_screen *ms = vd->active; 1594 1595 switch (cmd) { 1596 case WSDISPLAYIO_GTYPE: 1597 /* XXX is this the right type to return? */ 1598 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1599 return 0; 1600 1601 case WSDISPLAYIO_LINEBYTES: 1602 *(u_int *)data = sc->virt_x * sc->bits_per_pixel / 8; 1603 return 0; 1604 1605 case WSDISPLAYIO_GINFO: 1606 wdf = (void *)data; 1607 wdf->height = sc->virt_y; 1608 wdf->width = sc->virt_x; 1609 wdf->depth = sc->bits_per_pixel; 1610 wdf->cmsize = 256; 1611 return 0; 1612 1613 case WSDISPLAYIO_GETCMAP: 1614 return mach64_getcmap(sc, 1615 (struct wsdisplay_cmap *)data); 1616 1617 case WSDISPLAYIO_PUTCMAP: 1618 return mach64_putcmap(sc, 1619 (struct wsdisplay_cmap *)data); 1620 1621 /* PCI config read/write passthrough. */ 1622 case PCI_IOC_CFGREAD: 1623 case PCI_IOC_CFGWRITE: 1624 return (pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1625 cmd, data, flag, l)); 1626 1627 case WSDISPLAYIO_SMODE: 1628 { 1629 int new_mode = *(int*)data; 1630 1631 if (new_mode != sc->sc_mode) 1632 { 1633 sc->sc_mode = new_mode; 1634 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1635 && (ms != NULL)) 1636 { 1637 vcons_redraw_screen(ms); 1638 } 1639 } 1640 } 1641 return 0; 1642 1643 } 1644 return EPASSTHROUGH; 1645 } 1646 1647 static paddr_t 1648 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1649 { 1650 struct vcons_data *vd = v; 1651 struct mach64_softc *sc = vd->cookie; 1652 paddr_t pa; 1653 pcireg_t reg; 1654 1655 #ifndef __sparc64__ 1656 /* 1657 *'regular' framebuffer mmap()ing 1658 * disabled on sparc64 because some ATI firmware likes to map some PCI 1659 * resources to addresses that would collide with this ( like some Rage 1660 * IIc which uses 0x2000 for the 2nd register block ) 1661 * Other 64bit architectures might run into similar problems. 1662 */ 1663 if (offset<sc->sc_apersize) { 1664 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, offset, 1665 prot, BUS_SPACE_MAP_LINEAR); 1666 return pa; 1667 } 1668 #endif 1669 1670 /* 1671 * restrict all other mappings to processes with superuser privileges 1672 * or the kernel itself 1673 */ 1674 if (curlwp != NULL) { 1675 if (kauth_authorize_generic(kauth_cred_get(), 1676 KAUTH_GENERIC_ISSUSER, NULL) != 0) { 1677 printf("%s: mmap() rejected.\n", device_xname(&sc->sc_dev)); 1678 return -1; 1679 } 1680 } 1681 1682 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1683 if (reg != sc->sc_regphys) { 1684 #ifdef DIAGNOSTIC 1685 printf("%s: BAR 0x18 changed! (%x %x)\n", 1686 device_xname(&sc->sc_dev), (uint32_t)sc->sc_regphys, 1687 (uint32_t)reg); 1688 #endif 1689 sc->sc_regphys = reg; 1690 } 1691 1692 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1693 if (reg != sc->sc_aperphys) { 1694 #ifdef DIAGNOSTIC 1695 printf("%s: BAR 0x10 changed! (%x %x)\n", 1696 device_xname(&sc->sc_dev), (uint32_t)sc->sc_aperphys, 1697 (uint32_t)reg); 1698 #endif 1699 sc->sc_aperphys = reg; 1700 } 1701 1702 #if 0 1703 /* evil hack to allow mmap()ing other devices as well */ 1704 if ((offset > 0x80000000) && (offset <= 0xffffffff)) { 1705 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1706 BUS_SPACE_MAP_LINEAR); 1707 return pa; 1708 } 1709 #endif 1710 1711 if ((offset >= sc->sc_aperphys) && 1712 (offset < (sc->sc_aperphys + sc->sc_apersize))) { 1713 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1714 BUS_SPACE_MAP_LINEAR); 1715 return pa; 1716 } 1717 1718 if ((offset >= sc->sc_regphys) && 1719 (offset < (sc->sc_regphys + sc->sc_regsize))) { 1720 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1721 BUS_SPACE_MAP_LINEAR); 1722 return pa; 1723 } 1724 1725 return -1; 1726 } 1727 1728 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1729 static void 1730 set_address(struct rasops_info *ri, void *fb) 1731 { 1732 #ifdef notdef 1733 printf(" %d %d %d\n", ri->ri_xorigin, ri->ri_yorigin, ri->ri_stride); 1734 #endif 1735 ri->ri_bits = (void *)((char *)fb + ri->ri_stride * ri->ri_yorigin + 1736 ri->ri_xorigin); 1737 } 1738 1739 #if 0 1740 static int 1741 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1742 { 1743 1744 return 0; 1745 } 1746 #endif 1747 1748 void 1749 machfb_blank(struct mach64_softc *sc, int blank) 1750 { 1751 uint32_t reg; 1752 1753 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1754 1755 switch (blank) 1756 { 1757 case 0: 1758 reg = regr(sc, CRTC_GEN_CNTL); 1759 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1760 sc->sc_blanked = 0; 1761 break; 1762 case 1: 1763 reg = regr(sc, CRTC_GEN_CNTL); 1764 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1765 sc->sc_blanked = 1; 1766 break; 1767 default: 1768 break; 1769 } 1770 } 1771 1772 /* framebuffer device support */ 1773 #ifdef __sparc__ 1774 1775 static void 1776 machfb_unblank(device_t dev) 1777 { 1778 struct mach64_softc *sc = device_private(dev); 1779 1780 machfb_blank(sc, 0); 1781 } 1782 1783 static void 1784 machfb_fbattach(struct mach64_softc *sc) 1785 { 1786 struct fbdevice *fb = &sc->sc_fb; 1787 1788 fb->fb_device = &sc->sc_dev; 1789 fb->fb_driver = &machfb_fbdriver; 1790 1791 fb->fb_type.fb_cmsize = 256; 1792 fb->fb_type.fb_size = sc->memsize; 1793 1794 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 1795 fb->fb_flags = sc->sc_dev.dv_cfdata->cf_flags & FB_USERMASK; 1796 fb->fb_type.fb_depth = sc->bits_per_pixel; 1797 fb->fb_type.fb_width = sc->virt_x; 1798 fb->fb_type.fb_height = sc->virt_y; 1799 1800 fb->fb_pixels = sc->sc_aperture; 1801 fb_attach(fb, sc->sc_console); 1802 } 1803 1804 int 1805 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 1806 { 1807 struct mach64_softc *sc; 1808 1809 sc = device_lookup_private(&machfb_cd, minor(dev)); 1810 if (sc == NULL) 1811 return ENXIO; 1812 sc->sc_locked = 1; 1813 1814 #ifdef DEBUG_MACHFB 1815 printf("machfb_fbopen(%d)\n", minor(dev)); 1816 #endif 1817 return 0; 1818 } 1819 1820 int 1821 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 1822 { 1823 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1824 1825 #ifdef DEBUG_MACHFB 1826 printf("machfb_fbclose()\n"); 1827 #endif 1828 mach64_init_engine(sc); 1829 mach64_init_lut(sc); 1830 sc->sc_locked = 0; 1831 return 0; 1832 } 1833 1834 int 1835 machfb_fbioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1836 { 1837 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1838 1839 #ifdef DEBUG_MACHFB 1840 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 1841 #endif 1842 switch (cmd) { 1843 case FBIOGTYPE: 1844 *(struct fbtype *)data = sc->sc_fb.fb_type; 1845 break; 1846 1847 case FBIOGATTR: 1848 #define fba ((struct fbgattr *)data) 1849 fba->real_type = sc->sc_fb.fb_type.fb_type; 1850 fba->owner = 0; /* XXX ??? */ 1851 fba->fbtype = sc->sc_fb.fb_type; 1852 fba->sattr.flags = 0; 1853 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 1854 fba->sattr.dev_specific[0] = sc->sc_nbus; 1855 fba->sattr.dev_specific[1] = sc->sc_ndev; 1856 fba->sattr.dev_specific[2] = sc->sc_nfunc; 1857 fba->sattr.dev_specific[3] = -1; 1858 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 1859 fba->emu_types[1] = -1; 1860 #undef fba 1861 break; 1862 1863 #if 0 1864 case FBIOGETCMAP: 1865 #define p ((struct fbcmap *)data) 1866 return (bt_getcmap(p, &sc->sc_cmap, 256, 1)); 1867 1868 case FBIOPUTCMAP: 1869 /* copy to software map */ 1870 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 1871 if (error) 1872 return error; 1873 /* now blast them into the chip */ 1874 /* XXX should use retrace interrupt */ 1875 cg6_loadcmap(sc, p->index, p->count); 1876 #undef p 1877 break; 1878 #endif 1879 case FBIOGVIDEO: 1880 *(int *)data = sc->sc_blanked; 1881 break; 1882 1883 case FBIOSVIDEO: 1884 machfb_blank(sc, *(int *)data); 1885 break; 1886 1887 #if 0 1888 case FBIOGCURSOR: 1889 break; 1890 1891 case FBIOSCURSOR: 1892 break; 1893 1894 case FBIOGCURPOS: 1895 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 1896 break; 1897 1898 case FBIOSCURPOS: 1899 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 1900 break; 1901 1902 case FBIOGCURMAX: 1903 /* max cursor size is 32x32 */ 1904 ((struct fbcurpos *)data)->x = 32; 1905 ((struct fbcurpos *)data)->y = 32; 1906 break; 1907 #endif 1908 case PCI_IOC_CFGREAD: 1909 case PCI_IOC_CFGWRITE: 1910 { 1911 int ret; 1912 1913 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1914 cmd, data, flags, l); 1915 1916 #ifdef DEBUG_MACHFB 1917 printf("pci_devioctl: %d\n", ret); 1918 #endif 1919 return ret; 1920 } 1921 default: 1922 #ifdef DEBUG_MACHFB 1923 log(LOG_NOTICE, "machfb_fbioctl(0x%lx) (%s[%d])\n", cmd, 1924 p->p_comm, p->p_pid); 1925 #endif 1926 return ENOTTY; 1927 } 1928 #ifdef DEBUG_MACHFB 1929 printf("machfb_fbioctl done\n"); 1930 #endif 1931 return 0; 1932 } 1933 1934 paddr_t 1935 machfb_fbmmap(dev_t dev, off_t off, int prot) 1936 { 1937 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1938 1939 if (sc != NULL) 1940 return mach64_mmap(&sc->vd, NULL, off, prot); 1941 1942 return 0; 1943 } 1944 1945 #endif /* __sparc__ */ 1946
Indexes created Thu Oct 02 14:10:14 GMT 2025