machfb.c revision 1.57.2.1
1 /* $NetBSD: machfb.c,v 1.57.2.1 2010/04/30 14:43:39 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, 36 "$NetBSD: machfb.c,v 1.57.2.1 2010/04/30 14:43:39 uebayasi Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/callout.h> 44 #include <sys/kauth.h> 45 46 #ifdef __sparc__ 47 #include <machine/promlib.h> 48 #endif 49 50 #ifdef __powerpc__ 51 #include <dev/ofw/openfirm.h> 52 #include <dev/ofw/ofw_pci.h> 53 #endif 54 55 #include <dev/videomode/videomode.h> 56 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcidevs.h> 60 #include <dev/pci/pciio.h> 61 #include <dev/pci/machfbreg.h> 62 63 #ifdef __sparc__ 64 #include <dev/sun/fbio.h> 65 #include <dev/sun/fbvar.h> 66 #include <sys/conf.h> 67 #else 68 #include <dev/wscons/wsdisplayvar.h> 69 #endif 70 71 #include <dev/wscons/wsconsio.h> 72 #include <dev/wsfont/wsfont.h> 73 #include <dev/rasops/rasops.h> 74 75 #include <dev/wscons/wsdisplay_vconsvar.h> 76 77 #define MACH64_REG_SIZE 1024 78 #define MACH64_REG_OFF 0x7ffc00 79 80 #define NBARS 3 /* number of Mach64 PCI BARs */ 81 82 struct vga_bar { 83 bus_addr_t vb_base; 84 pcireg_t vb_busaddr; 85 bus_size_t vb_size; 86 pcireg_t vb_type; 87 int vb_flags; 88 }; 89 90 struct mach64_softc { 91 struct device sc_dev; 92 #ifdef __sparc__ 93 struct fbdevice sc_fb; 94 #endif 95 pci_chipset_tag_t sc_pc; 96 pcitag_t sc_pcitag; 97 98 struct vga_bar sc_bars[NBARS]; 99 struct vga_bar sc_rom; 100 101 #define sc_aperbase sc_bars[0].vb_base 102 #define sc_apersize sc_bars[0].vb_size 103 #define sc_aperphys sc_bars[0].vb_busaddr 104 105 #define sc_iobase sc_bars[1].vb_base 106 #define sc_iosize sc_bars[1].vb_size 107 108 #define sc_regbase sc_bars[2].vb_base 109 #define sc_regsize sc_bars[2].vb_size 110 #define sc_regphys sc_bars[2].vb_busaddr 111 112 bus_space_tag_t sc_regt; 113 bus_space_tag_t sc_memt; 114 bus_space_handle_t sc_regh; 115 bus_space_handle_t sc_memh; 116 void *sc_aperture; /* mapped aperture vaddr */ 117 void *sc_registers; /* mapped registers vaddr */ 118 119 uint32_t sc_nbus, sc_ndev, sc_nfunc; 120 size_t memsize; 121 int memtype; 122 123 int sc_mode; 124 int sc_bg; 125 int sc_locked; 126 127 int has_dsp; 128 int bits_per_pixel; 129 int max_x; 130 int max_y; 131 int virt_x; 132 int virt_y; 133 int color_depth; 134 135 int mem_freq; 136 int ramdac_freq; 137 int ref_freq; 138 139 int ref_div; 140 int log2_vclk_post_div; 141 int vclk_post_div; 142 int vclk_fb_div; 143 int mclk_post_div; 144 int mclk_fb_div; 145 146 struct videomode *sc_my_mode; 147 u_char sc_cmap_red[256]; 148 u_char sc_cmap_green[256]; 149 u_char sc_cmap_blue[256]; 150 int sc_dacw, sc_blanked, sc_console; 151 struct vcons_data vd; 152 }; 153 154 struct mach64_crtcregs { 155 uint32_t h_total_disp; 156 uint32_t h_sync_strt_wid; 157 uint32_t v_total_disp; 158 uint32_t v_sync_strt_wid; 159 uint32_t gen_cntl; 160 uint32_t clock_cntl; 161 uint32_t color_depth; 162 uint32_t dot_clock; 163 }; 164 165 static struct { 166 uint16_t chip_id; 167 uint32_t ramdac_freq; 168 } const mach64_info[] = { 169 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 170 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 171 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 172 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 173 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 174 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 175 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 176 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 178 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 179 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 182 #if 0 183 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 185 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 186 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 189 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 190 #endif 191 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 192 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 193 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 194 }; 195 196 static int mach64_chip_id, mach64_chip_rev; 197 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 198 199 static const char *mach64_memtype_names[] = { 200 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 201 "(unknown type)" 202 }; 203 204 static struct videomode mach64_modes[] = { 205 /* 640x400 @ 70 Hz, 31.5 kHz */ 206 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0, NULL, }, 207 /* 640x480 @ 72 Hz, 36.5 kHz */ 208 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0, NULL, }, 209 /* 800x600 @ 72 Hz, 48.0 kHz */ 210 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 211 VID_PHSYNC | VID_PVSYNC, NULL, }, 212 /* 1024x768 @ 70 Hz, 56.5 kHz */ 213 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 214 VID_NHSYNC | VID_NVSYNC, NULL, }, 215 /* 1152x864 @ 70 Hz, 62.4 kHz */ 216 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0, NULL, }, 217 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 218 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 219 VID_NHSYNC | VID_NVSYNC, NULL, } 220 }; 221 222 extern const u_char rasops_cmap[768]; 223 224 static int mach64_match(device_t, cfdata_t, void *); 225 static void mach64_attach(device_t, device_t, void *); 226 227 CFATTACH_DECL(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 228 NULL, NULL); 229 230 static void mach64_init(struct mach64_softc *); 231 static int mach64_get_memsize(struct mach64_softc *); 232 static int mach64_get_max_ramdac(struct mach64_softc *); 233 234 #if defined(__sparc__) || defined(__powerpc__) 235 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 236 #endif 237 238 static int mach64_calc_crtcregs(struct mach64_softc *, 239 struct mach64_crtcregs *, 240 struct videomode *); 241 static void mach64_set_crtcregs(struct mach64_softc *, 242 struct mach64_crtcregs *); 243 244 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 245 static void mach64_set_dsp(struct mach64_softc *); 246 static void mach64_set_pll(struct mach64_softc *, int); 247 static void mach64_reset_engine(struct mach64_softc *); 248 static void mach64_init_engine(struct mach64_softc *); 249 #if 0 250 static void mach64_adjust_frame(struct mach64_softc *, int, int); 251 #endif 252 static void mach64_init_lut(struct mach64_softc *); 253 254 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 255 static int mach64_set_screentype(struct mach64_softc *, 256 const struct wsscreen_descr *); 257 static int mach64_is_console(struct pci_attach_args *); 258 259 static void mach64_cursor(void *, int, int, int); 260 #if 0 261 static int mach64_mapchar(void *, int, u_int *); 262 #endif 263 static void mach64_putchar(void *, int, int, u_int, long); 264 static void mach64_copycols(void *, int, int, int, int); 265 static void mach64_erasecols(void *, int, int, int, long); 266 static void mach64_copyrows(void *, int, int, int); 267 static void mach64_eraserows(void *, int, int, long); 268 static int mach64_allocattr(void *, int, int, int, long *); 269 static void mach64_clearscreen(struct mach64_softc *); 270 271 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 272 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 273 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 274 uint8_t, uint8_t); 275 static void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, 276 int, int, int) ; 277 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 278 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 279 uint32_t, uint32_t); 280 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 281 #if 0 282 static void mach64_showpal(struct mach64_softc *); 283 #endif 284 285 static void set_address(struct rasops_info *, void *); 286 static void machfb_blank(struct mach64_softc *, int); 287 288 #if 0 289 static const struct wsdisplay_emulops mach64_emulops = { 290 mach64_cursor, 291 mach64_mapchar, 292 mach64_putchar, 293 mach64_copycols, 294 mach64_erasecols, 295 mach64_copyrows, 296 mach64_eraserows, 297 mach64_allocattr, 298 }; 299 #endif 300 301 static struct wsscreen_descr mach64_defaultscreen = { 302 "default", 303 80, 30, 304 NULL, 305 8, 16, 306 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 307 &default_mode 308 }, mach64_80x25_screen = { 309 "80x25", 80, 25, 310 NULL, 311 8, 16, 312 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 313 &mach64_modes[0] 314 }, mach64_80x30_screen = { 315 "80x30", 80, 30, 316 NULL, 317 8, 16, 318 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 319 &mach64_modes[1] 320 }, mach64_80x40_screen = { 321 "80x40", 80, 40, 322 NULL, 323 8, 10, 324 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 325 &mach64_modes[0] 326 }, mach64_80x50_screen = { 327 "80x50", 80, 50, 328 NULL, 329 8, 8, 330 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 331 &mach64_modes[0] 332 }, mach64_100x37_screen = { 333 "100x37", 100, 37, 334 NULL, 335 8, 16, 336 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 337 &mach64_modes[2] 338 }, mach64_128x48_screen = { 339 "128x48", 128, 48, 340 NULL, 341 8, 16, 342 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 343 &mach64_modes[3] 344 }, mach64_144x54_screen = { 345 "144x54", 144, 54, 346 NULL, 347 8, 16, 348 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 349 &mach64_modes[4] 350 }, mach64_160x64_screen = { 351 "160x54", 160, 64, 352 NULL, 353 8, 16, 354 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 355 &mach64_modes[5] 356 }; 357 358 static const struct wsscreen_descr *_mach64_scrlist[] = { 359 &mach64_defaultscreen, 360 &mach64_80x25_screen, 361 &mach64_80x30_screen, 362 &mach64_80x40_screen, 363 &mach64_80x50_screen, 364 &mach64_100x37_screen, 365 &mach64_128x48_screen, 366 &mach64_144x54_screen, 367 &mach64_160x64_screen 368 }; 369 370 static struct wsscreen_list mach64_screenlist = { 371 __arraycount(_mach64_scrlist), 372 _mach64_scrlist 373 }; 374 375 static int mach64_ioctl(void *, void *, u_long, void *, int, 376 struct lwp *); 377 static paddr_t mach64_mmap(void *, void *, off_t, int); 378 379 #if 0 380 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 381 #endif 382 383 static struct wsdisplay_accessops mach64_accessops = { 384 mach64_ioctl, 385 mach64_mmap, 386 NULL, /* vcons_alloc_screen */ 387 NULL, /* vcons_free_screen */ 388 NULL, /* vcons_show_screen */ 389 NULL, /* load_font */ 390 NULL, /* polls */ 391 NULL, /* scroll */ 392 }; 393 394 static struct vcons_screen mach64_console_screen; 395 396 /* framebuffer device, SPARC-only so far */ 397 #ifdef __sparc__ 398 399 static void machfb_unblank(device_t); 400 static void machfb_fbattach(struct mach64_softc *); 401 402 extern struct cfdriver machfb_cd; 403 404 dev_type_open(machfb_fbopen); 405 dev_type_close(machfb_fbclose); 406 dev_type_ioctl(machfb_fbioctl); 407 dev_type_mmap(machfb_fbmmap); 408 409 /* frame buffer generic driver */ 410 static struct fbdriver machfb_fbdriver = { 411 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 412 machfb_fbmmap, nokqfilter 413 }; 414 415 #endif /* __sparc__ */ 416 417 /* 418 * Inline functions for getting access to register aperture. 419 */ 420 421 static inline uint32_t 422 regr(struct mach64_softc *sc, uint32_t index) 423 { 424 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 425 } 426 427 static inline uint8_t 428 regrb(struct mach64_softc *sc, uint32_t index) 429 { 430 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 431 } 432 433 static inline void 434 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 435 { 436 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 437 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 438 BUS_SPACE_BARRIER_WRITE); 439 } 440 441 static inline void 442 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 443 { 444 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 445 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 446 BUS_SPACE_BARRIER_WRITE); 447 } 448 449 static inline void 450 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 451 { 452 regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); 453 regwb(sc, CLOCK_CNTL + 2, data); 454 regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); 455 } 456 457 static inline void 458 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 459 { 460 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 461 continue; 462 } 463 464 static inline void 465 wait_for_idle(struct mach64_softc *sc) 466 { 467 wait_for_fifo(sc, 16); 468 while ((regr(sc, GUI_STAT) & 1) != 0) 469 continue; 470 } 471 472 static int 473 mach64_match(device_t parent, cfdata_t match, void *aux) 474 { 475 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 476 int i; 477 478 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 479 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 480 return 0; 481 482 for (i = 0; i < __arraycount(mach64_info); i++) 483 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 484 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 485 mach64_chip_rev = PCI_REVISION(pa->pa_class); 486 return 100; 487 } 488 489 return 0; 490 } 491 492 static void 493 mach64_attach(device_t parent, device_t self, void *aux) 494 { 495 struct mach64_softc *sc = device_private(self); 496 struct pci_attach_args *pa = aux; 497 struct rasops_info *ri; 498 char devinfo[256]; 499 int bar, reg, id; 500 struct wsemuldisplaydev_attach_args aa; 501 long defattr; 502 int setmode; 503 pcireg_t screg; 504 505 sc->sc_pc = pa->pa_pc; 506 sc->sc_pcitag = pa->pa_tag; 507 sc->sc_dacw = -1; 508 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 509 sc->sc_nbus = pa->pa_bus; 510 sc->sc_ndev = pa->pa_device; 511 sc->sc_nfunc = pa->pa_function; 512 sc->sc_locked = 0; 513 514 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 515 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 516 aprint_naive(": Graphics processor\n"); 517 518 /* enable memory and IO access */ 519 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 520 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 521 pci_conf_write(sc->sc_pc, sc->sc_pcitag,PCI_COMMAND_STATUS_REG,screg); 522 523 for (bar = 0; bar < NBARS; bar++) { 524 reg = PCI_MAPREG_START + (bar * 4); 525 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 526 sc->sc_pcitag, reg); 527 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 528 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 529 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 530 sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc, 531 sc->sc_pcitag, reg)&0xfffffff0; 532 } 533 sc->sc_memt = pa->pa_memt; 534 535 mach64_init(sc); 536 537 aprint_normal_dev(&sc->sc_dev, 538 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 539 (u_int)(sc->sc_apersize / (1024 * 1024)), 540 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 541 (u_int)sc->sc_regphys); 542 543 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 544 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 545 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 546 (mach64_chip_rev & 0x07) == 0)) 547 sc->has_dsp = 0; 548 else 549 sc->has_dsp = 1; 550 551 sc->memsize = mach64_get_memsize(sc); 552 if (sc->memsize == 8192) 553 /* The last page is used as register aperture. */ 554 sc->memsize -= 4; 555 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 556 557 /* XXX is there any way to calculate reference frequency from 558 known values? */ 559 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 560 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 561 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 562 aprint_normal_dev(&sc->sc_dev, "ref_freq=29.498MHz\n"); 563 sc->ref_freq = 29498; 564 } else 565 sc->ref_freq = 14318; 566 567 regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); 568 sc->ref_div = regrb(sc, CLOCK_CNTL + 2); 569 regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); 570 sc->mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); 571 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 572 (sc->ref_div * 2); 573 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 574 (sc->mem_freq * sc->ref_div); 575 sc->ramdac_freq = mach64_get_max_ramdac(sc); 576 aprint_normal_dev(&sc->sc_dev, 577 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 578 (u_long)sc->memsize, 579 mach64_memtype_names[sc->memtype], 580 sc->mem_freq / 1000, sc->mem_freq % 1000, 581 sc->ramdac_freq / 1000); 582 583 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 584 if (id != mach64_chip_id) { 585 aprint_error_dev(&sc->sc_dev, 586 "chip ID mismatch, 0x%x != 0x%x\n", id, mach64_chip_id); 587 return; 588 } 589 590 sc->sc_console = mach64_is_console(pa); 591 #ifdef DIAGNOSTIC 592 aprint_normal("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 593 #endif 594 #if defined(__sparc__) || defined(__powerpc__) 595 if (sc->sc_console) { 596 mach64_get_mode(sc, &default_mode); 597 setmode = 0; 598 sc->sc_my_mode = &default_mode; 599 } else { 600 /* fill in default_mode if it's empty */ 601 mach64_get_mode(sc, &default_mode); 602 if (default_mode.dot_clock == 0) { 603 memcpy(&default_mode, &mach64_modes[4], 604 sizeof(default_mode)); 605 } 606 sc->sc_my_mode = &default_mode; 607 setmode = 1; 608 } 609 #else 610 if (default_mode.dot_clock == 0) { 611 memcpy(&default_mode, &mach64_modes[0], 612 sizeof(default_mode)); 613 } 614 sc->sc_my_mode = &mach64_modes[0]; 615 setmode = 1; 616 #endif 617 618 sc->bits_per_pixel = 8; 619 sc->virt_x = sc->sc_my_mode->hdisplay; 620 sc->virt_y = sc->sc_my_mode->vdisplay; 621 sc->max_x = sc->virt_x - 1; 622 sc->max_y = (sc->memsize * 1024) / 623 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 624 625 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 626 627 mach64_init_engine(sc); 628 #if 0 629 mach64_adjust_frame(0, 0); 630 if (sc->bits_per_pixel == 8) 631 mach64_init_lut(sc); 632 #endif 633 634 aprint_normal_dev(&sc->sc_dev, 635 "initial resolution %dx%d at %d bpp\n", 636 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 637 sc->bits_per_pixel); 638 639 #ifdef __sparc__ 640 machfb_fbattach(sc); 641 #endif 642 643 wsfont_init(); 644 645 sc->sc_bg = WS_DEFAULT_BG; 646 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &mach64_accessops); 647 sc->vd.init_screen = mach64_init_screen; 648 649 if (sc->sc_console) { 650 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 651 &defattr); 652 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 653 654 ri = &mach64_console_screen.scr_ri; 655 mach64_defaultscreen.textops = &ri->ri_ops; 656 mach64_defaultscreen.capabilities = ri->ri_caps; 657 mach64_defaultscreen.nrows = ri->ri_rows; 658 mach64_defaultscreen.ncols = ri->ri_cols; 659 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 660 } else { 661 /* 662 * since we're not the console we can postpone the rest 663 * until someone actually allocates a screen for us 664 */ 665 mach64_modeswitch(sc, sc->sc_my_mode); 666 } 667 668 mach64_init_lut(sc); 669 mach64_clearscreen(sc); 670 machfb_blank(sc, 0); /* unblank the screen */ 671 672 aa.console = sc->sc_console; 673 aa.scrdata = &mach64_screenlist; 674 aa.accessops = &mach64_accessops; 675 aa.accesscookie = &sc->vd; 676 677 config_found(self, &aa, wsemuldisplaydevprint); 678 } 679 680 static void 681 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 682 long *defattr) 683 { 684 struct mach64_softc *sc = cookie; 685 struct rasops_info *ri = &scr->scr_ri; 686 687 /* XXX for now */ 688 #define setmode 0 689 690 ri->ri_depth = sc->bits_per_pixel; 691 ri->ri_width = sc->sc_my_mode->hdisplay; 692 ri->ri_height = sc->sc_my_mode->vdisplay; 693 ri->ri_stride = ri->ri_width; 694 ri->ri_flg = RI_CENTER; 695 set_address(ri, sc->sc_aperture); 696 697 if (existing) { 698 ri->ri_flg |= RI_CLEAR; 699 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 700 panic("%s: failed to switch video mode", 701 device_xname(&sc->sc_dev)); 702 } 703 } 704 705 rasops_init(ri, sc->sc_my_mode->vdisplay/8, 706 sc->sc_my_mode->hdisplay/8); 707 ri->ri_caps = WSSCREEN_WSCOLORS; 708 709 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 710 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 711 712 /* enable acceleration */ 713 ri->ri_hw = scr; 714 ri->ri_ops.copyrows = mach64_copyrows; 715 ri->ri_ops.copycols = mach64_copycols; 716 ri->ri_ops.eraserows = mach64_eraserows; 717 ri->ri_ops.erasecols = mach64_erasecols; 718 ri->ri_ops.cursor = mach64_cursor; 719 ri->ri_ops.putchar = mach64_putchar; 720 ri->ri_ops.allocattr = mach64_allocattr; 721 } 722 723 static void 724 mach64_init(struct mach64_softc *sc) 725 { 726 uint32_t *p32, saved_value; 727 uint8_t *p; 728 int need_swap; 729 730 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 731 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 732 panic("%s: failed to map aperture", device_xname(&sc->sc_dev)); 733 } 734 sc->sc_aperture = (void *)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 735 736 sc->sc_regt = sc->sc_memt; 737 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 738 sc->sc_regsize, &sc->sc_regh); 739 sc->sc_registers = (char *)sc->sc_aperture + 0x7ffc00; 740 741 /* 742 * Test wether the aperture is byte swapped or not 743 */ 744 p32 = (uint32_t*)sc->sc_aperture; 745 saved_value = *p32; 746 p = (uint8_t*)(u_long)sc->sc_aperture; 747 *p32 = 0x12345678; 748 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 749 need_swap = 0; 750 else 751 need_swap = 1; 752 if (need_swap) { 753 sc->sc_aperture = (char *)sc->sc_aperture + 0x800000; 754 sc->sc_aperbase += 0x800000; 755 sc->sc_apersize -= 0x800000; 756 } 757 *p32 = saved_value; 758 759 sc->sc_blanked = 0; 760 } 761 762 static int 763 mach64_get_memsize(struct mach64_softc *sc) 764 { 765 int tmp, memsize; 766 int mem_tab[] = { 767 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 768 }; 769 tmp = regr(sc, MEM_CNTL); 770 #ifdef DIAGNOSTIC 771 aprint_debug_dev(&sc->sc_dev, "memctl %08x\n", tmp); 772 #endif 773 if (sc->has_dsp) { 774 tmp &= 0x0000000f; 775 if (tmp < 8) 776 memsize = (tmp + 1) * 512; 777 else if (tmp < 12) 778 memsize = (tmp - 3) * 1024; 779 else 780 memsize = (tmp - 7) * 2048; 781 } else { 782 memsize = mem_tab[tmp & 0x07]; 783 } 784 785 return memsize; 786 } 787 788 static int 789 mach64_get_max_ramdac(struct mach64_softc *sc) 790 { 791 int i; 792 793 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 794 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 795 (mach64_chip_rev & 0x07)) 796 return 170000; 797 798 for (i = 0; i < __arraycount(mach64_info); i++) 799 if (mach64_chip_id == mach64_info[i].chip_id) 800 return mach64_info[i].ramdac_freq; 801 802 if (sc->bits_per_pixel == 8) 803 return 135000; 804 else 805 return 80000; 806 } 807 808 #if defined(__sparc__) || defined(__powerpc__) 809 static void 810 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 811 { 812 struct mach64_crtcregs crtc; 813 814 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 815 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 816 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 817 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 818 819 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 820 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 821 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 822 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 823 mode->hsync_start; 824 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 825 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 826 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 827 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 828 829 #ifdef DEBUG_MACHFB 830 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 831 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 832 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 833 #endif 834 } 835 #endif 836 837 static int 838 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 839 struct videomode *mode) 840 { 841 842 if (mode->dot_clock > sc->ramdac_freq) 843 /* Clock too high. */ 844 return 1; 845 846 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 847 ((mode->htotal >> 3) - 1); 848 crtc->h_sync_strt_wid = 849 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 850 ((mode->hsync_start >> 3) - 1); 851 852 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 853 (mode->vtotal - 1); 854 crtc->v_sync_strt_wid = 855 ((mode->vsync_end - mode->vsync_start) << 16) | 856 (mode->vsync_start - 1); 857 858 if (mode->flags & VID_NVSYNC) 859 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 860 861 switch (sc->bits_per_pixel) { 862 case 8: 863 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 864 break; 865 case 16: 866 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 867 break; 868 case 32: 869 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 870 break; 871 } 872 873 crtc->gen_cntl = 0; 874 if (mode->flags & VID_INTERLACE) 875 crtc->gen_cntl |= CRTC_INTERLACE_EN; 876 877 if (mode->flags & VID_CSYNC) 878 crtc->gen_cntl |= CRTC_CSYNC_EN; 879 880 crtc->dot_clock = mode->dot_clock; 881 882 return 0; 883 } 884 885 static void 886 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 887 { 888 889 mach64_set_pll(sc, crtc->dot_clock); 890 891 if (sc->has_dsp) 892 mach64_set_dsp(sc); 893 894 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 895 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 896 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 897 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 898 899 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 900 901 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 902 903 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 904 /* XXX this unconditionally enables composite sync on SPARC */ 905 #ifdef __sparc__ 906 CRTC_CSYNC_EN | 907 #endif 908 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 909 } 910 911 static int 912 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 913 { 914 struct mach64_crtcregs crtc; 915 916 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 917 918 if (mach64_calc_crtcregs(sc, &crtc, mode)) 919 return 1; 920 921 mach64_set_crtcregs(sc, &crtc); 922 return 0; 923 } 924 925 static void 926 mach64_reset_engine(struct mach64_softc *sc) 927 { 928 929 /* Reset engine.*/ 930 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 931 932 /* Enable engine. */ 933 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 934 935 /* Ensure engine is not locked up by clearing any FIFO or 936 host errors. */ 937 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 938 BUS_FIFO_ERR_ACK); 939 } 940 941 static void 942 mach64_init_engine(struct mach64_softc *sc) 943 { 944 uint32_t pitch_value; 945 946 pitch_value = sc->virt_x; 947 948 if (sc->bits_per_pixel == 24) 949 pitch_value *= 3; 950 951 mach64_reset_engine(sc); 952 953 wait_for_fifo(sc, 14); 954 955 regw(sc, CONTEXT_MASK, 0xffffffff); 956 957 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 958 959 regw(sc, DST_Y_X, 0); 960 regw(sc, DST_HEIGHT, 0); 961 regw(sc, DST_BRES_ERR, 0); 962 regw(sc, DST_BRES_INC, 0); 963 regw(sc, DST_BRES_DEC, 0); 964 965 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 966 DST_Y_TOP_TO_BOTTOM); 967 968 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 969 970 regw(sc, SRC_Y_X, 0); 971 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 972 regw(sc, SRC_Y_X_START, 0); 973 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 974 975 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 976 977 wait_for_fifo(sc, 13); 978 regw(sc, HOST_CNTL, 0); 979 980 regw(sc, PAT_REG0, 0); 981 regw(sc, PAT_REG1, 0); 982 regw(sc, PAT_CNTL, 0); 983 984 regw(sc, SC_LEFT, 0); 985 regw(sc, SC_TOP, 0); 986 regw(sc, SC_BOTTOM, sc->sc_my_mode->vdisplay - 1); 987 regw(sc, SC_RIGHT, pitch_value - 1); 988 989 regw(sc, DP_BKGD_CLR, 0); 990 regw(sc, DP_FRGD_CLR, 0xffffffff); 991 regw(sc, DP_WRITE_MASK, 0xffffffff); 992 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 993 994 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 995 996 wait_for_fifo(sc, 3); 997 regw(sc, CLR_CMP_CLR, 0); 998 regw(sc, CLR_CMP_MASK, 0xffffffff); 999 regw(sc, CLR_CMP_CNTL, 0); 1000 1001 wait_for_fifo(sc, 2); 1002 switch (sc->bits_per_pixel) { 1003 case 8: 1004 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 1005 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1006 /* We want 8 bit per channel */ 1007 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1008 break; 1009 #if 0 1010 case 32: 1011 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 1012 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1013 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1014 break; 1015 #endif 1016 } 1017 1018 wait_for_fifo(sc, 5); 1019 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1020 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1021 1022 wait_for_idle(sc); 1023 } 1024 1025 #if 0 1026 static void 1027 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1028 { 1029 int offset; 1030 1031 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1032 1033 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1034 offset); 1035 } 1036 #endif 1037 1038 static void 1039 mach64_set_dsp(struct mach64_softc *sc) 1040 { 1041 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1042 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1043 uint32_t xclks_per_qw, y; 1044 uint32_t fifo_off, fifo_on; 1045 1046 aprint_normal_dev(&sc->sc_dev, "initializing the DSP\n"); 1047 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1048 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1049 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1050 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1051 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1052 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1053 dsp_loop_latency = 0; 1054 fifo_depth = 24; 1055 } else { 1056 dsp_loop_latency = 2; 1057 fifo_depth = 32; 1058 } 1059 1060 dsp_precision = 0; 1061 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1062 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1063 y = (xclks_per_qw * fifo_depth) >> 11; 1064 while (y) { 1065 y >>= 1; 1066 dsp_precision++; 1067 } 1068 dsp_precision -= 5; 1069 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1070 1071 switch (sc->memtype) { 1072 case DRAM: 1073 case EDO_DRAM: 1074 case PSEUDO_EDO: 1075 if (sc->memsize > 1024) { 1076 page_size = 9; 1077 dsp_loop_latency += 6; 1078 } else { 1079 page_size = 10; 1080 if (sc->memtype == DRAM) 1081 dsp_loop_latency += 8; 1082 else 1083 dsp_loop_latency += 7; 1084 } 1085 break; 1086 case SDRAM: 1087 case SGRAM: 1088 if (sc->memsize > 1024) { 1089 page_size = 8; 1090 dsp_loop_latency += 8; 1091 } else { 1092 page_size = 10; 1093 dsp_loop_latency += 9; 1094 } 1095 break; 1096 default: 1097 page_size = 10; 1098 dsp_loop_latency += 9; 1099 break; 1100 } 1101 1102 if (xclks_per_qw >= (page_size << 11)) 1103 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1104 else 1105 fifo_on = (3 * page_size + 2) << 6; 1106 1107 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1108 dsp_on = fifo_on >> dsp_precision; 1109 dsp_off = fifo_off >> dsp_precision; 1110 1111 #ifdef DEBUG_MACHFB 1112 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1113 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1114 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1115 "mclk_post_div = %d, vclk_post_div = %d\n", 1116 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1117 sc->mclk_fb_div, sc->vclk_fb_div, 1118 sc->mclk_post_div, sc->vclk_post_div); 1119 #endif 1120 1121 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1122 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1123 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1124 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1125 } 1126 1127 static void 1128 mach64_set_pll(struct mach64_softc *sc, int clock) 1129 { 1130 int q; 1131 1132 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1133 #ifdef DEBUG_MACHFB 1134 printf("q = %d\n", q); 1135 #endif 1136 if (q > 25500) { 1137 printf("Warning: q > 25500\n"); 1138 q = 25500; 1139 sc->vclk_post_div = 1; 1140 sc->log2_vclk_post_div = 0; 1141 } else if (q > 12750) { 1142 sc->vclk_post_div = 1; 1143 sc->log2_vclk_post_div = 0; 1144 } else if (q > 6350) { 1145 sc->vclk_post_div = 2; 1146 sc->log2_vclk_post_div = 1; 1147 } else if (q > 3150) { 1148 sc->vclk_post_div = 4; 1149 sc->log2_vclk_post_div = 2; 1150 } else if (q >= 1600) { 1151 sc->vclk_post_div = 8; 1152 sc->log2_vclk_post_div = 3; 1153 } else { 1154 printf("Warning: q < 1600\n"); 1155 sc->vclk_post_div = 8; 1156 sc->log2_vclk_post_div = 3; 1157 } 1158 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1159 1160 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1161 regwb_pll(sc, VCLK_POST_DIV, sc->log2_vclk_post_div); 1162 regwb_pll(sc, VCLK0_FB_DIV, sc->vclk_fb_div); 1163 } 1164 1165 static void 1166 mach64_init_lut(struct mach64_softc *sc) 1167 { 1168 int i, idx; 1169 1170 idx = 0; 1171 for (i = 0; i < 256; i++) { 1172 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1], 1173 rasops_cmap[idx + 2]); 1174 idx += 3; 1175 } 1176 } 1177 1178 static int 1179 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1180 uint8_t b) 1181 { 1182 sc->sc_cmap_red[index] = r; 1183 sc->sc_cmap_green[index] = g; 1184 sc->sc_cmap_blue[index] = b; 1185 /* 1186 * writing the dac index takes a while, in theory we can poll some 1187 * register to see when it's ready - but we better avoid writing it 1188 * unnecessarily 1189 */ 1190 if (index != sc->sc_dacw) { 1191 regwb(sc, DAC_MASK, 0xff); 1192 regwb(sc, DAC_WINDEX, index); 1193 } 1194 sc->sc_dacw = index + 1; 1195 regwb(sc, DAC_DATA, r); 1196 regwb(sc, DAC_DATA, g); 1197 regwb(sc, DAC_DATA, b); 1198 return 0; 1199 } 1200 1201 static int 1202 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1203 { 1204 uint index = cm->index; 1205 uint count = cm->count; 1206 int i, error; 1207 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1208 uint8_t *r, *g, *b; 1209 1210 if (cm->index >= 256 || cm->count > 256 || 1211 (cm->index + cm->count) > 256) 1212 return EINVAL; 1213 error = copyin(cm->red, &rbuf[index], count); 1214 if (error) 1215 return error; 1216 error = copyin(cm->green, &gbuf[index], count); 1217 if (error) 1218 return error; 1219 error = copyin(cm->blue, &bbuf[index], count); 1220 if (error) 1221 return error; 1222 1223 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1224 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1225 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1226 1227 r = &sc->sc_cmap_red[index]; 1228 g = &sc->sc_cmap_green[index]; 1229 b = &sc->sc_cmap_blue[index]; 1230 1231 for (i = 0; i < count; i++) { 1232 mach64_putpalreg(sc, index, *r, *g, *b); 1233 index++; 1234 r++, g++, b++; 1235 } 1236 return 0; 1237 } 1238 1239 static int 1240 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1241 { 1242 u_int index = cm->index; 1243 u_int count = cm->count; 1244 int error; 1245 1246 if (index >= 255 || count > 256 || index + count > 256) 1247 return EINVAL; 1248 1249 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1250 if (error) 1251 return error; 1252 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1253 if (error) 1254 return error; 1255 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1256 if (error) 1257 return error; 1258 1259 return 0; 1260 } 1261 1262 static int 1263 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1264 { 1265 struct mach64_crtcregs regs; 1266 1267 if (mach64_calc_crtcregs(sc, ®s, 1268 (struct videomode *)des->modecookie)) 1269 return 1; 1270 1271 mach64_set_crtcregs(sc, ®s); 1272 return 0; 1273 } 1274 1275 static int 1276 mach64_is_console(struct pci_attach_args *pa) 1277 { 1278 #ifdef __sparc__ 1279 int node; 1280 1281 node = PCITAG_NODE(pa->pa_tag); 1282 if (node == -1) 1283 return 0; 1284 1285 return (node == prom_instance_to_package(prom_stdout())); 1286 #elif defined(__powerpc__) 1287 /* check if we're the /chosen console device */ 1288 int chosen, stdout, node, us; 1289 1290 us = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 1291 chosen = OF_finddevice("/chosen"); 1292 OF_getprop(chosen, "stdout", &stdout, 4); 1293 node = OF_instance_to_package(stdout); 1294 return (us == node); 1295 #else 1296 return 1; 1297 #endif 1298 } 1299 1300 /* 1301 * wsdisplay_emulops 1302 */ 1303 1304 static void 1305 mach64_cursor(void *cookie, int on, int row, int col) 1306 { 1307 struct rasops_info *ri = cookie; 1308 struct vcons_screen *scr = ri->ri_hw; 1309 struct mach64_softc *sc = scr->scr_cookie; 1310 int x, y, wi, he; 1311 1312 wi = ri->ri_font->fontwidth; 1313 he = ri->ri_font->fontheight; 1314 1315 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1316 x = ri->ri_ccol * wi + ri->ri_xorigin; 1317 y = ri->ri_crow * he + ri->ri_yorigin; 1318 if (ri->ri_flg & RI_CURSOR) { 1319 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1320 0xff); 1321 ri->ri_flg &= ~RI_CURSOR; 1322 } 1323 ri->ri_crow = row; 1324 ri->ri_ccol = col; 1325 if (on) { 1326 x = ri->ri_ccol * wi + ri->ri_xorigin; 1327 y = ri->ri_crow * he + ri->ri_yorigin; 1328 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1329 0xff); 1330 ri->ri_flg |= RI_CURSOR; 1331 } 1332 } else { 1333 scr->scr_ri.ri_crow = row; 1334 scr->scr_ri.ri_ccol = col; 1335 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1336 } 1337 } 1338 1339 #if 0 1340 static int 1341 mach64_mapchar(void *cookie, int uni, u_int *index) 1342 { 1343 return 0; 1344 } 1345 #endif 1346 1347 static void 1348 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1349 { 1350 struct rasops_info *ri = cookie; 1351 struct vcons_screen *scr = ri->ri_hw; 1352 struct mach64_softc *sc = scr->scr_cookie; 1353 1354 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1355 int fg, bg, uc; 1356 uint8_t *data; 1357 int x, y, wi, he; 1358 wi = ri->ri_font->fontwidth; 1359 he = ri->ri_font->fontheight; 1360 1361 if (!CHAR_IN_FONT(c, ri->ri_font)) 1362 return; 1363 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0xf]; 1364 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0xf]; 1365 x = ri->ri_xorigin + col * wi; 1366 y = ri->ri_yorigin + row * he; 1367 if (c == 0x20) { 1368 mach64_rectfill(sc, x, y, wi, he, bg); 1369 } else { 1370 uc = c-ri->ri_font->firstchar; 1371 data = (uint8_t *)ri->ri_font->data + uc * 1372 ri->ri_fontscale; 1373 1374 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1375 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1376 } 1377 } 1378 } 1379 1380 1381 static void 1382 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1383 { 1384 struct rasops_info *ri = cookie; 1385 struct vcons_screen *scr = ri->ri_hw; 1386 struct mach64_softc *sc = scr->scr_cookie; 1387 int32_t xs, xd, y, width, height; 1388 1389 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1390 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1391 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1392 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1393 width = ri->ri_font->fontwidth * ncols; 1394 height = ri->ri_font->fontheight; 1395 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff); 1396 } 1397 } 1398 1399 static void 1400 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1401 { 1402 struct rasops_info *ri = cookie; 1403 struct vcons_screen *scr = ri->ri_hw; 1404 struct mach64_softc *sc = scr->scr_cookie; 1405 int32_t x, y, width, height, fg, bg, ul; 1406 1407 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1408 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1409 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1410 width = ri->ri_font->fontwidth * ncols; 1411 height = ri->ri_font->fontheight; 1412 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1413 1414 mach64_rectfill(sc, x, y, width, height, bg); 1415 } 1416 } 1417 1418 static void 1419 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1420 { 1421 struct rasops_info *ri = cookie; 1422 struct vcons_screen *scr = ri->ri_hw; 1423 struct mach64_softc *sc = scr->scr_cookie; 1424 int32_t x, ys, yd, width, height; 1425 1426 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1427 x = ri->ri_xorigin; 1428 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1429 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1430 width = ri->ri_emuwidth; 1431 height = ri->ri_font->fontheight*nrows; 1432 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff); 1433 } 1434 } 1435 1436 static void 1437 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1438 { 1439 struct rasops_info *ri = cookie; 1440 struct vcons_screen *scr = ri->ri_hw; 1441 struct mach64_softc *sc = scr->scr_cookie; 1442 int32_t x, y, width, height, fg, bg, ul; 1443 1444 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1445 x = ri->ri_xorigin; 1446 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1447 width = ri->ri_emuwidth; 1448 height = ri->ri_font->fontheight * nrows; 1449 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1450 1451 mach64_rectfill(sc, x, y, width, height, bg); 1452 } 1453 } 1454 1455 static void 1456 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1457 { 1458 uint32_t dest_ctl = 0; 1459 1460 wait_for_idle(sc); 1461 regw(sc, DP_WRITE_MASK, mask); /* XXX only good for 8 bit */ 1462 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1463 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1464 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1465 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1466 if (yd < ys) { 1467 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1468 } else { 1469 ys += height - 1; 1470 yd += height - 1; 1471 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1472 } 1473 if (xd < xs) { 1474 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1475 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1476 } else { 1477 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1478 xs += width - 1; 1479 xd += width - 1; 1480 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1481 } 1482 regw(sc, DST_CNTL, dest_ctl); 1483 1484 regw(sc, SRC_Y_X, (xs << 16) | ys); 1485 regw(sc, SRC_WIDTH1, width); 1486 regw(sc, DST_Y_X, (xd << 16) | yd); 1487 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1488 } 1489 1490 static void 1491 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1492 int height, uint32_t fg, uint32_t bg) 1493 { 1494 wait_for_idle(sc); 1495 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1496 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1497 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1498 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1499 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1500 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1501 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1502 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1503 regw(sc, DP_BKGD_CLR, bg); 1504 regw(sc, DP_FRGD_CLR, fg); 1505 regw(sc, SRC_Y_X, 0); 1506 regw(sc, SRC_WIDTH1, width); 1507 regw(sc, DST_Y_X, (xd << 16) | yd); 1508 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1509 /* now feed the data into the chip */ 1510 } 1511 1512 static void 1513 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1514 { 1515 int i; 1516 uint32_t latch = 0, bork; 1517 int shift = 0; 1518 int reg = 0; 1519 1520 for (i=0;i<count;i++) { 1521 bork = data[i]; 1522 latch |= (bork << shift); 1523 if (shift == 24) { 1524 regw(sc, HOST_DATA0 + reg, latch); 1525 latch = 0; 1526 shift = 0; 1527 reg = (reg + 4) & 0x3c; 1528 } else 1529 shift += 8; 1530 } 1531 if (shift != 0) /* 24 */ 1532 regw(sc, HOST_DATA0 + reg, latch); 1533 } 1534 1535 1536 static void 1537 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1538 int colour) 1539 { 1540 wait_for_idle(sc); 1541 regw(sc, DP_WRITE_MASK, 0xff); 1542 regw(sc, DP_FRGD_CLR, colour); 1543 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1544 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1545 regw(sc, DP_MIX, MIX_SRC << 16); 1546 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1547 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1548 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1549 1550 regw(sc, SRC_Y_X, (x << 16) | y); 1551 regw(sc, SRC_WIDTH1, width); 1552 regw(sc, DST_Y_X, (x << 16) | y); 1553 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1554 } 1555 1556 static void 1557 mach64_clearscreen(struct mach64_softc *sc) 1558 { 1559 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1560 } 1561 1562 1563 #if 0 1564 static void 1565 mach64_showpal(struct mach64_softc *sc) 1566 { 1567 int i, x = 0; 1568 1569 for (i = 0; i < 16; i++) { 1570 mach64_rectfill(sc, x, 0, 64, 64, i); 1571 x += 64; 1572 } 1573 } 1574 #endif 1575 1576 static int 1577 mach64_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1578 { 1579 if ((fg == 0) && (bg == 0)) 1580 { 1581 fg = WS_DEFAULT_FG; 1582 bg = WS_DEFAULT_BG; 1583 } 1584 *attrp = (fg & 0xf) << 24 | (bg & 0xf) << 16 | (flags & 0xff) << 8; 1585 return 0; 1586 } 1587 1588 /* 1589 * wsdisplay_accessops 1590 */ 1591 1592 static int 1593 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1594 struct lwp *l) 1595 { 1596 struct vcons_data *vd = v; 1597 struct mach64_softc *sc = vd->cookie; 1598 struct wsdisplay_fbinfo *wdf; 1599 struct vcons_screen *ms = vd->active; 1600 1601 switch (cmd) { 1602 case WSDISPLAYIO_GTYPE: 1603 /* XXX is this the right type to return? */ 1604 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1605 return 0; 1606 1607 case WSDISPLAYIO_LINEBYTES: 1608 *(u_int *)data = sc->virt_x * sc->bits_per_pixel / 8; 1609 return 0; 1610 1611 case WSDISPLAYIO_GINFO: 1612 wdf = (void *)data; 1613 wdf->height = sc->virt_y; 1614 wdf->width = sc->virt_x; 1615 wdf->depth = sc->bits_per_pixel; 1616 wdf->cmsize = 256; 1617 return 0; 1618 1619 case WSDISPLAYIO_GETCMAP: 1620 return mach64_getcmap(sc, 1621 (struct wsdisplay_cmap *)data); 1622 1623 case WSDISPLAYIO_PUTCMAP: 1624 return mach64_putcmap(sc, 1625 (struct wsdisplay_cmap *)data); 1626 1627 /* PCI config read/write passthrough. */ 1628 case PCI_IOC_CFGREAD: 1629 case PCI_IOC_CFGWRITE: 1630 return (pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1631 cmd, data, flag, l)); 1632 1633 case WSDISPLAYIO_SMODE: 1634 { 1635 int new_mode = *(int*)data; 1636 1637 if (new_mode != sc->sc_mode) 1638 { 1639 sc->sc_mode = new_mode; 1640 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1641 && (ms != NULL)) 1642 { 1643 vcons_redraw_screen(ms); 1644 } 1645 } 1646 } 1647 return 0; 1648 1649 } 1650 return EPASSTHROUGH; 1651 } 1652 1653 static paddr_t 1654 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1655 { 1656 struct vcons_data *vd = v; 1657 struct mach64_softc *sc = vd->cookie; 1658 paddr_t pa; 1659 pcireg_t reg; 1660 1661 #ifndef __sparc64__ 1662 /* 1663 *'regular' framebuffer mmap()ing 1664 * disabled on sparc64 because some ATI firmware likes to map some PCI 1665 * resources to addresses that would collide with this ( like some Rage 1666 * IIc which uses 0x2000 for the 2nd register block ) 1667 * Other 64bit architectures might run into similar problems. 1668 */ 1669 if (offset<sc->sc_apersize) { 1670 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, offset, 1671 prot, BUS_SPACE_MAP_LINEAR); 1672 return pa; 1673 } 1674 #endif 1675 1676 /* 1677 * restrict all other mappings to processes with superuser privileges 1678 * or the kernel itself 1679 */ 1680 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1681 NULL) != 0) { 1682 #if 0 1683 printf("%s: mmap() rejected.\n", device_xname(&sc->sc_dev)); 1684 #endif 1685 return -1; 1686 } 1687 1688 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1689 if (reg != sc->sc_regphys) { 1690 #ifdef DIAGNOSTIC 1691 printf("%s: BAR 0x18 changed! (%x %x)\n", 1692 device_xname(&sc->sc_dev), (uint32_t)sc->sc_regphys, 1693 (uint32_t)reg); 1694 #endif 1695 sc->sc_regphys = reg; 1696 } 1697 1698 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1699 if (reg != sc->sc_aperphys) { 1700 #ifdef DIAGNOSTIC 1701 printf("%s: BAR 0x10 changed! (%x %x)\n", 1702 device_xname(&sc->sc_dev), (uint32_t)sc->sc_aperphys, 1703 (uint32_t)reg); 1704 #endif 1705 sc->sc_aperphys = reg; 1706 } 1707 1708 #if 0 1709 /* evil hack to allow mmap()ing other devices as well */ 1710 if ((offset > 0x80000000) && (offset <= 0xffffffff)) { 1711 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1712 BUS_SPACE_MAP_LINEAR); 1713 return pa; 1714 } 1715 #endif 1716 1717 if ((offset >= sc->sc_aperphys) && 1718 (offset < (sc->sc_aperphys + sc->sc_apersize))) { 1719 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1720 BUS_SPACE_MAP_LINEAR); 1721 return pa; 1722 } 1723 1724 if ((offset >= sc->sc_regphys) && 1725 (offset < (sc->sc_regphys + sc->sc_regsize))) { 1726 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1727 BUS_SPACE_MAP_LINEAR); 1728 return pa; 1729 } 1730 1731 return -1; 1732 } 1733 1734 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1735 static void 1736 set_address(struct rasops_info *ri, void *fb) 1737 { 1738 #ifdef notdef 1739 printf(" %d %d %d\n", ri->ri_xorigin, ri->ri_yorigin, ri->ri_stride); 1740 #endif 1741 ri->ri_bits = (void *)((char *)fb + ri->ri_stride * ri->ri_yorigin + 1742 ri->ri_xorigin); 1743 } 1744 1745 #if 0 1746 static int 1747 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1748 { 1749 1750 return 0; 1751 } 1752 #endif 1753 1754 void 1755 machfb_blank(struct mach64_softc *sc, int blank) 1756 { 1757 uint32_t reg; 1758 1759 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1760 1761 switch (blank) 1762 { 1763 case 0: 1764 reg = regr(sc, CRTC_GEN_CNTL); 1765 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1766 sc->sc_blanked = 0; 1767 break; 1768 case 1: 1769 reg = regr(sc, CRTC_GEN_CNTL); 1770 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1771 sc->sc_blanked = 1; 1772 break; 1773 default: 1774 break; 1775 } 1776 } 1777 1778 /* framebuffer device support */ 1779 #ifdef __sparc__ 1780 1781 static void 1782 machfb_unblank(device_t dev) 1783 { 1784 struct mach64_softc *sc = device_private(dev); 1785 1786 machfb_blank(sc, 0); 1787 } 1788 1789 static void 1790 machfb_fbattach(struct mach64_softc *sc) 1791 { 1792 struct fbdevice *fb = &sc->sc_fb; 1793 1794 fb->fb_device = &sc->sc_dev; 1795 fb->fb_driver = &machfb_fbdriver; 1796 1797 fb->fb_type.fb_cmsize = 256; 1798 fb->fb_type.fb_size = sc->memsize; 1799 1800 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 1801 fb->fb_flags = sc->sc_dev.dv_cfdata->cf_flags & FB_USERMASK; 1802 fb->fb_type.fb_depth = sc->bits_per_pixel; 1803 fb->fb_type.fb_width = sc->virt_x; 1804 fb->fb_type.fb_height = sc->virt_y; 1805 1806 fb->fb_pixels = sc->sc_aperture; 1807 fb_attach(fb, sc->sc_console); 1808 } 1809 1810 int 1811 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 1812 { 1813 struct mach64_softc *sc; 1814 1815 sc = device_lookup_private(&machfb_cd, minor(dev)); 1816 if (sc == NULL) 1817 return ENXIO; 1818 sc->sc_locked = 1; 1819 1820 #ifdef DEBUG_MACHFB 1821 printf("machfb_fbopen(%d)\n", minor(dev)); 1822 #endif 1823 return 0; 1824 } 1825 1826 int 1827 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 1828 { 1829 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1830 1831 #ifdef DEBUG_MACHFB 1832 printf("machfb_fbclose()\n"); 1833 #endif 1834 mach64_init_engine(sc); 1835 mach64_init_lut(sc); 1836 sc->sc_locked = 0; 1837 return 0; 1838 } 1839 1840 int 1841 machfb_fbioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1842 { 1843 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1844 1845 #ifdef DEBUG_MACHFB 1846 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 1847 #endif 1848 switch (cmd) { 1849 case FBIOGTYPE: 1850 *(struct fbtype *)data = sc->sc_fb.fb_type; 1851 break; 1852 1853 case FBIOGATTR: 1854 #define fba ((struct fbgattr *)data) 1855 fba->real_type = sc->sc_fb.fb_type.fb_type; 1856 fba->owner = 0; /* XXX ??? */ 1857 fba->fbtype = sc->sc_fb.fb_type; 1858 fba->sattr.flags = 0; 1859 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 1860 fba->sattr.dev_specific[0] = sc->sc_nbus; 1861 fba->sattr.dev_specific[1] = sc->sc_ndev; 1862 fba->sattr.dev_specific[2] = sc->sc_nfunc; 1863 fba->sattr.dev_specific[3] = -1; 1864 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 1865 fba->emu_types[1] = -1; 1866 #undef fba 1867 break; 1868 1869 #if 0 1870 case FBIOGETCMAP: 1871 #define p ((struct fbcmap *)data) 1872 return (bt_getcmap(p, &sc->sc_cmap, 256, 1)); 1873 1874 case FBIOPUTCMAP: 1875 /* copy to software map */ 1876 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 1877 if (error) 1878 return error; 1879 /* now blast them into the chip */ 1880 /* XXX should use retrace interrupt */ 1881 cg6_loadcmap(sc, p->index, p->count); 1882 #undef p 1883 break; 1884 #endif 1885 case FBIOGVIDEO: 1886 *(int *)data = sc->sc_blanked; 1887 break; 1888 1889 case FBIOSVIDEO: 1890 machfb_blank(sc, *(int *)data); 1891 break; 1892 1893 #if 0 1894 case FBIOGCURSOR: 1895 break; 1896 1897 case FBIOSCURSOR: 1898 break; 1899 1900 case FBIOGCURPOS: 1901 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 1902 break; 1903 1904 case FBIOSCURPOS: 1905 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 1906 break; 1907 1908 case FBIOGCURMAX: 1909 /* max cursor size is 32x32 */ 1910 ((struct fbcurpos *)data)->x = 32; 1911 ((struct fbcurpos *)data)->y = 32; 1912 break; 1913 #endif 1914 case PCI_IOC_CFGREAD: 1915 case PCI_IOC_CFGWRITE: 1916 { 1917 int ret; 1918 1919 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1920 cmd, data, flags, l); 1921 1922 #ifdef DEBUG_MACHFB 1923 printf("pci_devioctl: %d\n", ret); 1924 #endif 1925 return ret; 1926 } 1927 default: 1928 #ifdef DEBUG_MACHFB 1929 log(LOG_NOTICE, "machfb_fbioctl(0x%lx) (%s[%d])\n", cmd, 1930 p->p_comm, p->p_pid); 1931 #endif 1932 return ENOTTY; 1933 } 1934 #ifdef DEBUG_MACHFB 1935 printf("machfb_fbioctl done\n"); 1936 #endif 1937 return 0; 1938 } 1939 1940 paddr_t 1941 machfb_fbmmap(dev_t dev, off_t off, int prot) 1942 { 1943 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1944 1945 if (sc != NULL) 1946 return mach64_mmap(&sc->vd, NULL, off, prot); 1947 1948 return 0; 1949 } 1950 1951 #endif /* __sparc__ */ 1952
Indexes created Fri Oct 03 02:09:57 GMT 2025