machfb.c revision 1.58.2.3
1 /* $NetBSD: machfb.c,v 1.58.2.3 2011/05/31 03:04:41 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.58.2.3 2011/05/31 03:04:41 rmind Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #ifdef __sparc__ 58 #include <dev/sun/fbio.h> 59 #include <dev/sun/fbvar.h> 60 #include <sys/conf.h> 61 #else 62 #include <dev/wscons/wsdisplayvar.h> 63 #endif 64 65 #include <dev/wscons/wsconsio.h> 66 #include <dev/wsfont/wsfont.h> 67 #include <dev/rasops/rasops.h> 68 #include <dev/pci/wsdisplay_pci.h> 69 70 #include <dev/wscons/wsdisplay_vconsvar.h> 71 72 #include "opt_wsemul.h" 73 #include "opt_machfb.h" 74 75 #define MACH64_REG_SIZE 1024 76 #define MACH64_REG_OFF 0x7ffc00 77 78 #define NBARS 3 /* number of Mach64 PCI BARs */ 79 80 struct vga_bar { 81 bus_addr_t vb_base; 82 pcireg_t vb_busaddr; 83 bus_size_t vb_size; 84 pcireg_t vb_type; 85 int vb_flags; 86 }; 87 88 struct mach64_softc { 89 device_t sc_dev; 90 #ifdef __sparc__ 91 struct fbdevice sc_fb; 92 #endif 93 pci_chipset_tag_t sc_pc; 94 pcitag_t sc_pcitag; 95 96 struct vga_bar sc_bars[NBARS]; 97 struct vga_bar sc_rom; 98 99 #define sc_aperbase sc_bars[0].vb_base 100 #define sc_apersize sc_bars[0].vb_size 101 #define sc_aperphys sc_bars[0].vb_busaddr 102 103 #define sc_iobase sc_bars[1].vb_base 104 #define sc_iosize sc_bars[1].vb_size 105 106 #define sc_regbase sc_bars[2].vb_base 107 #define sc_regsize sc_bars[2].vb_size 108 #define sc_regphys sc_bars[2].vb_busaddr 109 110 bus_space_tag_t sc_regt; 111 bus_space_tag_t sc_memt; 112 bus_space_tag_t sc_iot; 113 bus_space_handle_t sc_regh; 114 bus_space_handle_t sc_memh; 115 void *sc_aperture; /* mapped aperture vaddr */ 116 void *sc_registers; /* mapped registers vaddr */ 117 118 uint32_t sc_nbus, sc_ndev, sc_nfunc; 119 size_t memsize; 120 int memtype; 121 122 int sc_mode; 123 int sc_bg; 124 int sc_locked; 125 126 int has_dsp; 127 int bits_per_pixel; 128 int max_x; 129 int max_y; 130 int virt_x; 131 int virt_y; 132 int color_depth; 133 134 int mem_freq; 135 int ramdac_freq; 136 int ref_freq; 137 138 int ref_div; 139 int log2_vclk_post_div; 140 int vclk_post_div; 141 int vclk_fb_div; 142 int mclk_post_div; 143 int mclk_fb_div; 144 int sc_clock; /* which clock to use */ 145 146 struct videomode *sc_my_mode; 147 int sc_edid_size; 148 uint8_t sc_edid_data[1024]; 149 150 u_char sc_cmap_red[256]; 151 u_char sc_cmap_green[256]; 152 u_char sc_cmap_blue[256]; 153 int sc_dacw, sc_blanked, sc_console; 154 struct vcons_data vd; 155 }; 156 157 struct mach64_crtcregs { 158 uint32_t h_total_disp; 159 uint32_t h_sync_strt_wid; 160 uint32_t v_total_disp; 161 uint32_t v_sync_strt_wid; 162 uint32_t gen_cntl; 163 uint32_t clock_cntl; 164 uint32_t color_depth; 165 uint32_t dot_clock; 166 }; 167 168 static struct { 169 uint16_t chip_id; 170 uint32_t ramdac_freq; 171 } const mach64_info[] = { 172 { PCI_PRODUCT_ATI_MACH64_GX, 135000 }, 173 { PCI_PRODUCT_ATI_MACH64_CX, 135000 }, 174 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 175 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 176 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 184 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 185 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 186 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 188 #if 0 189 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 190 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 192 #endif 193 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 194 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 195 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 196 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 197 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 198 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 199 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 200 }; 201 202 static int mach64_chip_id, mach64_chip_rev; 203 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 204 205 static const char *mach64_gx_memtype_names[] = { 206 "DRAM", "VRAM", "VRAM", "DRAM", 207 "DRAM", "VRAM", "VRAM", "(unknown type)" 208 }; 209 210 static const char *mach64_memtype_names[] = { 211 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 212 "(unknown type)" 213 }; 214 215 static struct videomode mach64_modes[] = { 216 /* 640x400 @ 70 Hz, 31.5 kHz */ 217 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0, NULL, }, 218 /* 640x480 @ 72 Hz, 36.5 kHz */ 219 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0, NULL, }, 220 /* 800x600 @ 72 Hz, 48.0 kHz */ 221 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 222 VID_PHSYNC | VID_PVSYNC, NULL, }, 223 /* 1024x768 @ 70 Hz, 56.5 kHz */ 224 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 225 VID_NHSYNC | VID_NVSYNC, NULL, }, 226 /* 1152x864 @ 70 Hz, 62.4 kHz */ 227 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0, NULL, }, 228 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 229 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 230 VID_NHSYNC | VID_NVSYNC, NULL, } 231 }; 232 233 extern const u_char rasops_cmap[768]; 234 235 static int mach64_match(device_t, cfdata_t, void *); 236 static void mach64_attach(device_t, device_t, void *); 237 238 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 239 NULL, NULL); 240 241 static void mach64_init(struct mach64_softc *); 242 static int mach64_get_memsize(struct mach64_softc *); 243 static int mach64_get_max_ramdac(struct mach64_softc *); 244 245 #if defined(__sparc__) || defined(__powerpc__) 246 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 247 #endif 248 249 static int mach64_calc_crtcregs(struct mach64_softc *, 250 struct mach64_crtcregs *, 251 struct videomode *); 252 static void mach64_set_crtcregs(struct mach64_softc *, 253 struct mach64_crtcregs *); 254 255 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 256 static void mach64_set_dsp(struct mach64_softc *); 257 static void mach64_set_pll(struct mach64_softc *, int); 258 static void mach64_reset_engine(struct mach64_softc *); 259 static void mach64_init_engine(struct mach64_softc *); 260 #if 0 261 static void mach64_adjust_frame(struct mach64_softc *, int, int); 262 #endif 263 static void mach64_init_lut(struct mach64_softc *); 264 265 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 266 static int mach64_set_screentype(struct mach64_softc *, 267 const struct wsscreen_descr *); 268 static int mach64_is_console(struct mach64_softc *); 269 270 static void mach64_cursor(void *, int, int, int); 271 #if 0 272 static int mach64_mapchar(void *, int, u_int *); 273 #endif 274 static void mach64_putchar(void *, int, int, u_int, long); 275 static void mach64_copycols(void *, int, int, int, int); 276 static void mach64_erasecols(void *, int, int, int, long); 277 static void mach64_copyrows(void *, int, int, int); 278 static void mach64_eraserows(void *, int, int, long); 279 static void mach64_clearscreen(struct mach64_softc *); 280 281 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 282 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 283 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 284 uint8_t, uint8_t); 285 static void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, 286 int, int, int) ; 287 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 288 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 289 uint32_t, uint32_t); 290 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 291 #if 0 292 static void mach64_showpal(struct mach64_softc *); 293 #endif 294 295 static void set_address(struct rasops_info *, void *); 296 static void machfb_blank(struct mach64_softc *, int); 297 static int machfb_drm_print(void *, const char *); 298 299 static struct wsscreen_descr mach64_defaultscreen = { 300 "default", 301 80, 30, 302 NULL, 303 8, 16, 304 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 305 &default_mode 306 }, mach64_80x25_screen = { 307 "80x25", 80, 25, 308 NULL, 309 8, 16, 310 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 311 &mach64_modes[0] 312 }, mach64_80x30_screen = { 313 "80x30", 80, 30, 314 NULL, 315 8, 16, 316 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 317 &mach64_modes[1] 318 }, mach64_80x40_screen = { 319 "80x40", 80, 40, 320 NULL, 321 8, 10, 322 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 323 &mach64_modes[0] 324 }, mach64_80x50_screen = { 325 "80x50", 80, 50, 326 NULL, 327 8, 8, 328 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 329 &mach64_modes[0] 330 }, mach64_100x37_screen = { 331 "100x37", 100, 37, 332 NULL, 333 8, 16, 334 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 335 &mach64_modes[2] 336 }, mach64_128x48_screen = { 337 "128x48", 128, 48, 338 NULL, 339 8, 16, 340 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 341 &mach64_modes[3] 342 }, mach64_144x54_screen = { 343 "144x54", 144, 54, 344 NULL, 345 8, 16, 346 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 347 &mach64_modes[4] 348 }, mach64_160x64_screen = { 349 "160x54", 160, 64, 350 NULL, 351 8, 16, 352 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 353 &mach64_modes[5] 354 }; 355 356 static const struct wsscreen_descr *_mach64_scrlist[] = { 357 &mach64_defaultscreen, 358 &mach64_80x25_screen, 359 &mach64_80x30_screen, 360 &mach64_80x40_screen, 361 &mach64_80x50_screen, 362 &mach64_100x37_screen, 363 &mach64_128x48_screen, 364 &mach64_144x54_screen, 365 &mach64_160x64_screen 366 }; 367 368 static struct wsscreen_list mach64_screenlist = { 369 __arraycount(_mach64_scrlist), 370 _mach64_scrlist 371 }; 372 373 static int mach64_ioctl(void *, void *, u_long, void *, int, 374 struct lwp *); 375 static paddr_t mach64_mmap(void *, void *, off_t, int); 376 377 #if 0 378 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 379 #endif 380 381 static struct wsdisplay_accessops mach64_accessops = { 382 mach64_ioctl, 383 mach64_mmap, 384 NULL, /* vcons_alloc_screen */ 385 NULL, /* vcons_free_screen */ 386 NULL, /* vcons_show_screen */ 387 NULL, /* load_font */ 388 NULL, /* polls */ 389 NULL, /* scroll */ 390 }; 391 392 static struct vcons_screen mach64_console_screen; 393 394 /* framebuffer device, SPARC-only so far */ 395 #ifdef __sparc__ 396 397 static void machfb_unblank(device_t); 398 static void machfb_fbattach(struct mach64_softc *); 399 400 extern struct cfdriver machfb_cd; 401 402 dev_type_open(machfb_fbopen); 403 dev_type_close(machfb_fbclose); 404 dev_type_ioctl(machfb_fbioctl); 405 dev_type_mmap(machfb_fbmmap); 406 407 /* frame buffer generic driver */ 408 static struct fbdriver machfb_fbdriver = { 409 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 410 machfb_fbmmap, nokqfilter 411 }; 412 413 #endif /* __sparc__ */ 414 415 /* 416 * Inline functions for getting access to register aperture. 417 */ 418 419 static inline uint32_t 420 regr(struct mach64_softc *sc, uint32_t index) 421 { 422 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 423 } 424 425 static inline uint8_t 426 regrb(struct mach64_softc *sc, uint32_t index) 427 { 428 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 429 } 430 431 static inline void 432 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 433 { 434 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 435 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 436 BUS_SPACE_BARRIER_WRITE); 437 } 438 439 static inline void 440 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 441 { 442 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 443 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 444 BUS_SPACE_BARRIER_WRITE); 445 } 446 447 static inline void 448 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 449 { 450 uint32_t reg; 451 452 reg = regr(sc, CLOCK_CNTL); 453 reg |= PLL_WR_EN; 454 regw(sc, CLOCK_CNTL, reg); 455 reg &= ~(PLL_ADDR | PLL_DATA); 456 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 457 reg |= data << PLL_DATA_SHIFT; 458 reg |= CLOCK_STROBE; 459 regw(sc, CLOCK_CNTL, reg); 460 reg &= ~PLL_WR_EN; 461 regw(sc, CLOCK_CNTL, reg); 462 } 463 464 static inline uint8_t 465 regrb_pll(struct mach64_softc *sc, uint32_t index) 466 { 467 468 regwb(sc, CLOCK_CNTL + 1, index << 2); 469 return regrb(sc, CLOCK_CNTL + 2); 470 } 471 472 static inline void 473 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 474 { 475 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 476 continue; 477 } 478 479 static inline void 480 wait_for_idle(struct mach64_softc *sc) 481 { 482 wait_for_fifo(sc, 16); 483 while ((regr(sc, GUI_STAT) & 1) != 0) 484 continue; 485 } 486 487 static int 488 mach64_match(device_t parent, cfdata_t match, void *aux) 489 { 490 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 491 int i; 492 493 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 494 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 495 return 0; 496 497 for (i = 0; i < __arraycount(mach64_info); i++) 498 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 499 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 500 mach64_chip_rev = PCI_REVISION(pa->pa_class); 501 return 100; 502 } 503 504 return 0; 505 } 506 507 static void 508 mach64_attach(device_t parent, device_t self, void *aux) 509 { 510 struct mach64_softc *sc = device_private(self); 511 struct pci_attach_args *pa = aux; 512 struct rasops_info *ri; 513 prop_data_t edid_data; 514 const struct videomode *mode = NULL; 515 char devinfo[256]; 516 int bar, id, expected_id; 517 int is_gx; 518 const char **memtype_names; 519 struct wsemuldisplaydev_attach_args aa; 520 long defattr; 521 int setmode, width, height; 522 pcireg_t screg; 523 uint32_t reg; 524 const pcireg_t enables = PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE; 525 526 sc->sc_dev = self; 527 sc->sc_pc = pa->pa_pc; 528 sc->sc_pcitag = pa->pa_tag; 529 sc->sc_dacw = -1; 530 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 531 sc->sc_nbus = pa->pa_bus; 532 sc->sc_ndev = pa->pa_device; 533 sc->sc_nfunc = pa->pa_function; 534 sc->sc_locked = 0; 535 sc->sc_iot = pa->pa_iot; 536 537 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 538 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 539 PCI_REVISION(pa->pa_class)); 540 aprint_naive(": Graphics processor\n"); 541 #ifdef MACHFB_DEBUG 542 printf(prop_dictionary_externalize(device_properties(self))); 543 #endif 544 545 /* enable memory and disable IO access */ 546 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 547 if ((screg & enables) != enables) { 548 screg |= enables; 549 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 550 PCI_COMMAND_STATUS_REG, screg); 551 } 552 for (bar = 0; bar < NBARS; bar++) { 553 reg = PCI_MAPREG_START + (bar * 4); 554 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 555 sc->sc_pcitag, reg); 556 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 557 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 558 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 559 sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc, 560 sc->sc_pcitag, reg) & 0xfffffff0; 561 } 562 printf("%s: aperture size %08x\n", device_xname(sc->sc_dev), 563 (uint32_t)sc->sc_apersize); 564 565 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 566 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 567 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 568 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 569 sc->sc_memt = pa->pa_memt; 570 571 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 572 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 573 panic("%s: failed to map aperture", device_xname(sc->sc_dev)); 574 } 575 sc->sc_aperture = (void *)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 576 577 /* If the BAR was never mapped, fix it up in MMIO. */ 578 if(sc->sc_regsize == 0) { 579 sc->sc_regsize = MACH64_REG_SIZE; 580 sc->sc_regbase = sc->sc_aperbase + MACH64_REG_OFF; 581 sc->sc_regphys = sc->sc_aperphys + MACH64_REG_OFF; 582 } 583 584 sc->sc_regt = sc->sc_memt; 585 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 586 sc->sc_regsize, &sc->sc_regh); 587 sc->sc_registers = (char *)sc->sc_aperture + 0x7ffc00; 588 589 mach64_init(sc); 590 591 aprint_normal_dev(sc->sc_dev, 592 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 593 (u_int)(sc->sc_apersize / (1024 * 1024)), 594 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 595 (u_int)sc->sc_regphys); 596 597 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 598 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 599 600 prop_dictionary_get_uint32(device_properties(self), "width", &width); 601 prop_dictionary_get_uint32(device_properties(self), "height", &height); 602 603 if ((edid_data = prop_dictionary_get(device_properties(self), "EDID")) 604 != NULL) { 605 struct edid_info ei; 606 607 sc->sc_edid_size = min(1024, prop_data_size(edid_data)); 608 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 609 memcpy(sc->sc_edid_data, prop_data_data_nocopy(edid_data), 610 sc->sc_edid_size); 611 612 edid_parse(sc->sc_edid_data, &ei); 613 614 #ifdef MACHFB_DEBUG 615 edid_print(&ei); 616 #endif 617 if (ei.edid_have_range) { 618 619 /* ei has dotclock in MHz, struct videomode in kHz */ 620 mode = pick_mode_by_dotclock(width, height, 621 ei.edid_range.er_max_clock * 1000); 622 if (mode != NULL) 623 printf("mode: %s\n", mode->name); 624 } 625 } 626 627 is_gx = 0; 628 switch(mach64_chip_id) { 629 case PCI_PRODUCT_ATI_MACH64_GX: 630 case PCI_PRODUCT_ATI_MACH64_CX: 631 is_gx = 1; 632 case PCI_PRODUCT_ATI_MACH64_CT: 633 sc->has_dsp = 0; 634 break; 635 case PCI_PRODUCT_ATI_MACH64_VT: 636 case PCI_PRODUCT_ATI_RAGE_II: 637 if((mach64_chip_rev & 0x07) == 0) { 638 sc->has_dsp = 0; 639 break; 640 } 641 /* Otherwise fall through. */ 642 default: 643 sc->has_dsp = 1; 644 } 645 646 memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names; 647 648 sc->memsize = mach64_get_memsize(sc); 649 if (sc->memsize == 8192) 650 /* The last page is used as register aperture. */ 651 sc->memsize -= 4; 652 if(is_gx) 653 sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07; 654 else 655 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 656 657 /* XXX is there any way to calculate reference frequency from 658 known values? */ 659 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 660 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 661 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 662 aprint_normal_dev(sc->sc_dev, "ref_freq=29.498MHz\n"); 663 sc->ref_freq = 29498; 664 } else 665 sc->ref_freq = 14318; 666 667 reg = regr(sc, CLOCK_CNTL); 668 printf("CLOCK_CNTL: %08x\n", reg); 669 sc->sc_clock = reg & 3; 670 printf("using clock %d\n", sc->sc_clock); 671 672 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 673 printf("ref_div: %d\n", sc->ref_div); 674 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 675 printf("mclk_fb_div: %d\n", sc->mclk_fb_div); 676 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 677 (sc->ref_div * 2); 678 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 679 (sc->mem_freq * sc->ref_div); 680 sc->ramdac_freq = mach64_get_max_ramdac(sc); 681 aprint_normal_dev(sc->sc_dev, 682 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 683 (u_long)sc->memsize, 684 memtype_names[sc->memtype], 685 sc->mem_freq / 1000, sc->mem_freq % 1000, 686 sc->ramdac_freq / 1000); 687 688 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 689 switch(mach64_chip_id) { 690 case PCI_PRODUCT_ATI_MACH64_GX: 691 expected_id = 0x00d7; 692 break; 693 case PCI_PRODUCT_ATI_MACH64_CX: 694 expected_id = 0x0057; 695 break; 696 default: 697 /* Most chip IDs match their PCI product ID. */ 698 expected_id = mach64_chip_id; 699 } 700 701 if (id != expected_id) { 702 aprint_error_dev(sc->sc_dev, 703 "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id); 704 return; 705 } 706 707 sc->sc_console = mach64_is_console(sc); 708 #ifdef DIAGNOSTIC 709 aprint_normal("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 710 #endif 711 #if defined(__sparc__) || defined(__powerpc__) 712 if (sc->sc_console) { 713 if (mode != NULL) { 714 memcpy(&default_mode, mode, sizeof(struct videomode)); 715 setmode = 1; 716 } else { 717 mach64_get_mode(sc, &default_mode); 718 setmode = 0; 719 } 720 sc->sc_my_mode = &default_mode; 721 } else { 722 /* fill in default_mode if it's empty */ 723 mach64_get_mode(sc, &default_mode); 724 if (default_mode.dot_clock == 0) { 725 memcpy(&default_mode, &mach64_modes[4], 726 sizeof(default_mode)); 727 } 728 sc->sc_my_mode = &default_mode; 729 setmode = 1; 730 } 731 #else 732 if (default_mode.dot_clock == 0) { 733 memcpy(&default_mode, &mach64_modes[0], 734 sizeof(default_mode)); 735 } 736 sc->sc_my_mode = &mach64_modes[0]; 737 setmode = 1; 738 #endif 739 740 sc->bits_per_pixel = 8; 741 sc->virt_x = sc->sc_my_mode->hdisplay; 742 sc->virt_y = sc->sc_my_mode->vdisplay; 743 sc->max_x = sc->virt_x - 1; 744 sc->max_y = (sc->memsize * 1024) / 745 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 746 747 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 748 749 mach64_init_engine(sc); 750 751 if (setmode) 752 mach64_modeswitch(sc, sc->sc_my_mode); 753 754 aprint_normal_dev(sc->sc_dev, 755 "initial resolution %dx%d at %d bpp\n", 756 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 757 sc->bits_per_pixel); 758 759 #ifdef __sparc__ 760 machfb_fbattach(sc); 761 #endif 762 763 wsfont_init(); 764 765 sc->sc_bg = WS_DEFAULT_BG; 766 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &mach64_accessops); 767 sc->vd.init_screen = mach64_init_screen; 768 769 mach64_init_lut(sc); 770 mach64_clearscreen(sc); 771 machfb_blank(sc, 0); /* unblank the screen */ 772 773 if (sc->sc_console) { 774 775 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 776 &defattr); 777 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 778 779 ri = &mach64_console_screen.scr_ri; 780 mach64_defaultscreen.textops = &ri->ri_ops; 781 mach64_defaultscreen.capabilities = ri->ri_caps; 782 mach64_defaultscreen.nrows = ri->ri_rows; 783 mach64_defaultscreen.ncols = ri->ri_cols; 784 785 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 786 vcons_replay_msgbuf(&mach64_console_screen); 787 } else { 788 /* 789 * since we're not the console we can postpone the rest 790 * until someone actually allocates a screen for us 791 */ 792 mach64_modeswitch(sc, sc->sc_my_mode); 793 } 794 795 aa.console = sc->sc_console; 796 aa.scrdata = &mach64_screenlist; 797 aa.accessops = &mach64_accessops; 798 aa.accesscookie = &sc->vd; 799 800 config_found(self, &aa, wsemuldisplaydevprint); 801 802 config_found_ia(self, "drm", aux, machfb_drm_print); 803 } 804 805 static int 806 machfb_drm_print(void *aux, const char *pnp) 807 { 808 if (pnp) 809 aprint_normal("direct rendering for %s", pnp); 810 return (UNSUPP); 811 } 812 813 static void 814 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 815 long *defattr) 816 { 817 struct mach64_softc *sc = cookie; 818 struct rasops_info *ri = &scr->scr_ri; 819 820 /* XXX for now */ 821 #define setmode 0 822 823 ri->ri_depth = sc->bits_per_pixel; 824 ri->ri_width = sc->sc_my_mode->hdisplay; 825 ri->ri_height = sc->sc_my_mode->vdisplay; 826 ri->ri_stride = ri->ri_width; 827 ri->ri_flg = RI_CENTER; 828 set_address(ri, sc->sc_aperture); 829 830 #ifdef VCONS_DRAW_INTR 831 scr->scr_flags |= VCONS_DONT_READ; 832 #endif 833 834 if (existing) { 835 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 836 panic("%s: failed to switch video mode", 837 device_xname(sc->sc_dev)); 838 } 839 } 840 841 rasops_init(ri, sc->sc_my_mode->vdisplay / 8, 842 sc->sc_my_mode->hdisplay / 8); 843 ri->ri_caps = WSSCREEN_WSCOLORS; 844 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 845 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 846 847 /* enable acceleration */ 848 ri->ri_hw = scr; 849 ri->ri_ops.copyrows = mach64_copyrows; 850 ri->ri_ops.copycols = mach64_copycols; 851 ri->ri_ops.eraserows = mach64_eraserows; 852 ri->ri_ops.erasecols = mach64_erasecols; 853 ri->ri_ops.cursor = mach64_cursor; 854 ri->ri_ops.putchar = mach64_putchar; 855 } 856 857 static void 858 mach64_init(struct mach64_softc *sc) 859 { 860 uint32_t *p32, saved_value; 861 uint8_t *p; 862 int need_swap; 863 864 /* 865 * Test wether the aperture is byte swapped or not 866 */ 867 p32 = (uint32_t*)sc->sc_aperture; 868 saved_value = *p32; 869 p = (uint8_t*)(u_long)sc->sc_aperture; 870 *p32 = 0x12345678; 871 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 872 need_swap = 0; 873 else 874 need_swap = 1; 875 if (need_swap) { 876 sc->sc_aperture = (char *)sc->sc_aperture + 0x800000; 877 #if 0 878 /* what the fsck is this for? */ 879 sc->sc_aperbase += 0x800000; 880 sc->sc_apersize -= 0x800000; 881 #endif 882 } 883 *p32 = saved_value; 884 885 sc->sc_blanked = 0; 886 } 887 888 static int 889 mach64_get_memsize(struct mach64_softc *sc) 890 { 891 int tmp, memsize; 892 int mem_tab[] = { 893 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 894 }; 895 tmp = regr(sc, MEM_CNTL); 896 #ifdef DIAGNOSTIC 897 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 898 #endif 899 if (sc->has_dsp) { 900 tmp &= 0x0000000f; 901 if (tmp < 8) 902 memsize = (tmp + 1) * 512; 903 else if (tmp < 12) 904 memsize = (tmp - 3) * 1024; 905 else 906 memsize = (tmp - 7) * 2048; 907 } else { 908 memsize = mem_tab[tmp & 0x07]; 909 } 910 911 return memsize; 912 } 913 914 static int 915 mach64_get_max_ramdac(struct mach64_softc *sc) 916 { 917 int i; 918 919 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 920 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 921 (mach64_chip_rev & 0x07)) 922 return 170000; 923 924 for (i = 0; i < __arraycount(mach64_info); i++) 925 if (mach64_chip_id == mach64_info[i].chip_id) 926 return mach64_info[i].ramdac_freq; 927 928 if (sc->bits_per_pixel == 8) 929 return 135000; 930 else 931 return 80000; 932 } 933 934 #if defined(__sparc__) || defined(__powerpc__) 935 static void 936 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 937 { 938 struct mach64_crtcregs crtc; 939 940 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 941 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 942 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 943 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 944 945 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 946 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 947 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 948 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 949 mode->hsync_start; 950 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 951 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 952 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 953 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 954 955 #ifdef MACHFB_DEBUG 956 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 957 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 958 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 959 #endif 960 } 961 #endif 962 963 static int 964 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 965 struct videomode *mode) 966 { 967 968 if (mode->dot_clock > sc->ramdac_freq) 969 /* Clock too high. */ 970 return 1; 971 972 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 973 ((mode->htotal >> 3) - 1); 974 crtc->h_sync_strt_wid = 975 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 976 ((mode->hsync_start >> 3) - 1); 977 978 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 979 (mode->vtotal - 1); 980 crtc->v_sync_strt_wid = 981 ((mode->vsync_end - mode->vsync_start) << 16) | 982 (mode->vsync_start - 1); 983 984 if (mode->flags & VID_NVSYNC) 985 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 986 987 switch (sc->bits_per_pixel) { 988 case 8: 989 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 990 break; 991 case 16: 992 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 993 break; 994 case 32: 995 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 996 break; 997 } 998 999 crtc->gen_cntl = 0; 1000 if (mode->flags & VID_INTERLACE) 1001 crtc->gen_cntl |= CRTC_INTERLACE_EN; 1002 1003 if (mode->flags & VID_CSYNC) 1004 crtc->gen_cntl |= CRTC_CSYNC_EN; 1005 1006 crtc->dot_clock = mode->dot_clock; 1007 1008 return 0; 1009 } 1010 1011 static void 1012 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 1013 { 1014 1015 mach64_set_pll(sc, crtc->dot_clock); 1016 1017 if (sc->has_dsp) 1018 mach64_set_dsp(sc); 1019 #if 1 1020 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 1021 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1022 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 1023 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1024 1025 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 1026 1027 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1028 1029 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 1030 /* XXX this unconditionally enables composite sync on SPARC */ 1031 #ifdef __sparc__ 1032 CRTC_CSYNC_EN | 1033 #endif 1034 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 1035 #endif 1036 } 1037 1038 static int 1039 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 1040 { 1041 struct mach64_crtcregs crtc; 1042 1043 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 1044 1045 if (mach64_calc_crtcregs(sc, &crtc, mode)) 1046 return 1; 1047 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 1048 if (crtc.dot_clock == 0) { 1049 aprint_error("%s: preposterous dot clock (%d)\n", 1050 device_xname(sc->sc_dev), crtc.dot_clock); 1051 return 1; 1052 } 1053 mach64_set_crtcregs(sc, &crtc); 1054 return 0; 1055 } 1056 1057 static void 1058 mach64_reset_engine(struct mach64_softc *sc) 1059 { 1060 1061 /* Reset engine.*/ 1062 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1063 1064 /* Enable engine. */ 1065 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1066 1067 /* Ensure engine is not locked up by clearing any FIFO or 1068 host errors. */ 1069 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1070 BUS_FIFO_ERR_ACK); 1071 } 1072 1073 static void 1074 mach64_init_engine(struct mach64_softc *sc) 1075 { 1076 uint32_t pitch_value; 1077 1078 pitch_value = sc->virt_x; 1079 1080 if (sc->bits_per_pixel == 24) 1081 pitch_value *= 3; 1082 1083 mach64_reset_engine(sc); 1084 1085 wait_for_fifo(sc, 14); 1086 1087 regw(sc, CONTEXT_MASK, 0xffffffff); 1088 1089 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 1090 1091 /* make sure the visible area starts where we're going to draw */ 1092 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1093 1094 regw(sc, DST_Y_X, 0); 1095 regw(sc, DST_HEIGHT, 0); 1096 regw(sc, DST_BRES_ERR, 0); 1097 regw(sc, DST_BRES_INC, 0); 1098 regw(sc, DST_BRES_DEC, 0); 1099 1100 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1101 DST_Y_TOP_TO_BOTTOM); 1102 1103 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 1104 1105 regw(sc, SRC_Y_X, 0); 1106 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1107 regw(sc, SRC_Y_X_START, 0); 1108 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1109 1110 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1111 1112 wait_for_fifo(sc, 13); 1113 regw(sc, HOST_CNTL, 0); 1114 1115 regw(sc, PAT_REG0, 0); 1116 regw(sc, PAT_REG1, 0); 1117 regw(sc, PAT_CNTL, 0); 1118 1119 regw(sc, SC_LEFT, 0); 1120 regw(sc, SC_TOP, 0); 1121 regw(sc, SC_BOTTOM, sc->sc_my_mode->vdisplay - 1); 1122 regw(sc, SC_RIGHT, pitch_value - 1); 1123 1124 regw(sc, DP_BKGD_CLR, WS_DEFAULT_BG); 1125 regw(sc, DP_FRGD_CLR, WS_DEFAULT_FG); 1126 regw(sc, DP_WRITE_MASK, 0xffffffff); 1127 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1128 1129 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1130 1131 wait_for_fifo(sc, 3); 1132 regw(sc, CLR_CMP_CLR, 0); 1133 regw(sc, CLR_CMP_MASK, 0xffffffff); 1134 regw(sc, CLR_CMP_CNTL, 0); 1135 1136 wait_for_fifo(sc, 2); 1137 switch (sc->bits_per_pixel) { 1138 case 8: 1139 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP); 1140 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1141 /* We want 8 bit per channel */ 1142 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1143 break; 1144 case 32: 1145 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP); 1146 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1147 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1148 break; 1149 } 1150 1151 wait_for_fifo(sc, 5); 1152 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1153 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1154 1155 wait_for_idle(sc); 1156 } 1157 1158 #if 0 1159 static void 1160 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1161 { 1162 int offset; 1163 1164 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1165 1166 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1167 offset); 1168 } 1169 #endif 1170 1171 static void 1172 mach64_set_dsp(struct mach64_softc *sc) 1173 { 1174 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1175 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1176 uint32_t xclks_per_qw, y; 1177 uint32_t fifo_off, fifo_on; 1178 1179 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1180 1181 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1182 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1183 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1184 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1185 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1186 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1187 dsp_loop_latency = 0; 1188 fifo_depth = 24; 1189 } else { 1190 dsp_loop_latency = 2; 1191 fifo_depth = 32; 1192 } 1193 1194 dsp_precision = 0; 1195 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1196 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1197 y = (xclks_per_qw * fifo_depth) >> 11; 1198 while (y) { 1199 y >>= 1; 1200 dsp_precision++; 1201 } 1202 dsp_precision -= 5; 1203 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1204 1205 switch (sc->memtype) { 1206 case DRAM: 1207 case EDO_DRAM: 1208 case PSEUDO_EDO: 1209 if (sc->memsize > 1024) { 1210 page_size = 9; 1211 dsp_loop_latency += 6; 1212 } else { 1213 page_size = 10; 1214 if (sc->memtype == DRAM) 1215 dsp_loop_latency += 8; 1216 else 1217 dsp_loop_latency += 7; 1218 } 1219 break; 1220 case SDRAM: 1221 case SGRAM: 1222 if (sc->memsize > 1024) { 1223 page_size = 8; 1224 dsp_loop_latency += 8; 1225 } else { 1226 page_size = 10; 1227 dsp_loop_latency += 9; 1228 } 1229 break; 1230 default: 1231 page_size = 10; 1232 dsp_loop_latency += 9; 1233 break; 1234 } 1235 1236 if (xclks_per_qw >= (page_size << 11)) 1237 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1238 else 1239 fifo_on = (3 * page_size + 2) << 6; 1240 1241 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1242 dsp_on = fifo_on >> dsp_precision; 1243 dsp_off = fifo_off >> dsp_precision; 1244 1245 #ifdef MACHFB_DEBUG 1246 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1247 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1248 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1249 "mclk_post_div = %d, vclk_post_div = %d\n", 1250 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1251 sc->mclk_fb_div, sc->vclk_fb_div, 1252 sc->mclk_post_div, sc->vclk_post_div); 1253 #endif 1254 1255 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1256 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1257 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1258 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1259 } 1260 1261 static void 1262 mach64_set_pll(struct mach64_softc *sc, int clock) 1263 { 1264 uint32_t q, clockreg; 1265 int clockshift = sc->sc_clock << 1; 1266 uint8_t reg, vclk_ctl; 1267 1268 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1269 #ifdef MACHFB_DEBUG 1270 printf("q = %d\n", q); 1271 #endif 1272 if (q > 25500) { 1273 printf("Warning: q > 25500\n"); 1274 q = 25500; 1275 sc->vclk_post_div = 1; 1276 sc->log2_vclk_post_div = 0; 1277 } else if (q > 12750) { 1278 sc->vclk_post_div = 1; 1279 sc->log2_vclk_post_div = 0; 1280 } else if (q > 6350) { 1281 sc->vclk_post_div = 2; 1282 sc->log2_vclk_post_div = 1; 1283 } else if (q > 3150) { 1284 sc->vclk_post_div = 4; 1285 sc->log2_vclk_post_div = 2; 1286 } else if (q >= 1600) { 1287 sc->vclk_post_div = 8; 1288 sc->log2_vclk_post_div = 3; 1289 } else { 1290 printf("Warning: q < 1600\n"); 1291 sc->vclk_post_div = 8; 1292 sc->log2_vclk_post_div = 3; 1293 } 1294 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1295 printf("post_div: %d log2_post_div: %d mclk_div: %d\n", sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1296 1297 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1298 printf("vclk_ctl: %02x\n", vclk_ctl); 1299 vclk_ctl |= PLL_VCLK_RESET; 1300 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1301 1302 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1303 reg = regrb_pll(sc, VCLK_POST_DIV); 1304 reg &= ~(3 << clockshift); 1305 reg |= (sc->log2_vclk_post_div << clockshift); 1306 regwb_pll(sc, VCLK_POST_DIV, reg); 1307 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1308 1309 vclk_ctl &= ~PLL_VCLK_RESET; 1310 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1311 1312 clockreg = regr(sc, CLOCK_CNTL); 1313 clockreg &= ~CLOCK_SEL; 1314 clockreg |= sc->sc_clock | CLOCK_STROBE; 1315 regw(sc, CLOCK_CNTL, clockreg); 1316 } 1317 1318 static void 1319 mach64_init_lut(struct mach64_softc *sc) 1320 { 1321 int i, idx; 1322 1323 idx = 0; 1324 for (i = 0; i < 256; i++) { 1325 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1], 1326 rasops_cmap[idx + 2]); 1327 idx += 3; 1328 } 1329 } 1330 1331 static int 1332 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1333 uint8_t b) 1334 { 1335 sc->sc_cmap_red[index] = r; 1336 sc->sc_cmap_green[index] = g; 1337 sc->sc_cmap_blue[index] = b; 1338 /* 1339 * writing the dac index takes a while, in theory we can poll some 1340 * register to see when it's ready - but we better avoid writing it 1341 * unnecessarily 1342 */ 1343 if (index != sc->sc_dacw) { 1344 regwb(sc, DAC_MASK, 0xff); 1345 regwb(sc, DAC_WINDEX, index); 1346 } 1347 sc->sc_dacw = index + 1; 1348 regwb(sc, DAC_DATA, r); 1349 regwb(sc, DAC_DATA, g); 1350 regwb(sc, DAC_DATA, b); 1351 return 0; 1352 } 1353 1354 static int 1355 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1356 { 1357 uint index = cm->index; 1358 uint count = cm->count; 1359 int i, error; 1360 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1361 uint8_t *r, *g, *b; 1362 1363 if (cm->index >= 256 || cm->count > 256 || 1364 (cm->index + cm->count) > 256) 1365 return EINVAL; 1366 error = copyin(cm->red, &rbuf[index], count); 1367 if (error) 1368 return error; 1369 error = copyin(cm->green, &gbuf[index], count); 1370 if (error) 1371 return error; 1372 error = copyin(cm->blue, &bbuf[index], count); 1373 if (error) 1374 return error; 1375 1376 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1377 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1378 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1379 1380 r = &sc->sc_cmap_red[index]; 1381 g = &sc->sc_cmap_green[index]; 1382 b = &sc->sc_cmap_blue[index]; 1383 1384 for (i = 0; i < count; i++) { 1385 mach64_putpalreg(sc, index, *r, *g, *b); 1386 index++; 1387 r++, g++, b++; 1388 } 1389 return 0; 1390 } 1391 1392 static int 1393 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1394 { 1395 u_int index = cm->index; 1396 u_int count = cm->count; 1397 int error; 1398 1399 if (index >= 255 || count > 256 || index + count > 256) 1400 return EINVAL; 1401 1402 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1403 if (error) 1404 return error; 1405 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1406 if (error) 1407 return error; 1408 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1409 if (error) 1410 return error; 1411 1412 return 0; 1413 } 1414 1415 static int 1416 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1417 { 1418 struct mach64_crtcregs regs; 1419 1420 if (mach64_calc_crtcregs(sc, ®s, 1421 (struct videomode *)des->modecookie)) 1422 return 1; 1423 1424 mach64_set_crtcregs(sc, ®s); 1425 return 0; 1426 } 1427 1428 static int 1429 mach64_is_console(struct mach64_softc *sc) 1430 { 1431 bool console = 0; 1432 1433 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1434 "is_console", &console); 1435 return console; 1436 } 1437 1438 /* 1439 * wsdisplay_emulops 1440 */ 1441 1442 static void 1443 mach64_cursor(void *cookie, int on, int row, int col) 1444 { 1445 struct rasops_info *ri = cookie; 1446 struct vcons_screen *scr = ri->ri_hw; 1447 struct mach64_softc *sc = scr->scr_cookie; 1448 int x, y, wi, he; 1449 1450 wi = ri->ri_font->fontwidth; 1451 he = ri->ri_font->fontheight; 1452 1453 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1454 x = ri->ri_ccol * wi + ri->ri_xorigin; 1455 y = ri->ri_crow * he + ri->ri_yorigin; 1456 if (ri->ri_flg & RI_CURSOR) { 1457 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1458 0xff); 1459 ri->ri_flg &= ~RI_CURSOR; 1460 } 1461 ri->ri_crow = row; 1462 ri->ri_ccol = col; 1463 if (on) { 1464 x = ri->ri_ccol * wi + ri->ri_xorigin; 1465 y = ri->ri_crow * he + ri->ri_yorigin; 1466 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1467 0xff); 1468 ri->ri_flg |= RI_CURSOR; 1469 } 1470 } else { 1471 scr->scr_ri.ri_crow = row; 1472 scr->scr_ri.ri_ccol = col; 1473 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1474 } 1475 } 1476 1477 #if 0 1478 static int 1479 mach64_mapchar(void *cookie, int uni, u_int *index) 1480 { 1481 return 0; 1482 } 1483 #endif 1484 1485 static void 1486 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1487 { 1488 struct rasops_info *ri = cookie; 1489 struct wsdisplay_font *font = PICK_FONT(ri, c); 1490 struct vcons_screen *scr = ri->ri_hw; 1491 struct mach64_softc *sc = scr->scr_cookie; 1492 1493 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1494 int fg, bg, uc; 1495 uint8_t *data; 1496 int x, y, wi, he; 1497 wi = font->fontwidth; 1498 he = font->fontheight; 1499 1500 if (!CHAR_IN_FONT(c, font)) 1501 return; 1502 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1503 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f]; 1504 x = ri->ri_xorigin + col * wi; 1505 y = ri->ri_yorigin + row * he; 1506 if (c == 0x20) { 1507 mach64_rectfill(sc, x, y, wi, he, bg); 1508 } else { 1509 uc = c - font->firstchar; 1510 data = (uint8_t *)font->data + uc * 1511 ri->ri_fontscale; 1512 1513 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1514 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1515 } 1516 } 1517 } 1518 1519 1520 static void 1521 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1522 { 1523 struct rasops_info *ri = cookie; 1524 struct vcons_screen *scr = ri->ri_hw; 1525 struct mach64_softc *sc = scr->scr_cookie; 1526 int32_t xs, xd, y, width, height; 1527 1528 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1529 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1530 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1531 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1532 width = ri->ri_font->fontwidth * ncols; 1533 height = ri->ri_font->fontheight; 1534 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff); 1535 } 1536 } 1537 1538 static void 1539 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1540 { 1541 struct rasops_info *ri = cookie; 1542 struct vcons_screen *scr = ri->ri_hw; 1543 struct mach64_softc *sc = scr->scr_cookie; 1544 int32_t x, y, width, height, fg, bg, ul; 1545 1546 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1547 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1548 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1549 width = ri->ri_font->fontwidth * ncols; 1550 height = ri->ri_font->fontheight; 1551 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1552 1553 mach64_rectfill(sc, x, y, width, height, bg); 1554 } 1555 } 1556 1557 static void 1558 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1559 { 1560 struct rasops_info *ri = cookie; 1561 struct vcons_screen *scr = ri->ri_hw; 1562 struct mach64_softc *sc = scr->scr_cookie; 1563 int32_t x, ys, yd, width, height; 1564 1565 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1566 x = ri->ri_xorigin; 1567 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1568 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1569 width = ri->ri_emuwidth; 1570 height = ri->ri_font->fontheight*nrows; 1571 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff); 1572 } 1573 } 1574 1575 static void 1576 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1577 { 1578 struct rasops_info *ri = cookie; 1579 struct vcons_screen *scr = ri->ri_hw; 1580 struct mach64_softc *sc = scr->scr_cookie; 1581 int32_t x, y, width, height, fg, bg, ul; 1582 1583 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1584 x = ri->ri_xorigin; 1585 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1586 width = ri->ri_emuwidth; 1587 height = ri->ri_font->fontheight * nrows; 1588 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1589 1590 mach64_rectfill(sc, x, y, width, height, bg); 1591 } 1592 } 1593 1594 static void 1595 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1596 { 1597 uint32_t dest_ctl = 0; 1598 1599 wait_for_idle(sc); 1600 regw(sc, DP_WRITE_MASK, mask); /* XXX only good for 8 bit */ 1601 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1602 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1603 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1604 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1605 if (yd < ys) { 1606 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1607 } else { 1608 ys += height - 1; 1609 yd += height - 1; 1610 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1611 } 1612 if (xd < xs) { 1613 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1614 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1615 } else { 1616 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1617 xs += width - 1; 1618 xd += width - 1; 1619 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1620 } 1621 regw(sc, DST_CNTL, dest_ctl); 1622 1623 regw(sc, SRC_Y_X, (xs << 16) | ys); 1624 regw(sc, SRC_WIDTH1, width); 1625 regw(sc, DST_Y_X, (xd << 16) | yd); 1626 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1627 } 1628 1629 static void 1630 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1631 int height, uint32_t fg, uint32_t bg) 1632 { 1633 wait_for_idle(sc); 1634 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1635 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1636 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1637 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1638 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1639 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1640 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1641 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1642 regw(sc, DP_BKGD_CLR, bg); 1643 regw(sc, DP_FRGD_CLR, fg); 1644 regw(sc, SRC_Y_X, 0); 1645 regw(sc, SRC_WIDTH1, width); 1646 regw(sc, DST_Y_X, (xd << 16) | yd); 1647 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1648 /* now feed the data into the chip */ 1649 } 1650 1651 static void 1652 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1653 { 1654 int i; 1655 uint32_t latch = 0, bork; 1656 int shift = 0; 1657 int reg = 0; 1658 1659 for (i = 0; i < count; i++) { 1660 bork = data[i]; 1661 latch |= (bork << shift); 1662 if (shift == 24) { 1663 regw(sc, HOST_DATA0 + reg, latch); 1664 latch = 0; 1665 shift = 0; 1666 reg = (reg + 4) & 0x3c; 1667 } else 1668 shift += 8; 1669 } 1670 if (shift != 0) /* 24 */ 1671 regw(sc, HOST_DATA0 + reg, latch); 1672 } 1673 1674 1675 static void 1676 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1677 int colour) 1678 { 1679 wait_for_idle(sc); 1680 regw(sc, DP_WRITE_MASK, 0xff); 1681 regw(sc, DP_FRGD_CLR, colour); 1682 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1683 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1684 regw(sc, DP_MIX, MIX_SRC << 16); 1685 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1686 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1687 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1688 1689 regw(sc, SRC_Y_X, (x << 16) | y); 1690 regw(sc, SRC_WIDTH1, width); 1691 regw(sc, DST_Y_X, (x << 16) | y); 1692 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1693 } 1694 1695 static void 1696 mach64_clearscreen(struct mach64_softc *sc) 1697 { 1698 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1699 } 1700 1701 1702 #if 0 1703 static void 1704 mach64_showpal(struct mach64_softc *sc) 1705 { 1706 int i, x = 0; 1707 1708 for (i = 0; i < 16; i++) { 1709 mach64_rectfill(sc, x, 0, 64, 64, i); 1710 x += 64; 1711 } 1712 } 1713 #endif 1714 1715 /* 1716 * wsdisplay_accessops 1717 */ 1718 1719 static int 1720 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1721 struct lwp *l) 1722 { 1723 struct vcons_data *vd = v; 1724 struct mach64_softc *sc = vd->cookie; 1725 struct wsdisplay_fbinfo *wdf; 1726 struct vcons_screen *ms = vd->active; 1727 1728 switch (cmd) { 1729 case WSDISPLAYIO_GTYPE: 1730 /* XXX is this the right type to return? */ 1731 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1732 return 0; 1733 1734 case WSDISPLAYIO_LINEBYTES: 1735 *(u_int *)data = sc->virt_x * sc->bits_per_pixel / 8; 1736 return 0; 1737 1738 case WSDISPLAYIO_GINFO: 1739 wdf = (void *)data; 1740 wdf->height = sc->virt_y; 1741 wdf->width = sc->virt_x; 1742 wdf->depth = sc->bits_per_pixel; 1743 wdf->cmsize = 256; 1744 return 0; 1745 1746 case WSDISPLAYIO_GETCMAP: 1747 return mach64_getcmap(sc, 1748 (struct wsdisplay_cmap *)data); 1749 1750 case WSDISPLAYIO_PUTCMAP: 1751 return mach64_putcmap(sc, 1752 (struct wsdisplay_cmap *)data); 1753 1754 /* PCI config read/write passthrough. */ 1755 case PCI_IOC_CFGREAD: 1756 case PCI_IOC_CFGWRITE: 1757 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1758 cmd, data, flag, l); 1759 1760 case WSDISPLAYIO_GET_BUSID: 1761 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1762 sc->sc_pcitag, data); 1763 1764 case WSDISPLAYIO_SMODE: { 1765 int new_mode = *(int*)data; 1766 if (new_mode != sc->sc_mode) { 1767 sc->sc_mode = new_mode; 1768 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1769 && (ms != NULL)) 1770 { 1771 /* restore initial video mode */ 1772 mach64_init(sc); 1773 mach64_init_engine(sc); 1774 mach64_init_lut(sc); 1775 mach64_modeswitch(sc, sc->sc_my_mode); 1776 vcons_redraw_screen(ms); 1777 } 1778 } 1779 } 1780 return 0; 1781 1782 } 1783 return EPASSTHROUGH; 1784 } 1785 1786 static paddr_t 1787 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1788 { 1789 struct vcons_data *vd = v; 1790 struct mach64_softc *sc = vd->cookie; 1791 paddr_t pa; 1792 pcireg_t reg; 1793 1794 #ifndef __sparc64__ 1795 /* 1796 *'regular' framebuffer mmap()ing 1797 * disabled on sparc64 because some ATI firmware likes to map some PCI 1798 * resources to addresses that would collide with this ( like some Rage 1799 * IIc which uses 0x2000 for the 2nd register block ) 1800 * Other 64bit architectures might run into similar problems. 1801 */ 1802 if (offset<sc->sc_apersize) { 1803 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, offset, 1804 prot, BUS_SPACE_MAP_LINEAR); 1805 return pa; 1806 } 1807 #endif 1808 1809 /* 1810 * restrict all other mappings to processes with superuser privileges 1811 * or the kernel itself 1812 */ 1813 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1814 NULL) != 0) { 1815 return -1; 1816 } 1817 1818 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1819 if (reg != sc->sc_regphys) { 1820 #ifdef DIAGNOSTIC 1821 printf("%s: BAR 0x18 changed! (%x %x)\n", 1822 device_xname(sc->sc_dev), (uint32_t)sc->sc_regphys, 1823 (uint32_t)reg); 1824 #endif 1825 sc->sc_regphys = reg; 1826 } 1827 1828 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1829 if (reg != sc->sc_aperphys) { 1830 #ifdef DIAGNOSTIC 1831 printf("%s: BAR 0x10 changed! (%x %x)\n", 1832 device_xname(sc->sc_dev), (uint32_t)sc->sc_aperphys, 1833 (uint32_t)reg); 1834 #endif 1835 sc->sc_aperphys = reg; 1836 } 1837 1838 if ((offset >= sc->sc_aperphys) && 1839 (offset < (sc->sc_aperphys + sc->sc_apersize))) { 1840 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1841 BUS_SPACE_MAP_LINEAR); 1842 return pa; 1843 } 1844 1845 if ((offset >= sc->sc_regphys) && 1846 (offset < (sc->sc_regphys + sc->sc_regsize))) { 1847 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1848 BUS_SPACE_MAP_LINEAR); 1849 return pa; 1850 } 1851 1852 if ((offset >= sc->sc_rom.vb_base) && 1853 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 1854 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1855 BUS_SPACE_MAP_LINEAR); 1856 return pa; 1857 } 1858 1859 #ifdef PCI_MAGIC_IO_RANGE 1860 if ((offset >= PCI_MAGIC_IO_RANGE) && 1861 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 1862 return bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1863 0, prot, BUS_SPACE_MAP_LINEAR); 1864 } 1865 #endif 1866 1867 return -1; 1868 } 1869 1870 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1871 static void 1872 set_address(struct rasops_info *ri, void *fb) 1873 { 1874 #ifdef notdef 1875 printf(" %d %d %d\n", ri->ri_xorigin, ri->ri_yorigin, ri->ri_stride); 1876 #endif 1877 ri->ri_bits = (void *)((char *)fb + ri->ri_stride * ri->ri_yorigin + 1878 ri->ri_xorigin); 1879 } 1880 1881 #if 0 1882 static int 1883 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1884 { 1885 1886 return 0; 1887 } 1888 #endif 1889 1890 void 1891 machfb_blank(struct mach64_softc *sc, int blank) 1892 { 1893 uint32_t reg; 1894 1895 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1896 1897 switch (blank) 1898 { 1899 case 0: 1900 reg = regr(sc, CRTC_GEN_CNTL); 1901 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1902 sc->sc_blanked = 0; 1903 break; 1904 case 1: 1905 reg = regr(sc, CRTC_GEN_CNTL); 1906 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1907 sc->sc_blanked = 1; 1908 break; 1909 default: 1910 break; 1911 } 1912 } 1913 1914 /* framebuffer device support */ 1915 #ifdef __sparc__ 1916 1917 static void 1918 machfb_unblank(device_t dev) 1919 { 1920 struct mach64_softc *sc = device_private(dev); 1921 1922 machfb_blank(sc, 0); 1923 } 1924 1925 static void 1926 machfb_fbattach(struct mach64_softc *sc) 1927 { 1928 struct fbdevice *fb = &sc->sc_fb; 1929 1930 fb->fb_device = sc->sc_dev; 1931 fb->fb_driver = &machfb_fbdriver; 1932 1933 fb->fb_type.fb_cmsize = 256; 1934 fb->fb_type.fb_size = sc->memsize; 1935 1936 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 1937 fb->fb_flags = sc->sc_dev->dv_cfdata->cf_flags & FB_USERMASK; 1938 fb->fb_type.fb_depth = sc->bits_per_pixel; 1939 fb->fb_type.fb_width = sc->virt_x; 1940 fb->fb_type.fb_height = sc->virt_y; 1941 1942 fb->fb_pixels = sc->sc_aperture; 1943 fb_attach(fb, sc->sc_console); 1944 } 1945 1946 int 1947 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 1948 { 1949 struct mach64_softc *sc; 1950 1951 sc = device_lookup_private(&machfb_cd, minor(dev)); 1952 if (sc == NULL) 1953 return ENXIO; 1954 sc->sc_locked = 1; 1955 1956 #ifdef MACHFB_DEBUG 1957 printf("machfb_fbopen(%d)\n", minor(dev)); 1958 #endif 1959 return 0; 1960 } 1961 1962 int 1963 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 1964 { 1965 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1966 1967 #ifdef MACHFB_DEBUG 1968 printf("machfb_fbclose()\n"); 1969 #endif 1970 mach64_init_engine(sc); 1971 mach64_init_lut(sc); 1972 sc->sc_locked = 0; 1973 return 0; 1974 } 1975 1976 int 1977 machfb_fbioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1978 { 1979 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1980 1981 #ifdef MACHFB_DEBUG 1982 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 1983 #endif 1984 switch (cmd) { 1985 case FBIOGTYPE: 1986 *(struct fbtype *)data = sc->sc_fb.fb_type; 1987 break; 1988 1989 case FBIOGATTR: 1990 #define fba ((struct fbgattr *)data) 1991 fba->real_type = sc->sc_fb.fb_type.fb_type; 1992 fba->owner = 0; /* XXX ??? */ 1993 fba->fbtype = sc->sc_fb.fb_type; 1994 fba->sattr.flags = 0; 1995 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 1996 fba->sattr.dev_specific[0] = sc->sc_nbus; 1997 fba->sattr.dev_specific[1] = sc->sc_ndev; 1998 fba->sattr.dev_specific[2] = sc->sc_nfunc; 1999 fba->sattr.dev_specific[3] = -1; 2000 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 2001 fba->emu_types[1] = -1; 2002 #undef fba 2003 break; 2004 2005 #if 0 2006 case FBIOGETCMAP: 2007 #define p ((struct fbcmap *)data) 2008 return bt_getcmap(p, &sc->sc_cmap, 256, 1); 2009 2010 case FBIOPUTCMAP: 2011 /* copy to software map */ 2012 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 2013 if (error) 2014 return error; 2015 /* now blast them into the chip */ 2016 /* XXX should use retrace interrupt */ 2017 cg6_loadcmap(sc, p->index, p->count); 2018 #undef p 2019 break; 2020 #endif 2021 case FBIOGVIDEO: 2022 *(int *)data = sc->sc_blanked; 2023 break; 2024 2025 case FBIOSVIDEO: 2026 machfb_blank(sc, *(int *)data); 2027 break; 2028 2029 #if 0 2030 case FBIOGCURSOR: 2031 break; 2032 2033 case FBIOSCURSOR: 2034 break; 2035 2036 case FBIOGCURPOS: 2037 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 2038 break; 2039 2040 case FBIOSCURPOS: 2041 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 2042 break; 2043 2044 case FBIOGCURMAX: 2045 /* max cursor size is 32x32 */ 2046 ((struct fbcurpos *)data)->x = 32; 2047 ((struct fbcurpos *)data)->y = 32; 2048 break; 2049 #endif 2050 case PCI_IOC_CFGREAD: 2051 case PCI_IOC_CFGWRITE: { 2052 int ret; 2053 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 2054 cmd, data, flags, l); 2055 2056 #ifdef MACHFB_DEBUG 2057 printf("pci_devioctl: %d\n", ret); 2058 #endif 2059 return ret; 2060 } 2061 2062 case WSDISPLAYIO_GET_BUSID: 2063 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 2064 sc->sc_pcitag, data); 2065 2066 default: 2067 #ifdef MACHFB_DEBUG 2068 log(LOG_NOTICE, "machfb_fbioctl(0x%lx) (%s[%d])\n", cmd, 2069 p->p_comm, p->p_pid); 2070 #endif 2071 return ENOTTY; 2072 } 2073 #ifdef MACHFB_DEBUG 2074 printf("machfb_fbioctl done\n"); 2075 #endif 2076 return 0; 2077 } 2078 2079 paddr_t 2080 machfb_fbmmap(dev_t dev, off_t off, int prot) 2081 { 2082 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 2083 2084 if (sc != NULL) 2085 return mach64_mmap(&sc->vd, NULL, off, prot); 2086 2087 return 0; 2088 } 2089 2090 #endif /* __sparc__ */ 2091
Indexes created Fri Oct 03 02:09:57 GMT 2025