machfb.c revision 1.6
1 /* $NetBSD: machfb.c,v 1.6 2002/10/29 17:54:40 junyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 32 */ 33 34 #include <sys/cdefs.h> 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/callout.h> 42 43 #ifdef __sparc__ 44 #include <machine/openfirm.h> 45 #endif 46 47 #include <dev/ic/videomode.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcidevs.h> 52 #include <dev/pci/pciio.h> 53 #include <dev/pci/machfbreg.h> 54 55 #include <dev/wscons/wsdisplayvar.h> 56 #include <dev/wscons/wsconsio.h> 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/rasops/rasops.h> 59 60 #define MACH64_REG_SIZE 1024 61 #define MACH64_REG_OFF 0x7ffc00 62 63 #define NBARS 3 /* number of Mach64 PCI BARs */ 64 65 struct vga_bar { 66 bus_addr_t vb_base; 67 bus_size_t vb_size; 68 pcireg_t vb_type; 69 int vb_flags; 70 }; 71 72 struct mach64_softc { 73 struct device sc_dev; 74 pci_chipset_tag_t sc_pc; 75 pcitag_t sc_pcitag; 76 77 struct vga_bar sc_bars[NBARS]; 78 struct vga_bar sc_rom; 79 80 #define sc_aperbase sc_bars[0].vb_base 81 #define sc_apersize sc_bars[0].vb_size 82 83 #define sc_iobase sc_bars[1].vb_base 84 #define sc_iosize sc_bars[1].vb_size 85 86 #define sc_regbase sc_bars[2].vb_base 87 #define sc_regsize sc_bars[2].vb_size 88 89 bus_space_tag_t sc_regt; 90 bus_space_tag_t sc_memt; 91 bus_space_handle_t sc_regh; 92 bus_space_handle_t sc_memh; 93 94 size_t memsize; 95 int memtype; 96 97 int has_dsp; 98 int bits_per_pixel; 99 int max_x, max_y; 100 int virt_x, virt_y; 101 int color_depth; 102 103 int mem_freq; 104 int ramdac_freq; 105 int ref_freq; 106 107 int ref_div; 108 int log2_vclk_post_div; 109 int vclk_post_div; 110 int vclk_fb_div; 111 int mclk_post_div; 112 int mclk_fb_div; 113 114 struct mach64screen *wanted; 115 struct mach64screen *active; 116 void (*switchcb)(void *, int, int); 117 void *switchcbarg; 118 struct callout switch_callout; 119 int nscreens; 120 LIST_HEAD(, mach64screen) screens; 121 const struct wsscreen_descr *currenttype; 122 }; 123 124 struct mach64screen { 125 LIST_ENTRY(mach64screen) next; 126 struct mach64_softc *sc; 127 const struct wsscreen_descr *type; 128 int active; 129 u_int16_t *mem; 130 int dispoffset; 131 int mindispoffset; 132 int maxdispoffset; 133 134 int cursoron; 135 int cursorcol; 136 int cursorrow; 137 u_int16_t cursortmp; 138 }; 139 140 struct mach64_crtcregs { 141 u_int32_t h_total_disp; 142 u_int32_t h_sync_strt_wid; 143 u_int32_t v_total_disp; 144 u_int32_t v_sync_strt_wid; 145 u_int32_t gen_cntl; 146 u_int32_t clock_cntl; 147 u_int32_t color_depth; 148 u_int32_t dot_clock; 149 }; 150 151 struct { 152 u_int16_t chip_id; 153 u_int32_t ramdac_freq; 154 } mach64_info[] = { 155 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 156 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 157 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 158 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 159 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 160 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 161 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 162 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 163 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 164 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 165 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 166 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 167 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 168 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 169 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 170 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 171 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 172 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 173 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 174 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 175 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 176 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 177 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 178 }; 179 180 static int mach64_chip_id, mach64_chip_rev; 181 static struct videomode default_mode; 182 struct rasops_info mach64_rasops_info; 183 static struct mach64screen mach64_console_screen; 184 185 static char *mach64_memtype_names[] = { 186 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 187 "(unknown type)" 188 }; 189 190 struct videomode mach64_modes[] = { 191 /* 640x400 @ 70 Hz, 31.5 kHz */ 192 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0 }, 193 /* 640x480 @ 72 Hz, 36.5 kHz */ 194 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0 }, 195 /* 800x600 @ 72 Hz, 48.0 kHz */ 196 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 197 VID_PHSYNC | VID_PVSYNC }, 198 /* 1024x768 @ 70 Hz, 56.5 kHz */ 199 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 200 VID_NHSYNC | VID_NVSYNC }, 201 /* 1152x864 @ 70 Hz, 62.4 kHz */ 202 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0 }, 203 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 204 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 205 VID_NHSYNC | VID_NVSYNC } 206 }; 207 208 /* FIXME values are wrong! */ 209 const u_char mach64_cmap[16 * 3] = { 210 0x00, 0x00, 0x00, /* black */ 211 0x7f, 0x00, 0x00, /* red */ 212 0x00, 0x7f, 0x00, /* green */ 213 0x7f, 0x7f, 0x00, /* brown */ 214 0x00, 0x00, 0x7f, /* blue */ 215 0x7f, 0x00, 0x7f, /* magenta */ 216 0x00, 0x7f, 0x7f, /* cyan */ 217 0xff, 0xff, 0xff, /* white */ 218 219 0x7f, 0x7f, 0x7f, /* black */ 220 0xff, 0x00, 0x00, /* red */ 221 0x00, 0xff, 0x00, /* green */ 222 0xff, 0xff, 0x00, /* brown */ 223 0x00, 0x00, 0xff, /* blue */ 224 0xff, 0x00, 0xff, /* magenta */ 225 0x00, 0xff, 0xff, /* cyan */ 226 0xff, 0xff, 0xff, /* white */ 227 }; 228 229 int mach64_match(struct device *, struct cfdata *, void *); 230 void mach64_attach(struct device *, struct device *, void *); 231 232 CFATTACH_DECL(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 233 NULL, NULL); 234 235 void mach64_init(struct mach64_softc *); 236 int mach64_get_memsize(struct mach64_softc *); 237 int mach64_get_max_ramdac(struct mach64_softc *); 238 void mach64_get_mode(struct mach64_softc *, struct videomode *); 239 int mach64_calc_crtcregs(struct mach64_softc *, struct mach64_crtcregs *, 240 struct videomode *); 241 void mach64_set_crtcregs(struct mach64_softc *, struct mach64_crtcregs *); 242 int mach64_modeswitch(struct mach64_softc *, struct videomode *); 243 void mach64_set_dsp(struct mach64_softc *); 244 void mach64_set_pll(struct mach64_softc *, int); 245 void mach64_reset_engine(struct mach64_softc *); 246 void mach64_init_engine(struct mach64_softc *); 247 void mach64_adjust_frame(struct mach64_softc *, int, int); 248 void mach64_init_lut(struct mach64_softc *); 249 void mach64_switch_screen(struct mach64_softc *); 250 void mach64_init_screen(struct mach64_softc *, struct mach64screen *, 251 const struct wsscreen_descr *, int, long *, int); 252 void mach64_restore_screen(struct mach64screen *, 253 const struct wsscreen_descr *, u_int16_t *); 254 int mach64_set_screentype(struct mach64_softc *, 255 const struct wsscreen_descr *); 256 int mach64_is_console(struct pci_attach_args *); 257 258 void mach64_cursor(void *, int, int, int); 259 int mach64_mapchar(void *, int, u_int *); 260 void mach64_putchar(void *, int, int, u_int, long); 261 void mach64_copycols(void *, int, int, int, int); 262 void mach64_erasecols(void *, int, int, int, long); 263 void mach64_copyrows(void *, int, int, int); 264 void mach64_eraserows(void *, int, int, long); 265 int mach64_allocattr(void *, int, int, int, long *); 266 267 const struct wsdisplay_emulops mach64_emulops = { 268 mach64_cursor, 269 mach64_mapchar, 270 mach64_putchar, 271 mach64_copycols, 272 mach64_erasecols, 273 mach64_copyrows, 274 mach64_eraserows, 275 mach64_allocattr, 276 }; 277 278 struct wsscreen_descr mach64_defaultscreen = { 279 "default", 280 0, 0, 281 &mach64_rasops_info.ri_ops, 282 8, 16, 283 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 284 &default_mode 285 }, mach64_80x25_screen = { 286 "80x25", 80, 25, 287 &mach64_rasops_info.ri_ops, 288 8, 16, 289 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 290 &mach64_modes[0] 291 }, mach64_80x30_screen = { 292 "80x30", 80, 30, 293 &mach64_rasops_info.ri_ops, 294 8, 16, 295 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 296 &mach64_modes[1] 297 }, mach64_80x40_screen = { 298 "80x40", 80, 40, 299 &mach64_rasops_info.ri_ops, 300 8, 10, 301 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 302 &mach64_modes[0] 303 }, mach64_80x50_screen = { 304 "80x50", 80, 50, 305 &mach64_rasops_info.ri_ops, 306 8, 8, 307 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 308 &mach64_modes[0] 309 }, mach64_100x37_screen = { 310 "100x37", 100, 37, 311 &mach64_rasops_info.ri_ops, 312 8, 16, 313 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 314 &mach64_modes[2] 315 }, mach64_128x48_screen = { 316 "128x48", 128, 48, 317 &mach64_rasops_info.ri_ops, 318 8, 16, 319 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 320 &mach64_modes[3] 321 }, mach64_144x54_screen = { 322 "144x54", 144, 54, 323 &mach64_rasops_info.ri_ops, 324 8, 16, 325 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 326 &mach64_modes[4] 327 }, mach64_160x64_screen = { 328 "160x54", 160, 64, 329 &mach64_rasops_info.ri_ops, 330 8, 16, 331 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 332 &mach64_modes[5] 333 }; 334 335 const struct wsscreen_descr *_mach64_scrlist[] = { 336 &mach64_defaultscreen, 337 &mach64_80x25_screen, 338 &mach64_80x30_screen, 339 &mach64_80x40_screen, 340 &mach64_80x50_screen, 341 &mach64_100x37_screen, 342 &mach64_128x48_screen, 343 &mach64_144x54_screen, 344 &mach64_160x64_screen 345 }; 346 347 struct wsscreen_list mach64_screenlist = { 348 sizeof(_mach64_scrlist) / sizeof(struct wsscreen_descr *), 349 _mach64_scrlist 350 }; 351 352 int mach64_ioctl(void *, u_long, caddr_t, int, struct proc *); 353 paddr_t mach64_mmap(void *, off_t, int); 354 int mach64_alloc_screen(void *, const struct wsscreen_descr *, void **, 355 int *, int *, long *); 356 void mach64_free_screen(void *, void *); 357 int mach64_show_screen(void *, void *, int, void (*)(void *, int, int), 358 void *); 359 int mach64_load_font(void *, void *, struct wsdisplay_font *); 360 361 struct wsdisplay_accessops mach64_accessops = { 362 mach64_ioctl, 363 mach64_mmap, 364 mach64_alloc_screen, 365 mach64_free_screen, 366 mach64_show_screen, 367 NULL 368 }; 369 370 /* 371 * Inline functions for getting access to register aperture. 372 */ 373 static inline u_int32_t regr(struct mach64_softc *, u_int32_t); 374 static inline u_int8_t regrb(struct mach64_softc *, u_int32_t); 375 static inline void regw(struct mach64_softc *, u_int32_t, u_int32_t); 376 static inline void regwb(struct mach64_softc *, u_int32_t, u_int8_t); 377 static inline void regwb_pll(struct mach64_softc *, u_int32_t, u_int8_t); 378 379 static inline u_int32_t 380 regr(struct mach64_softc *sc, u_int32_t index) 381 { 382 383 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 384 } 385 386 static inline u_int8_t 387 regrb(struct mach64_softc *sc, u_int32_t index) 388 { 389 390 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 391 } 392 393 static inline void 394 regw(struct mach64_softc *sc, u_int32_t index, u_int32_t data) 395 { 396 397 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 398 } 399 400 static inline void 401 regwb(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 402 { 403 404 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 405 } 406 407 static inline void 408 regwb_pll(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 409 { 410 411 regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); 412 regwb(sc, CLOCK_CNTL + 2, data); 413 regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); 414 } 415 416 static inline void 417 wait_for_fifo(struct mach64_softc *sc, u_int8_t v) 418 { 419 420 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 421 ; 422 } 423 424 static inline void 425 wait_for_idle(struct mach64_softc *sc) 426 { 427 428 wait_for_fifo(sc, 16); 429 while ((regr(sc, GUI_STAT) & 1) != 0) 430 ; 431 } 432 433 int 434 mach64_match(struct device *parent, struct cfdata *match, void *aux) 435 { 436 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 437 int i; 438 439 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 440 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 441 return 0; 442 443 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 444 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 445 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 446 mach64_chip_rev = PCI_REVISION(pa->pa_class); 447 return 1; 448 } 449 450 return 0; 451 } 452 453 void 454 mach64_attach(struct device *parent, struct device *self, void *aux) 455 { 456 struct mach64_softc *sc = (void *)self; 457 struct pci_attach_args *pa = aux; 458 char devinfo[256]; 459 int bar, reg, id; 460 struct wsemuldisplaydev_attach_args aa; 461 int console; 462 long defattr; 463 int setmode; 464 465 sc->sc_pc = pa->pa_pc; 466 sc->sc_pcitag = pa->pa_tag; 467 468 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 469 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 470 471 for (bar = 0; bar < NBARS; bar++) { 472 reg = PCI_MAPREG_START + (bar * 4); 473 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 474 sc->sc_pcitag, reg); 475 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 476 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 477 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 478 } 479 sc->sc_memt = pa->pa_memt; 480 481 mach64_init(sc); 482 483 printf("%s: %d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 484 sc->sc_dev.dv_xname, (u_int)(sc->sc_apersize / (1024 * 1024)), 485 (u_int)sc->sc_aperbase, (u_int)(sc->sc_regsize / 1024), 486 (u_int)sc->sc_regbase); 487 488 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 489 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 490 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 491 (mach64_chip_rev & 0x07) == 0)) 492 sc->has_dsp = 0; 493 else 494 sc->has_dsp = 1; 495 496 sc->memsize = mach64_get_memsize(sc); 497 if (sc->memsize == 8192) 498 /* The last page is used as register aperture. */ 499 sc->memsize -= 4; 500 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 501 502 /* XXX is there any way to calculate reference frequency from 503 known values? */ 504 if (mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) 505 sc->ref_freq = 29498; 506 else 507 sc->ref_freq = 14318; 508 509 regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); 510 sc->ref_div = regrb(sc, CLOCK_CNTL + 2); 511 regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); 512 sc->mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); 513 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 514 (sc->ref_div * 2); 515 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 516 (sc->mem_freq * sc->ref_div); 517 sc->ramdac_freq = mach64_get_max_ramdac(sc); 518 printf("%s: %ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 519 sc->sc_dev.dv_xname, (u_long)sc->memsize, 520 mach64_memtype_names[sc->memtype], 521 sc->mem_freq / 1000, sc->mem_freq % 1000, 522 sc->ramdac_freq / 1000); 523 524 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 525 if (id != mach64_chip_id) { 526 printf("%s: chip ID mismatch, 0x%x != 0x%x\n", 527 sc->sc_dev.dv_xname, id, mach64_chip_id); 528 return; 529 } 530 531 #ifdef __sparc__ 532 mach64_get_mode(sc, &default_mode); 533 setmode = 0; 534 #else 535 memcpy(&default_mode, &mach64_modes[0], sizeof(struct videomode)); 536 setmode = 1; 537 #endif 538 539 sc->bits_per_pixel = 8; 540 sc->virt_x = default_mode.hdisplay; 541 sc->virt_y = default_mode.vdisplay; 542 sc->max_x = sc->virt_x - 1; 543 sc->max_y = (sc->memsize * 1024) / 544 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 545 546 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 547 548 mach64_init_engine(sc); 549 #if 0 550 mach64_adjust_frame(0, 0); 551 if (sc->bits_per_pixel == 8) 552 mach64_init_lut(sc); 553 #endif 554 555 printf("%s: initial resolution %dx%d at %d bpp\n", sc->sc_dev.dv_xname, 556 default_mode.hdisplay, default_mode.vdisplay, 557 sc->bits_per_pixel); 558 559 mach64_rasops_info.ri_depth = sc->bits_per_pixel; 560 mach64_rasops_info.ri_bits = (void *)sc->sc_aperbase; 561 mach64_rasops_info.ri_width = default_mode.hdisplay; 562 mach64_rasops_info.ri_height = default_mode.vdisplay; 563 mach64_rasops_info.ri_stride = mach64_rasops_info.ri_width; 564 mach64_rasops_info.ri_flg = RI_CLEAR; 565 566 rasops_init(&mach64_rasops_info, mach64_rasops_info.ri_height / 16, 567 mach64_rasops_info.ri_width / 8); 568 569 mach64_defaultscreen.nrows = mach64_rasops_info.ri_rows; 570 mach64_defaultscreen.ncols = mach64_rasops_info.ri_cols; 571 572 mach64_init_screen(sc, &mach64_console_screen, 573 &mach64_defaultscreen, 1, &defattr, setmode); 574 575 mach64_rasops_info.ri_ops.allocattr(&mach64_rasops_info, 0, 0, 0, 576 &defattr); 577 578 console = mach64_is_console(pa); 579 if (console) 580 wsdisplay_cnattach(&mach64_defaultscreen, &mach64_rasops_info, 581 0, 0, defattr); 582 583 aa.console = console; 584 aa.scrdata = &mach64_screenlist; 585 aa.accessops = &mach64_accessops; 586 aa.accesscookie = sc; 587 588 config_found(self, &aa, wsemuldisplaydevprint); 589 } 590 591 void 592 mach64_init_screen(struct mach64_softc *sc, struct mach64screen *scr, 593 const struct wsscreen_descr *type, int existing, long *attrp, int setmode) 594 { 595 596 scr->sc = sc; 597 scr->type = type; 598 scr->mindispoffset = 0; 599 scr->maxdispoffset = sc->memsize * 1024; 600 scr->dispoffset = 0; 601 scr->cursorcol = 0; 602 scr->cursorrow = 0; 603 604 if (existing) { 605 scr->mem = (u_int16_t *)malloc(type->nrows * type->ncols * 2, 606 M_DEVBUF, M_WAITOK); 607 scr->active = 1; 608 609 if (setmode && mach64_set_screentype(sc, type)) { 610 panic("%s: failed to switch video mode", 611 sc->sc_dev.dv_xname); 612 } 613 } else { 614 scr->active = 0; 615 scr->mem = NULL; 616 } 617 618 wsfont_init(); 619 620 sc->nscreens++; 621 LIST_INSERT_HEAD(&sc->screens, scr, next); 622 } 623 624 void 625 mach64_init(struct mach64_softc *sc) 626 { 627 628 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 629 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 630 panic("%s: failed to map aperture", sc->sc_dev.dv_xname); 631 } 632 sc->sc_aperbase = (vaddr_t)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 633 634 sc->sc_regt = sc->sc_memt; 635 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 636 sc->sc_regsize, &sc->sc_regh); 637 sc->sc_regbase = sc->sc_aperbase + 0x7ffc00; 638 639 #if _BYTE_ORDER == _BIG_ENDIAN 640 sc->sc_aperbase += 0x800000; 641 sc->sc_apersize -= 0x800000; 642 #endif 643 644 sc->nscreens = 0; 645 LIST_INIT(&sc->screens); 646 sc->active = NULL; 647 sc->currenttype = &mach64_defaultscreen; 648 callout_init(&sc->switch_callout); 649 } 650 651 int 652 mach64_get_memsize(struct mach64_softc *sc) 653 { 654 int tmp, memsize; 655 int mem_tab[] = { 656 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 657 }; 658 659 tmp = regr(sc, MEM_CNTL); 660 if (sc->has_dsp) { 661 tmp &= 0x0000000f; 662 if (tmp < 8) 663 memsize = (tmp + 1) * 512; 664 else if (tmp < 12) 665 memsize = (tmp - 3) * 1024; 666 else 667 memsize = (tmp - 7) * 2048; 668 } else { 669 memsize = mem_tab[tmp & 0x07]; 670 } 671 672 return memsize; 673 } 674 675 int 676 mach64_get_max_ramdac(struct mach64_softc *sc) 677 { 678 int i; 679 680 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 681 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 682 (mach64_chip_rev & 0x07)) 683 return 170000; 684 685 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 686 if (mach64_chip_id == mach64_info[i].chip_id) 687 return mach64_info[i].ramdac_freq; 688 689 if (sc->bits_per_pixel == 8) 690 return 135000; 691 else 692 return 80000; 693 } 694 695 void 696 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 697 { 698 struct mach64_crtcregs crtc; 699 700 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 701 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 702 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 703 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 704 705 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 706 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 707 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 708 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 709 mode->hsync_start; 710 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 711 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 712 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 713 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 714 715 #ifdef MACH64_DEBUG 716 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 717 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 718 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 719 #endif 720 } 721 722 int 723 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 724 struct videomode *mode) 725 { 726 727 if (mode->dot_clock > sc->ramdac_freq) 728 /* Clock too high. */ 729 return 1; 730 731 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 732 ((mode->htotal >> 3) - 1); 733 crtc->h_sync_strt_wid = 734 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 735 ((mode->hsync_start >> 3) - 1); 736 737 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 738 (mode->vtotal - 1); 739 crtc->v_sync_strt_wid = 740 ((mode->vsync_end - mode->vsync_start) << 16) | 741 (mode->vsync_start - 1); 742 743 if (mode->flags & VID_NVSYNC) 744 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 745 746 switch (sc->bits_per_pixel) { 747 case 8: 748 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 749 break; 750 case 16: 751 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 752 break; 753 case 32: 754 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 755 break; 756 } 757 758 crtc->gen_cntl = 0; 759 if (mode->flags & VID_INTERLACE) 760 crtc->gen_cntl |= CRTC_INTERLACE_EN; 761 if (mode->flags & VID_CSYNC) 762 crtc->gen_cntl |= CRTC_CSYNC_EN; 763 764 crtc->dot_clock = mode->dot_clock; 765 766 return 0; 767 } 768 769 void 770 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 771 { 772 773 mach64_set_pll(sc, crtc->dot_clock); 774 775 if (sc->has_dsp) 776 mach64_set_dsp(sc); 777 778 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 779 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 780 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 781 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 782 783 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 784 785 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 786 787 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 788 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 789 } 790 791 int 792 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 793 { 794 struct mach64_crtcregs crtc; 795 796 if (mach64_calc_crtcregs(sc, &crtc, mode)) 797 return 1; 798 799 mach64_set_crtcregs(sc, &crtc); 800 return 0; 801 } 802 803 void 804 mach64_reset_engine(struct mach64_softc *sc) 805 { 806 807 /* Reset engine.*/ 808 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 809 810 /* Enable engine. */ 811 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 812 813 /* Ensure engine is not locked up by clearing any FIFO or 814 host errors. */ 815 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 816 BUS_FIFO_ERR_ACK); 817 } 818 819 void 820 mach64_init_engine(struct mach64_softc *sc) 821 { 822 u_int32_t pitch_value; 823 824 pitch_value = sc->virt_x; 825 826 if (sc->bits_per_pixel == 24) 827 pitch_value *= 3; 828 829 mach64_reset_engine(sc); 830 831 wait_for_fifo(sc, 14); 832 833 regw(sc, CONTEXT_MASK, 0xffffffff); 834 835 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 836 837 regw(sc, DST_Y_X, 0); 838 regw(sc, DST_HEIGHT, 0); 839 regw(sc, DST_BRES_ERR, 0); 840 regw(sc, DST_BRES_INC, 0); 841 regw(sc, DST_BRES_DEC, 0); 842 843 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 844 DST_Y_TOP_TO_BOTTOM); 845 846 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 847 848 regw(sc, SRC_Y_X, 0); 849 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 850 regw(sc, SRC_Y_X_START, 0); 851 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 852 853 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 854 855 wait_for_fifo(sc, 13); 856 regw(sc, HOST_CNTL, 0); 857 858 regw(sc, PAT_REG0, 0); 859 regw(sc, PAT_REG1, 0); 860 regw(sc, PAT_CNTL, 0); 861 862 regw(sc, SC_LEFT, 0); 863 regw(sc, SC_TOP, 0); 864 regw(sc, SC_BOTTOM, default_mode.vdisplay - 1); 865 regw(sc, SC_RIGHT, pitch_value - 1); 866 867 regw(sc, DP_BKGD_CLR, 0); 868 regw(sc, DP_FRGD_CLR, 0xffffffff); 869 regw(sc, DP_WRITE_MASK, 0xffffffff); 870 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 871 872 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 873 874 wait_for_fifo(sc, 3); 875 regw(sc, CLR_CMP_CLR, 0); 876 regw(sc, CLR_CMP_MASK, 0xffffffff); 877 regw(sc, CLR_CMP_CNTL, 0); 878 879 wait_for_fifo(sc, 2); 880 switch (sc->bits_per_pixel) { 881 case 8: 882 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 883 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 884 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) & ~DAC_8BIT_EN); 885 break; 886 #if 0 887 case 32: 888 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 889 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 890 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 891 break; 892 #endif 893 } 894 895 wait_for_fifo(sc, 5); 896 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 897 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 898 899 wait_for_idle(sc); 900 } 901 902 void 903 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 904 { 905 int offset; 906 907 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 908 909 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 910 offset); 911 } 912 913 void 914 mach64_set_dsp(struct mach64_softc *sc) 915 { 916 u_int32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 917 u_int32_t dsp_off, dsp_on, dsp_xclks_per_qw; 918 u_int32_t xclks_per_qw, y; 919 u_int32_t fifo_off, fifo_on; 920 921 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 922 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 923 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 924 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 925 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 926 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 927 dsp_loop_latency = 0; 928 fifo_depth = 24; 929 } else { 930 dsp_loop_latency = 2; 931 fifo_depth = 32; 932 } 933 934 dsp_precision = 0; 935 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 936 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 937 y = (xclks_per_qw * fifo_depth) >> 11; 938 while (y) { 939 y >>= 1; 940 dsp_precision++; 941 } 942 dsp_precision -= 5; 943 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 944 945 switch (sc->memtype) { 946 case DRAM: 947 case EDO_DRAM: 948 case PSEUDO_EDO: 949 if (sc->memsize > 1024) { 950 page_size = 9; 951 dsp_loop_latency += 6; 952 } else { 953 page_size = 10; 954 if (sc->memtype == DRAM) 955 dsp_loop_latency += 8; 956 else 957 dsp_loop_latency += 7; 958 } 959 break; 960 case SDRAM: 961 case SGRAM: 962 if (sc->memsize > 1024) { 963 page_size = 8; 964 dsp_loop_latency += 8; 965 } else { 966 page_size = 10; 967 dsp_loop_latency += 9; 968 } 969 break; 970 default: 971 page_size = 10; 972 dsp_loop_latency += 9; 973 break; 974 } 975 976 if (xclks_per_qw >= (page_size << 11)) 977 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 978 else 979 fifo_on = (3 * page_size + 2) << 6; 980 981 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 982 dsp_on = fifo_on >> dsp_precision; 983 dsp_off = fifo_off >> dsp_precision; 984 985 #ifdef MACH64_DEBUG 986 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 987 "dsp_precision = %d, dsp_loop_latency = %d,\n" 988 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 989 "mclk_post_div = %d, vclk_post_div = %d\n", 990 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 991 sc->mclk_fb_div, sc->vclk_fb_div, 992 sc->mclk_post_div, sc->vclk_post_div); 993 #endif 994 995 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 996 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 997 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 998 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 999 } 1000 1001 void 1002 mach64_set_pll(struct mach64_softc *sc, int clock) 1003 { 1004 int q; 1005 1006 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1007 #ifdef MACH64_DEBUG 1008 printf("q = %d\n", q); 1009 #endif 1010 if (q > 25500) { 1011 printf("Warning: q > 25500\n"); 1012 q = 25500; 1013 sc->vclk_post_div = 1; 1014 sc->log2_vclk_post_div = 0; 1015 } else if (q > 12750) { 1016 sc->vclk_post_div = 1; 1017 sc->log2_vclk_post_div = 0; 1018 } else if (q > 6350) { 1019 sc->vclk_post_div = 2; 1020 sc->log2_vclk_post_div = 1; 1021 } else if (q > 3150) { 1022 sc->vclk_post_div = 4; 1023 sc->log2_vclk_post_div = 2; 1024 } else if (q >= 1600) { 1025 sc->vclk_post_div = 8; 1026 sc->log2_vclk_post_div = 3; 1027 } else { 1028 printf("Warning: q < 1600\n"); 1029 sc->vclk_post_div = 8; 1030 sc->log2_vclk_post_div = 3; 1031 } 1032 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1033 1034 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1035 regwb_pll(sc, VCLK_POST_DIV, sc->log2_vclk_post_div); 1036 regwb_pll(sc, VCLK0_FB_DIV, sc->vclk_fb_div); 1037 } 1038 1039 void 1040 mach64_init_lut(struct mach64_softc *sc) 1041 { 1042 int i; 1043 1044 regwb(sc, DAC_REGS, 0); 1045 1046 for (i = 0; i < 16; i++) { 1047 regwb(sc, DAC_REGS + 1, mach64_cmap[i * 3]); 1048 regwb(sc, DAC_REGS + 1, mach64_cmap[i * 3 + 1]); 1049 regwb(sc, DAC_REGS + 1, mach64_cmap[i + 3 + 2]); 1050 } 1051 } 1052 1053 void 1054 mach64_switch_screen(struct mach64_softc *sc) 1055 { 1056 struct mach64screen *scr, *oldscr; 1057 const struct wsscreen_descr *type; 1058 1059 scr = sc->wanted; 1060 if (!scr) { 1061 printf("mach64_switch_screen: disappeared\n"); 1062 (*sc->switchcb)(sc->switchcbarg, EIO, 0); 1063 return; 1064 } 1065 type = scr->type; 1066 oldscr = sc->active; /* can be NULL! */ 1067 #ifdef DIAGNOSTIC 1068 if (oldscr) { 1069 if (!oldscr->active) 1070 panic("mach64_switch_screen: not active"); 1071 if (oldscr->type != vc->currenttype) 1072 panic("mach64_switch_screen: bad type"); 1073 } 1074 #endif 1075 if (scr == oldscr) 1076 return; 1077 1078 #ifdef DIAGNOSTIC 1079 if (scr->active) 1080 panic("mach64_switch_screen: active"); 1081 #endif 1082 1083 if (oldscr) 1084 oldscr->active = 0; 1085 1086 if (sc->currenttype != type) { 1087 mach64_set_screentype(sc, type); 1088 sc->currenttype = type; 1089 } 1090 1091 scr->dispoffset = scr->mindispoffset; 1092 1093 if (!oldscr || (scr->dispoffset != oldscr->dispoffset)) { 1094 1095 } 1096 1097 /* Clear the entire screen. */ 1098 1099 scr->active = 1; 1100 mach64_restore_screen(scr, type, scr->mem); 1101 1102 sc->active = scr; 1103 1104 mach64_cursor(scr, scr->cursoron, scr->cursorrow, scr->cursorcol); 1105 1106 sc->wanted = 0; 1107 if (sc->switchcb) 1108 (*sc->switchcb)(sc->switchcbarg, 0, 0); 1109 } 1110 1111 void 1112 mach64_restore_screen(struct mach64screen *scr, 1113 const struct wsscreen_descr *type, u_int16_t *mem) 1114 { 1115 1116 } 1117 1118 int 1119 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1120 { 1121 struct mach64_crtcregs regs; 1122 1123 if (mach64_calc_crtcregs(sc, ®s, 1124 (struct videomode *)des->modecookie)) 1125 return 1; 1126 1127 mach64_set_crtcregs(sc, ®s); 1128 return 0; 1129 } 1130 1131 int 1132 mach64_is_console(struct pci_attach_args *pa) 1133 { 1134 #ifdef __sparc__ 1135 int node; 1136 1137 node = PCITAG_NODE(pa->pa_tag); 1138 if (node == -1) 1139 return 0; 1140 1141 return (node == OF_instance_to_package(OF_stdout())); 1142 #else 1143 return 1; 1144 #endif 1145 } 1146 1147 /* 1148 * wsdisplay_emulops 1149 */ 1150 1151 void 1152 mach64_cursor(void *cookie, int on, int row, int col) 1153 { 1154 1155 } 1156 1157 int 1158 mach64_mapchar(void *cookie, int uni, u_int *index) 1159 { 1160 1161 return 0; 1162 } 1163 1164 void 1165 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1166 { 1167 1168 } 1169 1170 void 1171 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1172 { 1173 1174 } 1175 1176 void 1177 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1178 { 1179 1180 } 1181 1182 void 1183 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1184 { 1185 1186 } 1187 1188 void 1189 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1190 { 1191 1192 } 1193 1194 int 1195 mach64_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1196 { 1197 1198 return 0; 1199 } 1200 1201 /* 1202 * wsdisplay_accessops 1203 */ 1204 1205 int 1206 mach64_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 1207 { 1208 1209 return ENOTTY; 1210 } 1211 1212 paddr_t 1213 mach64_mmap(void *v, off_t offset, int prot) 1214 { 1215 1216 return -1; 1217 } 1218 1219 int 1220 mach64_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, 1221 int *curxp, int *curyp, long *defattrp) 1222 { 1223 struct mach64_softc *sc = v; 1224 struct mach64screen *scr; 1225 1226 if (sc->nscreens == 1) 1227 sc->screens.lh_first->mem = scr->mem; 1228 1229 scr = malloc(sizeof(struct mach64screen), M_DEVBUF, M_WAITOK); 1230 mach64_init_screen(sc, scr, type, 0, defattrp, 0); 1231 1232 if (sc->nscreens == 1) { 1233 scr->active = 1; 1234 sc->active = scr; 1235 sc->currenttype = type; 1236 } else { 1237 scr->mem = malloc(type->ncols * type->nrows * 2, M_DEVBUF, 1238 M_WAITOK); 1239 mach64_eraserows(sc, 0, type->nrows, *defattrp); 1240 } 1241 1242 *cookiep = scr; 1243 *curxp = scr->cursorcol; 1244 *curyp = scr->cursorrow; 1245 1246 return 0; 1247 } 1248 1249 void 1250 mach64_free_screen(void *v, void *cookie) 1251 { 1252 struct mach64_softc *sc = v; 1253 struct mach64screen *scr = cookie; 1254 1255 LIST_REMOVE(scr, next); 1256 if (scr != &mach64_console_screen) 1257 free(scr, M_DEVBUF); 1258 else 1259 panic("mach64_free_screen: console"); 1260 1261 if (sc->active == scr) 1262 sc->active = 0; 1263 } 1264 1265 int 1266 mach64_show_screen(void *v, void *cookie, int waitok, 1267 void (*cb)(void *, int, int), void *cbarg) 1268 { 1269 struct mach64_softc *sc = v; 1270 struct mach64screen *scr, *oldscr; 1271 1272 scr = cookie; 1273 oldscr = sc->active; 1274 if (scr == oldscr) 1275 return 0; 1276 1277 sc->wanted = scr; 1278 sc->switchcb = cb; 1279 sc->switchcbarg = cbarg; 1280 if (cb) { 1281 callout_reset(&sc->switch_callout, 0, 1282 (void(*)(void *))mach64_switch_screen, sc); 1283 return EAGAIN; 1284 } 1285 1286 mach64_switch_screen(sc); 1287 1288 return 0; 1289 } 1290 1291 int 1292 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1293 { 1294 1295 return 0; 1296 } 1297
Indexes created Thu Oct 02 14:10:14 GMT 2025