machfb.c revision 1.60
1 /* $NetBSD: machfb.c,v 1.60 2010/10/02 23:50:04 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.60 2010/10/02 23:50:04 macallan Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #ifdef __sparc__ 58 #include <dev/sun/fbio.h> 59 #include <dev/sun/fbvar.h> 60 #include <sys/conf.h> 61 #else 62 #include <dev/wscons/wsdisplayvar.h> 63 #endif 64 65 #include <dev/wscons/wsconsio.h> 66 #include <dev/wsfont/wsfont.h> 67 #include <dev/rasops/rasops.h> 68 69 #include <dev/wscons/wsdisplay_vconsvar.h> 70 71 #include "opt_wsemul.h" 72 #include "opt_machfb.h" 73 74 #define MACH64_REG_SIZE 1024 75 #define MACH64_REG_OFF 0x7ffc00 76 77 #define NBARS 3 /* number of Mach64 PCI BARs */ 78 79 struct vga_bar { 80 bus_addr_t vb_base; 81 pcireg_t vb_busaddr; 82 bus_size_t vb_size; 83 pcireg_t vb_type; 84 int vb_flags; 85 }; 86 87 struct mach64_softc { 88 device_t sc_dev; 89 #ifdef __sparc__ 90 struct fbdevice sc_fb; 91 #endif 92 pci_chipset_tag_t sc_pc; 93 pcitag_t sc_pcitag; 94 95 struct vga_bar sc_bars[NBARS]; 96 struct vga_bar sc_rom; 97 98 #define sc_aperbase sc_bars[0].vb_base 99 #define sc_apersize sc_bars[0].vb_size 100 #define sc_aperphys sc_bars[0].vb_busaddr 101 102 #define sc_iobase sc_bars[1].vb_base 103 #define sc_iosize sc_bars[1].vb_size 104 105 #define sc_regbase sc_bars[2].vb_base 106 #define sc_regsize sc_bars[2].vb_size 107 #define sc_regphys sc_bars[2].vb_busaddr 108 109 bus_space_tag_t sc_regt; 110 bus_space_tag_t sc_memt; 111 bus_space_tag_t sc_iot; 112 bus_space_handle_t sc_regh; 113 bus_space_handle_t sc_memh; 114 void *sc_aperture; /* mapped aperture vaddr */ 115 void *sc_registers; /* mapped registers vaddr */ 116 117 uint32_t sc_nbus, sc_ndev, sc_nfunc; 118 size_t memsize; 119 int memtype; 120 121 int sc_mode; 122 int sc_bg; 123 int sc_locked; 124 125 int has_dsp; 126 int bits_per_pixel; 127 int max_x; 128 int max_y; 129 int virt_x; 130 int virt_y; 131 int color_depth; 132 133 int mem_freq; 134 int ramdac_freq; 135 int ref_freq; 136 137 int ref_div; 138 int log2_vclk_post_div; 139 int vclk_post_div; 140 int vclk_fb_div; 141 int mclk_post_div; 142 int mclk_fb_div; 143 int sc_clock; /* which clock to use */ 144 145 struct videomode *sc_my_mode; 146 int sc_edid_size; 147 uint8_t sc_edid_data[1024]; 148 149 u_char sc_cmap_red[256]; 150 u_char sc_cmap_green[256]; 151 u_char sc_cmap_blue[256]; 152 int sc_dacw, sc_blanked, sc_console; 153 struct vcons_data vd; 154 }; 155 156 struct mach64_crtcregs { 157 uint32_t h_total_disp; 158 uint32_t h_sync_strt_wid; 159 uint32_t v_total_disp; 160 uint32_t v_sync_strt_wid; 161 uint32_t gen_cntl; 162 uint32_t clock_cntl; 163 uint32_t color_depth; 164 uint32_t dot_clock; 165 }; 166 167 static struct { 168 uint16_t chip_id; 169 uint32_t ramdac_freq; 170 } const mach64_info[] = { 171 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 172 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 173 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 174 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 175 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 176 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 181 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 182 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 185 #if 0 186 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 189 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 190 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 191 #endif 192 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 193 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 194 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 195 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 196 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 197 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 198 }; 199 200 static int mach64_chip_id, mach64_chip_rev; 201 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 202 203 static const char *mach64_memtype_names[] = { 204 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 205 "(unknown type)" 206 }; 207 208 static struct videomode mach64_modes[] = { 209 /* 640x400 @ 70 Hz, 31.5 kHz */ 210 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0, NULL, }, 211 /* 640x480 @ 72 Hz, 36.5 kHz */ 212 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0, NULL, }, 213 /* 800x600 @ 72 Hz, 48.0 kHz */ 214 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 215 VID_PHSYNC | VID_PVSYNC, NULL, }, 216 /* 1024x768 @ 70 Hz, 56.5 kHz */ 217 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 218 VID_NHSYNC | VID_NVSYNC, NULL, }, 219 /* 1152x864 @ 70 Hz, 62.4 kHz */ 220 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0, NULL, }, 221 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 222 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 223 VID_NHSYNC | VID_NVSYNC, NULL, } 224 }; 225 226 extern const u_char rasops_cmap[768]; 227 228 static int mach64_match(device_t, cfdata_t, void *); 229 static void mach64_attach(device_t, device_t, void *); 230 231 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 232 NULL, NULL); 233 234 static void mach64_init(struct mach64_softc *); 235 static int mach64_get_memsize(struct mach64_softc *); 236 static int mach64_get_max_ramdac(struct mach64_softc *); 237 238 #if defined(__sparc__) || defined(__powerpc__) 239 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 240 #endif 241 242 static int mach64_calc_crtcregs(struct mach64_softc *, 243 struct mach64_crtcregs *, 244 struct videomode *); 245 static void mach64_set_crtcregs(struct mach64_softc *, 246 struct mach64_crtcregs *); 247 248 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 249 static void mach64_set_dsp(struct mach64_softc *); 250 static void mach64_set_pll(struct mach64_softc *, int); 251 static void mach64_reset_engine(struct mach64_softc *); 252 static void mach64_init_engine(struct mach64_softc *); 253 #if 0 254 static void mach64_adjust_frame(struct mach64_softc *, int, int); 255 #endif 256 static void mach64_init_lut(struct mach64_softc *); 257 258 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 259 static int mach64_set_screentype(struct mach64_softc *, 260 const struct wsscreen_descr *); 261 static int mach64_is_console(struct mach64_softc *); 262 263 static void mach64_cursor(void *, int, int, int); 264 #if 0 265 static int mach64_mapchar(void *, int, u_int *); 266 #endif 267 static void mach64_putchar(void *, int, int, u_int, long); 268 static void mach64_copycols(void *, int, int, int, int); 269 static void mach64_erasecols(void *, int, int, int, long); 270 static void mach64_copyrows(void *, int, int, int); 271 static void mach64_eraserows(void *, int, int, long); 272 static void mach64_clearscreen(struct mach64_softc *); 273 274 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 275 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 276 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 277 uint8_t, uint8_t); 278 static void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, 279 int, int, int) ; 280 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 281 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 282 uint32_t, uint32_t); 283 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 284 #if 0 285 static void mach64_showpal(struct mach64_softc *); 286 #endif 287 288 static void set_address(struct rasops_info *, void *); 289 static void machfb_blank(struct mach64_softc *, int); 290 static int machfb_drm_print(void *, const char *); 291 292 static struct wsscreen_descr mach64_defaultscreen = { 293 "default", 294 80, 30, 295 NULL, 296 8, 16, 297 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 298 &default_mode 299 }, mach64_80x25_screen = { 300 "80x25", 80, 25, 301 NULL, 302 8, 16, 303 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 304 &mach64_modes[0] 305 }, mach64_80x30_screen = { 306 "80x30", 80, 30, 307 NULL, 308 8, 16, 309 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 310 &mach64_modes[1] 311 }, mach64_80x40_screen = { 312 "80x40", 80, 40, 313 NULL, 314 8, 10, 315 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 316 &mach64_modes[0] 317 }, mach64_80x50_screen = { 318 "80x50", 80, 50, 319 NULL, 320 8, 8, 321 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 322 &mach64_modes[0] 323 }, mach64_100x37_screen = { 324 "100x37", 100, 37, 325 NULL, 326 8, 16, 327 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 328 &mach64_modes[2] 329 }, mach64_128x48_screen = { 330 "128x48", 128, 48, 331 NULL, 332 8, 16, 333 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 334 &mach64_modes[3] 335 }, mach64_144x54_screen = { 336 "144x54", 144, 54, 337 NULL, 338 8, 16, 339 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 340 &mach64_modes[4] 341 }, mach64_160x64_screen = { 342 "160x54", 160, 64, 343 NULL, 344 8, 16, 345 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 346 &mach64_modes[5] 347 }; 348 349 static const struct wsscreen_descr *_mach64_scrlist[] = { 350 &mach64_defaultscreen, 351 &mach64_80x25_screen, 352 &mach64_80x30_screen, 353 &mach64_80x40_screen, 354 &mach64_80x50_screen, 355 &mach64_100x37_screen, 356 &mach64_128x48_screen, 357 &mach64_144x54_screen, 358 &mach64_160x64_screen 359 }; 360 361 static struct wsscreen_list mach64_screenlist = { 362 __arraycount(_mach64_scrlist), 363 _mach64_scrlist 364 }; 365 366 static int mach64_ioctl(void *, void *, u_long, void *, int, 367 struct lwp *); 368 static paddr_t mach64_mmap(void *, void *, off_t, int); 369 370 #if 0 371 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 372 #endif 373 374 static struct wsdisplay_accessops mach64_accessops = { 375 mach64_ioctl, 376 mach64_mmap, 377 NULL, /* vcons_alloc_screen */ 378 NULL, /* vcons_free_screen */ 379 NULL, /* vcons_show_screen */ 380 NULL, /* load_font */ 381 NULL, /* polls */ 382 NULL, /* scroll */ 383 }; 384 385 static struct vcons_screen mach64_console_screen; 386 387 /* framebuffer device, SPARC-only so far */ 388 #ifdef __sparc__ 389 390 static void machfb_unblank(device_t); 391 static void machfb_fbattach(struct mach64_softc *); 392 393 extern struct cfdriver machfb_cd; 394 395 dev_type_open(machfb_fbopen); 396 dev_type_close(machfb_fbclose); 397 dev_type_ioctl(machfb_fbioctl); 398 dev_type_mmap(machfb_fbmmap); 399 400 /* frame buffer generic driver */ 401 static struct fbdriver machfb_fbdriver = { 402 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 403 machfb_fbmmap, nokqfilter 404 }; 405 406 #endif /* __sparc__ */ 407 408 /* 409 * Inline functions for getting access to register aperture. 410 */ 411 412 static inline uint32_t 413 regr(struct mach64_softc *sc, uint32_t index) 414 { 415 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 416 } 417 418 static inline uint8_t 419 regrb(struct mach64_softc *sc, uint32_t index) 420 { 421 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 422 } 423 424 static inline void 425 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 426 { 427 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 428 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 429 BUS_SPACE_BARRIER_WRITE); 430 } 431 432 static inline void 433 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 434 { 435 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 436 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 437 BUS_SPACE_BARRIER_WRITE); 438 } 439 440 static inline void 441 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 442 { 443 uint32_t reg; 444 445 reg = regr(sc, CLOCK_CNTL); 446 reg |= PLL_WR_EN; 447 regw(sc, CLOCK_CNTL, reg); 448 reg &= ~(PLL_ADDR | PLL_DATA); 449 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 450 reg |= data << PLL_DATA_SHIFT; 451 reg |= CLOCK_STROBE; 452 regw(sc, CLOCK_CNTL, reg); 453 reg &= ~PLL_WR_EN; 454 regw(sc, CLOCK_CNTL, reg); 455 } 456 457 static inline uint8_t 458 regrb_pll(struct mach64_softc *sc, uint32_t index) 459 { 460 461 regwb(sc, CLOCK_CNTL + 1, index << 2); 462 return regrb(sc, CLOCK_CNTL + 2); 463 } 464 465 static inline void 466 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 467 { 468 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 469 continue; 470 } 471 472 static inline void 473 wait_for_idle(struct mach64_softc *sc) 474 { 475 wait_for_fifo(sc, 16); 476 while ((regr(sc, GUI_STAT) & 1) != 0) 477 continue; 478 } 479 480 static int 481 mach64_match(device_t parent, cfdata_t match, void *aux) 482 { 483 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 484 int i; 485 486 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 487 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 488 return 0; 489 490 for (i = 0; i < __arraycount(mach64_info); i++) 491 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 492 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 493 mach64_chip_rev = PCI_REVISION(pa->pa_class); 494 return 100; 495 } 496 497 return 0; 498 } 499 500 static void 501 mach64_attach(device_t parent, device_t self, void *aux) 502 { 503 struct mach64_softc *sc = device_private(self); 504 struct pci_attach_args *pa = aux; 505 struct rasops_info *ri; 506 prop_data_t edid_data; 507 const struct videomode *mode = NULL; 508 char devinfo[256]; 509 int bar, id; 510 struct wsemuldisplaydev_attach_args aa; 511 long defattr; 512 int setmode, width, height; 513 pcireg_t screg; 514 uint32_t reg; 515 516 sc->sc_dev = self; 517 sc->sc_pc = pa->pa_pc; 518 sc->sc_pcitag = pa->pa_tag; 519 sc->sc_dacw = -1; 520 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 521 sc->sc_nbus = pa->pa_bus; 522 sc->sc_ndev = pa->pa_device; 523 sc->sc_nfunc = pa->pa_function; 524 sc->sc_locked = 0; 525 sc->sc_iot = pa->pa_iot; 526 527 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 528 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 529 PCI_REVISION(pa->pa_class)); 530 aprint_naive(": Graphics processor\n"); 531 #ifdef DEBUG 532 printf(prop_dictionary_externalize(device_properties(self))); 533 #endif 534 535 /* enable memory and disable IO access */ 536 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 537 if ((screg & PCI_FLAGS_MEM_ENABLED) == 0) { 538 screg |= PCI_FLAGS_IO_ENABLED; 539 screg |= PCI_FLAGS_MEM_ENABLED; 540 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 541 PCI_COMMAND_STATUS_REG, screg); 542 } 543 for (bar = 0; bar < NBARS; bar++) { 544 reg = PCI_MAPREG_START + (bar * 4); 545 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 546 sc->sc_pcitag, reg); 547 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 548 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 549 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 550 sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc, 551 sc->sc_pcitag, reg) & 0xfffffff0; 552 } 553 printf("%s: aperture size %08x\n", device_xname(sc->sc_dev), 554 (uint32_t)sc->sc_apersize); 555 556 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 557 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 558 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 559 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 560 sc->sc_memt = pa->pa_memt; 561 562 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 563 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 564 panic("%s: failed to map aperture", device_xname(sc->sc_dev)); 565 } 566 sc->sc_aperture = (void *)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 567 568 sc->sc_regt = sc->sc_memt; 569 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 570 sc->sc_regsize, &sc->sc_regh); 571 sc->sc_registers = (char *)sc->sc_aperture + 0x7ffc00; 572 573 mach64_init(sc); 574 575 aprint_normal_dev(sc->sc_dev, 576 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 577 (u_int)(sc->sc_apersize / (1024 * 1024)), 578 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 579 (u_int)sc->sc_regphys); 580 581 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 582 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 583 584 prop_dictionary_get_uint32(device_properties(self), "width", &width); 585 prop_dictionary_get_uint32(device_properties(self), "height", &height); 586 587 if ((edid_data = prop_dictionary_get(device_properties(self), "EDID")) 588 != NULL) { 589 struct edid_info ei; 590 591 sc->sc_edid_size = min(1024, prop_data_size(edid_data)); 592 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 593 memcpy(sc->sc_edid_data, prop_data_data_nocopy(edid_data), 594 sc->sc_edid_size); 595 596 edid_parse(sc->sc_edid_data, &ei); 597 598 #ifdef DEBUG 599 edid_print(&ei); 600 #endif 601 if (ei.edid_have_range) { 602 603 /* ei has dotclock in MHz, struct videomode in kHz */ 604 mode = pick_mode_by_dotclock(width, height, 605 ei.edid_range.er_max_clock * 1000); 606 if (mode != NULL) 607 printf("mode: %s\n", mode->name); 608 } 609 } 610 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 611 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 612 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 613 (mach64_chip_rev & 0x07) == 0)) 614 sc->has_dsp = 0; 615 else 616 sc->has_dsp = 1; 617 618 sc->memsize = mach64_get_memsize(sc); 619 if (sc->memsize == 8192) 620 /* The last page is used as register aperture. */ 621 sc->memsize -= 4; 622 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 623 624 /* XXX is there any way to calculate reference frequency from 625 known values? */ 626 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 627 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 628 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 629 aprint_normal_dev(sc->sc_dev, "ref_freq=29.498MHz\n"); 630 sc->ref_freq = 29498; 631 } else 632 sc->ref_freq = 14318; 633 634 reg = regr(sc, CLOCK_CNTL); 635 printf("CLOCK_CNTL: %08x\n", reg); 636 sc->sc_clock = reg & 3; 637 printf("using clock %d\n", sc->sc_clock); 638 639 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 640 printf("ref_div: %d\n", sc->ref_div); 641 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 642 printf("mclk_fb_div: %d\n", sc->mclk_fb_div); 643 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 644 (sc->ref_div * 2); 645 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 646 (sc->mem_freq * sc->ref_div); 647 sc->ramdac_freq = mach64_get_max_ramdac(sc); 648 aprint_normal_dev(sc->sc_dev, 649 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 650 (u_long)sc->memsize, 651 mach64_memtype_names[sc->memtype], 652 sc->mem_freq / 1000, sc->mem_freq % 1000, 653 sc->ramdac_freq / 1000); 654 655 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 656 if (id != mach64_chip_id) { 657 aprint_error_dev(sc->sc_dev, 658 "chip ID mismatch, 0x%x != 0x%x\n", id, mach64_chip_id); 659 return; 660 } 661 662 sc->sc_console = mach64_is_console(sc); 663 #ifdef DIAGNOSTIC 664 aprint_normal("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 665 #endif 666 #if defined(__sparc__) || defined(__powerpc__) 667 if (sc->sc_console) { 668 if (mode != NULL) { 669 memcpy(&default_mode, mode, sizeof(struct videomode)); 670 setmode = 1; 671 } else { 672 mach64_get_mode(sc, &default_mode); 673 setmode = 0; 674 } 675 sc->sc_my_mode = &default_mode; 676 } else { 677 /* fill in default_mode if it's empty */ 678 mach64_get_mode(sc, &default_mode); 679 if (default_mode.dot_clock == 0) { 680 memcpy(&default_mode, &mach64_modes[4], 681 sizeof(default_mode)); 682 } 683 sc->sc_my_mode = &default_mode; 684 setmode = 1; 685 } 686 #else 687 if (default_mode.dot_clock == 0) { 688 memcpy(&default_mode, &mach64_modes[0], 689 sizeof(default_mode)); 690 } 691 sc->sc_my_mode = &mach64_modes[0]; 692 setmode = 1; 693 #endif 694 695 sc->bits_per_pixel = 8; 696 sc->virt_x = sc->sc_my_mode->hdisplay; 697 sc->virt_y = sc->sc_my_mode->vdisplay; 698 sc->max_x = sc->virt_x - 1; 699 sc->max_y = (sc->memsize * 1024) / 700 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 701 702 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 703 704 mach64_init_engine(sc); 705 706 if (setmode) 707 mach64_modeswitch(sc, sc->sc_my_mode); 708 #if 0 709 mach64_adjust_frame(0, 0); 710 if (sc->bits_per_pixel == 8) 711 mach64_init_lut(sc); 712 #endif 713 714 aprint_normal_dev(sc->sc_dev, 715 "initial resolution %dx%d at %d bpp\n", 716 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 717 sc->bits_per_pixel); 718 719 #ifdef __sparc__ 720 machfb_fbattach(sc); 721 #endif 722 723 wsfont_init(); 724 725 sc->sc_bg = WS_DEFAULT_BG; 726 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &mach64_accessops); 727 sc->vd.init_screen = mach64_init_screen; 728 729 mach64_init_lut(sc); 730 mach64_clearscreen(sc); 731 machfb_blank(sc, 0); /* unblank the screen */ 732 733 if (sc->sc_console) { 734 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 735 &defattr); 736 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 737 738 ri = &mach64_console_screen.scr_ri; 739 mach64_defaultscreen.textops = &ri->ri_ops; 740 mach64_defaultscreen.capabilities = ri->ri_caps; 741 mach64_defaultscreen.nrows = ri->ri_rows; 742 mach64_defaultscreen.ncols = ri->ri_cols; 743 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 744 vcons_replay_msgbuf(&mach64_console_screen); 745 } else { 746 /* 747 * since we're not the console we can postpone the rest 748 * until someone actually allocates a screen for us 749 */ 750 mach64_modeswitch(sc, sc->sc_my_mode); 751 } 752 753 aa.console = sc->sc_console; 754 aa.scrdata = &mach64_screenlist; 755 aa.accessops = &mach64_accessops; 756 aa.accesscookie = &sc->vd; 757 758 config_found(self, &aa, wsemuldisplaydevprint); 759 760 config_found_ia(self, "drm", aux, machfb_drm_print); 761 } 762 763 static int 764 machfb_drm_print(void *aux, const char *pnp) 765 { 766 if (pnp) 767 aprint_normal("direct rendering for %s", pnp); 768 return (UNSUPP); 769 } 770 771 static void 772 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 773 long *defattr) 774 { 775 struct mach64_softc *sc = cookie; 776 struct rasops_info *ri = &scr->scr_ri; 777 778 /* XXX for now */ 779 #define setmode 0 780 781 ri->ri_depth = sc->bits_per_pixel; 782 ri->ri_width = sc->sc_my_mode->hdisplay; 783 ri->ri_height = sc->sc_my_mode->vdisplay; 784 ri->ri_stride = ri->ri_width; 785 ri->ri_flg = RI_CENTER; 786 set_address(ri, sc->sc_aperture); 787 788 if (existing) { 789 ri->ri_flg |= RI_CLEAR; 790 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 791 panic("%s: failed to switch video mode", 792 device_xname(sc->sc_dev)); 793 } 794 } 795 796 rasops_init(ri, sc->sc_my_mode->vdisplay / 8, 797 sc->sc_my_mode->hdisplay / 8); 798 ri->ri_caps = WSSCREEN_WSCOLORS; 799 800 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 801 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 802 803 /* enable acceleration */ 804 ri->ri_hw = scr; 805 ri->ri_ops.copyrows = mach64_copyrows; 806 ri->ri_ops.copycols = mach64_copycols; 807 ri->ri_ops.eraserows = mach64_eraserows; 808 ri->ri_ops.erasecols = mach64_erasecols; 809 ri->ri_ops.cursor = mach64_cursor; 810 ri->ri_ops.putchar = mach64_putchar; 811 } 812 813 static void 814 mach64_init(struct mach64_softc *sc) 815 { 816 uint32_t *p32, saved_value; 817 uint8_t *p; 818 int need_swap; 819 820 /* 821 * Test wether the aperture is byte swapped or not 822 */ 823 p32 = (uint32_t*)sc->sc_aperture; 824 saved_value = *p32; 825 p = (uint8_t*)(u_long)sc->sc_aperture; 826 *p32 = 0x12345678; 827 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 828 need_swap = 0; 829 else 830 need_swap = 1; 831 if (need_swap) { 832 sc->sc_aperture = (char *)sc->sc_aperture + 0x800000; 833 #if 0 834 /* what the fsck is this for? */ 835 sc->sc_aperbase += 0x800000; 836 sc->sc_apersize -= 0x800000; 837 #endif 838 } 839 *p32 = saved_value; 840 841 sc->sc_blanked = 0; 842 } 843 844 static int 845 mach64_get_memsize(struct mach64_softc *sc) 846 { 847 int tmp, memsize; 848 int mem_tab[] = { 849 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 850 }; 851 tmp = regr(sc, MEM_CNTL); 852 #ifdef DIAGNOSTIC 853 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 854 #endif 855 if (sc->has_dsp) { 856 tmp &= 0x0000000f; 857 if (tmp < 8) 858 memsize = (tmp + 1) * 512; 859 else if (tmp < 12) 860 memsize = (tmp - 3) * 1024; 861 else 862 memsize = (tmp - 7) * 2048; 863 } else { 864 memsize = mem_tab[tmp & 0x07]; 865 } 866 867 return memsize; 868 } 869 870 static int 871 mach64_get_max_ramdac(struct mach64_softc *sc) 872 { 873 int i; 874 875 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 876 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 877 (mach64_chip_rev & 0x07)) 878 return 170000; 879 880 for (i = 0; i < __arraycount(mach64_info); i++) 881 if (mach64_chip_id == mach64_info[i].chip_id) 882 return mach64_info[i].ramdac_freq; 883 884 if (sc->bits_per_pixel == 8) 885 return 135000; 886 else 887 return 80000; 888 } 889 890 #if defined(__sparc__) || defined(__powerpc__) 891 static void 892 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 893 { 894 struct mach64_crtcregs crtc; 895 896 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 897 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 898 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 899 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 900 901 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 902 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 903 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 904 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 905 mode->hsync_start; 906 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 907 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 908 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 909 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 910 911 #ifdef DEBUG_MACHFB 912 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 913 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 914 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 915 #endif 916 } 917 #endif 918 919 static int 920 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 921 struct videomode *mode) 922 { 923 924 if (mode->dot_clock > sc->ramdac_freq) 925 /* Clock too high. */ 926 return 1; 927 928 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 929 ((mode->htotal >> 3) - 1); 930 crtc->h_sync_strt_wid = 931 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 932 ((mode->hsync_start >> 3) - 1); 933 934 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 935 (mode->vtotal - 1); 936 crtc->v_sync_strt_wid = 937 ((mode->vsync_end - mode->vsync_start) << 16) | 938 (mode->vsync_start - 1); 939 940 if (mode->flags & VID_NVSYNC) 941 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 942 943 switch (sc->bits_per_pixel) { 944 case 8: 945 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 946 break; 947 case 16: 948 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 949 break; 950 case 32: 951 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 952 break; 953 } 954 955 crtc->gen_cntl = 0; 956 if (mode->flags & VID_INTERLACE) 957 crtc->gen_cntl |= CRTC_INTERLACE_EN; 958 959 if (mode->flags & VID_CSYNC) 960 crtc->gen_cntl |= CRTC_CSYNC_EN; 961 962 crtc->dot_clock = mode->dot_clock; 963 964 return 0; 965 } 966 967 static void 968 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 969 { 970 971 mach64_set_pll(sc, crtc->dot_clock); 972 973 if (sc->has_dsp) 974 mach64_set_dsp(sc); 975 #if 1 976 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 977 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 978 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 979 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 980 981 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 982 983 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 984 985 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 986 /* XXX this unconditionally enables composite sync on SPARC */ 987 #ifdef __sparc__ 988 CRTC_CSYNC_EN | 989 #endif 990 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 991 #endif 992 } 993 994 static int 995 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 996 { 997 struct mach64_crtcregs crtc; 998 999 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 1000 1001 if (mach64_calc_crtcregs(sc, &crtc, mode)) 1002 return 1; 1003 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 1004 if (crtc.dot_clock == 0) { 1005 aprint_error("%s: preposterous dot clock (%d)\n", 1006 device_xname(sc->sc_dev), crtc.dot_clock); 1007 return 1; 1008 } 1009 mach64_set_crtcregs(sc, &crtc); 1010 return 0; 1011 } 1012 1013 static void 1014 mach64_reset_engine(struct mach64_softc *sc) 1015 { 1016 1017 /* Reset engine.*/ 1018 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1019 1020 /* Enable engine. */ 1021 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1022 1023 /* Ensure engine is not locked up by clearing any FIFO or 1024 host errors. */ 1025 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1026 BUS_FIFO_ERR_ACK); 1027 } 1028 1029 static void 1030 mach64_init_engine(struct mach64_softc *sc) 1031 { 1032 uint32_t pitch_value; 1033 1034 pitch_value = sc->virt_x; 1035 1036 if (sc->bits_per_pixel == 24) 1037 pitch_value *= 3; 1038 1039 mach64_reset_engine(sc); 1040 1041 wait_for_fifo(sc, 14); 1042 1043 regw(sc, CONTEXT_MASK, 0xffffffff); 1044 1045 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 1046 1047 regw(sc, DST_Y_X, 0); 1048 regw(sc, DST_HEIGHT, 0); 1049 regw(sc, DST_BRES_ERR, 0); 1050 regw(sc, DST_BRES_INC, 0); 1051 regw(sc, DST_BRES_DEC, 0); 1052 1053 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1054 DST_Y_TOP_TO_BOTTOM); 1055 1056 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 1057 1058 regw(sc, SRC_Y_X, 0); 1059 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1060 regw(sc, SRC_Y_X_START, 0); 1061 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1062 1063 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1064 1065 wait_for_fifo(sc, 13); 1066 regw(sc, HOST_CNTL, 0); 1067 1068 regw(sc, PAT_REG0, 0); 1069 regw(sc, PAT_REG1, 0); 1070 regw(sc, PAT_CNTL, 0); 1071 1072 regw(sc, SC_LEFT, 0); 1073 regw(sc, SC_TOP, 0); 1074 regw(sc, SC_BOTTOM, sc->sc_my_mode->vdisplay - 1); 1075 regw(sc, SC_RIGHT, pitch_value - 1); 1076 1077 regw(sc, DP_BKGD_CLR, 0); 1078 regw(sc, DP_FRGD_CLR, 0xffffffff); 1079 regw(sc, DP_WRITE_MASK, 0xffffffff); 1080 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1081 1082 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1083 1084 wait_for_fifo(sc, 3); 1085 regw(sc, CLR_CMP_CLR, 0); 1086 regw(sc, CLR_CMP_MASK, 0xffffffff); 1087 regw(sc, CLR_CMP_CNTL, 0); 1088 1089 wait_for_fifo(sc, 2); 1090 switch (sc->bits_per_pixel) { 1091 case 8: 1092 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 1093 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1094 /* We want 8 bit per channel */ 1095 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1096 break; 1097 case 32: 1098 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 1099 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1100 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1101 break; 1102 } 1103 1104 wait_for_fifo(sc, 5); 1105 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1106 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1107 1108 wait_for_idle(sc); 1109 } 1110 1111 #if 0 1112 static void 1113 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1114 { 1115 int offset; 1116 1117 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1118 1119 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1120 offset); 1121 } 1122 #endif 1123 1124 static void 1125 mach64_set_dsp(struct mach64_softc *sc) 1126 { 1127 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1128 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1129 uint32_t xclks_per_qw, y; 1130 uint32_t fifo_off, fifo_on; 1131 1132 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1133 1134 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1135 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1136 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1137 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1138 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1139 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1140 dsp_loop_latency = 0; 1141 fifo_depth = 24; 1142 } else { 1143 dsp_loop_latency = 2; 1144 fifo_depth = 32; 1145 } 1146 1147 dsp_precision = 0; 1148 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1149 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1150 y = (xclks_per_qw * fifo_depth) >> 11; 1151 while (y) { 1152 y >>= 1; 1153 dsp_precision++; 1154 } 1155 dsp_precision -= 5; 1156 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1157 1158 switch (sc->memtype) { 1159 case DRAM: 1160 case EDO_DRAM: 1161 case PSEUDO_EDO: 1162 if (sc->memsize > 1024) { 1163 page_size = 9; 1164 dsp_loop_latency += 6; 1165 } else { 1166 page_size = 10; 1167 if (sc->memtype == DRAM) 1168 dsp_loop_latency += 8; 1169 else 1170 dsp_loop_latency += 7; 1171 } 1172 break; 1173 case SDRAM: 1174 case SGRAM: 1175 if (sc->memsize > 1024) { 1176 page_size = 8; 1177 dsp_loop_latency += 8; 1178 } else { 1179 page_size = 10; 1180 dsp_loop_latency += 9; 1181 } 1182 break; 1183 default: 1184 page_size = 10; 1185 dsp_loop_latency += 9; 1186 break; 1187 } 1188 1189 if (xclks_per_qw >= (page_size << 11)) 1190 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1191 else 1192 fifo_on = (3 * page_size + 2) << 6; 1193 1194 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1195 dsp_on = fifo_on >> dsp_precision; 1196 dsp_off = fifo_off >> dsp_precision; 1197 1198 #ifdef MACHFB_DEBUG 1199 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1200 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1201 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1202 "mclk_post_div = %d, vclk_post_div = %d\n", 1203 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1204 sc->mclk_fb_div, sc->vclk_fb_div, 1205 sc->mclk_post_div, sc->vclk_post_div); 1206 #endif 1207 1208 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1209 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1210 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1211 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1212 } 1213 1214 static void 1215 mach64_set_pll(struct mach64_softc *sc, int clock) 1216 { 1217 uint32_t q, clockreg; 1218 int clockshift = sc->sc_clock << 1; 1219 uint8_t reg, vclk_ctl; 1220 1221 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1222 #ifdef MACHFB_DEBUG 1223 printf("q = %d\n", q); 1224 #endif 1225 if (q > 25500) { 1226 printf("Warning: q > 25500\n"); 1227 q = 25500; 1228 sc->vclk_post_div = 1; 1229 sc->log2_vclk_post_div = 0; 1230 } else if (q > 12750) { 1231 sc->vclk_post_div = 1; 1232 sc->log2_vclk_post_div = 0; 1233 } else if (q > 6350) { 1234 sc->vclk_post_div = 2; 1235 sc->log2_vclk_post_div = 1; 1236 } else if (q > 3150) { 1237 sc->vclk_post_div = 4; 1238 sc->log2_vclk_post_div = 2; 1239 } else if (q >= 1600) { 1240 sc->vclk_post_div = 8; 1241 sc->log2_vclk_post_div = 3; 1242 } else { 1243 printf("Warning: q < 1600\n"); 1244 sc->vclk_post_div = 8; 1245 sc->log2_vclk_post_div = 3; 1246 } 1247 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1248 printf("post_div: %d log2_post_div: %d mclk_div: %d\n", sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1249 1250 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1251 printf("vclk_ctl: %02x\n", vclk_ctl); 1252 vclk_ctl |= PLL_VCLK_RESET; 1253 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1254 1255 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1256 reg = regrb_pll(sc, VCLK_POST_DIV); 1257 reg &= ~(3 << clockshift); 1258 reg |= (sc->log2_vclk_post_div << clockshift); 1259 regwb_pll(sc, VCLK_POST_DIV, reg); 1260 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1261 1262 vclk_ctl &= ~PLL_VCLK_RESET; 1263 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1264 1265 clockreg = regr(sc, CLOCK_CNTL); 1266 clockreg &= ~CLOCK_SEL; 1267 clockreg |= sc->sc_clock | CLOCK_STROBE; 1268 regw(sc, CLOCK_CNTL, clockreg); 1269 } 1270 1271 static void 1272 mach64_init_lut(struct mach64_softc *sc) 1273 { 1274 int i, idx; 1275 1276 idx = 0; 1277 for (i = 0; i < 256; i++) { 1278 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1], 1279 rasops_cmap[idx + 2]); 1280 idx += 3; 1281 } 1282 } 1283 1284 static int 1285 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1286 uint8_t b) 1287 { 1288 sc->sc_cmap_red[index] = r; 1289 sc->sc_cmap_green[index] = g; 1290 sc->sc_cmap_blue[index] = b; 1291 /* 1292 * writing the dac index takes a while, in theory we can poll some 1293 * register to see when it's ready - but we better avoid writing it 1294 * unnecessarily 1295 */ 1296 if (index != sc->sc_dacw) { 1297 regwb(sc, DAC_MASK, 0xff); 1298 regwb(sc, DAC_WINDEX, index); 1299 } 1300 sc->sc_dacw = index + 1; 1301 regwb(sc, DAC_DATA, r); 1302 regwb(sc, DAC_DATA, g); 1303 regwb(sc, DAC_DATA, b); 1304 return 0; 1305 } 1306 1307 static int 1308 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1309 { 1310 uint index = cm->index; 1311 uint count = cm->count; 1312 int i, error; 1313 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1314 uint8_t *r, *g, *b; 1315 1316 if (cm->index >= 256 || cm->count > 256 || 1317 (cm->index + cm->count) > 256) 1318 return EINVAL; 1319 error = copyin(cm->red, &rbuf[index], count); 1320 if (error) 1321 return error; 1322 error = copyin(cm->green, &gbuf[index], count); 1323 if (error) 1324 return error; 1325 error = copyin(cm->blue, &bbuf[index], count); 1326 if (error) 1327 return error; 1328 1329 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1330 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1331 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1332 1333 r = &sc->sc_cmap_red[index]; 1334 g = &sc->sc_cmap_green[index]; 1335 b = &sc->sc_cmap_blue[index]; 1336 1337 for (i = 0; i < count; i++) { 1338 mach64_putpalreg(sc, index, *r, *g, *b); 1339 index++; 1340 r++, g++, b++; 1341 } 1342 return 0; 1343 } 1344 1345 static int 1346 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1347 { 1348 u_int index = cm->index; 1349 u_int count = cm->count; 1350 int error; 1351 1352 if (index >= 255 || count > 256 || index + count > 256) 1353 return EINVAL; 1354 1355 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1356 if (error) 1357 return error; 1358 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1359 if (error) 1360 return error; 1361 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1362 if (error) 1363 return error; 1364 1365 return 0; 1366 } 1367 1368 static int 1369 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1370 { 1371 struct mach64_crtcregs regs; 1372 1373 if (mach64_calc_crtcregs(sc, ®s, 1374 (struct videomode *)des->modecookie)) 1375 return 1; 1376 1377 mach64_set_crtcregs(sc, ®s); 1378 return 0; 1379 } 1380 1381 static int 1382 mach64_is_console(struct mach64_softc *sc) 1383 { 1384 bool console = 0; 1385 1386 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1387 "is_console", &console); 1388 return console; 1389 } 1390 1391 /* 1392 * wsdisplay_emulops 1393 */ 1394 1395 static void 1396 mach64_cursor(void *cookie, int on, int row, int col) 1397 { 1398 struct rasops_info *ri = cookie; 1399 struct vcons_screen *scr = ri->ri_hw; 1400 struct mach64_softc *sc = scr->scr_cookie; 1401 int x, y, wi, he; 1402 1403 wi = ri->ri_font->fontwidth; 1404 he = ri->ri_font->fontheight; 1405 1406 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1407 x = ri->ri_ccol * wi + ri->ri_xorigin; 1408 y = ri->ri_crow * he + ri->ri_yorigin; 1409 if (ri->ri_flg & RI_CURSOR) { 1410 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1411 0xff); 1412 ri->ri_flg &= ~RI_CURSOR; 1413 } 1414 ri->ri_crow = row; 1415 ri->ri_ccol = col; 1416 if (on) { 1417 x = ri->ri_ccol * wi + ri->ri_xorigin; 1418 y = ri->ri_crow * he + ri->ri_yorigin; 1419 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1420 0xff); 1421 ri->ri_flg |= RI_CURSOR; 1422 } 1423 } else { 1424 scr->scr_ri.ri_crow = row; 1425 scr->scr_ri.ri_ccol = col; 1426 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1427 } 1428 } 1429 1430 #if 0 1431 static int 1432 mach64_mapchar(void *cookie, int uni, u_int *index) 1433 { 1434 return 0; 1435 } 1436 #endif 1437 1438 static void 1439 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1440 { 1441 struct rasops_info *ri = cookie; 1442 struct wsdisplay_font *font = PICK_FONT(ri, c); 1443 struct vcons_screen *scr = ri->ri_hw; 1444 struct mach64_softc *sc = scr->scr_cookie; 1445 1446 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1447 int fg, bg, uc; 1448 uint8_t *data; 1449 int x, y, wi, he; 1450 wi = font->fontwidth; 1451 he = font->fontheight; 1452 1453 if (!CHAR_IN_FONT(c, font)) 1454 return; 1455 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1456 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f]; 1457 x = ri->ri_xorigin + col * wi; 1458 y = ri->ri_yorigin + row * he; 1459 if (c == 0x20) { 1460 mach64_rectfill(sc, x, y, wi, he, bg); 1461 } else { 1462 uc = c - font->firstchar; 1463 data = (uint8_t *)font->data + uc * 1464 ri->ri_fontscale; 1465 1466 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1467 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1468 } 1469 } 1470 } 1471 1472 1473 static void 1474 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1475 { 1476 struct rasops_info *ri = cookie; 1477 struct vcons_screen *scr = ri->ri_hw; 1478 struct mach64_softc *sc = scr->scr_cookie; 1479 int32_t xs, xd, y, width, height; 1480 1481 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1482 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1483 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1484 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1485 width = ri->ri_font->fontwidth * ncols; 1486 height = ri->ri_font->fontheight; 1487 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff); 1488 } 1489 } 1490 1491 static void 1492 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1493 { 1494 struct rasops_info *ri = cookie; 1495 struct vcons_screen *scr = ri->ri_hw; 1496 struct mach64_softc *sc = scr->scr_cookie; 1497 int32_t x, y, width, height, fg, bg, ul; 1498 1499 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1500 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1501 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1502 width = ri->ri_font->fontwidth * ncols; 1503 height = ri->ri_font->fontheight; 1504 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1505 1506 mach64_rectfill(sc, x, y, width, height, bg); 1507 } 1508 } 1509 1510 static void 1511 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1512 { 1513 struct rasops_info *ri = cookie; 1514 struct vcons_screen *scr = ri->ri_hw; 1515 struct mach64_softc *sc = scr->scr_cookie; 1516 int32_t x, ys, yd, width, height; 1517 1518 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1519 x = ri->ri_xorigin; 1520 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1521 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1522 width = ri->ri_emuwidth; 1523 height = ri->ri_font->fontheight*nrows; 1524 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff); 1525 } 1526 } 1527 1528 static void 1529 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1530 { 1531 struct rasops_info *ri = cookie; 1532 struct vcons_screen *scr = ri->ri_hw; 1533 struct mach64_softc *sc = scr->scr_cookie; 1534 int32_t x, y, width, height, fg, bg, ul; 1535 1536 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1537 x = ri->ri_xorigin; 1538 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1539 width = ri->ri_emuwidth; 1540 height = ri->ri_font->fontheight * nrows; 1541 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1542 1543 mach64_rectfill(sc, x, y, width, height, bg); 1544 } 1545 } 1546 1547 static void 1548 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1549 { 1550 uint32_t dest_ctl = 0; 1551 1552 wait_for_idle(sc); 1553 regw(sc, DP_WRITE_MASK, mask); /* XXX only good for 8 bit */ 1554 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1555 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1556 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1557 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1558 if (yd < ys) { 1559 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1560 } else { 1561 ys += height - 1; 1562 yd += height - 1; 1563 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1564 } 1565 if (xd < xs) { 1566 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1567 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1568 } else { 1569 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1570 xs += width - 1; 1571 xd += width - 1; 1572 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1573 } 1574 regw(sc, DST_CNTL, dest_ctl); 1575 1576 regw(sc, SRC_Y_X, (xs << 16) | ys); 1577 regw(sc, SRC_WIDTH1, width); 1578 regw(sc, DST_Y_X, (xd << 16) | yd); 1579 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1580 } 1581 1582 static void 1583 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1584 int height, uint32_t fg, uint32_t bg) 1585 { 1586 wait_for_idle(sc); 1587 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1588 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1589 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1590 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1591 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1592 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1593 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1594 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1595 regw(sc, DP_BKGD_CLR, bg); 1596 regw(sc, DP_FRGD_CLR, fg); 1597 regw(sc, SRC_Y_X, 0); 1598 regw(sc, SRC_WIDTH1, width); 1599 regw(sc, DST_Y_X, (xd << 16) | yd); 1600 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1601 /* now feed the data into the chip */ 1602 } 1603 1604 static void 1605 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1606 { 1607 int i; 1608 uint32_t latch = 0, bork; 1609 int shift = 0; 1610 int reg = 0; 1611 1612 for (i=0;i<count;i++) { 1613 bork = data[i]; 1614 latch |= (bork << shift); 1615 if (shift == 24) { 1616 regw(sc, HOST_DATA0 + reg, latch); 1617 latch = 0; 1618 shift = 0; 1619 reg = (reg + 4) & 0x3c; 1620 } else 1621 shift += 8; 1622 } 1623 if (shift != 0) /* 24 */ 1624 regw(sc, HOST_DATA0 + reg, latch); 1625 } 1626 1627 1628 static void 1629 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1630 int colour) 1631 { 1632 wait_for_idle(sc); 1633 regw(sc, DP_WRITE_MASK, 0xff); 1634 regw(sc, DP_FRGD_CLR, colour); 1635 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1636 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1637 regw(sc, DP_MIX, MIX_SRC << 16); 1638 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1639 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1640 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1641 1642 regw(sc, SRC_Y_X, (x << 16) | y); 1643 regw(sc, SRC_WIDTH1, width); 1644 regw(sc, DST_Y_X, (x << 16) | y); 1645 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1646 } 1647 1648 static void 1649 mach64_clearscreen(struct mach64_softc *sc) 1650 { 1651 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1652 } 1653 1654 1655 #if 0 1656 static void 1657 mach64_showpal(struct mach64_softc *sc) 1658 { 1659 int i, x = 0; 1660 1661 for (i = 0; i < 16; i++) { 1662 mach64_rectfill(sc, x, 0, 64, 64, i); 1663 x += 64; 1664 } 1665 } 1666 #endif 1667 1668 /* 1669 * wsdisplay_accessops 1670 */ 1671 1672 static int 1673 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1674 struct lwp *l) 1675 { 1676 struct vcons_data *vd = v; 1677 struct mach64_softc *sc = vd->cookie; 1678 struct wsdisplay_fbinfo *wdf; 1679 struct vcons_screen *ms = vd->active; 1680 1681 switch (cmd) { 1682 case WSDISPLAYIO_GTYPE: 1683 /* XXX is this the right type to return? */ 1684 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1685 return 0; 1686 1687 case WSDISPLAYIO_LINEBYTES: 1688 *(u_int *)data = sc->virt_x * sc->bits_per_pixel / 8; 1689 return 0; 1690 1691 case WSDISPLAYIO_GINFO: 1692 wdf = (void *)data; 1693 wdf->height = sc->virt_y; 1694 wdf->width = sc->virt_x; 1695 wdf->depth = sc->bits_per_pixel; 1696 wdf->cmsize = 256; 1697 return 0; 1698 1699 case WSDISPLAYIO_GETCMAP: 1700 return mach64_getcmap(sc, 1701 (struct wsdisplay_cmap *)data); 1702 1703 case WSDISPLAYIO_PUTCMAP: 1704 return mach64_putcmap(sc, 1705 (struct wsdisplay_cmap *)data); 1706 1707 /* PCI config read/write passthrough. */ 1708 case PCI_IOC_CFGREAD: 1709 case PCI_IOC_CFGWRITE: 1710 return (pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1711 cmd, data, flag, l)); 1712 1713 case WSDISPLAYIO_SMODE: 1714 { 1715 int new_mode = *(int*)data; 1716 1717 if (new_mode != sc->sc_mode) 1718 { 1719 sc->sc_mode = new_mode; 1720 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1721 && (ms != NULL)) 1722 { 1723 /* restore initial video mode */ 1724 mach64_init(sc); 1725 mach64_init_engine(sc); 1726 mach64_init_lut(sc); 1727 mach64_modeswitch(sc, sc->sc_my_mode); 1728 vcons_redraw_screen(ms); 1729 } 1730 } 1731 } 1732 return 0; 1733 1734 } 1735 return EPASSTHROUGH; 1736 } 1737 1738 static paddr_t 1739 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1740 { 1741 struct vcons_data *vd = v; 1742 struct mach64_softc *sc = vd->cookie; 1743 paddr_t pa; 1744 pcireg_t reg; 1745 1746 #ifndef __sparc64__ 1747 /* 1748 *'regular' framebuffer mmap()ing 1749 * disabled on sparc64 because some ATI firmware likes to map some PCI 1750 * resources to addresses that would collide with this ( like some Rage 1751 * IIc which uses 0x2000 for the 2nd register block ) 1752 * Other 64bit architectures might run into similar problems. 1753 */ 1754 if (offset<sc->sc_apersize) { 1755 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, offset, 1756 prot, BUS_SPACE_MAP_LINEAR); 1757 return pa; 1758 } 1759 #endif 1760 1761 /* 1762 * restrict all other mappings to processes with superuser privileges 1763 * or the kernel itself 1764 */ 1765 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1766 NULL) != 0) { 1767 return -1; 1768 } 1769 1770 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1771 if (reg != sc->sc_regphys) { 1772 #ifdef DIAGNOSTIC 1773 printf("%s: BAR 0x18 changed! (%x %x)\n", 1774 device_xname(sc->sc_dev), (uint32_t)sc->sc_regphys, 1775 (uint32_t)reg); 1776 #endif 1777 sc->sc_regphys = reg; 1778 } 1779 1780 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1781 if (reg != sc->sc_aperphys) { 1782 #ifdef DIAGNOSTIC 1783 printf("%s: BAR 0x10 changed! (%x %x)\n", 1784 device_xname(sc->sc_dev), (uint32_t)sc->sc_aperphys, 1785 (uint32_t)reg); 1786 #endif 1787 sc->sc_aperphys = reg; 1788 } 1789 1790 if ((offset >= sc->sc_aperphys) && 1791 (offset < (sc->sc_aperphys + sc->sc_apersize))) { 1792 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1793 BUS_SPACE_MAP_LINEAR); 1794 return pa; 1795 } 1796 1797 if ((offset >= sc->sc_regphys) && 1798 (offset < (sc->sc_regphys + sc->sc_regsize))) { 1799 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1800 BUS_SPACE_MAP_LINEAR); 1801 return pa; 1802 } 1803 1804 if ((offset >= sc->sc_rom.vb_base) && 1805 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 1806 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1807 BUS_SPACE_MAP_LINEAR); 1808 return pa; 1809 } 1810 1811 #ifdef PCI_MAGIC_IO_RANGE 1812 if ((offset >= PCI_MAGIC_IO_RANGE) && 1813 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 1814 return bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1815 0, prot, BUS_SPACE_MAP_LINEAR); 1816 } 1817 #endif 1818 1819 return -1; 1820 } 1821 1822 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1823 static void 1824 set_address(struct rasops_info *ri, void *fb) 1825 { 1826 #ifdef notdef 1827 printf(" %d %d %d\n", ri->ri_xorigin, ri->ri_yorigin, ri->ri_stride); 1828 #endif 1829 ri->ri_bits = (void *)((char *)fb + ri->ri_stride * ri->ri_yorigin + 1830 ri->ri_xorigin); 1831 } 1832 1833 #if 0 1834 static int 1835 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1836 { 1837 1838 return 0; 1839 } 1840 #endif 1841 1842 void 1843 machfb_blank(struct mach64_softc *sc, int blank) 1844 { 1845 uint32_t reg; 1846 1847 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1848 1849 switch (blank) 1850 { 1851 case 0: 1852 reg = regr(sc, CRTC_GEN_CNTL); 1853 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1854 sc->sc_blanked = 0; 1855 break; 1856 case 1: 1857 reg = regr(sc, CRTC_GEN_CNTL); 1858 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1859 sc->sc_blanked = 1; 1860 break; 1861 default: 1862 break; 1863 } 1864 } 1865 1866 /* framebuffer device support */ 1867 #ifdef __sparc__ 1868 1869 static void 1870 machfb_unblank(device_t dev) 1871 { 1872 struct mach64_softc *sc = device_private(dev); 1873 1874 machfb_blank(sc, 0); 1875 } 1876 1877 static void 1878 machfb_fbattach(struct mach64_softc *sc) 1879 { 1880 struct fbdevice *fb = &sc->sc_fb; 1881 1882 fb->fb_device = sc->sc_dev; 1883 fb->fb_driver = &machfb_fbdriver; 1884 1885 fb->fb_type.fb_cmsize = 256; 1886 fb->fb_type.fb_size = sc->memsize; 1887 1888 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 1889 fb->fb_flags = sc->sc_dev->dv_cfdata->cf_flags & FB_USERMASK; 1890 fb->fb_type.fb_depth = sc->bits_per_pixel; 1891 fb->fb_type.fb_width = sc->virt_x; 1892 fb->fb_type.fb_height = sc->virt_y; 1893 1894 fb->fb_pixels = sc->sc_aperture; 1895 fb_attach(fb, sc->sc_console); 1896 } 1897 1898 int 1899 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 1900 { 1901 struct mach64_softc *sc; 1902 1903 sc = device_lookup_private(&machfb_cd, minor(dev)); 1904 if (sc == NULL) 1905 return ENXIO; 1906 sc->sc_locked = 1; 1907 1908 #ifdef MACHFB_DEBUG 1909 printf("machfb_fbopen(%d)\n", minor(dev)); 1910 #endif 1911 return 0; 1912 } 1913 1914 int 1915 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 1916 { 1917 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1918 1919 #ifdef MACHFB_DEBUG 1920 printf("machfb_fbclose()\n"); 1921 #endif 1922 mach64_init_engine(sc); 1923 mach64_init_lut(sc); 1924 sc->sc_locked = 0; 1925 return 0; 1926 } 1927 1928 int 1929 machfb_fbioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1930 { 1931 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1932 1933 #ifdef MACHFB_DEBUG 1934 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 1935 #endif 1936 switch (cmd) { 1937 case FBIOGTYPE: 1938 *(struct fbtype *)data = sc->sc_fb.fb_type; 1939 break; 1940 1941 case FBIOGATTR: 1942 #define fba ((struct fbgattr *)data) 1943 fba->real_type = sc->sc_fb.fb_type.fb_type; 1944 fba->owner = 0; /* XXX ??? */ 1945 fba->fbtype = sc->sc_fb.fb_type; 1946 fba->sattr.flags = 0; 1947 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 1948 fba->sattr.dev_specific[0] = sc->sc_nbus; 1949 fba->sattr.dev_specific[1] = sc->sc_ndev; 1950 fba->sattr.dev_specific[2] = sc->sc_nfunc; 1951 fba->sattr.dev_specific[3] = -1; 1952 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 1953 fba->emu_types[1] = -1; 1954 #undef fba 1955 break; 1956 1957 #if 0 1958 case FBIOGETCMAP: 1959 #define p ((struct fbcmap *)data) 1960 return (bt_getcmap(p, &sc->sc_cmap, 256, 1)); 1961 1962 case FBIOPUTCMAP: 1963 /* copy to software map */ 1964 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 1965 if (error) 1966 return error; 1967 /* now blast them into the chip */ 1968 /* XXX should use retrace interrupt */ 1969 cg6_loadcmap(sc, p->index, p->count); 1970 #undef p 1971 break; 1972 #endif 1973 case FBIOGVIDEO: 1974 *(int *)data = sc->sc_blanked; 1975 break; 1976 1977 case FBIOSVIDEO: 1978 machfb_blank(sc, *(int *)data); 1979 break; 1980 1981 #if 0 1982 case FBIOGCURSOR: 1983 break; 1984 1985 case FBIOSCURSOR: 1986 break; 1987 1988 case FBIOGCURPOS: 1989 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 1990 break; 1991 1992 case FBIOSCURPOS: 1993 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 1994 break; 1995 1996 case FBIOGCURMAX: 1997 /* max cursor size is 32x32 */ 1998 ((struct fbcurpos *)data)->x = 32; 1999 ((struct fbcurpos *)data)->y = 32; 2000 break; 2001 #endif 2002 case PCI_IOC_CFGREAD: 2003 case PCI_IOC_CFGWRITE: 2004 { 2005 int ret; 2006 2007 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 2008 cmd, data, flags, l); 2009 2010 #ifdef MACHFB_DEBUG 2011 printf("pci_devioctl: %d\n", ret); 2012 #endif 2013 return ret; 2014 } 2015 default: 2016 #ifdef MACHFB_DEBUG 2017 log(LOG_NOTICE, "machfb_fbioctl(0x%lx) (%s[%d])\n", cmd, 2018 p->p_comm, p->p_pid); 2019 #endif 2020 return ENOTTY; 2021 } 2022 #ifdef MACHFB_DEBUG 2023 printf("machfb_fbioctl done\n"); 2024 #endif 2025 return 0; 2026 } 2027 2028 paddr_t 2029 machfb_fbmmap(dev_t dev, off_t off, int prot) 2030 { 2031 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 2032 2033 if (sc != NULL) 2034 return mach64_mmap(&sc->vd, NULL, off, prot); 2035 2036 return 0; 2037 } 2038 2039 #endif /* __sparc__ */ 2040
Indexes created Thu Oct 02 14:10:14 GMT 2025