machfb.c revision 1.62.2.1
1 /* $NetBSD: machfb.c,v 1.62.2.1 2011/06/06 09:08:17 jruoho Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.62.2.1 2011/06/06 09:08:17 jruoho Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #ifdef __sparc__ 58 #include <dev/sun/fbio.h> 59 #include <dev/sun/fbvar.h> 60 #include <sys/conf.h> 61 #else 62 #include <dev/wscons/wsdisplayvar.h> 63 #endif 64 65 #include <dev/wscons/wsconsio.h> 66 #include <dev/wsfont/wsfont.h> 67 #include <dev/rasops/rasops.h> 68 #include <dev/pci/wsdisplay_pci.h> 69 70 #include <dev/wscons/wsdisplay_vconsvar.h> 71 72 #include "opt_wsemul.h" 73 #include "opt_machfb.h" 74 75 #define MACH64_REG_SIZE 1024 76 #define MACH64_REG_OFF 0x7ffc00 77 78 #define NBARS 3 /* number of Mach64 PCI BARs */ 79 80 struct vga_bar { 81 bus_addr_t vb_base; 82 pcireg_t vb_busaddr; 83 bus_size_t vb_size; 84 pcireg_t vb_type; 85 int vb_flags; 86 }; 87 88 struct mach64_softc { 89 device_t sc_dev; 90 #ifdef __sparc__ 91 struct fbdevice sc_fb; 92 #endif 93 pci_chipset_tag_t sc_pc; 94 pcitag_t sc_pcitag; 95 96 struct vga_bar sc_bars[NBARS]; 97 struct vga_bar sc_rom; 98 99 #define sc_aperbase sc_bars[0].vb_base 100 #define sc_apersize sc_bars[0].vb_size 101 #define sc_aperphys sc_bars[0].vb_busaddr 102 103 #define sc_iobase sc_bars[1].vb_base 104 #define sc_iosize sc_bars[1].vb_size 105 106 #define sc_regbase sc_bars[2].vb_base 107 #define sc_regsize sc_bars[2].vb_size 108 #define sc_regphys sc_bars[2].vb_busaddr 109 110 bus_space_tag_t sc_regt; 111 bus_space_tag_t sc_memt; 112 bus_space_tag_t sc_iot; 113 bus_space_handle_t sc_regh; 114 bus_space_handle_t sc_memh; 115 void *sc_aperture; /* mapped aperture vaddr */ 116 void *sc_registers; /* mapped registers vaddr */ 117 118 uint32_t sc_nbus, sc_ndev, sc_nfunc; 119 size_t memsize; 120 int memtype; 121 122 int sc_mode; 123 int sc_bg; 124 int sc_locked; 125 126 int has_dsp; 127 int bits_per_pixel; 128 int max_x; 129 int max_y; 130 int virt_x; 131 int virt_y; 132 int color_depth; 133 134 int mem_freq; 135 int ramdac_freq; 136 int ref_freq; 137 138 int ref_div; 139 int log2_vclk_post_div; 140 int vclk_post_div; 141 int vclk_fb_div; 142 int mclk_post_div; 143 int mclk_fb_div; 144 int sc_clock; /* which clock to use */ 145 146 struct videomode *sc_my_mode; 147 int sc_edid_size; 148 uint8_t sc_edid_data[1024]; 149 150 u_char sc_cmap_red[256]; 151 u_char sc_cmap_green[256]; 152 u_char sc_cmap_blue[256]; 153 int sc_dacw, sc_blanked, sc_console; 154 struct vcons_data vd; 155 struct wsdisplay_accessops sc_accessops; 156 }; 157 158 struct mach64_crtcregs { 159 uint32_t h_total_disp; 160 uint32_t h_sync_strt_wid; 161 uint32_t v_total_disp; 162 uint32_t v_sync_strt_wid; 163 uint32_t gen_cntl; 164 uint32_t clock_cntl; 165 uint32_t color_depth; 166 uint32_t dot_clock; 167 }; 168 169 static struct { 170 uint16_t chip_id; 171 uint32_t ramdac_freq; 172 } const mach64_info[] = { 173 { PCI_PRODUCT_ATI_MACH64_GX, 135000 }, 174 { PCI_PRODUCT_ATI_MACH64_CX, 135000 }, 175 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 176 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 185 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 186 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 189 #if 0 190 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 192 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 193 #endif 194 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 195 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 196 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 197 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 198 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 199 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 200 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 201 }; 202 203 static int mach64_chip_id, mach64_chip_rev; 204 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 205 206 static const char *mach64_gx_memtype_names[] = { 207 "DRAM", "VRAM", "VRAM", "DRAM", 208 "DRAM", "VRAM", "VRAM", "(unknown type)" 209 }; 210 211 static const char *mach64_memtype_names[] = { 212 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 213 "(unknown type)" 214 }; 215 216 static struct videomode mach64_modes[] = { 217 /* 640x400 @ 70 Hz, 31.5 kHz */ 218 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0, NULL, }, 219 /* 640x480 @ 72 Hz, 36.5 kHz */ 220 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0, NULL, }, 221 /* 800x600 @ 72 Hz, 48.0 kHz */ 222 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 223 VID_PHSYNC | VID_PVSYNC, NULL, }, 224 /* 1024x768 @ 70 Hz, 56.5 kHz */ 225 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 226 VID_NHSYNC | VID_NVSYNC, NULL, }, 227 /* 1152x864 @ 70 Hz, 62.4 kHz */ 228 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0, NULL, }, 229 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 230 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 231 VID_NHSYNC | VID_NVSYNC, NULL, } 232 }; 233 234 extern const u_char rasops_cmap[768]; 235 236 static int mach64_match(device_t, cfdata_t, void *); 237 static void mach64_attach(device_t, device_t, void *); 238 239 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 240 NULL, NULL); 241 242 static void mach64_init(struct mach64_softc *); 243 static int mach64_get_memsize(struct mach64_softc *); 244 static int mach64_get_max_ramdac(struct mach64_softc *); 245 246 #if defined(__sparc__) || defined(__powerpc__) 247 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 248 #endif 249 250 static int mach64_calc_crtcregs(struct mach64_softc *, 251 struct mach64_crtcregs *, 252 struct videomode *); 253 static void mach64_set_crtcregs(struct mach64_softc *, 254 struct mach64_crtcregs *); 255 256 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 257 static void mach64_set_dsp(struct mach64_softc *); 258 static void mach64_set_pll(struct mach64_softc *, int); 259 static void mach64_reset_engine(struct mach64_softc *); 260 static void mach64_init_engine(struct mach64_softc *); 261 #if 0 262 static void mach64_adjust_frame(struct mach64_softc *, int, int); 263 #endif 264 static void mach64_init_lut(struct mach64_softc *); 265 266 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 267 static int mach64_set_screentype(struct mach64_softc *, 268 const struct wsscreen_descr *); 269 static int mach64_is_console(struct mach64_softc *); 270 271 static void mach64_cursor(void *, int, int, int); 272 #if 0 273 static int mach64_mapchar(void *, int, u_int *); 274 #endif 275 static void mach64_putchar(void *, int, int, u_int, long); 276 static void mach64_copycols(void *, int, int, int, int); 277 static void mach64_erasecols(void *, int, int, int, long); 278 static void mach64_copyrows(void *, int, int, int); 279 static void mach64_eraserows(void *, int, int, long); 280 static void mach64_clearscreen(struct mach64_softc *); 281 282 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 283 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 284 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 285 uint8_t, uint8_t); 286 static void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, 287 int, int, int) ; 288 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 289 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 290 uint32_t, uint32_t); 291 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 292 #if 0 293 static void mach64_showpal(struct mach64_softc *); 294 #endif 295 296 static void set_address(struct rasops_info *, void *); 297 static void machfb_blank(struct mach64_softc *, int); 298 static int machfb_drm_print(void *, const char *); 299 300 static struct wsscreen_descr mach64_defaultscreen = { 301 "default", 302 80, 30, 303 NULL, 304 8, 16, 305 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 306 &default_mode 307 }, mach64_80x25_screen = { 308 "80x25", 80, 25, 309 NULL, 310 8, 16, 311 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 312 &mach64_modes[0] 313 }, mach64_80x30_screen = { 314 "80x30", 80, 30, 315 NULL, 316 8, 16, 317 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 318 &mach64_modes[1] 319 }, mach64_80x40_screen = { 320 "80x40", 80, 40, 321 NULL, 322 8, 10, 323 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 324 &mach64_modes[0] 325 }, mach64_80x50_screen = { 326 "80x50", 80, 50, 327 NULL, 328 8, 8, 329 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 330 &mach64_modes[0] 331 }, mach64_100x37_screen = { 332 "100x37", 100, 37, 333 NULL, 334 8, 16, 335 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 336 &mach64_modes[2] 337 }, mach64_128x48_screen = { 338 "128x48", 128, 48, 339 NULL, 340 8, 16, 341 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 342 &mach64_modes[3] 343 }, mach64_144x54_screen = { 344 "144x54", 144, 54, 345 NULL, 346 8, 16, 347 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 348 &mach64_modes[4] 349 }, mach64_160x64_screen = { 350 "160x54", 160, 64, 351 NULL, 352 8, 16, 353 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 354 &mach64_modes[5] 355 }; 356 357 static const struct wsscreen_descr *_mach64_scrlist[] = { 358 &mach64_defaultscreen, 359 &mach64_80x25_screen, 360 &mach64_80x30_screen, 361 &mach64_80x40_screen, 362 &mach64_80x50_screen, 363 &mach64_100x37_screen, 364 &mach64_128x48_screen, 365 &mach64_144x54_screen, 366 &mach64_160x64_screen 367 }; 368 369 static struct wsscreen_list mach64_screenlist = { 370 __arraycount(_mach64_scrlist), 371 _mach64_scrlist 372 }; 373 374 static int mach64_ioctl(void *, void *, u_long, void *, int, 375 struct lwp *); 376 static paddr_t mach64_mmap(void *, void *, off_t, int); 377 378 #if 0 379 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 380 #endif 381 382 383 static struct vcons_screen mach64_console_screen; 384 385 /* framebuffer device, SPARC-only so far */ 386 #ifdef __sparc__ 387 388 static void machfb_unblank(device_t); 389 static void machfb_fbattach(struct mach64_softc *); 390 391 extern struct cfdriver machfb_cd; 392 393 dev_type_open(machfb_fbopen); 394 dev_type_close(machfb_fbclose); 395 dev_type_ioctl(machfb_fbioctl); 396 dev_type_mmap(machfb_fbmmap); 397 398 /* frame buffer generic driver */ 399 static struct fbdriver machfb_fbdriver = { 400 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 401 machfb_fbmmap, nokqfilter 402 }; 403 404 #endif /* __sparc__ */ 405 406 /* 407 * Inline functions for getting access to register aperture. 408 */ 409 410 static inline uint32_t 411 regr(struct mach64_softc *sc, uint32_t index) 412 { 413 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 414 } 415 416 static inline uint8_t 417 regrb(struct mach64_softc *sc, uint32_t index) 418 { 419 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 420 } 421 422 static inline void 423 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 424 { 425 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 426 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 427 BUS_SPACE_BARRIER_WRITE); 428 } 429 430 static inline void 431 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 432 { 433 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 434 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 435 BUS_SPACE_BARRIER_WRITE); 436 } 437 438 static inline void 439 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 440 { 441 uint32_t reg; 442 443 reg = regr(sc, CLOCK_CNTL); 444 reg |= PLL_WR_EN; 445 regw(sc, CLOCK_CNTL, reg); 446 reg &= ~(PLL_ADDR | PLL_DATA); 447 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 448 reg |= data << PLL_DATA_SHIFT; 449 reg |= CLOCK_STROBE; 450 regw(sc, CLOCK_CNTL, reg); 451 reg &= ~PLL_WR_EN; 452 regw(sc, CLOCK_CNTL, reg); 453 } 454 455 static inline uint8_t 456 regrb_pll(struct mach64_softc *sc, uint32_t index) 457 { 458 459 regwb(sc, CLOCK_CNTL + 1, index << 2); 460 return regrb(sc, CLOCK_CNTL + 2); 461 } 462 463 static inline void 464 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 465 { 466 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 467 continue; 468 } 469 470 static inline void 471 wait_for_idle(struct mach64_softc *sc) 472 { 473 wait_for_fifo(sc, 16); 474 while ((regr(sc, GUI_STAT) & 1) != 0) 475 continue; 476 } 477 478 static int 479 mach64_match(device_t parent, cfdata_t match, void *aux) 480 { 481 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 482 int i; 483 484 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 485 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 486 return 0; 487 488 for (i = 0; i < __arraycount(mach64_info); i++) 489 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 490 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 491 mach64_chip_rev = PCI_REVISION(pa->pa_class); 492 return 100; 493 } 494 495 return 0; 496 } 497 498 static void 499 mach64_attach(device_t parent, device_t self, void *aux) 500 { 501 struct mach64_softc *sc = device_private(self); 502 struct pci_attach_args *pa = aux; 503 struct rasops_info *ri; 504 prop_data_t edid_data; 505 const struct videomode *mode = NULL; 506 char devinfo[256]; 507 int bar, id, expected_id; 508 int is_gx; 509 const char **memtype_names; 510 struct wsemuldisplaydev_attach_args aa; 511 long defattr; 512 int setmode, width, height; 513 pcireg_t screg; 514 uint32_t reg; 515 const pcireg_t enables = PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE; 516 517 sc->sc_dev = self; 518 sc->sc_pc = pa->pa_pc; 519 sc->sc_pcitag = pa->pa_tag; 520 sc->sc_dacw = -1; 521 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 522 sc->sc_nbus = pa->pa_bus; 523 sc->sc_ndev = pa->pa_device; 524 sc->sc_nfunc = pa->pa_function; 525 sc->sc_locked = 0; 526 sc->sc_iot = pa->pa_iot; 527 sc->sc_accessops.ioctl = mach64_ioctl; 528 sc->sc_accessops.mmap = mach64_mmap; 529 530 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 531 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 532 PCI_REVISION(pa->pa_class)); 533 aprint_naive(": Graphics processor\n"); 534 #ifdef MACHFB_DEBUG 535 printf(prop_dictionary_externalize(device_properties(self))); 536 #endif 537 538 /* enable memory and disable IO access */ 539 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 540 if ((screg & enables) != enables) { 541 screg |= enables; 542 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 543 PCI_COMMAND_STATUS_REG, screg); 544 } 545 for (bar = 0; bar < NBARS; bar++) { 546 reg = PCI_MAPREG_START + (bar * 4); 547 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 548 sc->sc_pcitag, reg); 549 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 550 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 551 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 552 sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc, 553 sc->sc_pcitag, reg) & 0xfffffff0; 554 } 555 printf("%s: aperture size %08x\n", device_xname(sc->sc_dev), 556 (uint32_t)sc->sc_apersize); 557 558 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 559 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 560 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 561 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 562 sc->sc_memt = pa->pa_memt; 563 564 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 565 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 566 panic("%s: failed to map aperture", device_xname(sc->sc_dev)); 567 } 568 sc->sc_aperture = (void *)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 569 570 /* If the BAR was never mapped, fix it up in MMIO. */ 571 if(sc->sc_regsize == 0) { 572 sc->sc_regsize = MACH64_REG_SIZE; 573 sc->sc_regbase = sc->sc_aperbase + MACH64_REG_OFF; 574 sc->sc_regphys = sc->sc_aperphys + MACH64_REG_OFF; 575 } 576 577 sc->sc_regt = sc->sc_memt; 578 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 579 sc->sc_regsize, &sc->sc_regh); 580 sc->sc_registers = (char *)sc->sc_aperture + 0x7ffc00; 581 582 mach64_init(sc); 583 584 aprint_normal_dev(sc->sc_dev, 585 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 586 (u_int)(sc->sc_apersize / (1024 * 1024)), 587 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 588 (u_int)sc->sc_regphys); 589 590 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 591 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 592 593 prop_dictionary_get_uint32(device_properties(self), "width", &width); 594 prop_dictionary_get_uint32(device_properties(self), "height", &height); 595 596 if ((edid_data = prop_dictionary_get(device_properties(self), "EDID")) 597 != NULL) { 598 struct edid_info ei; 599 600 sc->sc_edid_size = min(1024, prop_data_size(edid_data)); 601 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 602 memcpy(sc->sc_edid_data, prop_data_data_nocopy(edid_data), 603 sc->sc_edid_size); 604 605 edid_parse(sc->sc_edid_data, &ei); 606 607 #ifdef MACHFB_DEBUG 608 edid_print(&ei); 609 #endif 610 if (ei.edid_have_range) { 611 612 /* ei has dotclock in MHz, struct videomode in kHz */ 613 mode = pick_mode_by_dotclock(width, height, 614 ei.edid_range.er_max_clock * 1000); 615 if (mode != NULL) 616 printf("mode: %s\n", mode->name); 617 } 618 } 619 620 is_gx = 0; 621 switch(mach64_chip_id) { 622 case PCI_PRODUCT_ATI_MACH64_GX: 623 case PCI_PRODUCT_ATI_MACH64_CX: 624 is_gx = 1; 625 case PCI_PRODUCT_ATI_MACH64_CT: 626 sc->has_dsp = 0; 627 break; 628 case PCI_PRODUCT_ATI_MACH64_VT: 629 case PCI_PRODUCT_ATI_RAGE_II: 630 if((mach64_chip_rev & 0x07) == 0) { 631 sc->has_dsp = 0; 632 break; 633 } 634 /* Otherwise fall through. */ 635 default: 636 sc->has_dsp = 1; 637 } 638 639 memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names; 640 641 sc->memsize = mach64_get_memsize(sc); 642 if (sc->memsize == 8192) 643 /* The last page is used as register aperture. */ 644 sc->memsize -= 4; 645 if(is_gx) 646 sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07; 647 else 648 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 649 650 /* XXX is there any way to calculate reference frequency from 651 known values? */ 652 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 653 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 654 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 655 aprint_normal_dev(sc->sc_dev, "ref_freq=29.498MHz\n"); 656 sc->ref_freq = 29498; 657 } else 658 sc->ref_freq = 14318; 659 660 reg = regr(sc, CLOCK_CNTL); 661 printf("CLOCK_CNTL: %08x\n", reg); 662 sc->sc_clock = reg & 3; 663 printf("using clock %d\n", sc->sc_clock); 664 665 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 666 printf("ref_div: %d\n", sc->ref_div); 667 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 668 printf("mclk_fb_div: %d\n", sc->mclk_fb_div); 669 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 670 (sc->ref_div * 2); 671 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 672 (sc->mem_freq * sc->ref_div); 673 sc->ramdac_freq = mach64_get_max_ramdac(sc); 674 aprint_normal_dev(sc->sc_dev, 675 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 676 (u_long)sc->memsize, 677 memtype_names[sc->memtype], 678 sc->mem_freq / 1000, sc->mem_freq % 1000, 679 sc->ramdac_freq / 1000); 680 681 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 682 switch(mach64_chip_id) { 683 case PCI_PRODUCT_ATI_MACH64_GX: 684 expected_id = 0x00d7; 685 break; 686 case PCI_PRODUCT_ATI_MACH64_CX: 687 expected_id = 0x0057; 688 break; 689 default: 690 /* Most chip IDs match their PCI product ID. */ 691 expected_id = mach64_chip_id; 692 } 693 694 if (id != expected_id) { 695 aprint_error_dev(sc->sc_dev, 696 "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id); 697 return; 698 } 699 700 sc->sc_console = mach64_is_console(sc); 701 #ifdef DIAGNOSTIC 702 aprint_normal("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 703 #endif 704 #if defined(__sparc__) || defined(__powerpc__) 705 if (sc->sc_console) { 706 if (mode != NULL) { 707 memcpy(&default_mode, mode, sizeof(struct videomode)); 708 setmode = 1; 709 } else { 710 mach64_get_mode(sc, &default_mode); 711 setmode = 0; 712 } 713 sc->sc_my_mode = &default_mode; 714 } else { 715 /* fill in default_mode if it's empty */ 716 mach64_get_mode(sc, &default_mode); 717 if (default_mode.dot_clock == 0) { 718 memcpy(&default_mode, &mach64_modes[4], 719 sizeof(default_mode)); 720 } 721 sc->sc_my_mode = &default_mode; 722 setmode = 1; 723 } 724 #else 725 if (default_mode.dot_clock == 0) { 726 memcpy(&default_mode, &mach64_modes[0], 727 sizeof(default_mode)); 728 } 729 sc->sc_my_mode = &mach64_modes[0]; 730 setmode = 1; 731 #endif 732 733 sc->bits_per_pixel = 8; 734 sc->virt_x = sc->sc_my_mode->hdisplay; 735 sc->virt_y = sc->sc_my_mode->vdisplay; 736 sc->max_x = sc->virt_x - 1; 737 sc->max_y = (sc->memsize * 1024) / 738 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 739 740 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 741 742 mach64_init_engine(sc); 743 744 if (setmode) 745 mach64_modeswitch(sc, sc->sc_my_mode); 746 747 aprint_normal_dev(sc->sc_dev, 748 "initial resolution %dx%d at %d bpp\n", 749 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 750 sc->bits_per_pixel); 751 752 #ifdef __sparc__ 753 machfb_fbattach(sc); 754 #endif 755 756 wsfont_init(); 757 758 sc->sc_bg = WS_DEFAULT_BG; 759 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &sc->sc_accessops); 760 sc->vd.init_screen = mach64_init_screen; 761 762 mach64_init_lut(sc); 763 mach64_clearscreen(sc); 764 machfb_blank(sc, 0); /* unblank the screen */ 765 766 if (sc->sc_console) { 767 768 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 769 &defattr); 770 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 771 772 ri = &mach64_console_screen.scr_ri; 773 mach64_defaultscreen.textops = &ri->ri_ops; 774 mach64_defaultscreen.capabilities = ri->ri_caps; 775 mach64_defaultscreen.nrows = ri->ri_rows; 776 mach64_defaultscreen.ncols = ri->ri_cols; 777 778 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 779 vcons_replay_msgbuf(&mach64_console_screen); 780 } else { 781 /* 782 * since we're not the console we can postpone the rest 783 * until someone actually allocates a screen for us 784 */ 785 mach64_modeswitch(sc, sc->sc_my_mode); 786 } 787 788 aa.console = sc->sc_console; 789 aa.scrdata = &mach64_screenlist; 790 aa.accessops = &sc->sc_accessops; 791 aa.accesscookie = &sc->vd; 792 793 config_found(self, &aa, wsemuldisplaydevprint); 794 795 config_found_ia(self, "drm", aux, machfb_drm_print); 796 } 797 798 static int 799 machfb_drm_print(void *aux, const char *pnp) 800 { 801 if (pnp) 802 aprint_normal("direct rendering for %s", pnp); 803 return (UNSUPP); 804 } 805 806 static void 807 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 808 long *defattr) 809 { 810 struct mach64_softc *sc = cookie; 811 struct rasops_info *ri = &scr->scr_ri; 812 813 /* XXX for now */ 814 #define setmode 0 815 816 ri->ri_depth = sc->bits_per_pixel; 817 ri->ri_width = sc->sc_my_mode->hdisplay; 818 ri->ri_height = sc->sc_my_mode->vdisplay; 819 ri->ri_stride = ri->ri_width; 820 ri->ri_flg = RI_CENTER; 821 set_address(ri, sc->sc_aperture); 822 823 #ifdef VCONS_DRAW_INTR 824 scr->scr_flags |= VCONS_DONT_READ; 825 #endif 826 827 if (existing) { 828 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 829 panic("%s: failed to switch video mode", 830 device_xname(sc->sc_dev)); 831 } 832 } 833 834 rasops_init(ri, sc->sc_my_mode->vdisplay / 8, 835 sc->sc_my_mode->hdisplay / 8); 836 ri->ri_caps = WSSCREEN_WSCOLORS; 837 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 838 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 839 840 /* enable acceleration */ 841 ri->ri_hw = scr; 842 ri->ri_ops.copyrows = mach64_copyrows; 843 ri->ri_ops.copycols = mach64_copycols; 844 ri->ri_ops.eraserows = mach64_eraserows; 845 ri->ri_ops.erasecols = mach64_erasecols; 846 ri->ri_ops.cursor = mach64_cursor; 847 ri->ri_ops.putchar = mach64_putchar; 848 } 849 850 static void 851 mach64_init(struct mach64_softc *sc) 852 { 853 uint32_t *p32, saved_value; 854 uint8_t *p; 855 int need_swap; 856 857 /* 858 * Test wether the aperture is byte swapped or not 859 */ 860 p32 = (uint32_t*)sc->sc_aperture; 861 saved_value = *p32; 862 p = (uint8_t*)(u_long)sc->sc_aperture; 863 *p32 = 0x12345678; 864 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 865 need_swap = 0; 866 else 867 need_swap = 1; 868 if (need_swap) { 869 sc->sc_aperture = (char *)sc->sc_aperture + 0x800000; 870 #if 0 871 /* what the fsck is this for? */ 872 sc->sc_aperbase += 0x800000; 873 sc->sc_apersize -= 0x800000; 874 #endif 875 } 876 *p32 = saved_value; 877 878 sc->sc_blanked = 0; 879 } 880 881 static int 882 mach64_get_memsize(struct mach64_softc *sc) 883 { 884 int tmp, memsize; 885 int mem_tab[] = { 886 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 887 }; 888 tmp = regr(sc, MEM_CNTL); 889 #ifdef DIAGNOSTIC 890 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 891 #endif 892 if (sc->has_dsp) { 893 tmp &= 0x0000000f; 894 if (tmp < 8) 895 memsize = (tmp + 1) * 512; 896 else if (tmp < 12) 897 memsize = (tmp - 3) * 1024; 898 else 899 memsize = (tmp - 7) * 2048; 900 } else { 901 memsize = mem_tab[tmp & 0x07]; 902 } 903 904 return memsize; 905 } 906 907 static int 908 mach64_get_max_ramdac(struct mach64_softc *sc) 909 { 910 int i; 911 912 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 913 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 914 (mach64_chip_rev & 0x07)) 915 return 170000; 916 917 for (i = 0; i < __arraycount(mach64_info); i++) 918 if (mach64_chip_id == mach64_info[i].chip_id) 919 return mach64_info[i].ramdac_freq; 920 921 if (sc->bits_per_pixel == 8) 922 return 135000; 923 else 924 return 80000; 925 } 926 927 #if defined(__sparc__) || defined(__powerpc__) 928 static void 929 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 930 { 931 struct mach64_crtcregs crtc; 932 933 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 934 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 935 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 936 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 937 938 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 939 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 940 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 941 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 942 mode->hsync_start; 943 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 944 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 945 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 946 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 947 948 #ifdef MACHFB_DEBUG 949 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 950 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 951 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 952 #endif 953 } 954 #endif 955 956 static int 957 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 958 struct videomode *mode) 959 { 960 961 if (mode->dot_clock > sc->ramdac_freq) 962 /* Clock too high. */ 963 return 1; 964 965 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 966 ((mode->htotal >> 3) - 1); 967 crtc->h_sync_strt_wid = 968 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 969 ((mode->hsync_start >> 3) - 1); 970 971 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 972 (mode->vtotal - 1); 973 crtc->v_sync_strt_wid = 974 ((mode->vsync_end - mode->vsync_start) << 16) | 975 (mode->vsync_start - 1); 976 977 if (mode->flags & VID_NVSYNC) 978 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 979 980 switch (sc->bits_per_pixel) { 981 case 8: 982 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 983 break; 984 case 16: 985 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 986 break; 987 case 32: 988 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 989 break; 990 } 991 992 crtc->gen_cntl = 0; 993 if (mode->flags & VID_INTERLACE) 994 crtc->gen_cntl |= CRTC_INTERLACE_EN; 995 996 if (mode->flags & VID_CSYNC) 997 crtc->gen_cntl |= CRTC_CSYNC_EN; 998 999 crtc->dot_clock = mode->dot_clock; 1000 1001 return 0; 1002 } 1003 1004 static void 1005 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 1006 { 1007 1008 mach64_set_pll(sc, crtc->dot_clock); 1009 1010 if (sc->has_dsp) 1011 mach64_set_dsp(sc); 1012 #if 1 1013 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 1014 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1015 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 1016 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1017 1018 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 1019 1020 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1021 1022 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 1023 /* XXX this unconditionally enables composite sync on SPARC */ 1024 #ifdef __sparc__ 1025 CRTC_CSYNC_EN | 1026 #endif 1027 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 1028 #endif 1029 } 1030 1031 static int 1032 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 1033 { 1034 struct mach64_crtcregs crtc; 1035 1036 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 1037 1038 if (mach64_calc_crtcregs(sc, &crtc, mode)) 1039 return 1; 1040 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 1041 if (crtc.dot_clock == 0) { 1042 aprint_error("%s: preposterous dot clock (%d)\n", 1043 device_xname(sc->sc_dev), crtc.dot_clock); 1044 return 1; 1045 } 1046 mach64_set_crtcregs(sc, &crtc); 1047 return 0; 1048 } 1049 1050 static void 1051 mach64_reset_engine(struct mach64_softc *sc) 1052 { 1053 1054 /* Reset engine.*/ 1055 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1056 1057 /* Enable engine. */ 1058 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1059 1060 /* Ensure engine is not locked up by clearing any FIFO or 1061 host errors. */ 1062 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1063 BUS_FIFO_ERR_ACK); 1064 } 1065 1066 static void 1067 mach64_init_engine(struct mach64_softc *sc) 1068 { 1069 uint32_t pitch_value; 1070 1071 pitch_value = sc->virt_x; 1072 1073 if (sc->bits_per_pixel == 24) 1074 pitch_value *= 3; 1075 1076 mach64_reset_engine(sc); 1077 1078 wait_for_fifo(sc, 14); 1079 1080 regw(sc, CONTEXT_MASK, 0xffffffff); 1081 1082 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 1083 1084 /* make sure the visible area starts where we're going to draw */ 1085 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1086 1087 regw(sc, DST_Y_X, 0); 1088 regw(sc, DST_HEIGHT, 0); 1089 regw(sc, DST_BRES_ERR, 0); 1090 regw(sc, DST_BRES_INC, 0); 1091 regw(sc, DST_BRES_DEC, 0); 1092 1093 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1094 DST_Y_TOP_TO_BOTTOM); 1095 1096 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 1097 1098 regw(sc, SRC_Y_X, 0); 1099 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1100 regw(sc, SRC_Y_X_START, 0); 1101 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1102 1103 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1104 1105 wait_for_fifo(sc, 13); 1106 regw(sc, HOST_CNTL, 0); 1107 1108 regw(sc, PAT_REG0, 0); 1109 regw(sc, PAT_REG1, 0); 1110 regw(sc, PAT_CNTL, 0); 1111 1112 regw(sc, SC_LEFT, 0); 1113 regw(sc, SC_TOP, 0); 1114 regw(sc, SC_BOTTOM, sc->sc_my_mode->vdisplay - 1); 1115 regw(sc, SC_RIGHT, pitch_value - 1); 1116 1117 regw(sc, DP_BKGD_CLR, WS_DEFAULT_BG); 1118 regw(sc, DP_FRGD_CLR, WS_DEFAULT_FG); 1119 regw(sc, DP_WRITE_MASK, 0xffffffff); 1120 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1121 1122 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1123 1124 wait_for_fifo(sc, 3); 1125 regw(sc, CLR_CMP_CLR, 0); 1126 regw(sc, CLR_CMP_MASK, 0xffffffff); 1127 regw(sc, CLR_CMP_CNTL, 0); 1128 1129 wait_for_fifo(sc, 2); 1130 switch (sc->bits_per_pixel) { 1131 case 8: 1132 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP); 1133 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1134 /* We want 8 bit per channel */ 1135 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1136 break; 1137 case 32: 1138 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP); 1139 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1140 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1141 break; 1142 } 1143 1144 wait_for_fifo(sc, 5); 1145 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1146 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1147 1148 wait_for_idle(sc); 1149 } 1150 1151 #if 0 1152 static void 1153 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1154 { 1155 int offset; 1156 1157 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1158 1159 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1160 offset); 1161 } 1162 #endif 1163 1164 static void 1165 mach64_set_dsp(struct mach64_softc *sc) 1166 { 1167 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1168 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1169 uint32_t xclks_per_qw, y; 1170 uint32_t fifo_off, fifo_on; 1171 1172 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1173 1174 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1175 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1176 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1177 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1178 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1179 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1180 dsp_loop_latency = 0; 1181 fifo_depth = 24; 1182 } else { 1183 dsp_loop_latency = 2; 1184 fifo_depth = 32; 1185 } 1186 1187 dsp_precision = 0; 1188 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1189 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1190 y = (xclks_per_qw * fifo_depth) >> 11; 1191 while (y) { 1192 y >>= 1; 1193 dsp_precision++; 1194 } 1195 dsp_precision -= 5; 1196 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1197 1198 switch (sc->memtype) { 1199 case DRAM: 1200 case EDO_DRAM: 1201 case PSEUDO_EDO: 1202 if (sc->memsize > 1024) { 1203 page_size = 9; 1204 dsp_loop_latency += 6; 1205 } else { 1206 page_size = 10; 1207 if (sc->memtype == DRAM) 1208 dsp_loop_latency += 8; 1209 else 1210 dsp_loop_latency += 7; 1211 } 1212 break; 1213 case SDRAM: 1214 case SGRAM: 1215 if (sc->memsize > 1024) { 1216 page_size = 8; 1217 dsp_loop_latency += 8; 1218 } else { 1219 page_size = 10; 1220 dsp_loop_latency += 9; 1221 } 1222 break; 1223 default: 1224 page_size = 10; 1225 dsp_loop_latency += 9; 1226 break; 1227 } 1228 1229 if (xclks_per_qw >= (page_size << 11)) 1230 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1231 else 1232 fifo_on = (3 * page_size + 2) << 6; 1233 1234 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1235 dsp_on = fifo_on >> dsp_precision; 1236 dsp_off = fifo_off >> dsp_precision; 1237 1238 #ifdef MACHFB_DEBUG 1239 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1240 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1241 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1242 "mclk_post_div = %d, vclk_post_div = %d\n", 1243 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1244 sc->mclk_fb_div, sc->vclk_fb_div, 1245 sc->mclk_post_div, sc->vclk_post_div); 1246 #endif 1247 1248 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1249 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1250 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1251 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1252 } 1253 1254 static void 1255 mach64_set_pll(struct mach64_softc *sc, int clock) 1256 { 1257 uint32_t q, clockreg; 1258 int clockshift = sc->sc_clock << 1; 1259 uint8_t reg, vclk_ctl; 1260 1261 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1262 #ifdef MACHFB_DEBUG 1263 printf("q = %d\n", q); 1264 #endif 1265 if (q > 25500) { 1266 printf("Warning: q > 25500\n"); 1267 q = 25500; 1268 sc->vclk_post_div = 1; 1269 sc->log2_vclk_post_div = 0; 1270 } else if (q > 12750) { 1271 sc->vclk_post_div = 1; 1272 sc->log2_vclk_post_div = 0; 1273 } else if (q > 6350) { 1274 sc->vclk_post_div = 2; 1275 sc->log2_vclk_post_div = 1; 1276 } else if (q > 3150) { 1277 sc->vclk_post_div = 4; 1278 sc->log2_vclk_post_div = 2; 1279 } else if (q >= 1600) { 1280 sc->vclk_post_div = 8; 1281 sc->log2_vclk_post_div = 3; 1282 } else { 1283 printf("Warning: q < 1600\n"); 1284 sc->vclk_post_div = 8; 1285 sc->log2_vclk_post_div = 3; 1286 } 1287 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1288 printf("post_div: %d log2_post_div: %d mclk_div: %d\n", sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1289 1290 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1291 printf("vclk_ctl: %02x\n", vclk_ctl); 1292 vclk_ctl |= PLL_VCLK_RESET; 1293 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1294 1295 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1296 reg = regrb_pll(sc, VCLK_POST_DIV); 1297 reg &= ~(3 << clockshift); 1298 reg |= (sc->log2_vclk_post_div << clockshift); 1299 regwb_pll(sc, VCLK_POST_DIV, reg); 1300 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1301 1302 vclk_ctl &= ~PLL_VCLK_RESET; 1303 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1304 1305 clockreg = regr(sc, CLOCK_CNTL); 1306 clockreg &= ~CLOCK_SEL; 1307 clockreg |= sc->sc_clock | CLOCK_STROBE; 1308 regw(sc, CLOCK_CNTL, clockreg); 1309 } 1310 1311 static void 1312 mach64_init_lut(struct mach64_softc *sc) 1313 { 1314 int i, idx; 1315 1316 idx = 0; 1317 for (i = 0; i < 256; i++) { 1318 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1], 1319 rasops_cmap[idx + 2]); 1320 idx += 3; 1321 } 1322 } 1323 1324 static int 1325 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1326 uint8_t b) 1327 { 1328 sc->sc_cmap_red[index] = r; 1329 sc->sc_cmap_green[index] = g; 1330 sc->sc_cmap_blue[index] = b; 1331 /* 1332 * writing the dac index takes a while, in theory we can poll some 1333 * register to see when it's ready - but we better avoid writing it 1334 * unnecessarily 1335 */ 1336 if (index != sc->sc_dacw) { 1337 regwb(sc, DAC_MASK, 0xff); 1338 regwb(sc, DAC_WINDEX, index); 1339 } 1340 sc->sc_dacw = index + 1; 1341 regwb(sc, DAC_DATA, r); 1342 regwb(sc, DAC_DATA, g); 1343 regwb(sc, DAC_DATA, b); 1344 return 0; 1345 } 1346 1347 static int 1348 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1349 { 1350 uint index = cm->index; 1351 uint count = cm->count; 1352 int i, error; 1353 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1354 uint8_t *r, *g, *b; 1355 1356 if (cm->index >= 256 || cm->count > 256 || 1357 (cm->index + cm->count) > 256) 1358 return EINVAL; 1359 error = copyin(cm->red, &rbuf[index], count); 1360 if (error) 1361 return error; 1362 error = copyin(cm->green, &gbuf[index], count); 1363 if (error) 1364 return error; 1365 error = copyin(cm->blue, &bbuf[index], count); 1366 if (error) 1367 return error; 1368 1369 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1370 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1371 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1372 1373 r = &sc->sc_cmap_red[index]; 1374 g = &sc->sc_cmap_green[index]; 1375 b = &sc->sc_cmap_blue[index]; 1376 1377 for (i = 0; i < count; i++) { 1378 mach64_putpalreg(sc, index, *r, *g, *b); 1379 index++; 1380 r++, g++, b++; 1381 } 1382 return 0; 1383 } 1384 1385 static int 1386 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1387 { 1388 u_int index = cm->index; 1389 u_int count = cm->count; 1390 int error; 1391 1392 if (index >= 255 || count > 256 || index + count > 256) 1393 return EINVAL; 1394 1395 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1396 if (error) 1397 return error; 1398 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1399 if (error) 1400 return error; 1401 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1402 if (error) 1403 return error; 1404 1405 return 0; 1406 } 1407 1408 static int 1409 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1410 { 1411 struct mach64_crtcregs regs; 1412 1413 if (mach64_calc_crtcregs(sc, ®s, 1414 (struct videomode *)des->modecookie)) 1415 return 1; 1416 1417 mach64_set_crtcregs(sc, ®s); 1418 return 0; 1419 } 1420 1421 static int 1422 mach64_is_console(struct mach64_softc *sc) 1423 { 1424 bool console = 0; 1425 1426 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1427 "is_console", &console); 1428 return console; 1429 } 1430 1431 /* 1432 * wsdisplay_emulops 1433 */ 1434 1435 static void 1436 mach64_cursor(void *cookie, int on, int row, int col) 1437 { 1438 struct rasops_info *ri = cookie; 1439 struct vcons_screen *scr = ri->ri_hw; 1440 struct mach64_softc *sc = scr->scr_cookie; 1441 int x, y, wi, he; 1442 1443 wi = ri->ri_font->fontwidth; 1444 he = ri->ri_font->fontheight; 1445 1446 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1447 x = ri->ri_ccol * wi + ri->ri_xorigin; 1448 y = ri->ri_crow * he + ri->ri_yorigin; 1449 if (ri->ri_flg & RI_CURSOR) { 1450 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1451 0xff); 1452 ri->ri_flg &= ~RI_CURSOR; 1453 } 1454 ri->ri_crow = row; 1455 ri->ri_ccol = col; 1456 if (on) { 1457 x = ri->ri_ccol * wi + ri->ri_xorigin; 1458 y = ri->ri_crow * he + ri->ri_yorigin; 1459 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1460 0xff); 1461 ri->ri_flg |= RI_CURSOR; 1462 } 1463 } else { 1464 scr->scr_ri.ri_crow = row; 1465 scr->scr_ri.ri_ccol = col; 1466 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1467 } 1468 } 1469 1470 #if 0 1471 static int 1472 mach64_mapchar(void *cookie, int uni, u_int *index) 1473 { 1474 return 0; 1475 } 1476 #endif 1477 1478 static void 1479 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1480 { 1481 struct rasops_info *ri = cookie; 1482 struct wsdisplay_font *font = PICK_FONT(ri, c); 1483 struct vcons_screen *scr = ri->ri_hw; 1484 struct mach64_softc *sc = scr->scr_cookie; 1485 1486 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1487 int fg, bg, uc; 1488 uint8_t *data; 1489 int x, y, wi, he; 1490 wi = font->fontwidth; 1491 he = font->fontheight; 1492 1493 if (!CHAR_IN_FONT(c, font)) 1494 return; 1495 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1496 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f]; 1497 x = ri->ri_xorigin + col * wi; 1498 y = ri->ri_yorigin + row * he; 1499 if (c == 0x20) { 1500 mach64_rectfill(sc, x, y, wi, he, bg); 1501 } else { 1502 uc = c - font->firstchar; 1503 data = (uint8_t *)font->data + uc * 1504 ri->ri_fontscale; 1505 1506 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1507 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1508 } 1509 } 1510 } 1511 1512 1513 static void 1514 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1515 { 1516 struct rasops_info *ri = cookie; 1517 struct vcons_screen *scr = ri->ri_hw; 1518 struct mach64_softc *sc = scr->scr_cookie; 1519 int32_t xs, xd, y, width, height; 1520 1521 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1522 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1523 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1524 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1525 width = ri->ri_font->fontwidth * ncols; 1526 height = ri->ri_font->fontheight; 1527 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff); 1528 } 1529 } 1530 1531 static void 1532 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1533 { 1534 struct rasops_info *ri = cookie; 1535 struct vcons_screen *scr = ri->ri_hw; 1536 struct mach64_softc *sc = scr->scr_cookie; 1537 int32_t x, y, width, height, fg, bg, ul; 1538 1539 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1540 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1541 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1542 width = ri->ri_font->fontwidth * ncols; 1543 height = ri->ri_font->fontheight; 1544 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1545 1546 mach64_rectfill(sc, x, y, width, height, bg); 1547 } 1548 } 1549 1550 static void 1551 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1552 { 1553 struct rasops_info *ri = cookie; 1554 struct vcons_screen *scr = ri->ri_hw; 1555 struct mach64_softc *sc = scr->scr_cookie; 1556 int32_t x, ys, yd, width, height; 1557 1558 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1559 x = ri->ri_xorigin; 1560 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1561 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1562 width = ri->ri_emuwidth; 1563 height = ri->ri_font->fontheight*nrows; 1564 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff); 1565 } 1566 } 1567 1568 static void 1569 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1570 { 1571 struct rasops_info *ri = cookie; 1572 struct vcons_screen *scr = ri->ri_hw; 1573 struct mach64_softc *sc = scr->scr_cookie; 1574 int32_t x, y, width, height, fg, bg, ul; 1575 1576 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1577 x = ri->ri_xorigin; 1578 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1579 width = ri->ri_emuwidth; 1580 height = ri->ri_font->fontheight * nrows; 1581 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1582 1583 mach64_rectfill(sc, x, y, width, height, bg); 1584 } 1585 } 1586 1587 static void 1588 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1589 { 1590 uint32_t dest_ctl = 0; 1591 1592 wait_for_idle(sc); 1593 regw(sc, DP_WRITE_MASK, mask); /* XXX only good for 8 bit */ 1594 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1595 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1596 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1597 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1598 if (yd < ys) { 1599 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1600 } else { 1601 ys += height - 1; 1602 yd += height - 1; 1603 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1604 } 1605 if (xd < xs) { 1606 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1607 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1608 } else { 1609 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1610 xs += width - 1; 1611 xd += width - 1; 1612 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1613 } 1614 regw(sc, DST_CNTL, dest_ctl); 1615 1616 regw(sc, SRC_Y_X, (xs << 16) | ys); 1617 regw(sc, SRC_WIDTH1, width); 1618 regw(sc, DST_Y_X, (xd << 16) | yd); 1619 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1620 } 1621 1622 static void 1623 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1624 int height, uint32_t fg, uint32_t bg) 1625 { 1626 wait_for_idle(sc); 1627 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1628 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1629 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1630 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1631 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1632 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1633 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1634 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1635 regw(sc, DP_BKGD_CLR, bg); 1636 regw(sc, DP_FRGD_CLR, fg); 1637 regw(sc, SRC_Y_X, 0); 1638 regw(sc, SRC_WIDTH1, width); 1639 regw(sc, DST_Y_X, (xd << 16) | yd); 1640 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1641 /* now feed the data into the chip */ 1642 } 1643 1644 static void 1645 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1646 { 1647 int i; 1648 uint32_t latch = 0, bork; 1649 int shift = 0; 1650 int reg = 0; 1651 1652 for (i = 0; i < count; i++) { 1653 bork = data[i]; 1654 latch |= (bork << shift); 1655 if (shift == 24) { 1656 regw(sc, HOST_DATA0 + reg, latch); 1657 latch = 0; 1658 shift = 0; 1659 reg = (reg + 4) & 0x3c; 1660 } else 1661 shift += 8; 1662 } 1663 if (shift != 0) /* 24 */ 1664 regw(sc, HOST_DATA0 + reg, latch); 1665 } 1666 1667 1668 static void 1669 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1670 int colour) 1671 { 1672 wait_for_idle(sc); 1673 regw(sc, DP_WRITE_MASK, 0xff); 1674 regw(sc, DP_FRGD_CLR, colour); 1675 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1676 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1677 regw(sc, DP_MIX, MIX_SRC << 16); 1678 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1679 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1680 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1681 1682 regw(sc, SRC_Y_X, (x << 16) | y); 1683 regw(sc, SRC_WIDTH1, width); 1684 regw(sc, DST_Y_X, (x << 16) | y); 1685 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1686 } 1687 1688 static void 1689 mach64_clearscreen(struct mach64_softc *sc) 1690 { 1691 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1692 } 1693 1694 1695 #if 0 1696 static void 1697 mach64_showpal(struct mach64_softc *sc) 1698 { 1699 int i, x = 0; 1700 1701 for (i = 0; i < 16; i++) { 1702 mach64_rectfill(sc, x, 0, 64, 64, i); 1703 x += 64; 1704 } 1705 } 1706 #endif 1707 1708 /* 1709 * wsdisplay_accessops 1710 */ 1711 1712 static int 1713 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1714 struct lwp *l) 1715 { 1716 struct vcons_data *vd = v; 1717 struct mach64_softc *sc = vd->cookie; 1718 struct wsdisplay_fbinfo *wdf; 1719 struct vcons_screen *ms = vd->active; 1720 1721 switch (cmd) { 1722 case WSDISPLAYIO_GTYPE: 1723 /* XXX is this the right type to return? */ 1724 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1725 return 0; 1726 1727 case WSDISPLAYIO_LINEBYTES: 1728 *(u_int *)data = sc->virt_x * sc->bits_per_pixel / 8; 1729 return 0; 1730 1731 case WSDISPLAYIO_GINFO: 1732 wdf = (void *)data; 1733 wdf->height = sc->virt_y; 1734 wdf->width = sc->virt_x; 1735 wdf->depth = sc->bits_per_pixel; 1736 wdf->cmsize = 256; 1737 return 0; 1738 1739 case WSDISPLAYIO_GETCMAP: 1740 return mach64_getcmap(sc, 1741 (struct wsdisplay_cmap *)data); 1742 1743 case WSDISPLAYIO_PUTCMAP: 1744 return mach64_putcmap(sc, 1745 (struct wsdisplay_cmap *)data); 1746 1747 /* PCI config read/write passthrough. */ 1748 case PCI_IOC_CFGREAD: 1749 case PCI_IOC_CFGWRITE: 1750 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1751 cmd, data, flag, l); 1752 1753 case WSDISPLAYIO_GET_BUSID: 1754 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1755 sc->sc_pcitag, data); 1756 1757 case WSDISPLAYIO_SMODE: { 1758 int new_mode = *(int*)data; 1759 if (new_mode != sc->sc_mode) { 1760 sc->sc_mode = new_mode; 1761 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1762 && (ms != NULL)) 1763 { 1764 /* restore initial video mode */ 1765 mach64_init(sc); 1766 mach64_init_engine(sc); 1767 mach64_init_lut(sc); 1768 mach64_modeswitch(sc, sc->sc_my_mode); 1769 vcons_redraw_screen(ms); 1770 } 1771 } 1772 } 1773 return 0; 1774 1775 } 1776 return EPASSTHROUGH; 1777 } 1778 1779 static paddr_t 1780 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1781 { 1782 struct vcons_data *vd = v; 1783 struct mach64_softc *sc = vd->cookie; 1784 paddr_t pa; 1785 pcireg_t reg; 1786 1787 #ifndef __sparc64__ 1788 /* 1789 *'regular' framebuffer mmap()ing 1790 * disabled on sparc64 because some ATI firmware likes to map some PCI 1791 * resources to addresses that would collide with this ( like some Rage 1792 * IIc which uses 0x2000 for the 2nd register block ) 1793 * Other 64bit architectures might run into similar problems. 1794 */ 1795 if (offset<sc->sc_apersize) { 1796 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, offset, 1797 prot, BUS_SPACE_MAP_LINEAR); 1798 return pa; 1799 } 1800 #endif 1801 1802 /* 1803 * restrict all other mappings to processes with superuser privileges 1804 * or the kernel itself 1805 */ 1806 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1807 NULL) != 0) { 1808 return -1; 1809 } 1810 1811 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1812 if (reg != sc->sc_regphys) { 1813 #ifdef DIAGNOSTIC 1814 printf("%s: BAR 0x18 changed! (%x %x)\n", 1815 device_xname(sc->sc_dev), (uint32_t)sc->sc_regphys, 1816 (uint32_t)reg); 1817 #endif 1818 sc->sc_regphys = reg; 1819 } 1820 1821 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1822 if (reg != sc->sc_aperphys) { 1823 #ifdef DIAGNOSTIC 1824 printf("%s: BAR 0x10 changed! (%x %x)\n", 1825 device_xname(sc->sc_dev), (uint32_t)sc->sc_aperphys, 1826 (uint32_t)reg); 1827 #endif 1828 sc->sc_aperphys = reg; 1829 } 1830 1831 if ((offset >= sc->sc_aperphys) && 1832 (offset < (sc->sc_aperphys + sc->sc_apersize))) { 1833 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1834 BUS_SPACE_MAP_LINEAR); 1835 return pa; 1836 } 1837 1838 if ((offset >= sc->sc_regphys) && 1839 (offset < (sc->sc_regphys + sc->sc_regsize))) { 1840 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1841 BUS_SPACE_MAP_LINEAR); 1842 return pa; 1843 } 1844 1845 if ((offset >= sc->sc_rom.vb_base) && 1846 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 1847 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1848 BUS_SPACE_MAP_LINEAR); 1849 return pa; 1850 } 1851 1852 #ifdef PCI_MAGIC_IO_RANGE 1853 if ((offset >= PCI_MAGIC_IO_RANGE) && 1854 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 1855 return bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1856 0, prot, BUS_SPACE_MAP_LINEAR); 1857 } 1858 #endif 1859 1860 return -1; 1861 } 1862 1863 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1864 static void 1865 set_address(struct rasops_info *ri, void *fb) 1866 { 1867 #ifdef notdef 1868 printf(" %d %d %d\n", ri->ri_xorigin, ri->ri_yorigin, ri->ri_stride); 1869 #endif 1870 ri->ri_bits = (void *)((char *)fb + ri->ri_stride * ri->ri_yorigin + 1871 ri->ri_xorigin); 1872 } 1873 1874 #if 0 1875 static int 1876 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1877 { 1878 1879 return 0; 1880 } 1881 #endif 1882 1883 void 1884 machfb_blank(struct mach64_softc *sc, int blank) 1885 { 1886 uint32_t reg; 1887 1888 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1889 1890 switch (blank) 1891 { 1892 case 0: 1893 reg = regr(sc, CRTC_GEN_CNTL); 1894 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1895 sc->sc_blanked = 0; 1896 break; 1897 case 1: 1898 reg = regr(sc, CRTC_GEN_CNTL); 1899 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1900 sc->sc_blanked = 1; 1901 break; 1902 default: 1903 break; 1904 } 1905 } 1906 1907 /* framebuffer device support */ 1908 #ifdef __sparc__ 1909 1910 static void 1911 machfb_unblank(device_t dev) 1912 { 1913 struct mach64_softc *sc = device_private(dev); 1914 1915 machfb_blank(sc, 0); 1916 } 1917 1918 static void 1919 machfb_fbattach(struct mach64_softc *sc) 1920 { 1921 struct fbdevice *fb = &sc->sc_fb; 1922 1923 fb->fb_device = sc->sc_dev; 1924 fb->fb_driver = &machfb_fbdriver; 1925 1926 fb->fb_type.fb_cmsize = 256; 1927 fb->fb_type.fb_size = sc->memsize; 1928 1929 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 1930 fb->fb_flags = sc->sc_dev->dv_cfdata->cf_flags & FB_USERMASK; 1931 fb->fb_type.fb_depth = sc->bits_per_pixel; 1932 fb->fb_type.fb_width = sc->virt_x; 1933 fb->fb_type.fb_height = sc->virt_y; 1934 1935 fb->fb_pixels = sc->sc_aperture; 1936 fb_attach(fb, sc->sc_console); 1937 } 1938 1939 int 1940 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 1941 { 1942 struct mach64_softc *sc; 1943 1944 sc = device_lookup_private(&machfb_cd, minor(dev)); 1945 if (sc == NULL) 1946 return ENXIO; 1947 sc->sc_locked = 1; 1948 1949 #ifdef MACHFB_DEBUG 1950 printf("machfb_fbopen(%d)\n", minor(dev)); 1951 #endif 1952 return 0; 1953 } 1954 1955 int 1956 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 1957 { 1958 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1959 1960 #ifdef MACHFB_DEBUG 1961 printf("machfb_fbclose()\n"); 1962 #endif 1963 mach64_init_engine(sc); 1964 mach64_init_lut(sc); 1965 sc->sc_locked = 0; 1966 return 0; 1967 } 1968 1969 int 1970 machfb_fbioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1971 { 1972 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1973 1974 #ifdef MACHFB_DEBUG 1975 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 1976 #endif 1977 switch (cmd) { 1978 case FBIOGTYPE: 1979 *(struct fbtype *)data = sc->sc_fb.fb_type; 1980 break; 1981 1982 case FBIOGATTR: 1983 #define fba ((struct fbgattr *)data) 1984 fba->real_type = sc->sc_fb.fb_type.fb_type; 1985 fba->owner = 0; /* XXX ??? */ 1986 fba->fbtype = sc->sc_fb.fb_type; 1987 fba->sattr.flags = 0; 1988 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 1989 fba->sattr.dev_specific[0] = sc->sc_nbus; 1990 fba->sattr.dev_specific[1] = sc->sc_ndev; 1991 fba->sattr.dev_specific[2] = sc->sc_nfunc; 1992 fba->sattr.dev_specific[3] = -1; 1993 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 1994 fba->emu_types[1] = -1; 1995 #undef fba 1996 break; 1997 1998 #if 0 1999 case FBIOGETCMAP: 2000 #define p ((struct fbcmap *)data) 2001 return bt_getcmap(p, &sc->sc_cmap, 256, 1); 2002 2003 case FBIOPUTCMAP: 2004 /* copy to software map */ 2005 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 2006 if (error) 2007 return error; 2008 /* now blast them into the chip */ 2009 /* XXX should use retrace interrupt */ 2010 cg6_loadcmap(sc, p->index, p->count); 2011 #undef p 2012 break; 2013 #endif 2014 case FBIOGVIDEO: 2015 *(int *)data = sc->sc_blanked; 2016 break; 2017 2018 case FBIOSVIDEO: 2019 machfb_blank(sc, *(int *)data); 2020 break; 2021 2022 #if 0 2023 case FBIOGCURSOR: 2024 break; 2025 2026 case FBIOSCURSOR: 2027 break; 2028 2029 case FBIOGCURPOS: 2030 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 2031 break; 2032 2033 case FBIOSCURPOS: 2034 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 2035 break; 2036 2037 case FBIOGCURMAX: 2038 /* max cursor size is 32x32 */ 2039 ((struct fbcurpos *)data)->x = 32; 2040 ((struct fbcurpos *)data)->y = 32; 2041 break; 2042 #endif 2043 case PCI_IOC_CFGREAD: 2044 case PCI_IOC_CFGWRITE: { 2045 int ret; 2046 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 2047 cmd, data, flags, l); 2048 2049 #ifdef MACHFB_DEBUG 2050 printf("pci_devioctl: %d\n", ret); 2051 #endif 2052 return ret; 2053 } 2054 2055 case WSDISPLAYIO_GET_BUSID: 2056 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 2057 sc->sc_pcitag, data); 2058 2059 default: 2060 #ifdef MACHFB_DEBUG 2061 log(LOG_NOTICE, "machfb_fbioctl(0x%lx) (%s[%d])\n", cmd, 2062 p->p_comm, p->p_pid); 2063 #endif 2064 return ENOTTY; 2065 } 2066 #ifdef MACHFB_DEBUG 2067 printf("machfb_fbioctl done\n"); 2068 #endif 2069 return 0; 2070 } 2071 2072 paddr_t 2073 machfb_fbmmap(dev_t dev, off_t off, int prot) 2074 { 2075 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 2076 2077 if (sc != NULL) 2078 return mach64_mmap(&sc->vd, NULL, off, prot); 2079 2080 return 0; 2081 } 2082 2083 #endif /* __sparc__ */ 2084
Indexes created Thu Oct 02 14:10:14 GMT 2025