machfb.c revision 1.62.4.1
1 /* $NetBSD: machfb.c,v 1.62.4.1 2011/02/08 16:19:50 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.62.4.1 2011/02/08 16:19:50 bouyer Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #ifdef __sparc__ 58 #include <dev/sun/fbio.h> 59 #include <dev/sun/fbvar.h> 60 #include <sys/conf.h> 61 #else 62 #include <dev/wscons/wsdisplayvar.h> 63 #endif 64 65 #include <dev/wscons/wsconsio.h> 66 #include <dev/wsfont/wsfont.h> 67 #include <dev/rasops/rasops.h> 68 #include <dev/pci/wsdisplay_pci.h> 69 70 #include <dev/wscons/wsdisplay_vconsvar.h> 71 72 #include "opt_wsemul.h" 73 #include "opt_machfb.h" 74 75 #define MACH64_REG_SIZE 1024 76 #define MACH64_REG_OFF 0x7ffc00 77 78 #define NBARS 3 /* number of Mach64 PCI BARs */ 79 80 struct vga_bar { 81 bus_addr_t vb_base; 82 pcireg_t vb_busaddr; 83 bus_size_t vb_size; 84 pcireg_t vb_type; 85 int vb_flags; 86 }; 87 88 struct mach64_softc { 89 device_t sc_dev; 90 #ifdef __sparc__ 91 struct fbdevice sc_fb; 92 #endif 93 pci_chipset_tag_t sc_pc; 94 pcitag_t sc_pcitag; 95 96 struct vga_bar sc_bars[NBARS]; 97 struct vga_bar sc_rom; 98 99 #define sc_aperbase sc_bars[0].vb_base 100 #define sc_apersize sc_bars[0].vb_size 101 #define sc_aperphys sc_bars[0].vb_busaddr 102 103 #define sc_iobase sc_bars[1].vb_base 104 #define sc_iosize sc_bars[1].vb_size 105 106 #define sc_regbase sc_bars[2].vb_base 107 #define sc_regsize sc_bars[2].vb_size 108 #define sc_regphys sc_bars[2].vb_busaddr 109 110 bus_space_tag_t sc_regt; 111 bus_space_tag_t sc_memt; 112 bus_space_tag_t sc_iot; 113 bus_space_handle_t sc_regh; 114 bus_space_handle_t sc_memh; 115 void *sc_aperture; /* mapped aperture vaddr */ 116 void *sc_registers; /* mapped registers vaddr */ 117 118 uint32_t sc_nbus, sc_ndev, sc_nfunc; 119 size_t memsize; 120 int memtype; 121 122 int sc_mode; 123 int sc_bg; 124 int sc_locked; 125 126 int has_dsp; 127 int bits_per_pixel; 128 int max_x; 129 int max_y; 130 int virt_x; 131 int virt_y; 132 int color_depth; 133 134 int mem_freq; 135 int ramdac_freq; 136 int ref_freq; 137 138 int ref_div; 139 int log2_vclk_post_div; 140 int vclk_post_div; 141 int vclk_fb_div; 142 int mclk_post_div; 143 int mclk_fb_div; 144 int sc_clock; /* which clock to use */ 145 146 struct videomode *sc_my_mode; 147 int sc_edid_size; 148 uint8_t sc_edid_data[1024]; 149 150 u_char sc_cmap_red[256]; 151 u_char sc_cmap_green[256]; 152 u_char sc_cmap_blue[256]; 153 int sc_dacw, sc_blanked, sc_console; 154 struct vcons_data vd; 155 }; 156 157 struct mach64_crtcregs { 158 uint32_t h_total_disp; 159 uint32_t h_sync_strt_wid; 160 uint32_t v_total_disp; 161 uint32_t v_sync_strt_wid; 162 uint32_t gen_cntl; 163 uint32_t clock_cntl; 164 uint32_t color_depth; 165 uint32_t dot_clock; 166 }; 167 168 static struct { 169 uint16_t chip_id; 170 uint32_t ramdac_freq; 171 } const mach64_info[] = { 172 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 173 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 174 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 175 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 176 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 182 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 183 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 185 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 186 #if 0 187 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 189 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 190 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 192 #endif 193 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 194 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 195 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 196 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 197 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 198 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 199 }; 200 201 static int mach64_chip_id, mach64_chip_rev; 202 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 203 204 static const char *mach64_memtype_names[] = { 205 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 206 "(unknown type)" 207 }; 208 209 static struct videomode mach64_modes[] = { 210 /* 640x400 @ 70 Hz, 31.5 kHz */ 211 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0, NULL, }, 212 /* 640x480 @ 72 Hz, 36.5 kHz */ 213 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0, NULL, }, 214 /* 800x600 @ 72 Hz, 48.0 kHz */ 215 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 216 VID_PHSYNC | VID_PVSYNC, NULL, }, 217 /* 1024x768 @ 70 Hz, 56.5 kHz */ 218 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 219 VID_NHSYNC | VID_NVSYNC, NULL, }, 220 /* 1152x864 @ 70 Hz, 62.4 kHz */ 221 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0, NULL, }, 222 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 223 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 224 VID_NHSYNC | VID_NVSYNC, NULL, } 225 }; 226 227 extern const u_char rasops_cmap[768]; 228 229 static int mach64_match(device_t, cfdata_t, void *); 230 static void mach64_attach(device_t, device_t, void *); 231 232 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 233 NULL, NULL); 234 235 static void mach64_init(struct mach64_softc *); 236 static int mach64_get_memsize(struct mach64_softc *); 237 static int mach64_get_max_ramdac(struct mach64_softc *); 238 239 #if defined(__sparc__) || defined(__powerpc__) 240 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 241 #endif 242 243 static int mach64_calc_crtcregs(struct mach64_softc *, 244 struct mach64_crtcregs *, 245 struct videomode *); 246 static void mach64_set_crtcregs(struct mach64_softc *, 247 struct mach64_crtcregs *); 248 249 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 250 static void mach64_set_dsp(struct mach64_softc *); 251 static void mach64_set_pll(struct mach64_softc *, int); 252 static void mach64_reset_engine(struct mach64_softc *); 253 static void mach64_init_engine(struct mach64_softc *); 254 #if 0 255 static void mach64_adjust_frame(struct mach64_softc *, int, int); 256 #endif 257 static void mach64_init_lut(struct mach64_softc *); 258 259 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 260 static int mach64_set_screentype(struct mach64_softc *, 261 const struct wsscreen_descr *); 262 static int mach64_is_console(struct mach64_softc *); 263 264 static void mach64_cursor(void *, int, int, int); 265 #if 0 266 static int mach64_mapchar(void *, int, u_int *); 267 #endif 268 static void mach64_putchar(void *, int, int, u_int, long); 269 static void mach64_copycols(void *, int, int, int, int); 270 static void mach64_erasecols(void *, int, int, int, long); 271 static void mach64_copyrows(void *, int, int, int); 272 static void mach64_eraserows(void *, int, int, long); 273 static void mach64_clearscreen(struct mach64_softc *); 274 275 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 276 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 277 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 278 uint8_t, uint8_t); 279 static void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, 280 int, int, int) ; 281 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 282 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 283 uint32_t, uint32_t); 284 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 285 #if 0 286 static void mach64_showpal(struct mach64_softc *); 287 #endif 288 289 static void set_address(struct rasops_info *, void *); 290 static void machfb_blank(struct mach64_softc *, int); 291 static int machfb_drm_print(void *, const char *); 292 293 static struct wsscreen_descr mach64_defaultscreen = { 294 "default", 295 80, 30, 296 NULL, 297 8, 16, 298 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 299 &default_mode 300 }, mach64_80x25_screen = { 301 "80x25", 80, 25, 302 NULL, 303 8, 16, 304 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 305 &mach64_modes[0] 306 }, mach64_80x30_screen = { 307 "80x30", 80, 30, 308 NULL, 309 8, 16, 310 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 311 &mach64_modes[1] 312 }, mach64_80x40_screen = { 313 "80x40", 80, 40, 314 NULL, 315 8, 10, 316 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 317 &mach64_modes[0] 318 }, mach64_80x50_screen = { 319 "80x50", 80, 50, 320 NULL, 321 8, 8, 322 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 323 &mach64_modes[0] 324 }, mach64_100x37_screen = { 325 "100x37", 100, 37, 326 NULL, 327 8, 16, 328 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 329 &mach64_modes[2] 330 }, mach64_128x48_screen = { 331 "128x48", 128, 48, 332 NULL, 333 8, 16, 334 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 335 &mach64_modes[3] 336 }, mach64_144x54_screen = { 337 "144x54", 144, 54, 338 NULL, 339 8, 16, 340 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 341 &mach64_modes[4] 342 }, mach64_160x64_screen = { 343 "160x54", 160, 64, 344 NULL, 345 8, 16, 346 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 347 &mach64_modes[5] 348 }; 349 350 static const struct wsscreen_descr *_mach64_scrlist[] = { 351 &mach64_defaultscreen, 352 &mach64_80x25_screen, 353 &mach64_80x30_screen, 354 &mach64_80x40_screen, 355 &mach64_80x50_screen, 356 &mach64_100x37_screen, 357 &mach64_128x48_screen, 358 &mach64_144x54_screen, 359 &mach64_160x64_screen 360 }; 361 362 static struct wsscreen_list mach64_screenlist = { 363 __arraycount(_mach64_scrlist), 364 _mach64_scrlist 365 }; 366 367 static int mach64_ioctl(void *, void *, u_long, void *, int, 368 struct lwp *); 369 static paddr_t mach64_mmap(void *, void *, off_t, int); 370 371 #if 0 372 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 373 #endif 374 375 static struct wsdisplay_accessops mach64_accessops = { 376 mach64_ioctl, 377 mach64_mmap, 378 NULL, /* vcons_alloc_screen */ 379 NULL, /* vcons_free_screen */ 380 NULL, /* vcons_show_screen */ 381 NULL, /* load_font */ 382 NULL, /* polls */ 383 NULL, /* scroll */ 384 }; 385 386 static struct vcons_screen mach64_console_screen; 387 388 /* framebuffer device, SPARC-only so far */ 389 #ifdef __sparc__ 390 391 static void machfb_unblank(device_t); 392 static void machfb_fbattach(struct mach64_softc *); 393 394 extern struct cfdriver machfb_cd; 395 396 dev_type_open(machfb_fbopen); 397 dev_type_close(machfb_fbclose); 398 dev_type_ioctl(machfb_fbioctl); 399 dev_type_mmap(machfb_fbmmap); 400 401 /* frame buffer generic driver */ 402 static struct fbdriver machfb_fbdriver = { 403 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 404 machfb_fbmmap, nokqfilter 405 }; 406 407 #endif /* __sparc__ */ 408 409 /* 410 * Inline functions for getting access to register aperture. 411 */ 412 413 static inline uint32_t 414 regr(struct mach64_softc *sc, uint32_t index) 415 { 416 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 417 } 418 419 static inline uint8_t 420 regrb(struct mach64_softc *sc, uint32_t index) 421 { 422 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 423 } 424 425 static inline void 426 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 427 { 428 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 429 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 430 BUS_SPACE_BARRIER_WRITE); 431 } 432 433 static inline void 434 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 435 { 436 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 437 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 438 BUS_SPACE_BARRIER_WRITE); 439 } 440 441 static inline void 442 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 443 { 444 uint32_t reg; 445 446 reg = regr(sc, CLOCK_CNTL); 447 reg |= PLL_WR_EN; 448 regw(sc, CLOCK_CNTL, reg); 449 reg &= ~(PLL_ADDR | PLL_DATA); 450 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 451 reg |= data << PLL_DATA_SHIFT; 452 reg |= CLOCK_STROBE; 453 regw(sc, CLOCK_CNTL, reg); 454 reg &= ~PLL_WR_EN; 455 regw(sc, CLOCK_CNTL, reg); 456 } 457 458 static inline uint8_t 459 regrb_pll(struct mach64_softc *sc, uint32_t index) 460 { 461 462 regwb(sc, CLOCK_CNTL + 1, index << 2); 463 return regrb(sc, CLOCK_CNTL + 2); 464 } 465 466 static inline void 467 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 468 { 469 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 470 continue; 471 } 472 473 static inline void 474 wait_for_idle(struct mach64_softc *sc) 475 { 476 wait_for_fifo(sc, 16); 477 while ((regr(sc, GUI_STAT) & 1) != 0) 478 continue; 479 } 480 481 static int 482 mach64_match(device_t parent, cfdata_t match, void *aux) 483 { 484 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 485 int i; 486 487 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 488 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 489 return 0; 490 491 for (i = 0; i < __arraycount(mach64_info); i++) 492 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 493 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 494 mach64_chip_rev = PCI_REVISION(pa->pa_class); 495 return 100; 496 } 497 498 return 0; 499 } 500 501 static void 502 mach64_attach(device_t parent, device_t self, void *aux) 503 { 504 struct mach64_softc *sc = device_private(self); 505 struct pci_attach_args *pa = aux; 506 struct rasops_info *ri; 507 prop_data_t edid_data; 508 const struct videomode *mode = NULL; 509 char devinfo[256]; 510 int bar, id; 511 struct wsemuldisplaydev_attach_args aa; 512 long defattr; 513 int setmode, width, height; 514 pcireg_t screg; 515 uint32_t reg; 516 517 sc->sc_dev = self; 518 sc->sc_pc = pa->pa_pc; 519 sc->sc_pcitag = pa->pa_tag; 520 sc->sc_dacw = -1; 521 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 522 sc->sc_nbus = pa->pa_bus; 523 sc->sc_ndev = pa->pa_device; 524 sc->sc_nfunc = pa->pa_function; 525 sc->sc_locked = 0; 526 sc->sc_iot = pa->pa_iot; 527 528 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 529 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 530 PCI_REVISION(pa->pa_class)); 531 aprint_naive(": Graphics processor\n"); 532 #ifdef MACHFB_DEBUG 533 printf(prop_dictionary_externalize(device_properties(self))); 534 #endif 535 536 /* enable memory and disable IO access */ 537 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 538 if ((screg & PCI_FLAGS_MEM_ENABLED) == 0) { 539 screg |= PCI_FLAGS_IO_ENABLED; 540 screg |= PCI_FLAGS_MEM_ENABLED; 541 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 542 PCI_COMMAND_STATUS_REG, screg); 543 } 544 for (bar = 0; bar < NBARS; bar++) { 545 reg = PCI_MAPREG_START + (bar * 4); 546 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 547 sc->sc_pcitag, reg); 548 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 549 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 550 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 551 sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc, 552 sc->sc_pcitag, reg) & 0xfffffff0; 553 } 554 printf("%s: aperture size %08x\n", device_xname(sc->sc_dev), 555 (uint32_t)sc->sc_apersize); 556 557 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 558 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 559 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 560 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 561 sc->sc_memt = pa->pa_memt; 562 563 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 564 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 565 panic("%s: failed to map aperture", device_xname(sc->sc_dev)); 566 } 567 sc->sc_aperture = (void *)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 568 569 sc->sc_regt = sc->sc_memt; 570 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 571 sc->sc_regsize, &sc->sc_regh); 572 sc->sc_registers = (char *)sc->sc_aperture + 0x7ffc00; 573 574 mach64_init(sc); 575 576 aprint_normal_dev(sc->sc_dev, 577 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 578 (u_int)(sc->sc_apersize / (1024 * 1024)), 579 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 580 (u_int)sc->sc_regphys); 581 582 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 583 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 584 585 prop_dictionary_get_uint32(device_properties(self), "width", &width); 586 prop_dictionary_get_uint32(device_properties(self), "height", &height); 587 588 if ((edid_data = prop_dictionary_get(device_properties(self), "EDID")) 589 != NULL) { 590 struct edid_info ei; 591 592 sc->sc_edid_size = min(1024, prop_data_size(edid_data)); 593 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 594 memcpy(sc->sc_edid_data, prop_data_data_nocopy(edid_data), 595 sc->sc_edid_size); 596 597 edid_parse(sc->sc_edid_data, &ei); 598 599 #ifdef MACHFB_DEBUG 600 edid_print(&ei); 601 #endif 602 if (ei.edid_have_range) { 603 604 /* ei has dotclock in MHz, struct videomode in kHz */ 605 mode = pick_mode_by_dotclock(width, height, 606 ei.edid_range.er_max_clock * 1000); 607 if (mode != NULL) 608 printf("mode: %s\n", mode->name); 609 } 610 } 611 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 612 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 613 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 614 (mach64_chip_rev & 0x07) == 0)) 615 sc->has_dsp = 0; 616 else 617 sc->has_dsp = 1; 618 619 sc->memsize = mach64_get_memsize(sc); 620 if (sc->memsize == 8192) 621 /* The last page is used as register aperture. */ 622 sc->memsize -= 4; 623 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 624 625 /* XXX is there any way to calculate reference frequency from 626 known values? */ 627 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 628 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 629 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 630 aprint_normal_dev(sc->sc_dev, "ref_freq=29.498MHz\n"); 631 sc->ref_freq = 29498; 632 } else 633 sc->ref_freq = 14318; 634 635 reg = regr(sc, CLOCK_CNTL); 636 printf("CLOCK_CNTL: %08x\n", reg); 637 sc->sc_clock = reg & 3; 638 printf("using clock %d\n", sc->sc_clock); 639 640 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 641 printf("ref_div: %d\n", sc->ref_div); 642 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 643 printf("mclk_fb_div: %d\n", sc->mclk_fb_div); 644 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 645 (sc->ref_div * 2); 646 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 647 (sc->mem_freq * sc->ref_div); 648 sc->ramdac_freq = mach64_get_max_ramdac(sc); 649 aprint_normal_dev(sc->sc_dev, 650 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 651 (u_long)sc->memsize, 652 mach64_memtype_names[sc->memtype], 653 sc->mem_freq / 1000, sc->mem_freq % 1000, 654 sc->ramdac_freq / 1000); 655 656 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 657 if (id != mach64_chip_id) { 658 aprint_error_dev(sc->sc_dev, 659 "chip ID mismatch, 0x%x != 0x%x\n", id, mach64_chip_id); 660 return; 661 } 662 663 sc->sc_console = mach64_is_console(sc); 664 #ifdef DIAGNOSTIC 665 aprint_normal("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 666 #endif 667 #if defined(__sparc__) || defined(__powerpc__) 668 if (sc->sc_console) { 669 if (mode != NULL) { 670 memcpy(&default_mode, mode, sizeof(struct videomode)); 671 setmode = 1; 672 } else { 673 mach64_get_mode(sc, &default_mode); 674 setmode = 0; 675 } 676 sc->sc_my_mode = &default_mode; 677 } else { 678 /* fill in default_mode if it's empty */ 679 mach64_get_mode(sc, &default_mode); 680 if (default_mode.dot_clock == 0) { 681 memcpy(&default_mode, &mach64_modes[4], 682 sizeof(default_mode)); 683 } 684 sc->sc_my_mode = &default_mode; 685 setmode = 1; 686 } 687 #else 688 if (default_mode.dot_clock == 0) { 689 memcpy(&default_mode, &mach64_modes[0], 690 sizeof(default_mode)); 691 } 692 sc->sc_my_mode = &mach64_modes[0]; 693 setmode = 1; 694 #endif 695 696 sc->bits_per_pixel = 8; 697 sc->virt_x = sc->sc_my_mode->hdisplay; 698 sc->virt_y = sc->sc_my_mode->vdisplay; 699 sc->max_x = sc->virt_x - 1; 700 sc->max_y = (sc->memsize * 1024) / 701 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 702 703 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 704 705 mach64_init_engine(sc); 706 707 if (setmode) 708 mach64_modeswitch(sc, sc->sc_my_mode); 709 #if 0 710 mach64_adjust_frame(0, 0); 711 if (sc->bits_per_pixel == 8) 712 mach64_init_lut(sc); 713 #endif 714 715 aprint_normal_dev(sc->sc_dev, 716 "initial resolution %dx%d at %d bpp\n", 717 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 718 sc->bits_per_pixel); 719 720 #ifdef __sparc__ 721 machfb_fbattach(sc); 722 #endif 723 724 wsfont_init(); 725 726 sc->sc_bg = WS_DEFAULT_BG; 727 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &mach64_accessops); 728 sc->vd.init_screen = mach64_init_screen; 729 730 mach64_init_lut(sc); 731 mach64_clearscreen(sc); 732 machfb_blank(sc, 0); /* unblank the screen */ 733 734 if (sc->sc_console) { 735 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 736 &defattr); 737 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 738 739 ri = &mach64_console_screen.scr_ri; 740 mach64_defaultscreen.textops = &ri->ri_ops; 741 mach64_defaultscreen.capabilities = ri->ri_caps; 742 mach64_defaultscreen.nrows = ri->ri_rows; 743 mach64_defaultscreen.ncols = ri->ri_cols; 744 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 745 vcons_replay_msgbuf(&mach64_console_screen); 746 } else { 747 /* 748 * since we're not the console we can postpone the rest 749 * until someone actually allocates a screen for us 750 */ 751 mach64_modeswitch(sc, sc->sc_my_mode); 752 } 753 754 aa.console = sc->sc_console; 755 aa.scrdata = &mach64_screenlist; 756 aa.accessops = &mach64_accessops; 757 aa.accesscookie = &sc->vd; 758 759 config_found(self, &aa, wsemuldisplaydevprint); 760 761 config_found_ia(self, "drm", aux, machfb_drm_print); 762 } 763 764 static int 765 machfb_drm_print(void *aux, const char *pnp) 766 { 767 if (pnp) 768 aprint_normal("direct rendering for %s", pnp); 769 return (UNSUPP); 770 } 771 772 static void 773 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 774 long *defattr) 775 { 776 struct mach64_softc *sc = cookie; 777 struct rasops_info *ri = &scr->scr_ri; 778 779 /* XXX for now */ 780 #define setmode 0 781 782 ri->ri_depth = sc->bits_per_pixel; 783 ri->ri_width = sc->sc_my_mode->hdisplay; 784 ri->ri_height = sc->sc_my_mode->vdisplay; 785 ri->ri_stride = ri->ri_width; 786 ri->ri_flg = RI_CENTER; 787 set_address(ri, sc->sc_aperture); 788 789 if (existing) { 790 ri->ri_flg |= RI_CLEAR; 791 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 792 panic("%s: failed to switch video mode", 793 device_xname(sc->sc_dev)); 794 } 795 } 796 797 rasops_init(ri, sc->sc_my_mode->vdisplay / 8, 798 sc->sc_my_mode->hdisplay / 8); 799 ri->ri_caps = WSSCREEN_WSCOLORS; 800 801 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 802 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 803 804 /* enable acceleration */ 805 ri->ri_hw = scr; 806 ri->ri_ops.copyrows = mach64_copyrows; 807 ri->ri_ops.copycols = mach64_copycols; 808 ri->ri_ops.eraserows = mach64_eraserows; 809 ri->ri_ops.erasecols = mach64_erasecols; 810 ri->ri_ops.cursor = mach64_cursor; 811 ri->ri_ops.putchar = mach64_putchar; 812 } 813 814 static void 815 mach64_init(struct mach64_softc *sc) 816 { 817 uint32_t *p32, saved_value; 818 uint8_t *p; 819 int need_swap; 820 821 /* 822 * Test wether the aperture is byte swapped or not 823 */ 824 p32 = (uint32_t*)sc->sc_aperture; 825 saved_value = *p32; 826 p = (uint8_t*)(u_long)sc->sc_aperture; 827 *p32 = 0x12345678; 828 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 829 need_swap = 0; 830 else 831 need_swap = 1; 832 if (need_swap) { 833 sc->sc_aperture = (char *)sc->sc_aperture + 0x800000; 834 #if 0 835 /* what the fsck is this for? */ 836 sc->sc_aperbase += 0x800000; 837 sc->sc_apersize -= 0x800000; 838 #endif 839 } 840 *p32 = saved_value; 841 842 sc->sc_blanked = 0; 843 } 844 845 static int 846 mach64_get_memsize(struct mach64_softc *sc) 847 { 848 int tmp, memsize; 849 int mem_tab[] = { 850 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 851 }; 852 tmp = regr(sc, MEM_CNTL); 853 #ifdef DIAGNOSTIC 854 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 855 #endif 856 if (sc->has_dsp) { 857 tmp &= 0x0000000f; 858 if (tmp < 8) 859 memsize = (tmp + 1) * 512; 860 else if (tmp < 12) 861 memsize = (tmp - 3) * 1024; 862 else 863 memsize = (tmp - 7) * 2048; 864 } else { 865 memsize = mem_tab[tmp & 0x07]; 866 } 867 868 return memsize; 869 } 870 871 static int 872 mach64_get_max_ramdac(struct mach64_softc *sc) 873 { 874 int i; 875 876 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 877 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 878 (mach64_chip_rev & 0x07)) 879 return 170000; 880 881 for (i = 0; i < __arraycount(mach64_info); i++) 882 if (mach64_chip_id == mach64_info[i].chip_id) 883 return mach64_info[i].ramdac_freq; 884 885 if (sc->bits_per_pixel == 8) 886 return 135000; 887 else 888 return 80000; 889 } 890 891 #if defined(__sparc__) || defined(__powerpc__) 892 static void 893 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 894 { 895 struct mach64_crtcregs crtc; 896 897 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 898 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 899 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 900 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 901 902 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 903 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 904 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 905 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 906 mode->hsync_start; 907 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 908 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 909 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 910 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 911 912 #ifdef MACHFB_DEBUG 913 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 914 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 915 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 916 #endif 917 } 918 #endif 919 920 static int 921 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 922 struct videomode *mode) 923 { 924 925 if (mode->dot_clock > sc->ramdac_freq) 926 /* Clock too high. */ 927 return 1; 928 929 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 930 ((mode->htotal >> 3) - 1); 931 crtc->h_sync_strt_wid = 932 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 933 ((mode->hsync_start >> 3) - 1); 934 935 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 936 (mode->vtotal - 1); 937 crtc->v_sync_strt_wid = 938 ((mode->vsync_end - mode->vsync_start) << 16) | 939 (mode->vsync_start - 1); 940 941 if (mode->flags & VID_NVSYNC) 942 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 943 944 switch (sc->bits_per_pixel) { 945 case 8: 946 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 947 break; 948 case 16: 949 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 950 break; 951 case 32: 952 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 953 break; 954 } 955 956 crtc->gen_cntl = 0; 957 if (mode->flags & VID_INTERLACE) 958 crtc->gen_cntl |= CRTC_INTERLACE_EN; 959 960 if (mode->flags & VID_CSYNC) 961 crtc->gen_cntl |= CRTC_CSYNC_EN; 962 963 crtc->dot_clock = mode->dot_clock; 964 965 return 0; 966 } 967 968 static void 969 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 970 { 971 972 mach64_set_pll(sc, crtc->dot_clock); 973 974 if (sc->has_dsp) 975 mach64_set_dsp(sc); 976 #if 1 977 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 978 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 979 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 980 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 981 982 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 983 984 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 985 986 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 987 /* XXX this unconditionally enables composite sync on SPARC */ 988 #ifdef __sparc__ 989 CRTC_CSYNC_EN | 990 #endif 991 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 992 #endif 993 } 994 995 static int 996 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 997 { 998 struct mach64_crtcregs crtc; 999 1000 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 1001 1002 if (mach64_calc_crtcregs(sc, &crtc, mode)) 1003 return 1; 1004 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 1005 if (crtc.dot_clock == 0) { 1006 aprint_error("%s: preposterous dot clock (%d)\n", 1007 device_xname(sc->sc_dev), crtc.dot_clock); 1008 return 1; 1009 } 1010 mach64_set_crtcregs(sc, &crtc); 1011 return 0; 1012 } 1013 1014 static void 1015 mach64_reset_engine(struct mach64_softc *sc) 1016 { 1017 1018 /* Reset engine.*/ 1019 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1020 1021 /* Enable engine. */ 1022 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1023 1024 /* Ensure engine is not locked up by clearing any FIFO or 1025 host errors. */ 1026 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1027 BUS_FIFO_ERR_ACK); 1028 } 1029 1030 static void 1031 mach64_init_engine(struct mach64_softc *sc) 1032 { 1033 uint32_t pitch_value; 1034 1035 pitch_value = sc->virt_x; 1036 1037 if (sc->bits_per_pixel == 24) 1038 pitch_value *= 3; 1039 1040 mach64_reset_engine(sc); 1041 1042 wait_for_fifo(sc, 14); 1043 1044 regw(sc, CONTEXT_MASK, 0xffffffff); 1045 1046 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 1047 1048 regw(sc, DST_Y_X, 0); 1049 regw(sc, DST_HEIGHT, 0); 1050 regw(sc, DST_BRES_ERR, 0); 1051 regw(sc, DST_BRES_INC, 0); 1052 regw(sc, DST_BRES_DEC, 0); 1053 1054 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1055 DST_Y_TOP_TO_BOTTOM); 1056 1057 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 1058 1059 regw(sc, SRC_Y_X, 0); 1060 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1061 regw(sc, SRC_Y_X_START, 0); 1062 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1063 1064 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1065 1066 wait_for_fifo(sc, 13); 1067 regw(sc, HOST_CNTL, 0); 1068 1069 regw(sc, PAT_REG0, 0); 1070 regw(sc, PAT_REG1, 0); 1071 regw(sc, PAT_CNTL, 0); 1072 1073 regw(sc, SC_LEFT, 0); 1074 regw(sc, SC_TOP, 0); 1075 regw(sc, SC_BOTTOM, sc->sc_my_mode->vdisplay - 1); 1076 regw(sc, SC_RIGHT, pitch_value - 1); 1077 1078 regw(sc, DP_BKGD_CLR, 0); 1079 regw(sc, DP_FRGD_CLR, 0xffffffff); 1080 regw(sc, DP_WRITE_MASK, 0xffffffff); 1081 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1082 1083 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1084 1085 wait_for_fifo(sc, 3); 1086 regw(sc, CLR_CMP_CLR, 0); 1087 regw(sc, CLR_CMP_MASK, 0xffffffff); 1088 regw(sc, CLR_CMP_CNTL, 0); 1089 1090 wait_for_fifo(sc, 2); 1091 switch (sc->bits_per_pixel) { 1092 case 8: 1093 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 1094 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1095 /* We want 8 bit per channel */ 1096 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1097 break; 1098 case 32: 1099 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 1100 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1101 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1102 break; 1103 } 1104 1105 wait_for_fifo(sc, 5); 1106 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1107 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1108 1109 wait_for_idle(sc); 1110 } 1111 1112 #if 0 1113 static void 1114 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1115 { 1116 int offset; 1117 1118 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1119 1120 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1121 offset); 1122 } 1123 #endif 1124 1125 static void 1126 mach64_set_dsp(struct mach64_softc *sc) 1127 { 1128 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1129 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1130 uint32_t xclks_per_qw, y; 1131 uint32_t fifo_off, fifo_on; 1132 1133 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1134 1135 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1136 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1137 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1138 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1139 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1140 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1141 dsp_loop_latency = 0; 1142 fifo_depth = 24; 1143 } else { 1144 dsp_loop_latency = 2; 1145 fifo_depth = 32; 1146 } 1147 1148 dsp_precision = 0; 1149 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1150 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1151 y = (xclks_per_qw * fifo_depth) >> 11; 1152 while (y) { 1153 y >>= 1; 1154 dsp_precision++; 1155 } 1156 dsp_precision -= 5; 1157 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1158 1159 switch (sc->memtype) { 1160 case DRAM: 1161 case EDO_DRAM: 1162 case PSEUDO_EDO: 1163 if (sc->memsize > 1024) { 1164 page_size = 9; 1165 dsp_loop_latency += 6; 1166 } else { 1167 page_size = 10; 1168 if (sc->memtype == DRAM) 1169 dsp_loop_latency += 8; 1170 else 1171 dsp_loop_latency += 7; 1172 } 1173 break; 1174 case SDRAM: 1175 case SGRAM: 1176 if (sc->memsize > 1024) { 1177 page_size = 8; 1178 dsp_loop_latency += 8; 1179 } else { 1180 page_size = 10; 1181 dsp_loop_latency += 9; 1182 } 1183 break; 1184 default: 1185 page_size = 10; 1186 dsp_loop_latency += 9; 1187 break; 1188 } 1189 1190 if (xclks_per_qw >= (page_size << 11)) 1191 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1192 else 1193 fifo_on = (3 * page_size + 2) << 6; 1194 1195 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1196 dsp_on = fifo_on >> dsp_precision; 1197 dsp_off = fifo_off >> dsp_precision; 1198 1199 #ifdef MACHFB_DEBUG 1200 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1201 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1202 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1203 "mclk_post_div = %d, vclk_post_div = %d\n", 1204 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1205 sc->mclk_fb_div, sc->vclk_fb_div, 1206 sc->mclk_post_div, sc->vclk_post_div); 1207 #endif 1208 1209 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1210 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1211 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1212 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1213 } 1214 1215 static void 1216 mach64_set_pll(struct mach64_softc *sc, int clock) 1217 { 1218 uint32_t q, clockreg; 1219 int clockshift = sc->sc_clock << 1; 1220 uint8_t reg, vclk_ctl; 1221 1222 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1223 #ifdef MACHFB_DEBUG 1224 printf("q = %d\n", q); 1225 #endif 1226 if (q > 25500) { 1227 printf("Warning: q > 25500\n"); 1228 q = 25500; 1229 sc->vclk_post_div = 1; 1230 sc->log2_vclk_post_div = 0; 1231 } else if (q > 12750) { 1232 sc->vclk_post_div = 1; 1233 sc->log2_vclk_post_div = 0; 1234 } else if (q > 6350) { 1235 sc->vclk_post_div = 2; 1236 sc->log2_vclk_post_div = 1; 1237 } else if (q > 3150) { 1238 sc->vclk_post_div = 4; 1239 sc->log2_vclk_post_div = 2; 1240 } else if (q >= 1600) { 1241 sc->vclk_post_div = 8; 1242 sc->log2_vclk_post_div = 3; 1243 } else { 1244 printf("Warning: q < 1600\n"); 1245 sc->vclk_post_div = 8; 1246 sc->log2_vclk_post_div = 3; 1247 } 1248 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1249 printf("post_div: %d log2_post_div: %d mclk_div: %d\n", sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1250 1251 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1252 printf("vclk_ctl: %02x\n", vclk_ctl); 1253 vclk_ctl |= PLL_VCLK_RESET; 1254 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1255 1256 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1257 reg = regrb_pll(sc, VCLK_POST_DIV); 1258 reg &= ~(3 << clockshift); 1259 reg |= (sc->log2_vclk_post_div << clockshift); 1260 regwb_pll(sc, VCLK_POST_DIV, reg); 1261 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1262 1263 vclk_ctl &= ~PLL_VCLK_RESET; 1264 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1265 1266 clockreg = regr(sc, CLOCK_CNTL); 1267 clockreg &= ~CLOCK_SEL; 1268 clockreg |= sc->sc_clock | CLOCK_STROBE; 1269 regw(sc, CLOCK_CNTL, clockreg); 1270 } 1271 1272 static void 1273 mach64_init_lut(struct mach64_softc *sc) 1274 { 1275 int i, idx; 1276 1277 idx = 0; 1278 for (i = 0; i < 256; i++) { 1279 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1], 1280 rasops_cmap[idx + 2]); 1281 idx += 3; 1282 } 1283 } 1284 1285 static int 1286 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1287 uint8_t b) 1288 { 1289 sc->sc_cmap_red[index] = r; 1290 sc->sc_cmap_green[index] = g; 1291 sc->sc_cmap_blue[index] = b; 1292 /* 1293 * writing the dac index takes a while, in theory we can poll some 1294 * register to see when it's ready - but we better avoid writing it 1295 * unnecessarily 1296 */ 1297 if (index != sc->sc_dacw) { 1298 regwb(sc, DAC_MASK, 0xff); 1299 regwb(sc, DAC_WINDEX, index); 1300 } 1301 sc->sc_dacw = index + 1; 1302 regwb(sc, DAC_DATA, r); 1303 regwb(sc, DAC_DATA, g); 1304 regwb(sc, DAC_DATA, b); 1305 return 0; 1306 } 1307 1308 static int 1309 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1310 { 1311 uint index = cm->index; 1312 uint count = cm->count; 1313 int i, error; 1314 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1315 uint8_t *r, *g, *b; 1316 1317 if (cm->index >= 256 || cm->count > 256 || 1318 (cm->index + cm->count) > 256) 1319 return EINVAL; 1320 error = copyin(cm->red, &rbuf[index], count); 1321 if (error) 1322 return error; 1323 error = copyin(cm->green, &gbuf[index], count); 1324 if (error) 1325 return error; 1326 error = copyin(cm->blue, &bbuf[index], count); 1327 if (error) 1328 return error; 1329 1330 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1331 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1332 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1333 1334 r = &sc->sc_cmap_red[index]; 1335 g = &sc->sc_cmap_green[index]; 1336 b = &sc->sc_cmap_blue[index]; 1337 1338 for (i = 0; i < count; i++) { 1339 mach64_putpalreg(sc, index, *r, *g, *b); 1340 index++; 1341 r++, g++, b++; 1342 } 1343 return 0; 1344 } 1345 1346 static int 1347 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1348 { 1349 u_int index = cm->index; 1350 u_int count = cm->count; 1351 int error; 1352 1353 if (index >= 255 || count > 256 || index + count > 256) 1354 return EINVAL; 1355 1356 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1357 if (error) 1358 return error; 1359 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1360 if (error) 1361 return error; 1362 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1363 if (error) 1364 return error; 1365 1366 return 0; 1367 } 1368 1369 static int 1370 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1371 { 1372 struct mach64_crtcregs regs; 1373 1374 if (mach64_calc_crtcregs(sc, ®s, 1375 (struct videomode *)des->modecookie)) 1376 return 1; 1377 1378 mach64_set_crtcregs(sc, ®s); 1379 return 0; 1380 } 1381 1382 static int 1383 mach64_is_console(struct mach64_softc *sc) 1384 { 1385 bool console = 0; 1386 1387 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1388 "is_console", &console); 1389 return console; 1390 } 1391 1392 /* 1393 * wsdisplay_emulops 1394 */ 1395 1396 static void 1397 mach64_cursor(void *cookie, int on, int row, int col) 1398 { 1399 struct rasops_info *ri = cookie; 1400 struct vcons_screen *scr = ri->ri_hw; 1401 struct mach64_softc *sc = scr->scr_cookie; 1402 int x, y, wi, he; 1403 1404 wi = ri->ri_font->fontwidth; 1405 he = ri->ri_font->fontheight; 1406 1407 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1408 x = ri->ri_ccol * wi + ri->ri_xorigin; 1409 y = ri->ri_crow * he + ri->ri_yorigin; 1410 if (ri->ri_flg & RI_CURSOR) { 1411 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1412 0xff); 1413 ri->ri_flg &= ~RI_CURSOR; 1414 } 1415 ri->ri_crow = row; 1416 ri->ri_ccol = col; 1417 if (on) { 1418 x = ri->ri_ccol * wi + ri->ri_xorigin; 1419 y = ri->ri_crow * he + ri->ri_yorigin; 1420 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1421 0xff); 1422 ri->ri_flg |= RI_CURSOR; 1423 } 1424 } else { 1425 scr->scr_ri.ri_crow = row; 1426 scr->scr_ri.ri_ccol = col; 1427 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1428 } 1429 } 1430 1431 #if 0 1432 static int 1433 mach64_mapchar(void *cookie, int uni, u_int *index) 1434 { 1435 return 0; 1436 } 1437 #endif 1438 1439 static void 1440 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1441 { 1442 struct rasops_info *ri = cookie; 1443 struct wsdisplay_font *font = PICK_FONT(ri, c); 1444 struct vcons_screen *scr = ri->ri_hw; 1445 struct mach64_softc *sc = scr->scr_cookie; 1446 1447 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1448 int fg, bg, uc; 1449 uint8_t *data; 1450 int x, y, wi, he; 1451 wi = font->fontwidth; 1452 he = font->fontheight; 1453 1454 if (!CHAR_IN_FONT(c, font)) 1455 return; 1456 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1457 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f]; 1458 x = ri->ri_xorigin + col * wi; 1459 y = ri->ri_yorigin + row * he; 1460 if (c == 0x20) { 1461 mach64_rectfill(sc, x, y, wi, he, bg); 1462 } else { 1463 uc = c - font->firstchar; 1464 data = (uint8_t *)font->data + uc * 1465 ri->ri_fontscale; 1466 1467 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1468 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1469 } 1470 } 1471 } 1472 1473 1474 static void 1475 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1476 { 1477 struct rasops_info *ri = cookie; 1478 struct vcons_screen *scr = ri->ri_hw; 1479 struct mach64_softc *sc = scr->scr_cookie; 1480 int32_t xs, xd, y, width, height; 1481 1482 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1483 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1484 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1485 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1486 width = ri->ri_font->fontwidth * ncols; 1487 height = ri->ri_font->fontheight; 1488 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff); 1489 } 1490 } 1491 1492 static void 1493 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1494 { 1495 struct rasops_info *ri = cookie; 1496 struct vcons_screen *scr = ri->ri_hw; 1497 struct mach64_softc *sc = scr->scr_cookie; 1498 int32_t x, y, width, height, fg, bg, ul; 1499 1500 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1501 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1502 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1503 width = ri->ri_font->fontwidth * ncols; 1504 height = ri->ri_font->fontheight; 1505 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1506 1507 mach64_rectfill(sc, x, y, width, height, bg); 1508 } 1509 } 1510 1511 static void 1512 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1513 { 1514 struct rasops_info *ri = cookie; 1515 struct vcons_screen *scr = ri->ri_hw; 1516 struct mach64_softc *sc = scr->scr_cookie; 1517 int32_t x, ys, yd, width, height; 1518 1519 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1520 x = ri->ri_xorigin; 1521 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1522 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1523 width = ri->ri_emuwidth; 1524 height = ri->ri_font->fontheight*nrows; 1525 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff); 1526 } 1527 } 1528 1529 static void 1530 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1531 { 1532 struct rasops_info *ri = cookie; 1533 struct vcons_screen *scr = ri->ri_hw; 1534 struct mach64_softc *sc = scr->scr_cookie; 1535 int32_t x, y, width, height, fg, bg, ul; 1536 1537 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1538 x = ri->ri_xorigin; 1539 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1540 width = ri->ri_emuwidth; 1541 height = ri->ri_font->fontheight * nrows; 1542 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1543 1544 mach64_rectfill(sc, x, y, width, height, bg); 1545 } 1546 } 1547 1548 static void 1549 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1550 { 1551 uint32_t dest_ctl = 0; 1552 1553 wait_for_idle(sc); 1554 regw(sc, DP_WRITE_MASK, mask); /* XXX only good for 8 bit */ 1555 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1556 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1557 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1558 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1559 if (yd < ys) { 1560 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1561 } else { 1562 ys += height - 1; 1563 yd += height - 1; 1564 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1565 } 1566 if (xd < xs) { 1567 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1568 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1569 } else { 1570 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1571 xs += width - 1; 1572 xd += width - 1; 1573 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1574 } 1575 regw(sc, DST_CNTL, dest_ctl); 1576 1577 regw(sc, SRC_Y_X, (xs << 16) | ys); 1578 regw(sc, SRC_WIDTH1, width); 1579 regw(sc, DST_Y_X, (xd << 16) | yd); 1580 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1581 } 1582 1583 static void 1584 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1585 int height, uint32_t fg, uint32_t bg) 1586 { 1587 wait_for_idle(sc); 1588 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1589 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1590 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1591 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1592 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1593 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1594 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1595 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1596 regw(sc, DP_BKGD_CLR, bg); 1597 regw(sc, DP_FRGD_CLR, fg); 1598 regw(sc, SRC_Y_X, 0); 1599 regw(sc, SRC_WIDTH1, width); 1600 regw(sc, DST_Y_X, (xd << 16) | yd); 1601 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1602 /* now feed the data into the chip */ 1603 } 1604 1605 static void 1606 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1607 { 1608 int i; 1609 uint32_t latch = 0, bork; 1610 int shift = 0; 1611 int reg = 0; 1612 1613 for (i=0;i<count;i++) { 1614 bork = data[i]; 1615 latch |= (bork << shift); 1616 if (shift == 24) { 1617 regw(sc, HOST_DATA0 + reg, latch); 1618 latch = 0; 1619 shift = 0; 1620 reg = (reg + 4) & 0x3c; 1621 } else 1622 shift += 8; 1623 } 1624 if (shift != 0) /* 24 */ 1625 regw(sc, HOST_DATA0 + reg, latch); 1626 } 1627 1628 1629 static void 1630 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1631 int colour) 1632 { 1633 wait_for_idle(sc); 1634 regw(sc, DP_WRITE_MASK, 0xff); 1635 regw(sc, DP_FRGD_CLR, colour); 1636 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1637 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1638 regw(sc, DP_MIX, MIX_SRC << 16); 1639 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1640 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1641 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1642 1643 regw(sc, SRC_Y_X, (x << 16) | y); 1644 regw(sc, SRC_WIDTH1, width); 1645 regw(sc, DST_Y_X, (x << 16) | y); 1646 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1647 } 1648 1649 static void 1650 mach64_clearscreen(struct mach64_softc *sc) 1651 { 1652 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1653 } 1654 1655 1656 #if 0 1657 static void 1658 mach64_showpal(struct mach64_softc *sc) 1659 { 1660 int i, x = 0; 1661 1662 for (i = 0; i < 16; i++) { 1663 mach64_rectfill(sc, x, 0, 64, 64, i); 1664 x += 64; 1665 } 1666 } 1667 #endif 1668 1669 /* 1670 * wsdisplay_accessops 1671 */ 1672 1673 static int 1674 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1675 struct lwp *l) 1676 { 1677 struct vcons_data *vd = v; 1678 struct mach64_softc *sc = vd->cookie; 1679 struct wsdisplay_fbinfo *wdf; 1680 struct vcons_screen *ms = vd->active; 1681 1682 switch (cmd) { 1683 case WSDISPLAYIO_GTYPE: 1684 /* XXX is this the right type to return? */ 1685 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1686 return 0; 1687 1688 case WSDISPLAYIO_LINEBYTES: 1689 *(u_int *)data = sc->virt_x * sc->bits_per_pixel / 8; 1690 return 0; 1691 1692 case WSDISPLAYIO_GINFO: 1693 wdf = (void *)data; 1694 wdf->height = sc->virt_y; 1695 wdf->width = sc->virt_x; 1696 wdf->depth = sc->bits_per_pixel; 1697 wdf->cmsize = 256; 1698 return 0; 1699 1700 case WSDISPLAYIO_GETCMAP: 1701 return mach64_getcmap(sc, 1702 (struct wsdisplay_cmap *)data); 1703 1704 case WSDISPLAYIO_PUTCMAP: 1705 return mach64_putcmap(sc, 1706 (struct wsdisplay_cmap *)data); 1707 1708 /* PCI config read/write passthrough. */ 1709 case PCI_IOC_CFGREAD: 1710 case PCI_IOC_CFGWRITE: 1711 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1712 cmd, data, flag, l); 1713 1714 case WSDISPLAYIO_GET_BUSID: 1715 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1716 sc->sc_pcitag, data); 1717 1718 case WSDISPLAYIO_SMODE: { 1719 int new_mode = *(int*)data; 1720 if (new_mode != sc->sc_mode) { 1721 sc->sc_mode = new_mode; 1722 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1723 && (ms != NULL)) 1724 { 1725 /* restore initial video mode */ 1726 mach64_init(sc); 1727 mach64_init_engine(sc); 1728 mach64_init_lut(sc); 1729 mach64_modeswitch(sc, sc->sc_my_mode); 1730 vcons_redraw_screen(ms); 1731 } 1732 } 1733 } 1734 return 0; 1735 1736 } 1737 return EPASSTHROUGH; 1738 } 1739 1740 static paddr_t 1741 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1742 { 1743 struct vcons_data *vd = v; 1744 struct mach64_softc *sc = vd->cookie; 1745 paddr_t pa; 1746 pcireg_t reg; 1747 1748 #ifndef __sparc64__ 1749 /* 1750 *'regular' framebuffer mmap()ing 1751 * disabled on sparc64 because some ATI firmware likes to map some PCI 1752 * resources to addresses that would collide with this ( like some Rage 1753 * IIc which uses 0x2000 for the 2nd register block ) 1754 * Other 64bit architectures might run into similar problems. 1755 */ 1756 if (offset<sc->sc_apersize) { 1757 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, offset, 1758 prot, BUS_SPACE_MAP_LINEAR); 1759 return pa; 1760 } 1761 #endif 1762 1763 /* 1764 * restrict all other mappings to processes with superuser privileges 1765 * or the kernel itself 1766 */ 1767 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1768 NULL) != 0) { 1769 return -1; 1770 } 1771 1772 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1773 if (reg != sc->sc_regphys) { 1774 #ifdef DIAGNOSTIC 1775 printf("%s: BAR 0x18 changed! (%x %x)\n", 1776 device_xname(sc->sc_dev), (uint32_t)sc->sc_regphys, 1777 (uint32_t)reg); 1778 #endif 1779 sc->sc_regphys = reg; 1780 } 1781 1782 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1783 if (reg != sc->sc_aperphys) { 1784 #ifdef DIAGNOSTIC 1785 printf("%s: BAR 0x10 changed! (%x %x)\n", 1786 device_xname(sc->sc_dev), (uint32_t)sc->sc_aperphys, 1787 (uint32_t)reg); 1788 #endif 1789 sc->sc_aperphys = reg; 1790 } 1791 1792 if ((offset >= sc->sc_aperphys) && 1793 (offset < (sc->sc_aperphys + sc->sc_apersize))) { 1794 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1795 BUS_SPACE_MAP_LINEAR); 1796 return pa; 1797 } 1798 1799 if ((offset >= sc->sc_regphys) && 1800 (offset < (sc->sc_regphys + sc->sc_regsize))) { 1801 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1802 BUS_SPACE_MAP_LINEAR); 1803 return pa; 1804 } 1805 1806 if ((offset >= sc->sc_rom.vb_base) && 1807 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 1808 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1809 BUS_SPACE_MAP_LINEAR); 1810 return pa; 1811 } 1812 1813 #ifdef PCI_MAGIC_IO_RANGE 1814 if ((offset >= PCI_MAGIC_IO_RANGE) && 1815 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 1816 return bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1817 0, prot, BUS_SPACE_MAP_LINEAR); 1818 } 1819 #endif 1820 1821 return -1; 1822 } 1823 1824 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1825 static void 1826 set_address(struct rasops_info *ri, void *fb) 1827 { 1828 #ifdef notdef 1829 printf(" %d %d %d\n", ri->ri_xorigin, ri->ri_yorigin, ri->ri_stride); 1830 #endif 1831 ri->ri_bits = (void *)((char *)fb + ri->ri_stride * ri->ri_yorigin + 1832 ri->ri_xorigin); 1833 } 1834 1835 #if 0 1836 static int 1837 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1838 { 1839 1840 return 0; 1841 } 1842 #endif 1843 1844 void 1845 machfb_blank(struct mach64_softc *sc, int blank) 1846 { 1847 uint32_t reg; 1848 1849 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1850 1851 switch (blank) 1852 { 1853 case 0: 1854 reg = regr(sc, CRTC_GEN_CNTL); 1855 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1856 sc->sc_blanked = 0; 1857 break; 1858 case 1: 1859 reg = regr(sc, CRTC_GEN_CNTL); 1860 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1861 sc->sc_blanked = 1; 1862 break; 1863 default: 1864 break; 1865 } 1866 } 1867 1868 /* framebuffer device support */ 1869 #ifdef __sparc__ 1870 1871 static void 1872 machfb_unblank(device_t dev) 1873 { 1874 struct mach64_softc *sc = device_private(dev); 1875 1876 machfb_blank(sc, 0); 1877 } 1878 1879 static void 1880 machfb_fbattach(struct mach64_softc *sc) 1881 { 1882 struct fbdevice *fb = &sc->sc_fb; 1883 1884 fb->fb_device = sc->sc_dev; 1885 fb->fb_driver = &machfb_fbdriver; 1886 1887 fb->fb_type.fb_cmsize = 256; 1888 fb->fb_type.fb_size = sc->memsize; 1889 1890 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 1891 fb->fb_flags = sc->sc_dev->dv_cfdata->cf_flags & FB_USERMASK; 1892 fb->fb_type.fb_depth = sc->bits_per_pixel; 1893 fb->fb_type.fb_width = sc->virt_x; 1894 fb->fb_type.fb_height = sc->virt_y; 1895 1896 fb->fb_pixels = sc->sc_aperture; 1897 fb_attach(fb, sc->sc_console); 1898 } 1899 1900 int 1901 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 1902 { 1903 struct mach64_softc *sc; 1904 1905 sc = device_lookup_private(&machfb_cd, minor(dev)); 1906 if (sc == NULL) 1907 return ENXIO; 1908 sc->sc_locked = 1; 1909 1910 #ifdef MACHFB_DEBUG 1911 printf("machfb_fbopen(%d)\n", minor(dev)); 1912 #endif 1913 return 0; 1914 } 1915 1916 int 1917 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 1918 { 1919 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1920 1921 #ifdef MACHFB_DEBUG 1922 printf("machfb_fbclose()\n"); 1923 #endif 1924 mach64_init_engine(sc); 1925 mach64_init_lut(sc); 1926 sc->sc_locked = 0; 1927 return 0; 1928 } 1929 1930 int 1931 machfb_fbioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1932 { 1933 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1934 1935 #ifdef MACHFB_DEBUG 1936 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 1937 #endif 1938 switch (cmd) { 1939 case FBIOGTYPE: 1940 *(struct fbtype *)data = sc->sc_fb.fb_type; 1941 break; 1942 1943 case FBIOGATTR: 1944 #define fba ((struct fbgattr *)data) 1945 fba->real_type = sc->sc_fb.fb_type.fb_type; 1946 fba->owner = 0; /* XXX ??? */ 1947 fba->fbtype = sc->sc_fb.fb_type; 1948 fba->sattr.flags = 0; 1949 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 1950 fba->sattr.dev_specific[0] = sc->sc_nbus; 1951 fba->sattr.dev_specific[1] = sc->sc_ndev; 1952 fba->sattr.dev_specific[2] = sc->sc_nfunc; 1953 fba->sattr.dev_specific[3] = -1; 1954 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 1955 fba->emu_types[1] = -1; 1956 #undef fba 1957 break; 1958 1959 #if 0 1960 case FBIOGETCMAP: 1961 #define p ((struct fbcmap *)data) 1962 return bt_getcmap(p, &sc->sc_cmap, 256, 1); 1963 1964 case FBIOPUTCMAP: 1965 /* copy to software map */ 1966 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 1967 if (error) 1968 return error; 1969 /* now blast them into the chip */ 1970 /* XXX should use retrace interrupt */ 1971 cg6_loadcmap(sc, p->index, p->count); 1972 #undef p 1973 break; 1974 #endif 1975 case FBIOGVIDEO: 1976 *(int *)data = sc->sc_blanked; 1977 break; 1978 1979 case FBIOSVIDEO: 1980 machfb_blank(sc, *(int *)data); 1981 break; 1982 1983 #if 0 1984 case FBIOGCURSOR: 1985 break; 1986 1987 case FBIOSCURSOR: 1988 break; 1989 1990 case FBIOGCURPOS: 1991 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 1992 break; 1993 1994 case FBIOSCURPOS: 1995 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 1996 break; 1997 1998 case FBIOGCURMAX: 1999 /* max cursor size is 32x32 */ 2000 ((struct fbcurpos *)data)->x = 32; 2001 ((struct fbcurpos *)data)->y = 32; 2002 break; 2003 #endif 2004 case PCI_IOC_CFGREAD: 2005 case PCI_IOC_CFGWRITE: { 2006 int ret; 2007 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 2008 cmd, data, flags, l); 2009 2010 #ifdef MACHFB_DEBUG 2011 printf("pci_devioctl: %d\n", ret); 2012 #endif 2013 return ret; 2014 } 2015 2016 case WSDISPLAYIO_GET_BUSID: 2017 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 2018 sc->sc_pcitag, data); 2019 2020 default: 2021 #ifdef MACHFB_DEBUG 2022 log(LOG_NOTICE, "machfb_fbioctl(0x%lx) (%s[%d])\n", cmd, 2023 p->p_comm, p->p_pid); 2024 #endif 2025 return ENOTTY; 2026 } 2027 #ifdef MACHFB_DEBUG 2028 printf("machfb_fbioctl done\n"); 2029 #endif 2030 return 0; 2031 } 2032 2033 paddr_t 2034 machfb_fbmmap(dev_t dev, off_t off, int prot) 2035 { 2036 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 2037 2038 if (sc != NULL) 2039 return mach64_mmap(&sc->vd, NULL, off, prot); 2040 2041 return 0; 2042 } 2043 2044 #endif /* __sparc__ */ 2045
Indexes created Thu Oct 02 14:10:14 GMT 2025