machfb.c revision 1.7
1 /* $NetBSD: machfb.c,v 1.7 2002/10/31 14:10:07 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 32 */ 33 34 #include <sys/cdefs.h> 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/callout.h> 42 43 #ifdef __sparc__ 44 #include <machine/openfirm.h> 45 #endif 46 47 #include <dev/ic/videomode.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcidevs.h> 52 #include <dev/pci/pciio.h> 53 #include <dev/pci/machfbreg.h> 54 55 #include <dev/wscons/wsdisplayvar.h> 56 #include <dev/wscons/wsconsio.h> 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/rasops/rasops.h> 59 60 #define MACH64_REG_SIZE 1024 61 #define MACH64_REG_OFF 0x7ffc00 62 63 #define NBARS 3 /* number of Mach64 PCI BARs */ 64 65 struct vga_bar { 66 bus_addr_t vb_base; 67 bus_size_t vb_size; 68 pcireg_t vb_type; 69 int vb_flags; 70 }; 71 72 struct mach64_softc { 73 struct device sc_dev; 74 pci_chipset_tag_t sc_pc; 75 pcitag_t sc_pcitag; 76 77 struct vga_bar sc_bars[NBARS]; 78 struct vga_bar sc_rom; 79 80 #define sc_aperbase sc_bars[0].vb_base 81 #define sc_apersize sc_bars[0].vb_size 82 83 #define sc_iobase sc_bars[1].vb_base 84 #define sc_iosize sc_bars[1].vb_size 85 86 #define sc_regbase sc_bars[2].vb_base 87 #define sc_regsize sc_bars[2].vb_size 88 89 bus_space_tag_t sc_regt; 90 bus_space_tag_t sc_memt; 91 bus_space_handle_t sc_regh; 92 bus_space_handle_t sc_memh; 93 94 size_t memsize; 95 int memtype; 96 97 int has_dsp; 98 int bits_per_pixel; 99 int max_x, max_y; 100 int virt_x, virt_y; 101 int color_depth; 102 103 int mem_freq; 104 int ramdac_freq; 105 int ref_freq; 106 107 int ref_div; 108 int log2_vclk_post_div; 109 int vclk_post_div; 110 int vclk_fb_div; 111 int mclk_post_div; 112 int mclk_fb_div; 113 114 struct mach64screen *wanted; 115 struct mach64screen *active; 116 void (*switchcb)(void *, int, int); 117 void *switchcbarg; 118 struct callout switch_callout; 119 LIST_HEAD(, mach64screen) screens; 120 const struct wsscreen_descr *currenttype; 121 }; 122 123 struct mach64screen { 124 struct rasops_info ri; 125 LIST_ENTRY(mach64screen) next; 126 struct mach64_softc *sc; 127 const struct wsscreen_descr *type; 128 int active; 129 u_int16_t *mem; 130 int dispoffset; 131 int mindispoffset; 132 int maxdispoffset; 133 134 int cursoron; 135 int cursorcol; 136 int cursorrow; 137 u_int16_t cursortmp; 138 }; 139 140 struct mach64_crtcregs { 141 u_int32_t h_total_disp; 142 u_int32_t h_sync_strt_wid; 143 u_int32_t v_total_disp; 144 u_int32_t v_sync_strt_wid; 145 u_int32_t gen_cntl; 146 u_int32_t clock_cntl; 147 u_int32_t color_depth; 148 u_int32_t dot_clock; 149 }; 150 151 struct { 152 u_int16_t chip_id; 153 u_int32_t ramdac_freq; 154 } mach64_info[] = { 155 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 156 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 157 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 158 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 159 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 160 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 161 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 162 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 163 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 164 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 165 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 166 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 167 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 168 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 169 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 170 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 171 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 172 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 173 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 174 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 175 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 176 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 177 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 178 }; 179 180 static int mach64_chip_id, mach64_chip_rev; 181 static struct videomode default_mode; 182 static struct mach64screen mach64_console_screen; 183 184 static char *mach64_memtype_names[] = { 185 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 186 "(unknown type)" 187 }; 188 189 struct videomode mach64_modes[] = { 190 /* 640x400 @ 70 Hz, 31.5 kHz */ 191 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0 }, 192 /* 640x480 @ 72 Hz, 36.5 kHz */ 193 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0 }, 194 /* 800x600 @ 72 Hz, 48.0 kHz */ 195 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 196 VID_PHSYNC | VID_PVSYNC }, 197 /* 1024x768 @ 70 Hz, 56.5 kHz */ 198 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 199 VID_NHSYNC | VID_NVSYNC }, 200 /* 1152x864 @ 70 Hz, 62.4 kHz */ 201 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0 }, 202 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 203 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 204 VID_NHSYNC | VID_NVSYNC } 205 }; 206 207 /* FIXME values are wrong! */ 208 const u_char mach64_cmap[16 * 3] = { 209 0x00, 0x00, 0x00, /* black */ 210 0x7f, 0x00, 0x00, /* red */ 211 0x00, 0x7f, 0x00, /* green */ 212 0x7f, 0x7f, 0x00, /* brown */ 213 0x00, 0x00, 0x7f, /* blue */ 214 0x7f, 0x00, 0x7f, /* magenta */ 215 0x00, 0x7f, 0x7f, /* cyan */ 216 0xff, 0xff, 0xff, /* white */ 217 218 0x7f, 0x7f, 0x7f, /* black */ 219 0xff, 0x00, 0x00, /* red */ 220 0x00, 0xff, 0x00, /* green */ 221 0xff, 0xff, 0x00, /* brown */ 222 0x00, 0x00, 0xff, /* blue */ 223 0xff, 0x00, 0xff, /* magenta */ 224 0x00, 0xff, 0xff, /* cyan */ 225 0xff, 0xff, 0xff, /* white */ 226 }; 227 228 int mach64_match(struct device *, struct cfdata *, void *); 229 void mach64_attach(struct device *, struct device *, void *); 230 231 CFATTACH_DECL(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 232 NULL, NULL); 233 234 void mach64_init(struct mach64_softc *); 235 int mach64_get_memsize(struct mach64_softc *); 236 int mach64_get_max_ramdac(struct mach64_softc *); 237 void mach64_get_mode(struct mach64_softc *, struct videomode *); 238 int mach64_calc_crtcregs(struct mach64_softc *, struct mach64_crtcregs *, 239 struct videomode *); 240 void mach64_set_crtcregs(struct mach64_softc *, struct mach64_crtcregs *); 241 int mach64_modeswitch(struct mach64_softc *, struct videomode *); 242 void mach64_set_dsp(struct mach64_softc *); 243 void mach64_set_pll(struct mach64_softc *, int); 244 void mach64_reset_engine(struct mach64_softc *); 245 void mach64_init_engine(struct mach64_softc *); 246 void mach64_adjust_frame(struct mach64_softc *, int, int); 247 void mach64_init_lut(struct mach64_softc *); 248 void mach64_switch_screen(struct mach64_softc *); 249 void mach64_init_screen(struct mach64_softc *, struct mach64screen *, 250 const struct wsscreen_descr *, int, long *, int); 251 void mach64_restore_screen(struct mach64screen *, 252 const struct wsscreen_descr *, u_int16_t *); 253 int mach64_set_screentype(struct mach64_softc *, 254 const struct wsscreen_descr *); 255 int mach64_is_console(struct pci_attach_args *); 256 257 void mach64_cursor(void *, int, int, int); 258 int mach64_mapchar(void *, int, u_int *); 259 void mach64_putchar(void *, int, int, u_int, long); 260 void mach64_copycols(void *, int, int, int, int); 261 void mach64_erasecols(void *, int, int, int, long); 262 void mach64_copyrows(void *, int, int, int); 263 void mach64_eraserows(void *, int, int, long); 264 int mach64_allocattr(void *, int, int, int, long *); 265 266 #if 0 267 const struct wsdisplay_emulops mach64_emulops = { 268 mach64_cursor, 269 mach64_mapchar, 270 mach64_putchar, 271 mach64_copycols, 272 mach64_erasecols, 273 mach64_copyrows, 274 mach64_eraserows, 275 mach64_allocattr, 276 }; 277 #endif 278 279 struct wsscreen_descr mach64_defaultscreen = { 280 "default", 281 0, 0, 282 &mach64_console_screen.ri.ri_ops, 283 8, 16, 284 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 285 &default_mode 286 }, mach64_80x25_screen = { 287 "80x25", 80, 25, 288 &mach64_console_screen.ri.ri_ops, 289 8, 16, 290 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 291 &mach64_modes[0] 292 }, mach64_80x30_screen = { 293 "80x30", 80, 30, 294 &mach64_console_screen.ri.ri_ops, 295 8, 16, 296 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 297 &mach64_modes[1] 298 }, mach64_80x40_screen = { 299 "80x40", 80, 40, 300 &mach64_console_screen.ri.ri_ops, 301 8, 10, 302 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 303 &mach64_modes[0] 304 }, mach64_80x50_screen = { 305 "80x50", 80, 50, 306 &mach64_console_screen.ri.ri_ops, 307 8, 8, 308 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 309 &mach64_modes[0] 310 }, mach64_100x37_screen = { 311 "100x37", 100, 37, 312 &mach64_console_screen.ri.ri_ops, 313 8, 16, 314 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 315 &mach64_modes[2] 316 }, mach64_128x48_screen = { 317 "128x48", 128, 48, 318 &mach64_console_screen.ri.ri_ops, 319 8, 16, 320 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 321 &mach64_modes[3] 322 }, mach64_144x54_screen = { 323 "144x54", 144, 54, 324 &mach64_console_screen.ri.ri_ops, 325 8, 16, 326 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 327 &mach64_modes[4] 328 }, mach64_160x64_screen = { 329 "160x54", 160, 64, 330 &mach64_console_screen.ri.ri_ops, 331 8, 16, 332 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 333 &mach64_modes[5] 334 }; 335 336 const struct wsscreen_descr *_mach64_scrlist[] = { 337 &mach64_defaultscreen, 338 &mach64_80x25_screen, 339 &mach64_80x30_screen, 340 &mach64_80x40_screen, 341 &mach64_80x50_screen, 342 &mach64_100x37_screen, 343 &mach64_128x48_screen, 344 &mach64_144x54_screen, 345 &mach64_160x64_screen 346 }; 347 348 struct wsscreen_list mach64_screenlist = { 349 sizeof(_mach64_scrlist) / sizeof(struct wsscreen_descr *), 350 _mach64_scrlist 351 }; 352 353 int mach64_ioctl(void *, u_long, caddr_t, int, struct proc *); 354 paddr_t mach64_mmap(void *, off_t, int); 355 int mach64_alloc_screen(void *, const struct wsscreen_descr *, void **, 356 int *, int *, long *); 357 void mach64_free_screen(void *, void *); 358 int mach64_show_screen(void *, void *, int, void (*)(void *, int, int), 359 void *); 360 int mach64_load_font(void *, void *, struct wsdisplay_font *); 361 362 struct wsdisplay_accessops mach64_accessops = { 363 mach64_ioctl, 364 mach64_mmap, 365 mach64_alloc_screen, 366 mach64_free_screen, 367 mach64_show_screen, 368 NULL 369 }; 370 371 /* 372 * Inline functions for getting access to register aperture. 373 */ 374 static inline u_int32_t regr(struct mach64_softc *, u_int32_t); 375 static inline u_int8_t regrb(struct mach64_softc *, u_int32_t); 376 static inline void regw(struct mach64_softc *, u_int32_t, u_int32_t); 377 static inline void regwb(struct mach64_softc *, u_int32_t, u_int8_t); 378 static inline void regwb_pll(struct mach64_softc *, u_int32_t, u_int8_t); 379 380 static inline u_int32_t 381 regr(struct mach64_softc *sc, u_int32_t index) 382 { 383 384 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 385 } 386 387 static inline u_int8_t 388 regrb(struct mach64_softc *sc, u_int32_t index) 389 { 390 391 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 392 } 393 394 static inline void 395 regw(struct mach64_softc *sc, u_int32_t index, u_int32_t data) 396 { 397 398 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 399 } 400 401 static inline void 402 regwb(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 403 { 404 405 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 406 } 407 408 static inline void 409 regwb_pll(struct mach64_softc *sc, u_int32_t index, u_int8_t data) 410 { 411 412 regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); 413 regwb(sc, CLOCK_CNTL + 2, data); 414 regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); 415 } 416 417 static inline void 418 wait_for_fifo(struct mach64_softc *sc, u_int8_t v) 419 { 420 421 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 422 ; 423 } 424 425 static inline void 426 wait_for_idle(struct mach64_softc *sc) 427 { 428 429 wait_for_fifo(sc, 16); 430 while ((regr(sc, GUI_STAT) & 1) != 0) 431 ; 432 } 433 434 int 435 mach64_match(struct device *parent, struct cfdata *match, void *aux) 436 { 437 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 438 int i; 439 440 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 441 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 442 return 0; 443 444 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 445 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 446 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 447 mach64_chip_rev = PCI_REVISION(pa->pa_class); 448 return 1; 449 } 450 451 return 0; 452 } 453 454 void 455 mach64_attach(struct device *parent, struct device *self, void *aux) 456 { 457 struct mach64_softc *sc = (void *)self; 458 struct pci_attach_args *pa = aux; 459 char devinfo[256]; 460 int bar, reg, id; 461 struct wsemuldisplaydev_attach_args aa; 462 long defattr; 463 int setmode, console; 464 465 sc->sc_pc = pa->pa_pc; 466 sc->sc_pcitag = pa->pa_tag; 467 468 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 469 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 470 471 for (bar = 0; bar < NBARS; bar++) { 472 reg = PCI_MAPREG_START + (bar * 4); 473 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 474 sc->sc_pcitag, reg); 475 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 476 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 477 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 478 } 479 sc->sc_memt = pa->pa_memt; 480 481 mach64_init(sc); 482 483 printf("%s: %d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 484 sc->sc_dev.dv_xname, (u_int)(sc->sc_apersize / (1024 * 1024)), 485 (u_int)sc->sc_aperbase, (u_int)(sc->sc_regsize / 1024), 486 (u_int)sc->sc_regbase); 487 488 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_CT || 489 ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 490 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 491 (mach64_chip_rev & 0x07) == 0)) 492 sc->has_dsp = 0; 493 else 494 sc->has_dsp = 1; 495 496 sc->memsize = mach64_get_memsize(sc); 497 if (sc->memsize == 8192) 498 /* The last page is used as register aperture. */ 499 sc->memsize -= 4; 500 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 501 502 /* XXX is there any way to calculate reference frequency from 503 known values? */ 504 if (mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) 505 sc->ref_freq = 29498; 506 else 507 sc->ref_freq = 14318; 508 509 regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); 510 sc->ref_div = regrb(sc, CLOCK_CNTL + 2); 511 regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); 512 sc->mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); 513 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 514 (sc->ref_div * 2); 515 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 516 (sc->mem_freq * sc->ref_div); 517 sc->ramdac_freq = mach64_get_max_ramdac(sc); 518 printf("%s: %ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 519 sc->sc_dev.dv_xname, (u_long)sc->memsize, 520 mach64_memtype_names[sc->memtype], 521 sc->mem_freq / 1000, sc->mem_freq % 1000, 522 sc->ramdac_freq / 1000); 523 524 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 525 if (id != mach64_chip_id) { 526 printf("%s: chip ID mismatch, 0x%x != 0x%x\n", 527 sc->sc_dev.dv_xname, id, mach64_chip_id); 528 return; 529 } 530 531 console = mach64_is_console(pa); 532 533 #ifdef __sparc__ 534 if (console) { 535 mach64_get_mode(sc, &default_mode); 536 setmode = 0; 537 } else { 538 memcpy(&default_mode, &mach64_modes[0], sizeof(struct videomode)); 539 setmode = 1; 540 } 541 #else 542 memcpy(&default_mode, &mach64_modes[0], sizeof(struct videomode)); 543 setmode = 1; 544 #endif 545 546 sc->bits_per_pixel = 8; 547 sc->virt_x = default_mode.hdisplay; 548 sc->virt_y = default_mode.vdisplay; 549 sc->max_x = sc->virt_x - 1; 550 sc->max_y = (sc->memsize * 1024) / 551 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 552 553 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 554 555 mach64_init_engine(sc); 556 #if 0 557 mach64_adjust_frame(0, 0); 558 if (sc->bits_per_pixel == 8) 559 mach64_init_lut(sc); 560 #endif 561 562 printf("%s: initial resolution %dx%d at %d bpp\n", sc->sc_dev.dv_xname, 563 default_mode.hdisplay, default_mode.vdisplay, 564 sc->bits_per_pixel); 565 566 mach64_console_screen.ri.ri_hw = sc; 567 mach64_console_screen.ri.ri_depth = sc->bits_per_pixel; 568 mach64_console_screen.ri.ri_bits = (void *)sc->sc_aperbase; 569 mach64_console_screen.ri.ri_width = default_mode.hdisplay; 570 mach64_console_screen.ri.ri_height = default_mode.vdisplay; 571 mach64_console_screen.ri.ri_stride = mach64_console_screen.ri.ri_width; 572 mach64_console_screen.ri.ri_flg = RI_CLEAR; 573 574 rasops_init(&mach64_console_screen.ri, mach64_console_screen.ri.ri_height / 16, 575 mach64_console_screen.ri.ri_width / 8); 576 577 mach64_defaultscreen.nrows = mach64_console_screen.ri.ri_rows; 578 mach64_defaultscreen.ncols = mach64_console_screen.ri.ri_cols; 579 580 mach64_console_screen.ri.ri_ops.allocattr(&mach64_console_screen.ri, 0, 0, 0, 581 &defattr); 582 583 /* Initialize fonts */ 584 wsfont_init(); 585 586 if (console) { 587 mach64_init_screen(sc, &mach64_console_screen, 588 &mach64_defaultscreen, 1, &defattr, setmode); 589 wsdisplay_cnattach(&mach64_defaultscreen, &mach64_console_screen.ri, 590 0, 0, defattr); 591 } 592 593 aa.console = console; 594 aa.scrdata = &mach64_screenlist; 595 aa.accessops = &mach64_accessops; 596 aa.accesscookie = sc; 597 598 config_found(self, &aa, wsemuldisplaydevprint); 599 } 600 601 void 602 mach64_init_screen(struct mach64_softc *sc, struct mach64screen *scr, 603 const struct wsscreen_descr *type, int existing, long *attrp, int setmode) 604 { 605 606 scr->sc = sc; 607 scr->type = type; 608 scr->mindispoffset = 0; 609 scr->maxdispoffset = sc->memsize * 1024; 610 scr->dispoffset = 0; 611 scr->cursorcol = 0; 612 scr->cursorrow = 0; 613 614 scr->mem = (u_int16_t *)malloc(type->nrows * type->ncols * 2, 615 M_DEVBUF, M_WAITOK); 616 if (existing) { 617 scr->active = 1; 618 619 if (setmode && mach64_set_screentype(sc, type)) { 620 panic("%s: failed to switch video mode", 621 sc->sc_dev.dv_xname); 622 } 623 } else { 624 scr->active = 0; 625 } 626 627 LIST_INSERT_HEAD(&sc->screens, scr, next); 628 } 629 630 void 631 mach64_init(struct mach64_softc *sc) 632 { 633 634 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 635 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 636 panic("%s: failed to map aperture", sc->sc_dev.dv_xname); 637 } 638 sc->sc_aperbase = (vaddr_t)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 639 640 sc->sc_regt = sc->sc_memt; 641 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 642 sc->sc_regsize, &sc->sc_regh); 643 sc->sc_regbase = sc->sc_aperbase + 0x7ffc00; 644 645 #if _BYTE_ORDER == _BIG_ENDIAN 646 sc->sc_aperbase += 0x800000; 647 sc->sc_apersize -= 0x800000; 648 #endif 649 650 LIST_INIT(&sc->screens); 651 sc->active = NULL; 652 sc->currenttype = &mach64_defaultscreen; 653 callout_init(&sc->switch_callout); 654 } 655 656 int 657 mach64_get_memsize(struct mach64_softc *sc) 658 { 659 int tmp, memsize; 660 int mem_tab[] = { 661 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 662 }; 663 664 tmp = regr(sc, MEM_CNTL); 665 if (sc->has_dsp) { 666 tmp &= 0x0000000f; 667 if (tmp < 8) 668 memsize = (tmp + 1) * 512; 669 else if (tmp < 12) 670 memsize = (tmp - 3) * 1024; 671 else 672 memsize = (tmp - 7) * 2048; 673 } else { 674 memsize = mem_tab[tmp & 0x07]; 675 } 676 677 return memsize; 678 } 679 680 int 681 mach64_get_max_ramdac(struct mach64_softc *sc) 682 { 683 int i; 684 685 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 686 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 687 (mach64_chip_rev & 0x07)) 688 return 170000; 689 690 for (i = 0; i < sizeof(mach64_info) / sizeof(mach64_info[0]); i++) 691 if (mach64_chip_id == mach64_info[i].chip_id) 692 return mach64_info[i].ramdac_freq; 693 694 if (sc->bits_per_pixel == 8) 695 return 135000; 696 else 697 return 80000; 698 } 699 700 void 701 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 702 { 703 struct mach64_crtcregs crtc; 704 705 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 706 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 707 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 708 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 709 710 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 711 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 712 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 713 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 714 mode->hsync_start; 715 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 716 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 717 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 718 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 719 720 #ifdef MACH64_DEBUG 721 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 722 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 723 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 724 #endif 725 } 726 727 int 728 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 729 struct videomode *mode) 730 { 731 732 if (mode->dot_clock > sc->ramdac_freq) 733 /* Clock too high. */ 734 return 1; 735 736 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 737 ((mode->htotal >> 3) - 1); 738 crtc->h_sync_strt_wid = 739 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 740 ((mode->hsync_start >> 3) - 1); 741 742 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 743 (mode->vtotal - 1); 744 crtc->v_sync_strt_wid = 745 ((mode->vsync_end - mode->vsync_start) << 16) | 746 (mode->vsync_start - 1); 747 748 if (mode->flags & VID_NVSYNC) 749 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 750 751 switch (sc->bits_per_pixel) { 752 case 8: 753 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 754 break; 755 case 16: 756 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 757 break; 758 case 32: 759 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 760 break; 761 } 762 763 crtc->gen_cntl = 0; 764 if (mode->flags & VID_INTERLACE) 765 crtc->gen_cntl |= CRTC_INTERLACE_EN; 766 if (mode->flags & VID_CSYNC) 767 crtc->gen_cntl |= CRTC_CSYNC_EN; 768 769 crtc->dot_clock = mode->dot_clock; 770 771 return 0; 772 } 773 774 void 775 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 776 { 777 778 mach64_set_pll(sc, crtc->dot_clock); 779 780 if (sc->has_dsp) 781 mach64_set_dsp(sc); 782 783 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 784 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 785 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 786 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 787 788 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 789 790 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 791 792 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 793 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 794 } 795 796 int 797 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 798 { 799 struct mach64_crtcregs crtc; 800 801 if (mach64_calc_crtcregs(sc, &crtc, mode)) 802 return 1; 803 804 mach64_set_crtcregs(sc, &crtc); 805 return 0; 806 } 807 808 void 809 mach64_reset_engine(struct mach64_softc *sc) 810 { 811 812 /* Reset engine.*/ 813 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 814 815 /* Enable engine. */ 816 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 817 818 /* Ensure engine is not locked up by clearing any FIFO or 819 host errors. */ 820 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 821 BUS_FIFO_ERR_ACK); 822 } 823 824 void 825 mach64_init_engine(struct mach64_softc *sc) 826 { 827 u_int32_t pitch_value; 828 829 pitch_value = sc->virt_x; 830 831 if (sc->bits_per_pixel == 24) 832 pitch_value *= 3; 833 834 mach64_reset_engine(sc); 835 836 wait_for_fifo(sc, 14); 837 838 regw(sc, CONTEXT_MASK, 0xffffffff); 839 840 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 841 842 regw(sc, DST_Y_X, 0); 843 regw(sc, DST_HEIGHT, 0); 844 regw(sc, DST_BRES_ERR, 0); 845 regw(sc, DST_BRES_INC, 0); 846 regw(sc, DST_BRES_DEC, 0); 847 848 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 849 DST_Y_TOP_TO_BOTTOM); 850 851 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 852 853 regw(sc, SRC_Y_X, 0); 854 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 855 regw(sc, SRC_Y_X_START, 0); 856 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 857 858 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 859 860 wait_for_fifo(sc, 13); 861 regw(sc, HOST_CNTL, 0); 862 863 regw(sc, PAT_REG0, 0); 864 regw(sc, PAT_REG1, 0); 865 regw(sc, PAT_CNTL, 0); 866 867 regw(sc, SC_LEFT, 0); 868 regw(sc, SC_TOP, 0); 869 regw(sc, SC_BOTTOM, default_mode.vdisplay - 1); 870 regw(sc, SC_RIGHT, pitch_value - 1); 871 872 regw(sc, DP_BKGD_CLR, 0); 873 regw(sc, DP_FRGD_CLR, 0xffffffff); 874 regw(sc, DP_WRITE_MASK, 0xffffffff); 875 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 876 877 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 878 879 wait_for_fifo(sc, 3); 880 regw(sc, CLR_CMP_CLR, 0); 881 regw(sc, CLR_CMP_MASK, 0xffffffff); 882 regw(sc, CLR_CMP_CNTL, 0); 883 884 wait_for_fifo(sc, 2); 885 switch (sc->bits_per_pixel) { 886 case 8: 887 regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); 888 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 889 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) & ~DAC_8BIT_EN); 890 break; 891 #if 0 892 case 32: 893 regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); 894 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 895 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 896 break; 897 #endif 898 } 899 900 wait_for_fifo(sc, 5); 901 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 902 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 903 904 wait_for_idle(sc); 905 } 906 907 void 908 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 909 { 910 int offset; 911 912 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 913 914 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 915 offset); 916 } 917 918 void 919 mach64_set_dsp(struct mach64_softc *sc) 920 { 921 u_int32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 922 u_int32_t dsp_off, dsp_on, dsp_xclks_per_qw; 923 u_int32_t xclks_per_qw, y; 924 u_int32_t fifo_off, fifo_on; 925 926 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 927 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 928 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 929 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 930 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 931 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 932 dsp_loop_latency = 0; 933 fifo_depth = 24; 934 } else { 935 dsp_loop_latency = 2; 936 fifo_depth = 32; 937 } 938 939 dsp_precision = 0; 940 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 941 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 942 y = (xclks_per_qw * fifo_depth) >> 11; 943 while (y) { 944 y >>= 1; 945 dsp_precision++; 946 } 947 dsp_precision -= 5; 948 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 949 950 switch (sc->memtype) { 951 case DRAM: 952 case EDO_DRAM: 953 case PSEUDO_EDO: 954 if (sc->memsize > 1024) { 955 page_size = 9; 956 dsp_loop_latency += 6; 957 } else { 958 page_size = 10; 959 if (sc->memtype == DRAM) 960 dsp_loop_latency += 8; 961 else 962 dsp_loop_latency += 7; 963 } 964 break; 965 case SDRAM: 966 case SGRAM: 967 if (sc->memsize > 1024) { 968 page_size = 8; 969 dsp_loop_latency += 8; 970 } else { 971 page_size = 10; 972 dsp_loop_latency += 9; 973 } 974 break; 975 default: 976 page_size = 10; 977 dsp_loop_latency += 9; 978 break; 979 } 980 981 if (xclks_per_qw >= (page_size << 11)) 982 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 983 else 984 fifo_on = (3 * page_size + 2) << 6; 985 986 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 987 dsp_on = fifo_on >> dsp_precision; 988 dsp_off = fifo_off >> dsp_precision; 989 990 #ifdef MACH64_DEBUG 991 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 992 "dsp_precision = %d, dsp_loop_latency = %d,\n" 993 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 994 "mclk_post_div = %d, vclk_post_div = %d\n", 995 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 996 sc->mclk_fb_div, sc->vclk_fb_div, 997 sc->mclk_post_div, sc->vclk_post_div); 998 #endif 999 1000 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1001 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1002 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1003 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1004 } 1005 1006 void 1007 mach64_set_pll(struct mach64_softc *sc, int clock) 1008 { 1009 int q; 1010 1011 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1012 #ifdef MACH64_DEBUG 1013 printf("q = %d\n", q); 1014 #endif 1015 if (q > 25500) { 1016 printf("Warning: q > 25500\n"); 1017 q = 25500; 1018 sc->vclk_post_div = 1; 1019 sc->log2_vclk_post_div = 0; 1020 } else if (q > 12750) { 1021 sc->vclk_post_div = 1; 1022 sc->log2_vclk_post_div = 0; 1023 } else if (q > 6350) { 1024 sc->vclk_post_div = 2; 1025 sc->log2_vclk_post_div = 1; 1026 } else if (q > 3150) { 1027 sc->vclk_post_div = 4; 1028 sc->log2_vclk_post_div = 2; 1029 } else if (q >= 1600) { 1030 sc->vclk_post_div = 8; 1031 sc->log2_vclk_post_div = 3; 1032 } else { 1033 printf("Warning: q < 1600\n"); 1034 sc->vclk_post_div = 8; 1035 sc->log2_vclk_post_div = 3; 1036 } 1037 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1038 1039 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1040 regwb_pll(sc, VCLK_POST_DIV, sc->log2_vclk_post_div); 1041 regwb_pll(sc, VCLK0_FB_DIV, sc->vclk_fb_div); 1042 } 1043 1044 void 1045 mach64_init_lut(struct mach64_softc *sc) 1046 { 1047 int i; 1048 1049 regwb(sc, DAC_REGS, 0); 1050 1051 for (i = 0; i < 16; i++) { 1052 regwb(sc, DAC_REGS + 1, mach64_cmap[i * 3]); 1053 regwb(sc, DAC_REGS + 1, mach64_cmap[i * 3 + 1]); 1054 regwb(sc, DAC_REGS + 1, mach64_cmap[i + 3 + 2]); 1055 } 1056 } 1057 1058 void 1059 mach64_switch_screen(struct mach64_softc *sc) 1060 { 1061 struct mach64screen *scr, *oldscr; 1062 const struct wsscreen_descr *type; 1063 1064 scr = sc->wanted; 1065 if (!scr) { 1066 printf("mach64_switch_screen: disappeared\n"); 1067 (*sc->switchcb)(sc->switchcbarg, EIO, 0); 1068 return; 1069 } 1070 type = scr->type; 1071 oldscr = sc->active; /* can be NULL! */ 1072 #ifdef DIAGNOSTIC 1073 if (oldscr) { 1074 if (!oldscr->active) 1075 panic("mach64_switch_screen: not active"); 1076 if (oldscr->type != vc->currenttype) 1077 panic("mach64_switch_screen: bad type"); 1078 } 1079 #endif 1080 if (scr == oldscr) 1081 return; 1082 1083 #ifdef DIAGNOSTIC 1084 if (scr->active) 1085 panic("mach64_switch_screen: active"); 1086 #endif 1087 1088 if (oldscr) 1089 oldscr->active = 0; 1090 1091 if (sc->currenttype != type) { 1092 mach64_set_screentype(sc, type); 1093 sc->currenttype = type; 1094 } 1095 1096 scr->dispoffset = scr->mindispoffset; 1097 1098 if (!oldscr || (scr->dispoffset != oldscr->dispoffset)) { 1099 1100 } 1101 1102 /* Clear the entire screen. */ 1103 1104 scr->active = 1; 1105 mach64_restore_screen(scr, type, scr->mem); 1106 1107 sc->active = scr; 1108 1109 mach64_cursor(scr, scr->cursoron, scr->cursorrow, scr->cursorcol); 1110 1111 sc->wanted = 0; 1112 if (sc->switchcb) 1113 (*sc->switchcb)(sc->switchcbarg, 0, 0); 1114 } 1115 1116 void 1117 mach64_restore_screen(struct mach64screen *scr, 1118 const struct wsscreen_descr *type, u_int16_t *mem) 1119 { 1120 1121 } 1122 1123 int 1124 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1125 { 1126 struct mach64_crtcregs regs; 1127 1128 if (mach64_calc_crtcregs(sc, ®s, 1129 (struct videomode *)des->modecookie)) 1130 return 1; 1131 1132 mach64_set_crtcregs(sc, ®s); 1133 return 0; 1134 } 1135 1136 int 1137 mach64_is_console(struct pci_attach_args *pa) 1138 { 1139 #ifdef __sparc__ 1140 int node; 1141 1142 node = PCITAG_NODE(pa->pa_tag); 1143 if (node == -1) 1144 return 0; 1145 1146 return (node == OF_instance_to_package(OF_stdout())); 1147 #else 1148 return 1; 1149 #endif 1150 } 1151 1152 /* 1153 * wsdisplay_emulops 1154 */ 1155 1156 void 1157 mach64_cursor(void *cookie, int on, int row, int col) 1158 { 1159 1160 } 1161 1162 #if 0 1163 int 1164 mach64_mapchar(void *cookie, int uni, u_int *index) 1165 { 1166 1167 return 0; 1168 } 1169 1170 void 1171 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1172 { 1173 1174 } 1175 1176 void 1177 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1178 { 1179 1180 } 1181 1182 void 1183 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1184 { 1185 1186 } 1187 1188 void 1189 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1190 { 1191 1192 } 1193 1194 int 1195 mach64_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1196 { 1197 1198 return 0; 1199 } 1200 #endif 1201 1202 void 1203 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1204 { 1205 1206 } 1207 1208 /* 1209 * wsdisplay_accessops 1210 */ 1211 1212 int 1213 mach64_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 1214 { 1215 1216 return ENOTTY; 1217 } 1218 1219 paddr_t 1220 mach64_mmap(void *v, off_t offset, int prot) 1221 { 1222 1223 return -1; 1224 } 1225 1226 int 1227 mach64_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, 1228 int *curxp, int *curyp, long *defattrp) 1229 { 1230 struct mach64_softc *sc = v; 1231 struct mach64screen *scr; 1232 1233 scr = malloc(sizeof(struct mach64screen), M_DEVBUF, M_WAITOK|M_ZERO); 1234 mach64_init_screen(sc, scr, type, 0, defattrp, sc->active == NULL); 1235 rasops_init(&scr->ri, mach64_console_screen.ri.ri_height / 16, 1236 mach64_console_screen.ri.ri_width / 8); 1237 1238 scr->mem = malloc(type->ncols * type->nrows * 2, M_DEVBUF, 1239 M_WAITOK); 1240 mach64_eraserows(sc, 0, type->nrows, *defattrp); 1241 if (sc->active == NULL) { 1242 scr->active = 1; 1243 sc->active = scr; 1244 sc->currenttype = type; 1245 } 1246 1247 *cookiep = scr; 1248 *curxp = scr->cursorcol; 1249 *curyp = scr->cursorrow; 1250 1251 return 0; 1252 } 1253 1254 void 1255 mach64_free_screen(void *v, void *cookie) 1256 { 1257 struct mach64_softc *sc = v; 1258 struct mach64screen *scr = cookie; 1259 1260 LIST_REMOVE(scr, next); 1261 if (scr != &mach64_console_screen) 1262 free(scr, M_DEVBUF); 1263 else 1264 panic("mach64_free_screen: console"); 1265 1266 if (sc->active == scr) 1267 sc->active = 0; 1268 } 1269 1270 int 1271 mach64_show_screen(void *v, void *cookie, int waitok, 1272 void (*cb)(void *, int, int), void *cbarg) 1273 { 1274 struct mach64_softc *sc = v; 1275 struct mach64screen *scr, *oldscr; 1276 1277 scr = cookie; 1278 oldscr = sc->active; 1279 if (scr == oldscr) 1280 return 0; 1281 1282 sc->wanted = scr; 1283 sc->switchcb = cb; 1284 sc->switchcbarg = cbarg; 1285 if (cb) { 1286 callout_reset(&sc->switch_callout, 0, 1287 (void(*)(void *))mach64_switch_screen, sc); 1288 return EAGAIN; 1289 } 1290 1291 mach64_switch_screen(sc); 1292 1293 return 0; 1294 } 1295 1296 #if 0 1297 int 1298 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1299 { 1300 1301 return 0; 1302 } 1303 #endif 1304
Indexes created Thu Oct 02 14:10:14 GMT 2025