machfb.c revision 1.70
1 /* $NetBSD: machfb.c,v 1.70 2011/08/03 05:27:08 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.70 2011/08/03 05:27:08 macallan Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #ifdef __sparc__ 58 #include <dev/sun/fbio.h> 59 #include <dev/sun/fbvar.h> 60 #include <sys/conf.h> 61 #else 62 #include <dev/wscons/wsdisplayvar.h> 63 #endif 64 65 #include <dev/wscons/wsconsio.h> 66 #include <dev/wsfont/wsfont.h> 67 #include <dev/rasops/rasops.h> 68 #include <dev/pci/wsdisplay_pci.h> 69 70 #include <dev/wscons/wsdisplay_vconsvar.h> 71 72 #include "opt_wsemul.h" 73 #include "opt_machfb.h" 74 75 #define MACH64_REG_SIZE 1024 76 #define MACH64_REG_OFF 0x7ffc00 77 78 #define NBARS 3 /* number of Mach64 PCI BARs */ 79 80 struct vga_bar { 81 bus_addr_t vb_base; 82 pcireg_t vb_busaddr; 83 bus_size_t vb_size; 84 pcireg_t vb_type; 85 int vb_flags; 86 }; 87 88 struct mach64_softc { 89 device_t sc_dev; 90 #ifdef __sparc__ 91 struct fbdevice sc_fb; 92 #endif 93 pci_chipset_tag_t sc_pc; 94 pcitag_t sc_pcitag; 95 96 struct vga_bar sc_bars[NBARS]; 97 struct vga_bar sc_rom; 98 99 #define sc_aperbase sc_bars[0].vb_base 100 #define sc_apersize sc_bars[0].vb_size 101 #define sc_aperphys sc_bars[0].vb_busaddr 102 103 #define sc_iobase sc_bars[1].vb_base 104 #define sc_iosize sc_bars[1].vb_size 105 106 #define sc_regbase sc_bars[2].vb_base 107 #define sc_regsize sc_bars[2].vb_size 108 #define sc_regphys sc_bars[2].vb_busaddr 109 110 bus_space_tag_t sc_regt; 111 bus_space_tag_t sc_memt; 112 bus_space_tag_t sc_iot; 113 bus_space_handle_t sc_regh; 114 bus_space_handle_t sc_memh; 115 void *sc_aperture; /* mapped aperture vaddr */ 116 void *sc_registers; /* mapped registers vaddr */ 117 118 uint32_t sc_nbus, sc_ndev, sc_nfunc; 119 size_t memsize; 120 int memtype; 121 122 int sc_mode; 123 int sc_bg; 124 int sc_locked; 125 126 int has_dsp; 127 int bits_per_pixel; 128 int max_x; 129 int max_y; 130 int virt_x; 131 int virt_y; 132 int color_depth; 133 134 int mem_freq; 135 int ramdac_freq; 136 int ref_freq; 137 138 int ref_div; 139 int log2_vclk_post_div; 140 int vclk_post_div; 141 int vclk_fb_div; 142 int mclk_post_div; 143 int mclk_fb_div; 144 int sc_clock; /* which clock to use */ 145 146 struct videomode *sc_my_mode; 147 int sc_edid_size; 148 uint8_t sc_edid_data[1024]; 149 150 u_char sc_cmap_red[256]; 151 u_char sc_cmap_green[256]; 152 u_char sc_cmap_blue[256]; 153 int sc_dacw, sc_blanked, sc_console; 154 struct vcons_data vd; 155 struct wsdisplay_accessops sc_accessops; 156 }; 157 158 struct mach64_crtcregs { 159 uint32_t h_total_disp; 160 uint32_t h_sync_strt_wid; 161 uint32_t v_total_disp; 162 uint32_t v_sync_strt_wid; 163 uint32_t gen_cntl; 164 uint32_t clock_cntl; 165 uint32_t color_depth; 166 uint32_t dot_clock; 167 }; 168 169 static struct { 170 uint16_t chip_id; 171 uint32_t ramdac_freq; 172 } const mach64_info[] = { 173 { PCI_PRODUCT_ATI_MACH64_GX, 135000 }, 174 { PCI_PRODUCT_ATI_MACH64_CX, 135000 }, 175 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 176 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 185 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 186 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 189 #if 0 190 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 192 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 193 #endif 194 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 195 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 196 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 197 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 198 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 199 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 200 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 201 }; 202 203 static int mach64_chip_id, mach64_chip_rev; 204 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 205 206 static const char *mach64_gx_memtype_names[] = { 207 "DRAM", "VRAM", "VRAM", "DRAM", 208 "DRAM", "VRAM", "VRAM", "(unknown type)" 209 }; 210 211 static const char *mach64_memtype_names[] = { 212 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 213 "(unknown type)" 214 }; 215 216 static struct videomode mach64_modes[] = { 217 /* 640x400 @ 70 Hz, 31.5 kHz */ 218 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0, NULL, }, 219 /* 640x480 @ 72 Hz, 36.5 kHz */ 220 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0, NULL, }, 221 /* 800x600 @ 72 Hz, 48.0 kHz */ 222 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 223 VID_PHSYNC | VID_PVSYNC, NULL, }, 224 /* 1024x768 @ 70 Hz, 56.5 kHz */ 225 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 226 VID_NHSYNC | VID_NVSYNC, NULL, }, 227 /* 1152x864 @ 70 Hz, 62.4 kHz */ 228 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0, NULL, }, 229 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 230 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 231 VID_NHSYNC | VID_NVSYNC, NULL, } 232 }; 233 234 extern const u_char rasops_cmap[768]; 235 236 static int mach64_match(device_t, cfdata_t, void *); 237 static void mach64_attach(device_t, device_t, void *); 238 239 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 240 NULL, NULL); 241 242 static void mach64_init(struct mach64_softc *); 243 static int mach64_get_memsize(struct mach64_softc *); 244 static int mach64_get_max_ramdac(struct mach64_softc *); 245 246 #if defined(__sparc__) || defined(__powerpc__) 247 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 248 #endif 249 250 static int mach64_calc_crtcregs(struct mach64_softc *, 251 struct mach64_crtcregs *, 252 struct videomode *); 253 static void mach64_set_crtcregs(struct mach64_softc *, 254 struct mach64_crtcregs *); 255 256 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 257 static void mach64_set_dsp(struct mach64_softc *); 258 static void mach64_set_pll(struct mach64_softc *, int); 259 static void mach64_reset_engine(struct mach64_softc *); 260 static void mach64_init_engine(struct mach64_softc *); 261 #if 0 262 static void mach64_adjust_frame(struct mach64_softc *, int, int); 263 #endif 264 static void mach64_init_lut(struct mach64_softc *); 265 266 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 267 static int mach64_set_screentype(struct mach64_softc *, 268 const struct wsscreen_descr *); 269 static int mach64_is_console(struct mach64_softc *); 270 271 static void mach64_cursor(void *, int, int, int); 272 #if 0 273 static int mach64_mapchar(void *, int, u_int *); 274 #endif 275 static void mach64_putchar(void *, int, int, u_int, long); 276 static void mach64_copycols(void *, int, int, int, int); 277 static void mach64_erasecols(void *, int, int, int, long); 278 static void mach64_copyrows(void *, int, int, int); 279 static void mach64_eraserows(void *, int, int, long); 280 static void mach64_clearscreen(struct mach64_softc *); 281 282 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 283 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 284 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 285 uint8_t, uint8_t); 286 static void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, 287 int, int, int) ; 288 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 289 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 290 uint32_t, uint32_t); 291 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 292 #if 0 293 static void mach64_showpal(struct mach64_softc *); 294 #endif 295 296 static void set_address(struct rasops_info *, void *); 297 static void machfb_blank(struct mach64_softc *, int); 298 static int machfb_drm_print(void *, const char *); 299 300 static struct wsscreen_descr mach64_defaultscreen = { 301 "default", 302 80, 30, 303 NULL, 304 8, 16, 305 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 306 &default_mode 307 }, mach64_80x25_screen = { 308 "80x25", 80, 25, 309 NULL, 310 8, 16, 311 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 312 &mach64_modes[0] 313 }, mach64_80x30_screen = { 314 "80x30", 80, 30, 315 NULL, 316 8, 16, 317 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 318 &mach64_modes[1] 319 }, mach64_80x40_screen = { 320 "80x40", 80, 40, 321 NULL, 322 8, 10, 323 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 324 &mach64_modes[0] 325 }, mach64_80x50_screen = { 326 "80x50", 80, 50, 327 NULL, 328 8, 8, 329 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 330 &mach64_modes[0] 331 }, mach64_100x37_screen = { 332 "100x37", 100, 37, 333 NULL, 334 8, 16, 335 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 336 &mach64_modes[2] 337 }, mach64_128x48_screen = { 338 "128x48", 128, 48, 339 NULL, 340 8, 16, 341 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 342 &mach64_modes[3] 343 }, mach64_144x54_screen = { 344 "144x54", 144, 54, 345 NULL, 346 8, 16, 347 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 348 &mach64_modes[4] 349 }, mach64_160x64_screen = { 350 "160x54", 160, 64, 351 NULL, 352 8, 16, 353 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 354 &mach64_modes[5] 355 }; 356 357 static const struct wsscreen_descr *_mach64_scrlist[] = { 358 &mach64_defaultscreen, 359 &mach64_80x25_screen, 360 &mach64_80x30_screen, 361 &mach64_80x40_screen, 362 &mach64_80x50_screen, 363 &mach64_100x37_screen, 364 &mach64_128x48_screen, 365 &mach64_144x54_screen, 366 &mach64_160x64_screen 367 }; 368 369 static struct wsscreen_list mach64_screenlist = { 370 __arraycount(_mach64_scrlist), 371 _mach64_scrlist 372 }; 373 374 static int mach64_ioctl(void *, void *, u_long, void *, int, 375 struct lwp *); 376 static paddr_t mach64_mmap(void *, void *, off_t, int); 377 378 #if 0 379 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 380 #endif 381 382 383 static struct vcons_screen mach64_console_screen; 384 385 /* framebuffer device, SPARC-only so far */ 386 #ifdef __sparc__ 387 388 static void machfb_unblank(device_t); 389 static void machfb_fbattach(struct mach64_softc *); 390 391 extern struct cfdriver machfb_cd; 392 393 dev_type_open(machfb_fbopen); 394 dev_type_close(machfb_fbclose); 395 dev_type_ioctl(machfb_fbioctl); 396 dev_type_mmap(machfb_fbmmap); 397 398 /* frame buffer generic driver */ 399 static struct fbdriver machfb_fbdriver = { 400 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 401 machfb_fbmmap, nokqfilter 402 }; 403 404 #endif /* __sparc__ */ 405 406 /* 407 * Inline functions for getting access to register aperture. 408 */ 409 410 static inline uint32_t 411 regr(struct mach64_softc *sc, uint32_t index) 412 { 413 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 414 } 415 416 static inline uint8_t 417 regrb(struct mach64_softc *sc, uint32_t index) 418 { 419 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 420 } 421 422 static inline void 423 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 424 { 425 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 426 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 427 BUS_SPACE_BARRIER_WRITE); 428 } 429 430 static inline void 431 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 432 { 433 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 434 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 435 BUS_SPACE_BARRIER_WRITE); 436 } 437 438 static inline void 439 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 440 { 441 uint32_t reg; 442 443 reg = regr(sc, CLOCK_CNTL); 444 reg |= PLL_WR_EN; 445 regw(sc, CLOCK_CNTL, reg); 446 reg &= ~(PLL_ADDR | PLL_DATA); 447 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 448 reg |= data << PLL_DATA_SHIFT; 449 reg |= CLOCK_STROBE; 450 regw(sc, CLOCK_CNTL, reg); 451 reg &= ~PLL_WR_EN; 452 regw(sc, CLOCK_CNTL, reg); 453 } 454 455 static inline uint8_t 456 regrb_pll(struct mach64_softc *sc, uint32_t index) 457 { 458 459 regwb(sc, CLOCK_CNTL + 1, index << 2); 460 return regrb(sc, CLOCK_CNTL + 2); 461 } 462 463 static inline void 464 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 465 { 466 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 467 continue; 468 } 469 470 static inline void 471 wait_for_idle(struct mach64_softc *sc) 472 { 473 wait_for_fifo(sc, 16); 474 while ((regr(sc, GUI_STAT) & 1) != 0) 475 continue; 476 } 477 478 static int 479 mach64_match(device_t parent, cfdata_t match, void *aux) 480 { 481 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 482 int i; 483 484 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 485 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 486 return 0; 487 488 for (i = 0; i < __arraycount(mach64_info); i++) 489 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 490 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 491 mach64_chip_rev = PCI_REVISION(pa->pa_class); 492 return 100; 493 } 494 495 return 0; 496 } 497 498 static void 499 mach64_attach(device_t parent, device_t self, void *aux) 500 { 501 struct mach64_softc *sc = device_private(self); 502 struct pci_attach_args *pa = aux; 503 struct rasops_info *ri; 504 prop_data_t edid_data; 505 const struct videomode *mode = NULL; 506 char devinfo[256]; 507 int bar, id, expected_id; 508 int is_gx; 509 const char **memtype_names; 510 struct wsemuldisplaydev_attach_args aa; 511 long defattr; 512 int setmode, width, height; 513 pcireg_t screg; 514 uint32_t reg; 515 const pcireg_t enables = PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE; 516 517 sc->sc_dev = self; 518 sc->sc_pc = pa->pa_pc; 519 sc->sc_pcitag = pa->pa_tag; 520 sc->sc_dacw = -1; 521 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 522 sc->sc_nbus = pa->pa_bus; 523 sc->sc_ndev = pa->pa_device; 524 sc->sc_nfunc = pa->pa_function; 525 sc->sc_locked = 0; 526 sc->sc_iot = pa->pa_iot; 527 sc->sc_accessops.ioctl = mach64_ioctl; 528 sc->sc_accessops.mmap = mach64_mmap; 529 530 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 531 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 532 PCI_REVISION(pa->pa_class)); 533 aprint_naive(": Graphics processor\n"); 534 #ifdef MACHFB_DEBUG 535 printf(prop_dictionary_externalize(device_properties(self))); 536 #endif 537 538 /* enable memory and disable IO access */ 539 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 540 if ((screg & enables) != enables) { 541 screg |= enables; 542 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 543 PCI_COMMAND_STATUS_REG, screg); 544 } 545 for (bar = 0; bar < NBARS; bar++) { 546 reg = PCI_MAPREG_START + (bar * 4); 547 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 548 sc->sc_pcitag, reg); 549 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 550 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 551 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 552 sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc, 553 sc->sc_pcitag, reg) & 0xfffffff0; 554 } 555 printf("%s: aperture size %08x\n", device_xname(sc->sc_dev), 556 (uint32_t)sc->sc_apersize); 557 558 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 559 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 560 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 561 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 562 sc->sc_memt = pa->pa_memt; 563 564 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 565 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 566 panic("%s: failed to map aperture", device_xname(sc->sc_dev)); 567 } 568 sc->sc_aperture = (void *)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 569 570 /* If the BAR was never mapped, fix it up in MMIO. */ 571 if(sc->sc_regsize == 0) { 572 sc->sc_regsize = MACH64_REG_SIZE; 573 sc->sc_regbase = sc->sc_aperbase + MACH64_REG_OFF; 574 sc->sc_regphys = sc->sc_aperphys + MACH64_REG_OFF; 575 } 576 577 sc->sc_regt = sc->sc_memt; 578 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 579 sc->sc_regsize, &sc->sc_regh); 580 sc->sc_registers = (char *)sc->sc_aperture + 0x7ffc00; 581 582 mach64_init(sc); 583 584 aprint_normal_dev(sc->sc_dev, 585 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 586 (u_int)(sc->sc_apersize / (1024 * 1024)), 587 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 588 (u_int)sc->sc_regphys); 589 590 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 591 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 592 593 prop_dictionary_get_uint32(device_properties(self), "width", &width); 594 prop_dictionary_get_uint32(device_properties(self), "height", &height); 595 596 if ((edid_data = prop_dictionary_get(device_properties(self), "EDID")) 597 != NULL) { 598 struct edid_info ei; 599 600 sc->sc_edid_size = min(1024, prop_data_size(edid_data)); 601 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 602 memcpy(sc->sc_edid_data, prop_data_data_nocopy(edid_data), 603 sc->sc_edid_size); 604 605 edid_parse(sc->sc_edid_data, &ei); 606 607 #ifdef MACHFB_DEBUG 608 edid_print(&ei); 609 #endif 610 } 611 612 is_gx = 0; 613 switch(mach64_chip_id) { 614 case PCI_PRODUCT_ATI_MACH64_GX: 615 case PCI_PRODUCT_ATI_MACH64_CX: 616 is_gx = 1; 617 case PCI_PRODUCT_ATI_MACH64_CT: 618 sc->has_dsp = 0; 619 break; 620 case PCI_PRODUCT_ATI_MACH64_VT: 621 case PCI_PRODUCT_ATI_RAGE_II: 622 if((mach64_chip_rev & 0x07) == 0) { 623 sc->has_dsp = 0; 624 break; 625 } 626 /* Otherwise fall through. */ 627 default: 628 sc->has_dsp = 1; 629 } 630 631 memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names; 632 633 sc->memsize = mach64_get_memsize(sc); 634 if (sc->memsize == 8192) 635 /* The last page is used as register aperture. */ 636 sc->memsize -= 4; 637 if(is_gx) 638 sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07; 639 else 640 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 641 642 /* XXX is there any way to calculate reference frequency from 643 known values? */ 644 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 645 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 646 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 647 aprint_normal_dev(sc->sc_dev, "ref_freq=29.498MHz\n"); 648 sc->ref_freq = 29498; 649 } else 650 sc->ref_freq = 14318; 651 652 reg = regr(sc, CLOCK_CNTL); 653 printf("CLOCK_CNTL: %08x\n", reg); 654 sc->sc_clock = reg & 3; 655 printf("using clock %d\n", sc->sc_clock); 656 657 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 658 printf("ref_div: %d\n", sc->ref_div); 659 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 660 printf("mclk_fb_div: %d\n", sc->mclk_fb_div); 661 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 662 (sc->ref_div * 2); 663 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 664 (sc->mem_freq * sc->ref_div); 665 sc->ramdac_freq = mach64_get_max_ramdac(sc); 666 aprint_normal_dev(sc->sc_dev, 667 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 668 (u_long)sc->memsize, 669 memtype_names[sc->memtype], 670 sc->mem_freq / 1000, sc->mem_freq % 1000, 671 sc->ramdac_freq / 1000); 672 673 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 674 switch(mach64_chip_id) { 675 case PCI_PRODUCT_ATI_MACH64_GX: 676 expected_id = 0x00d7; 677 break; 678 case PCI_PRODUCT_ATI_MACH64_CX: 679 expected_id = 0x0057; 680 break; 681 default: 682 /* Most chip IDs match their PCI product ID. */ 683 expected_id = mach64_chip_id; 684 } 685 686 if (id != expected_id) { 687 aprint_error_dev(sc->sc_dev, 688 "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id); 689 return; 690 } 691 692 sc->sc_console = mach64_is_console(sc); 693 #ifdef DIAGNOSTIC 694 aprint_normal("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 695 #endif 696 #if defined(__sparc__) || defined(__powerpc__) 697 if (sc->sc_console) { 698 if (mode != NULL) { 699 memcpy(&default_mode, mode, sizeof(struct videomode)); 700 setmode = 1; 701 } else { 702 mach64_get_mode(sc, &default_mode); 703 setmode = 0; 704 } 705 sc->sc_my_mode = &default_mode; 706 } else { 707 /* fill in default_mode if it's empty */ 708 mach64_get_mode(sc, &default_mode); 709 if (default_mode.dot_clock == 0) { 710 memcpy(&default_mode, &mach64_modes[4], 711 sizeof(default_mode)); 712 } 713 sc->sc_my_mode = &default_mode; 714 setmode = 1; 715 } 716 #else 717 if (default_mode.dot_clock == 0) { 718 memcpy(&default_mode, &mach64_modes[0], 719 sizeof(default_mode)); 720 } 721 sc->sc_my_mode = &mach64_modes[0]; 722 setmode = 1; 723 #endif 724 725 sc->bits_per_pixel = 8; 726 sc->virt_x = sc->sc_my_mode->hdisplay; 727 sc->virt_y = sc->sc_my_mode->vdisplay; 728 sc->max_x = sc->virt_x - 1; 729 sc->max_y = (sc->memsize * 1024) / 730 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 731 732 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 733 734 mach64_init_engine(sc); 735 736 if (setmode) 737 mach64_modeswitch(sc, sc->sc_my_mode); 738 739 aprint_normal_dev(sc->sc_dev, 740 "initial resolution %dx%d at %d bpp\n", 741 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 742 sc->bits_per_pixel); 743 744 #ifdef __sparc__ 745 machfb_fbattach(sc); 746 #endif 747 748 wsfont_init(); 749 750 sc->sc_bg = WS_DEFAULT_BG; 751 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &sc->sc_accessops); 752 sc->vd.init_screen = mach64_init_screen; 753 754 mach64_init_lut(sc); 755 mach64_clearscreen(sc); 756 machfb_blank(sc, 0); /* unblank the screen */ 757 758 if (sc->sc_console) { 759 760 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 761 &defattr); 762 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 763 764 ri = &mach64_console_screen.scr_ri; 765 mach64_defaultscreen.textops = &ri->ri_ops; 766 mach64_defaultscreen.capabilities = ri->ri_caps; 767 mach64_defaultscreen.nrows = ri->ri_rows; 768 mach64_defaultscreen.ncols = ri->ri_cols; 769 770 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 771 vcons_replay_msgbuf(&mach64_console_screen); 772 } else { 773 /* 774 * since we're not the console we can postpone the rest 775 * until someone actually allocates a screen for us 776 */ 777 mach64_modeswitch(sc, sc->sc_my_mode); 778 } 779 780 aa.console = sc->sc_console; 781 aa.scrdata = &mach64_screenlist; 782 aa.accessops = &sc->sc_accessops; 783 aa.accesscookie = &sc->vd; 784 785 config_found(self, &aa, wsemuldisplaydevprint); 786 787 config_found_ia(self, "drm", aux, machfb_drm_print); 788 } 789 790 static int 791 machfb_drm_print(void *aux, const char *pnp) 792 { 793 if (pnp) 794 aprint_normal("direct rendering for %s", pnp); 795 return (UNSUPP); 796 } 797 798 static void 799 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 800 long *defattr) 801 { 802 struct mach64_softc *sc = cookie; 803 struct rasops_info *ri = &scr->scr_ri; 804 805 /* XXX for now */ 806 #define setmode 0 807 808 ri->ri_depth = sc->bits_per_pixel; 809 ri->ri_width = sc->sc_my_mode->hdisplay; 810 ri->ri_height = sc->sc_my_mode->vdisplay; 811 ri->ri_stride = ri->ri_width; 812 ri->ri_flg = RI_CENTER; 813 set_address(ri, sc->sc_aperture); 814 815 #ifdef VCONS_DRAW_INTR 816 scr->scr_flags |= VCONS_DONT_READ; 817 #endif 818 819 if (existing) { 820 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 821 panic("%s: failed to switch video mode", 822 device_xname(sc->sc_dev)); 823 } 824 } 825 826 rasops_init(ri, sc->sc_my_mode->vdisplay / 8, 827 sc->sc_my_mode->hdisplay / 8); 828 ri->ri_caps = WSSCREEN_WSCOLORS; 829 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 830 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 831 832 /* enable acceleration */ 833 ri->ri_hw = scr; 834 ri->ri_ops.copyrows = mach64_copyrows; 835 ri->ri_ops.copycols = mach64_copycols; 836 ri->ri_ops.eraserows = mach64_eraserows; 837 ri->ri_ops.erasecols = mach64_erasecols; 838 ri->ri_ops.cursor = mach64_cursor; 839 ri->ri_ops.putchar = mach64_putchar; 840 } 841 842 static void 843 mach64_init(struct mach64_softc *sc) 844 { 845 uint32_t *p32, saved_value; 846 uint8_t *p; 847 int need_swap; 848 849 /* 850 * Test whether the aperture is byte swapped or not 851 */ 852 p32 = (uint32_t*)sc->sc_aperture; 853 saved_value = *p32; 854 p = (uint8_t*)(u_long)sc->sc_aperture; 855 *p32 = 0x12345678; 856 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 857 need_swap = 0; 858 else 859 need_swap = 1; 860 if (need_swap) { 861 sc->sc_aperture = (char *)sc->sc_aperture + 0x800000; 862 #if 0 863 /* what the fsck is this for? */ 864 sc->sc_aperbase += 0x800000; 865 sc->sc_apersize -= 0x800000; 866 #endif 867 } 868 *p32 = saved_value; 869 870 sc->sc_blanked = 0; 871 } 872 873 static int 874 mach64_get_memsize(struct mach64_softc *sc) 875 { 876 int tmp, memsize; 877 int mem_tab[] = { 878 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 879 }; 880 tmp = regr(sc, MEM_CNTL); 881 #ifdef DIAGNOSTIC 882 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 883 #endif 884 if (sc->has_dsp) { 885 tmp &= 0x0000000f; 886 if (tmp < 8) 887 memsize = (tmp + 1) * 512; 888 else if (tmp < 12) 889 memsize = (tmp - 3) * 1024; 890 else 891 memsize = (tmp - 7) * 2048; 892 } else { 893 memsize = mem_tab[tmp & 0x07]; 894 } 895 896 return memsize; 897 } 898 899 static int 900 mach64_get_max_ramdac(struct mach64_softc *sc) 901 { 902 int i; 903 904 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 905 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 906 (mach64_chip_rev & 0x07)) 907 return 170000; 908 909 for (i = 0; i < __arraycount(mach64_info); i++) 910 if (mach64_chip_id == mach64_info[i].chip_id) 911 return mach64_info[i].ramdac_freq; 912 913 if (sc->bits_per_pixel == 8) 914 return 135000; 915 else 916 return 80000; 917 } 918 919 #if defined(__sparc__) || defined(__powerpc__) 920 static void 921 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 922 { 923 struct mach64_crtcregs crtc; 924 925 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 926 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 927 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 928 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 929 930 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 931 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 932 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 933 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 934 mode->hsync_start; 935 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 936 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 937 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 938 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 939 940 #ifdef MACHFB_DEBUG 941 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 942 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 943 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 944 #endif 945 } 946 #endif 947 948 static int 949 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 950 struct videomode *mode) 951 { 952 953 if (mode->dot_clock > sc->ramdac_freq) 954 /* Clock too high. */ 955 return 1; 956 957 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 958 ((mode->htotal >> 3) - 1); 959 crtc->h_sync_strt_wid = 960 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 961 ((mode->hsync_start >> 3) - 1); 962 963 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 964 (mode->vtotal - 1); 965 crtc->v_sync_strt_wid = 966 ((mode->vsync_end - mode->vsync_start) << 16) | 967 (mode->vsync_start - 1); 968 969 if (mode->flags & VID_NVSYNC) 970 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 971 972 switch (sc->bits_per_pixel) { 973 case 8: 974 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 975 break; 976 case 16: 977 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 978 break; 979 case 32: 980 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 981 break; 982 } 983 984 crtc->gen_cntl = 0; 985 if (mode->flags & VID_INTERLACE) 986 crtc->gen_cntl |= CRTC_INTERLACE_EN; 987 988 if (mode->flags & VID_CSYNC) 989 crtc->gen_cntl |= CRTC_CSYNC_EN; 990 991 crtc->dot_clock = mode->dot_clock; 992 993 return 0; 994 } 995 996 static void 997 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 998 { 999 1000 mach64_set_pll(sc, crtc->dot_clock); 1001 1002 if (sc->has_dsp) 1003 mach64_set_dsp(sc); 1004 #if 1 1005 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 1006 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1007 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 1008 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1009 1010 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 1011 1012 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1013 1014 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 1015 /* XXX this unconditionally enables composite sync on SPARC */ 1016 #ifdef __sparc__ 1017 CRTC_CSYNC_EN | 1018 #endif 1019 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 1020 #endif 1021 } 1022 1023 static int 1024 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 1025 { 1026 struct mach64_crtcregs crtc; 1027 1028 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 1029 1030 if (mach64_calc_crtcregs(sc, &crtc, mode)) 1031 return 1; 1032 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 1033 if (crtc.dot_clock == 0) { 1034 aprint_error("%s: preposterous dot clock (%d)\n", 1035 device_xname(sc->sc_dev), crtc.dot_clock); 1036 return 1; 1037 } 1038 mach64_set_crtcregs(sc, &crtc); 1039 return 0; 1040 } 1041 1042 static void 1043 mach64_reset_engine(struct mach64_softc *sc) 1044 { 1045 1046 /* Reset engine.*/ 1047 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1048 1049 /* Enable engine. */ 1050 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1051 1052 /* Ensure engine is not locked up by clearing any FIFO or 1053 host errors. */ 1054 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1055 BUS_FIFO_ERR_ACK); 1056 } 1057 1058 static void 1059 mach64_init_engine(struct mach64_softc *sc) 1060 { 1061 uint32_t pitch_value; 1062 1063 pitch_value = sc->virt_x; 1064 1065 if (sc->bits_per_pixel == 24) 1066 pitch_value *= 3; 1067 1068 mach64_reset_engine(sc); 1069 1070 wait_for_fifo(sc, 14); 1071 1072 regw(sc, CONTEXT_MASK, 0xffffffff); 1073 1074 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 1075 1076 /* make sure the visible area starts where we're going to draw */ 1077 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1078 1079 regw(sc, DST_Y_X, 0); 1080 regw(sc, DST_HEIGHT, 0); 1081 regw(sc, DST_BRES_ERR, 0); 1082 regw(sc, DST_BRES_INC, 0); 1083 regw(sc, DST_BRES_DEC, 0); 1084 1085 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1086 DST_Y_TOP_TO_BOTTOM); 1087 1088 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 1089 1090 regw(sc, SRC_Y_X, 0); 1091 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1092 regw(sc, SRC_Y_X_START, 0); 1093 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1094 1095 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1096 1097 wait_for_fifo(sc, 13); 1098 regw(sc, HOST_CNTL, 0); 1099 1100 regw(sc, PAT_REG0, 0); 1101 regw(sc, PAT_REG1, 0); 1102 regw(sc, PAT_CNTL, 0); 1103 1104 regw(sc, SC_LEFT, 0); 1105 regw(sc, SC_TOP, 0); 1106 regw(sc, SC_BOTTOM, sc->sc_my_mode->vdisplay - 1); 1107 regw(sc, SC_RIGHT, pitch_value - 1); 1108 1109 regw(sc, DP_BKGD_CLR, WS_DEFAULT_BG); 1110 regw(sc, DP_FRGD_CLR, WS_DEFAULT_FG); 1111 regw(sc, DP_WRITE_MASK, 0xffffffff); 1112 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1113 1114 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1115 1116 wait_for_fifo(sc, 3); 1117 regw(sc, CLR_CMP_CLR, 0); 1118 regw(sc, CLR_CMP_MASK, 0xffffffff); 1119 regw(sc, CLR_CMP_CNTL, 0); 1120 1121 wait_for_fifo(sc, 2); 1122 switch (sc->bits_per_pixel) { 1123 case 8: 1124 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP); 1125 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1126 /* We want 8 bit per channel */ 1127 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1128 break; 1129 case 32: 1130 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP); 1131 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1132 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1133 break; 1134 } 1135 1136 wait_for_fifo(sc, 5); 1137 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1138 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1139 1140 wait_for_idle(sc); 1141 } 1142 1143 #if 0 1144 static void 1145 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1146 { 1147 int offset; 1148 1149 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1150 1151 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1152 offset); 1153 } 1154 #endif 1155 1156 static void 1157 mach64_set_dsp(struct mach64_softc *sc) 1158 { 1159 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1160 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1161 uint32_t xclks_per_qw, y; 1162 uint32_t fifo_off, fifo_on; 1163 1164 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1165 1166 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1167 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1168 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1169 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1170 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1171 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1172 dsp_loop_latency = 0; 1173 fifo_depth = 24; 1174 } else { 1175 dsp_loop_latency = 2; 1176 fifo_depth = 32; 1177 } 1178 1179 dsp_precision = 0; 1180 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1181 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1182 y = (xclks_per_qw * fifo_depth) >> 11; 1183 while (y) { 1184 y >>= 1; 1185 dsp_precision++; 1186 } 1187 dsp_precision -= 5; 1188 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1189 1190 switch (sc->memtype) { 1191 case DRAM: 1192 case EDO_DRAM: 1193 case PSEUDO_EDO: 1194 if (sc->memsize > 1024) { 1195 page_size = 9; 1196 dsp_loop_latency += 6; 1197 } else { 1198 page_size = 10; 1199 if (sc->memtype == DRAM) 1200 dsp_loop_latency += 8; 1201 else 1202 dsp_loop_latency += 7; 1203 } 1204 break; 1205 case SDRAM: 1206 case SGRAM: 1207 if (sc->memsize > 1024) { 1208 page_size = 8; 1209 dsp_loop_latency += 8; 1210 } else { 1211 page_size = 10; 1212 dsp_loop_latency += 9; 1213 } 1214 break; 1215 default: 1216 page_size = 10; 1217 dsp_loop_latency += 9; 1218 break; 1219 } 1220 1221 if (xclks_per_qw >= (page_size << 11)) 1222 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1223 else 1224 fifo_on = (3 * page_size + 2) << 6; 1225 1226 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1227 dsp_on = fifo_on >> dsp_precision; 1228 dsp_off = fifo_off >> dsp_precision; 1229 1230 #ifdef MACHFB_DEBUG 1231 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1232 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1233 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1234 "mclk_post_div = %d, vclk_post_div = %d\n", 1235 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1236 sc->mclk_fb_div, sc->vclk_fb_div, 1237 sc->mclk_post_div, sc->vclk_post_div); 1238 #endif 1239 1240 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1241 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1242 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1243 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1244 } 1245 1246 static void 1247 mach64_set_pll(struct mach64_softc *sc, int clock) 1248 { 1249 uint32_t q, clockreg; 1250 int clockshift = sc->sc_clock << 1; 1251 uint8_t reg, vclk_ctl; 1252 1253 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1254 #ifdef MACHFB_DEBUG 1255 printf("q = %d\n", q); 1256 #endif 1257 if (q > 25500) { 1258 printf("Warning: q > 25500\n"); 1259 q = 25500; 1260 sc->vclk_post_div = 1; 1261 sc->log2_vclk_post_div = 0; 1262 } else if (q > 12750) { 1263 sc->vclk_post_div = 1; 1264 sc->log2_vclk_post_div = 0; 1265 } else if (q > 6350) { 1266 sc->vclk_post_div = 2; 1267 sc->log2_vclk_post_div = 1; 1268 } else if (q > 3150) { 1269 sc->vclk_post_div = 4; 1270 sc->log2_vclk_post_div = 2; 1271 } else if (q >= 1600) { 1272 sc->vclk_post_div = 8; 1273 sc->log2_vclk_post_div = 3; 1274 } else { 1275 printf("Warning: q < 1600\n"); 1276 sc->vclk_post_div = 8; 1277 sc->log2_vclk_post_div = 3; 1278 } 1279 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1280 printf("post_div: %d log2_post_div: %d mclk_div: %d\n", sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1281 1282 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1283 printf("vclk_ctl: %02x\n", vclk_ctl); 1284 vclk_ctl |= PLL_VCLK_RESET; 1285 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1286 1287 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1288 reg = regrb_pll(sc, VCLK_POST_DIV); 1289 reg &= ~(3 << clockshift); 1290 reg |= (sc->log2_vclk_post_div << clockshift); 1291 regwb_pll(sc, VCLK_POST_DIV, reg); 1292 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1293 1294 vclk_ctl &= ~PLL_VCLK_RESET; 1295 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1296 1297 clockreg = regr(sc, CLOCK_CNTL); 1298 clockreg &= ~CLOCK_SEL; 1299 clockreg |= sc->sc_clock | CLOCK_STROBE; 1300 regw(sc, CLOCK_CNTL, clockreg); 1301 } 1302 1303 static void 1304 mach64_init_lut(struct mach64_softc *sc) 1305 { 1306 int i, idx; 1307 1308 idx = 0; 1309 for (i = 0; i < 256; i++) { 1310 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1], 1311 rasops_cmap[idx + 2]); 1312 idx += 3; 1313 } 1314 } 1315 1316 static int 1317 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1318 uint8_t b) 1319 { 1320 sc->sc_cmap_red[index] = r; 1321 sc->sc_cmap_green[index] = g; 1322 sc->sc_cmap_blue[index] = b; 1323 /* 1324 * writing the dac index takes a while, in theory we can poll some 1325 * register to see when it's ready - but we better avoid writing it 1326 * unnecessarily 1327 */ 1328 if (index != sc->sc_dacw) { 1329 regwb(sc, DAC_MASK, 0xff); 1330 regwb(sc, DAC_WINDEX, index); 1331 } 1332 sc->sc_dacw = index + 1; 1333 regwb(sc, DAC_DATA, r); 1334 regwb(sc, DAC_DATA, g); 1335 regwb(sc, DAC_DATA, b); 1336 return 0; 1337 } 1338 1339 static int 1340 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1341 { 1342 uint index = cm->index; 1343 uint count = cm->count; 1344 int i, error; 1345 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1346 uint8_t *r, *g, *b; 1347 1348 if (cm->index >= 256 || cm->count > 256 || 1349 (cm->index + cm->count) > 256) 1350 return EINVAL; 1351 error = copyin(cm->red, &rbuf[index], count); 1352 if (error) 1353 return error; 1354 error = copyin(cm->green, &gbuf[index], count); 1355 if (error) 1356 return error; 1357 error = copyin(cm->blue, &bbuf[index], count); 1358 if (error) 1359 return error; 1360 1361 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1362 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1363 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1364 1365 r = &sc->sc_cmap_red[index]; 1366 g = &sc->sc_cmap_green[index]; 1367 b = &sc->sc_cmap_blue[index]; 1368 1369 for (i = 0; i < count; i++) { 1370 mach64_putpalreg(sc, index, *r, *g, *b); 1371 index++; 1372 r++, g++, b++; 1373 } 1374 return 0; 1375 } 1376 1377 static int 1378 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1379 { 1380 u_int index = cm->index; 1381 u_int count = cm->count; 1382 int error; 1383 1384 if (index >= 255 || count > 256 || index + count > 256) 1385 return EINVAL; 1386 1387 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1388 if (error) 1389 return error; 1390 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1391 if (error) 1392 return error; 1393 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1394 if (error) 1395 return error; 1396 1397 return 0; 1398 } 1399 1400 static int 1401 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1402 { 1403 struct mach64_crtcregs regs; 1404 1405 if (mach64_calc_crtcregs(sc, ®s, 1406 (struct videomode *)des->modecookie)) 1407 return 1; 1408 1409 mach64_set_crtcregs(sc, ®s); 1410 return 0; 1411 } 1412 1413 static int 1414 mach64_is_console(struct mach64_softc *sc) 1415 { 1416 bool console = 0; 1417 1418 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1419 "is_console", &console); 1420 return console; 1421 } 1422 1423 /* 1424 * wsdisplay_emulops 1425 */ 1426 1427 static void 1428 mach64_cursor(void *cookie, int on, int row, int col) 1429 { 1430 struct rasops_info *ri = cookie; 1431 struct vcons_screen *scr = ri->ri_hw; 1432 struct mach64_softc *sc = scr->scr_cookie; 1433 int x, y, wi, he; 1434 1435 wi = ri->ri_font->fontwidth; 1436 he = ri->ri_font->fontheight; 1437 1438 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1439 x = ri->ri_ccol * wi + ri->ri_xorigin; 1440 y = ri->ri_crow * he + ri->ri_yorigin; 1441 if (ri->ri_flg & RI_CURSOR) { 1442 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1443 0xff); 1444 ri->ri_flg &= ~RI_CURSOR; 1445 } 1446 ri->ri_crow = row; 1447 ri->ri_ccol = col; 1448 if (on) { 1449 x = ri->ri_ccol * wi + ri->ri_xorigin; 1450 y = ri->ri_crow * he + ri->ri_yorigin; 1451 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1452 0xff); 1453 ri->ri_flg |= RI_CURSOR; 1454 } 1455 } else { 1456 scr->scr_ri.ri_crow = row; 1457 scr->scr_ri.ri_ccol = col; 1458 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1459 } 1460 } 1461 1462 #if 0 1463 static int 1464 mach64_mapchar(void *cookie, int uni, u_int *index) 1465 { 1466 return 0; 1467 } 1468 #endif 1469 1470 static void 1471 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1472 { 1473 struct rasops_info *ri = cookie; 1474 struct wsdisplay_font *font = PICK_FONT(ri, c); 1475 struct vcons_screen *scr = ri->ri_hw; 1476 struct mach64_softc *sc = scr->scr_cookie; 1477 1478 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1479 int fg, bg, uc; 1480 uint8_t *data; 1481 int x, y, wi, he; 1482 wi = font->fontwidth; 1483 he = font->fontheight; 1484 1485 if (!CHAR_IN_FONT(c, font)) 1486 return; 1487 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1488 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f]; 1489 x = ri->ri_xorigin + col * wi; 1490 y = ri->ri_yorigin + row * he; 1491 if (c == 0x20) { 1492 mach64_rectfill(sc, x, y, wi, he, bg); 1493 } else { 1494 uc = c - font->firstchar; 1495 data = (uint8_t *)font->data + uc * 1496 ri->ri_fontscale; 1497 1498 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1499 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1500 } 1501 } 1502 } 1503 1504 1505 static void 1506 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1507 { 1508 struct rasops_info *ri = cookie; 1509 struct vcons_screen *scr = ri->ri_hw; 1510 struct mach64_softc *sc = scr->scr_cookie; 1511 int32_t xs, xd, y, width, height; 1512 1513 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1514 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1515 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1516 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1517 width = ri->ri_font->fontwidth * ncols; 1518 height = ri->ri_font->fontheight; 1519 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff); 1520 } 1521 } 1522 1523 static void 1524 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1525 { 1526 struct rasops_info *ri = cookie; 1527 struct vcons_screen *scr = ri->ri_hw; 1528 struct mach64_softc *sc = scr->scr_cookie; 1529 int32_t x, y, width, height, fg, bg, ul; 1530 1531 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1532 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1533 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1534 width = ri->ri_font->fontwidth * ncols; 1535 height = ri->ri_font->fontheight; 1536 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1537 1538 mach64_rectfill(sc, x, y, width, height, bg); 1539 } 1540 } 1541 1542 static void 1543 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1544 { 1545 struct rasops_info *ri = cookie; 1546 struct vcons_screen *scr = ri->ri_hw; 1547 struct mach64_softc *sc = scr->scr_cookie; 1548 int32_t x, ys, yd, width, height; 1549 1550 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1551 x = ri->ri_xorigin; 1552 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1553 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1554 width = ri->ri_emuwidth; 1555 height = ri->ri_font->fontheight*nrows; 1556 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff); 1557 } 1558 } 1559 1560 static void 1561 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1562 { 1563 struct rasops_info *ri = cookie; 1564 struct vcons_screen *scr = ri->ri_hw; 1565 struct mach64_softc *sc = scr->scr_cookie; 1566 int32_t x, y, width, height, fg, bg, ul; 1567 1568 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1569 x = ri->ri_xorigin; 1570 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1571 width = ri->ri_emuwidth; 1572 height = ri->ri_font->fontheight * nrows; 1573 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1574 1575 mach64_rectfill(sc, x, y, width, height, bg); 1576 } 1577 } 1578 1579 static void 1580 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1581 { 1582 uint32_t dest_ctl = 0; 1583 1584 wait_for_idle(sc); 1585 regw(sc, DP_WRITE_MASK, mask); /* XXX only good for 8 bit */ 1586 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1587 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1588 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1589 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1590 if (yd < ys) { 1591 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1592 } else { 1593 ys += height - 1; 1594 yd += height - 1; 1595 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1596 } 1597 if (xd < xs) { 1598 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1599 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1600 } else { 1601 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1602 xs += width - 1; 1603 xd += width - 1; 1604 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1605 } 1606 regw(sc, DST_CNTL, dest_ctl); 1607 1608 regw(sc, SRC_Y_X, (xs << 16) | ys); 1609 regw(sc, SRC_WIDTH1, width); 1610 regw(sc, DST_Y_X, (xd << 16) | yd); 1611 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1612 } 1613 1614 static void 1615 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1616 int height, uint32_t fg, uint32_t bg) 1617 { 1618 wait_for_idle(sc); 1619 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1620 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1621 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1622 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1623 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1624 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1625 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1626 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1627 regw(sc, DP_BKGD_CLR, bg); 1628 regw(sc, DP_FRGD_CLR, fg); 1629 regw(sc, SRC_Y_X, 0); 1630 regw(sc, SRC_WIDTH1, width); 1631 regw(sc, DST_Y_X, (xd << 16) | yd); 1632 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1633 /* now feed the data into the chip */ 1634 } 1635 1636 static void 1637 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1638 { 1639 int i; 1640 uint32_t latch = 0, bork; 1641 int shift = 0; 1642 int reg = 0; 1643 1644 for (i = 0; i < count; i++) { 1645 bork = data[i]; 1646 latch |= (bork << shift); 1647 if (shift == 24) { 1648 regw(sc, HOST_DATA0 + reg, latch); 1649 latch = 0; 1650 shift = 0; 1651 reg = (reg + 4) & 0x3c; 1652 } else 1653 shift += 8; 1654 } 1655 if (shift != 0) /* 24 */ 1656 regw(sc, HOST_DATA0 + reg, latch); 1657 } 1658 1659 1660 static void 1661 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1662 int colour) 1663 { 1664 wait_for_idle(sc); 1665 regw(sc, DP_WRITE_MASK, 0xff); 1666 regw(sc, DP_FRGD_CLR, colour); 1667 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1668 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1669 regw(sc, DP_MIX, MIX_SRC << 16); 1670 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1671 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1672 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1673 1674 regw(sc, SRC_Y_X, (x << 16) | y); 1675 regw(sc, SRC_WIDTH1, width); 1676 regw(sc, DST_Y_X, (x << 16) | y); 1677 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1678 } 1679 1680 static void 1681 mach64_clearscreen(struct mach64_softc *sc) 1682 { 1683 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1684 } 1685 1686 1687 #if 0 1688 static void 1689 mach64_showpal(struct mach64_softc *sc) 1690 { 1691 int i, x = 0; 1692 1693 for (i = 0; i < 16; i++) { 1694 mach64_rectfill(sc, x, 0, 64, 64, i); 1695 x += 64; 1696 } 1697 } 1698 #endif 1699 1700 /* 1701 * wsdisplay_accessops 1702 */ 1703 1704 static int 1705 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1706 struct lwp *l) 1707 { 1708 struct vcons_data *vd = v; 1709 struct mach64_softc *sc = vd->cookie; 1710 struct wsdisplay_fbinfo *wdf; 1711 struct vcons_screen *ms = vd->active; 1712 1713 switch (cmd) { 1714 case WSDISPLAYIO_GTYPE: 1715 /* XXX is this the right type to return? */ 1716 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1717 return 0; 1718 1719 case WSDISPLAYIO_LINEBYTES: 1720 *(u_int *)data = sc->virt_x * sc->bits_per_pixel / 8; 1721 return 0; 1722 1723 case WSDISPLAYIO_GINFO: 1724 wdf = (void *)data; 1725 wdf->height = sc->virt_y; 1726 wdf->width = sc->virt_x; 1727 wdf->depth = sc->bits_per_pixel; 1728 wdf->cmsize = 256; 1729 return 0; 1730 1731 case WSDISPLAYIO_GETCMAP: 1732 return mach64_getcmap(sc, 1733 (struct wsdisplay_cmap *)data); 1734 1735 case WSDISPLAYIO_PUTCMAP: 1736 return mach64_putcmap(sc, 1737 (struct wsdisplay_cmap *)data); 1738 1739 /* PCI config read/write passthrough. */ 1740 case PCI_IOC_CFGREAD: 1741 case PCI_IOC_CFGWRITE: 1742 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1743 cmd, data, flag, l); 1744 1745 case WSDISPLAYIO_GET_BUSID: 1746 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1747 sc->sc_pcitag, data); 1748 1749 case WSDISPLAYIO_SMODE: { 1750 int new_mode = *(int*)data; 1751 if (new_mode != sc->sc_mode) { 1752 sc->sc_mode = new_mode; 1753 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1754 && (ms != NULL)) 1755 { 1756 /* restore initial video mode */ 1757 mach64_init(sc); 1758 mach64_init_engine(sc); 1759 mach64_init_lut(sc); 1760 mach64_modeswitch(sc, sc->sc_my_mode); 1761 vcons_redraw_screen(ms); 1762 } 1763 } 1764 } 1765 return 0; 1766 case WSDISPLAYIO_GET_EDID: { 1767 struct wsdisplayio_edid_info *d = data; 1768 return wsdisplayio_get_edid(sc->sc_dev, d); 1769 } 1770 } 1771 return EPASSTHROUGH; 1772 } 1773 1774 static paddr_t 1775 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1776 { 1777 struct vcons_data *vd = v; 1778 struct mach64_softc *sc = vd->cookie; 1779 paddr_t pa; 1780 pcireg_t reg; 1781 1782 #ifndef __sparc64__ 1783 /* 1784 *'regular' framebuffer mmap()ing 1785 * disabled on sparc64 because some ATI firmware likes to map some PCI 1786 * resources to addresses that would collide with this ( like some Rage 1787 * IIc which uses 0x2000 for the 2nd register block ) 1788 * Other 64bit architectures might run into similar problems. 1789 */ 1790 if (offset<sc->sc_apersize) { 1791 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, offset, 1792 prot, BUS_SPACE_MAP_LINEAR); 1793 return pa; 1794 } 1795 #endif 1796 1797 /* 1798 * restrict all other mappings to processes with superuser privileges 1799 * or the kernel itself 1800 */ 1801 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1802 NULL) != 0) { 1803 return -1; 1804 } 1805 1806 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1807 if (reg != sc->sc_regphys) { 1808 #ifdef DIAGNOSTIC 1809 printf("%s: BAR 0x18 changed! (%x %x)\n", 1810 device_xname(sc->sc_dev), (uint32_t)sc->sc_regphys, 1811 (uint32_t)reg); 1812 #endif 1813 sc->sc_regphys = reg; 1814 } 1815 1816 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1817 if (reg != sc->sc_aperphys) { 1818 #ifdef DIAGNOSTIC 1819 printf("%s: BAR 0x10 changed! (%x %x)\n", 1820 device_xname(sc->sc_dev), (uint32_t)sc->sc_aperphys, 1821 (uint32_t)reg); 1822 #endif 1823 sc->sc_aperphys = reg; 1824 } 1825 1826 if ((offset >= sc->sc_aperphys) && 1827 (offset < (sc->sc_aperphys + sc->sc_apersize))) { 1828 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1829 BUS_SPACE_MAP_LINEAR); 1830 return pa; 1831 } 1832 1833 if ((offset >= sc->sc_regphys) && 1834 (offset < (sc->sc_regphys + sc->sc_regsize))) { 1835 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1836 BUS_SPACE_MAP_LINEAR); 1837 return pa; 1838 } 1839 1840 if ((offset >= sc->sc_rom.vb_base) && 1841 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 1842 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1843 BUS_SPACE_MAP_LINEAR); 1844 return pa; 1845 } 1846 1847 #ifdef PCI_MAGIC_IO_RANGE 1848 if ((offset >= PCI_MAGIC_IO_RANGE) && 1849 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 1850 return bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1851 0, prot, BUS_SPACE_MAP_LINEAR); 1852 } 1853 #endif 1854 1855 return -1; 1856 } 1857 1858 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1859 static void 1860 set_address(struct rasops_info *ri, void *fb) 1861 { 1862 #ifdef notdef 1863 printf(" %d %d %d\n", ri->ri_xorigin, ri->ri_yorigin, ri->ri_stride); 1864 #endif 1865 ri->ri_bits = (void *)((char *)fb + ri->ri_stride * ri->ri_yorigin + 1866 ri->ri_xorigin); 1867 } 1868 1869 #if 0 1870 static int 1871 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1872 { 1873 1874 return 0; 1875 } 1876 #endif 1877 1878 void 1879 machfb_blank(struct mach64_softc *sc, int blank) 1880 { 1881 uint32_t reg; 1882 1883 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1884 1885 switch (blank) 1886 { 1887 case 0: 1888 reg = regr(sc, CRTC_GEN_CNTL); 1889 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1890 sc->sc_blanked = 0; 1891 break; 1892 case 1: 1893 reg = regr(sc, CRTC_GEN_CNTL); 1894 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1895 sc->sc_blanked = 1; 1896 break; 1897 default: 1898 break; 1899 } 1900 } 1901 1902 /* framebuffer device support */ 1903 #ifdef __sparc__ 1904 1905 static void 1906 machfb_unblank(device_t dev) 1907 { 1908 struct mach64_softc *sc = device_private(dev); 1909 1910 machfb_blank(sc, 0); 1911 } 1912 1913 static void 1914 machfb_fbattach(struct mach64_softc *sc) 1915 { 1916 struct fbdevice *fb = &sc->sc_fb; 1917 1918 fb->fb_device = sc->sc_dev; 1919 fb->fb_driver = &machfb_fbdriver; 1920 1921 fb->fb_type.fb_cmsize = 256; 1922 fb->fb_type.fb_size = sc->memsize; 1923 1924 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 1925 fb->fb_flags = sc->sc_dev->dv_cfdata->cf_flags & FB_USERMASK; 1926 fb->fb_type.fb_depth = sc->bits_per_pixel; 1927 fb->fb_type.fb_width = sc->virt_x; 1928 fb->fb_type.fb_height = sc->virt_y; 1929 1930 fb->fb_pixels = sc->sc_aperture; 1931 fb_attach(fb, sc->sc_console); 1932 } 1933 1934 int 1935 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 1936 { 1937 struct mach64_softc *sc; 1938 1939 sc = device_lookup_private(&machfb_cd, minor(dev)); 1940 if (sc == NULL) 1941 return ENXIO; 1942 sc->sc_locked = 1; 1943 1944 #ifdef MACHFB_DEBUG 1945 printf("machfb_fbopen(%d)\n", minor(dev)); 1946 #endif 1947 return 0; 1948 } 1949 1950 int 1951 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 1952 { 1953 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1954 1955 #ifdef MACHFB_DEBUG 1956 printf("machfb_fbclose()\n"); 1957 #endif 1958 mach64_init_engine(sc); 1959 mach64_init_lut(sc); 1960 sc->sc_locked = 0; 1961 return 0; 1962 } 1963 1964 int 1965 machfb_fbioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1966 { 1967 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1968 1969 #ifdef MACHFB_DEBUG 1970 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 1971 #endif 1972 switch (cmd) { 1973 case FBIOGTYPE: 1974 *(struct fbtype *)data = sc->sc_fb.fb_type; 1975 break; 1976 1977 case FBIOGATTR: 1978 #define fba ((struct fbgattr *)data) 1979 fba->real_type = sc->sc_fb.fb_type.fb_type; 1980 fba->owner = 0; /* XXX ??? */ 1981 fba->fbtype = sc->sc_fb.fb_type; 1982 fba->sattr.flags = 0; 1983 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 1984 fba->sattr.dev_specific[0] = sc->sc_nbus; 1985 fba->sattr.dev_specific[1] = sc->sc_ndev; 1986 fba->sattr.dev_specific[2] = sc->sc_nfunc; 1987 fba->sattr.dev_specific[3] = -1; 1988 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 1989 fba->emu_types[1] = -1; 1990 #undef fba 1991 break; 1992 1993 #if 0 1994 case FBIOGETCMAP: 1995 #define p ((struct fbcmap *)data) 1996 return bt_getcmap(p, &sc->sc_cmap, 256, 1); 1997 1998 case FBIOPUTCMAP: 1999 /* copy to software map */ 2000 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 2001 if (error) 2002 return error; 2003 /* now blast them into the chip */ 2004 /* XXX should use retrace interrupt */ 2005 cg6_loadcmap(sc, p->index, p->count); 2006 #undef p 2007 break; 2008 #endif 2009 case FBIOGVIDEO: 2010 *(int *)data = sc->sc_blanked; 2011 break; 2012 2013 case FBIOSVIDEO: 2014 machfb_blank(sc, *(int *)data); 2015 break; 2016 2017 #if 0 2018 case FBIOGCURSOR: 2019 break; 2020 2021 case FBIOSCURSOR: 2022 break; 2023 2024 case FBIOGCURPOS: 2025 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 2026 break; 2027 2028 case FBIOSCURPOS: 2029 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 2030 break; 2031 2032 case FBIOGCURMAX: 2033 /* max cursor size is 32x32 */ 2034 ((struct fbcurpos *)data)->x = 32; 2035 ((struct fbcurpos *)data)->y = 32; 2036 break; 2037 #endif 2038 case PCI_IOC_CFGREAD: 2039 case PCI_IOC_CFGWRITE: { 2040 int ret; 2041 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 2042 cmd, data, flags, l); 2043 2044 #ifdef MACHFB_DEBUG 2045 printf("pci_devioctl: %d\n", ret); 2046 #endif 2047 return ret; 2048 } 2049 2050 case WSDISPLAYIO_GET_BUSID: 2051 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 2052 sc->sc_pcitag, data); 2053 2054 default: 2055 return ENOTTY; 2056 } 2057 #ifdef MACHFB_DEBUG 2058 printf("machfb_fbioctl done\n"); 2059 #endif 2060 return 0; 2061 } 2062 2063 paddr_t 2064 machfb_fbmmap(dev_t dev, off_t off, int prot) 2065 { 2066 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 2067 2068 if (sc != NULL) 2069 return mach64_mmap(&sc->vd, NULL, off, prot); 2070 2071 return 0; 2072 } 2073 2074 #endif /* __sparc__ */ 2075
Indexes created Thu Oct 02 14:10:14 GMT 2025