machfb.c revision 1.72
1 /* $NetBSD: machfb.c,v 1.72 2012/01/11 16:02:29 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.72 2012/01/11 16:02:29 macallan Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #ifdef __sparc__ 58 #include <dev/sun/fbio.h> 59 #include <dev/sun/fbvar.h> 60 #include <sys/conf.h> 61 #else 62 #include <dev/wscons/wsdisplayvar.h> 63 #endif 64 65 #include <dev/wscons/wsconsio.h> 66 #include <dev/wsfont/wsfont.h> 67 #include <dev/rasops/rasops.h> 68 #include <dev/pci/wsdisplay_pci.h> 69 70 #include <dev/wscons/wsdisplay_vconsvar.h> 71 72 #include "opt_wsemul.h" 73 #include "opt_machfb.h" 74 75 #define MACH64_REG_SIZE 1024 76 #define MACH64_REG_OFF 0x7ffc00 77 78 #define NBARS 3 /* number of Mach64 PCI BARs */ 79 80 struct vga_bar { 81 bus_addr_t vb_base; 82 pcireg_t vb_busaddr; 83 bus_size_t vb_size; 84 pcireg_t vb_type; 85 int vb_flags; 86 }; 87 88 struct mach64_softc { 89 device_t sc_dev; 90 #ifdef __sparc__ 91 struct fbdevice sc_fb; 92 #endif 93 pci_chipset_tag_t sc_pc; 94 pcitag_t sc_pcitag; 95 96 struct vga_bar sc_bars[NBARS]; 97 struct vga_bar sc_rom; 98 99 #define sc_aperbase sc_bars[0].vb_base 100 #define sc_apersize sc_bars[0].vb_size 101 #define sc_aperphys sc_bars[0].vb_busaddr 102 103 #define sc_iobase sc_bars[1].vb_base 104 #define sc_iosize sc_bars[1].vb_size 105 106 #define sc_regbase sc_bars[2].vb_base 107 #define sc_regsize sc_bars[2].vb_size 108 #define sc_regphys sc_bars[2].vb_busaddr 109 110 bus_space_tag_t sc_regt; 111 bus_space_tag_t sc_memt; 112 bus_space_tag_t sc_iot; 113 bus_space_handle_t sc_regh; 114 bus_space_handle_t sc_memh; 115 void *sc_aperture; /* mapped aperture vaddr */ 116 void *sc_registers; /* mapped registers vaddr */ 117 118 uint32_t sc_nbus, sc_ndev, sc_nfunc; 119 size_t memsize; 120 int memtype; 121 122 int sc_mode; 123 int sc_bg; 124 int sc_locked; 125 126 int has_dsp; 127 int bits_per_pixel; 128 int max_x; 129 int max_y; 130 int virt_x; 131 int virt_y; 132 int color_depth; 133 134 int mem_freq; 135 int ramdac_freq; 136 int ref_freq; 137 138 int ref_div; 139 int log2_vclk_post_div; 140 int vclk_post_div; 141 int vclk_fb_div; 142 int mclk_post_div; 143 int mclk_fb_div; 144 int sc_clock; /* which clock to use */ 145 146 struct videomode *sc_my_mode; 147 int sc_edid_size; 148 uint8_t sc_edid_data[1024]; 149 150 u_char sc_cmap_red[256]; 151 u_char sc_cmap_green[256]; 152 u_char sc_cmap_blue[256]; 153 int sc_dacw, sc_blanked, sc_console; 154 struct vcons_data vd; 155 struct wsdisplay_accessops sc_accessops; 156 }; 157 158 struct mach64_crtcregs { 159 uint32_t h_total_disp; 160 uint32_t h_sync_strt_wid; 161 uint32_t v_total_disp; 162 uint32_t v_sync_strt_wid; 163 uint32_t gen_cntl; 164 uint32_t clock_cntl; 165 uint32_t color_depth; 166 uint32_t dot_clock; 167 }; 168 169 static struct { 170 uint16_t chip_id; 171 uint32_t ramdac_freq; 172 } const mach64_info[] = { 173 { PCI_PRODUCT_ATI_MACH64_GX, 135000 }, 174 { PCI_PRODUCT_ATI_MACH64_CX, 135000 }, 175 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 176 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 185 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 186 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 189 #if 0 190 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 192 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 193 #endif 194 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 195 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 196 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 197 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 198 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 199 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 200 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 201 }; 202 203 static int mach64_chip_id, mach64_chip_rev; 204 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 205 206 static const char *mach64_gx_memtype_names[] = { 207 "DRAM", "VRAM", "VRAM", "DRAM", 208 "DRAM", "VRAM", "VRAM", "(unknown type)" 209 }; 210 211 static const char *mach64_memtype_names[] = { 212 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 213 "(unknown type)" 214 }; 215 216 static struct videomode mach64_modes[] = { 217 /* 640x400 @ 70 Hz, 31.5 kHz */ 218 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0, NULL, }, 219 /* 640x480 @ 72 Hz, 36.5 kHz */ 220 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0, NULL, }, 221 /* 800x600 @ 72 Hz, 48.0 kHz */ 222 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 223 VID_PHSYNC | VID_PVSYNC, NULL, }, 224 /* 1024x768 @ 70 Hz, 56.5 kHz */ 225 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 226 VID_NHSYNC | VID_NVSYNC, NULL, }, 227 /* 1152x864 @ 70 Hz, 62.4 kHz */ 228 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0, NULL, }, 229 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 230 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 231 VID_NHSYNC | VID_NVSYNC, NULL, } 232 }; 233 234 extern const u_char rasops_cmap[768]; 235 236 static int mach64_match(device_t, cfdata_t, void *); 237 static void mach64_attach(device_t, device_t, void *); 238 239 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 240 NULL, NULL); 241 242 static void mach64_init(struct mach64_softc *); 243 static int mach64_get_memsize(struct mach64_softc *); 244 static int mach64_get_max_ramdac(struct mach64_softc *); 245 246 #if defined(__sparc__) || defined(__powerpc__) 247 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 248 #endif 249 250 static int mach64_calc_crtcregs(struct mach64_softc *, 251 struct mach64_crtcregs *, 252 struct videomode *); 253 static void mach64_set_crtcregs(struct mach64_softc *, 254 struct mach64_crtcregs *); 255 256 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 257 static void mach64_set_dsp(struct mach64_softc *); 258 static void mach64_set_pll(struct mach64_softc *, int); 259 static void mach64_reset_engine(struct mach64_softc *); 260 static void mach64_init_engine(struct mach64_softc *); 261 #if 0 262 static void mach64_adjust_frame(struct mach64_softc *, int, int); 263 #endif 264 static void mach64_init_lut(struct mach64_softc *); 265 266 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 267 static int mach64_set_screentype(struct mach64_softc *, 268 const struct wsscreen_descr *); 269 static int mach64_is_console(struct mach64_softc *); 270 271 static void mach64_cursor(void *, int, int, int); 272 #if 0 273 static int mach64_mapchar(void *, int, u_int *); 274 #endif 275 static void mach64_putchar(void *, int, int, u_int, long); 276 static void mach64_copycols(void *, int, int, int, int); 277 static void mach64_erasecols(void *, int, int, int, long); 278 static void mach64_copyrows(void *, int, int, int); 279 static void mach64_eraserows(void *, int, int, long); 280 static void mach64_clearscreen(struct mach64_softc *); 281 282 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 283 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 284 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 285 uint8_t, uint8_t); 286 static void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, 287 int, int, int) ; 288 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 289 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 290 uint32_t, uint32_t); 291 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 292 #if 0 293 static void mach64_showpal(struct mach64_softc *); 294 #endif 295 296 static void set_address(struct rasops_info *, void *); 297 static void machfb_blank(struct mach64_softc *, int); 298 static int machfb_drm_print(void *, const char *); 299 300 static struct wsscreen_descr mach64_defaultscreen = { 301 "default", 302 80, 30, 303 NULL, 304 8, 16, 305 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 306 &default_mode 307 }, mach64_80x25_screen = { 308 "80x25", 80, 25, 309 NULL, 310 8, 16, 311 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 312 &mach64_modes[0] 313 }, mach64_80x30_screen = { 314 "80x30", 80, 30, 315 NULL, 316 8, 16, 317 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 318 &mach64_modes[1] 319 }, mach64_80x40_screen = { 320 "80x40", 80, 40, 321 NULL, 322 8, 10, 323 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 324 &mach64_modes[0] 325 }, mach64_80x50_screen = { 326 "80x50", 80, 50, 327 NULL, 328 8, 8, 329 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 330 &mach64_modes[0] 331 }, mach64_100x37_screen = { 332 "100x37", 100, 37, 333 NULL, 334 8, 16, 335 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 336 &mach64_modes[2] 337 }, mach64_128x48_screen = { 338 "128x48", 128, 48, 339 NULL, 340 8, 16, 341 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 342 &mach64_modes[3] 343 }, mach64_144x54_screen = { 344 "144x54", 144, 54, 345 NULL, 346 8, 16, 347 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 348 &mach64_modes[4] 349 }, mach64_160x64_screen = { 350 "160x54", 160, 64, 351 NULL, 352 8, 16, 353 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 354 &mach64_modes[5] 355 }; 356 357 static const struct wsscreen_descr *_mach64_scrlist[] = { 358 &mach64_defaultscreen, 359 &mach64_80x25_screen, 360 &mach64_80x30_screen, 361 &mach64_80x40_screen, 362 &mach64_80x50_screen, 363 &mach64_100x37_screen, 364 &mach64_128x48_screen, 365 &mach64_144x54_screen, 366 &mach64_160x64_screen 367 }; 368 369 static struct wsscreen_list mach64_screenlist = { 370 __arraycount(_mach64_scrlist), 371 _mach64_scrlist 372 }; 373 374 static int mach64_ioctl(void *, void *, u_long, void *, int, 375 struct lwp *); 376 static paddr_t mach64_mmap(void *, void *, off_t, int); 377 378 #if 0 379 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 380 #endif 381 382 383 static struct vcons_screen mach64_console_screen; 384 385 /* framebuffer device, SPARC-only so far */ 386 #ifdef __sparc__ 387 388 static void machfb_unblank(device_t); 389 static void machfb_fbattach(struct mach64_softc *); 390 391 extern struct cfdriver machfb_cd; 392 393 dev_type_open(machfb_fbopen); 394 dev_type_close(machfb_fbclose); 395 dev_type_ioctl(machfb_fbioctl); 396 dev_type_mmap(machfb_fbmmap); 397 398 /* frame buffer generic driver */ 399 static struct fbdriver machfb_fbdriver = { 400 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 401 machfb_fbmmap, nokqfilter 402 }; 403 404 #endif /* __sparc__ */ 405 406 /* 407 * Inline functions for getting access to register aperture. 408 */ 409 410 static inline uint32_t 411 regr(struct mach64_softc *sc, uint32_t index) 412 { 413 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 414 } 415 416 static inline uint8_t 417 regrb(struct mach64_softc *sc, uint32_t index) 418 { 419 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 420 } 421 422 static inline void 423 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 424 { 425 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 426 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 427 BUS_SPACE_BARRIER_WRITE); 428 } 429 430 static inline void 431 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 432 { 433 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 434 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 435 BUS_SPACE_BARRIER_WRITE); 436 } 437 438 static inline void 439 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 440 { 441 uint32_t reg; 442 443 reg = regr(sc, CLOCK_CNTL); 444 reg |= PLL_WR_EN; 445 regw(sc, CLOCK_CNTL, reg); 446 reg &= ~(PLL_ADDR | PLL_DATA); 447 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 448 reg |= data << PLL_DATA_SHIFT; 449 reg |= CLOCK_STROBE; 450 regw(sc, CLOCK_CNTL, reg); 451 reg &= ~PLL_WR_EN; 452 regw(sc, CLOCK_CNTL, reg); 453 } 454 455 static inline uint8_t 456 regrb_pll(struct mach64_softc *sc, uint32_t index) 457 { 458 459 regwb(sc, CLOCK_CNTL + 1, index << 2); 460 return regrb(sc, CLOCK_CNTL + 2); 461 } 462 463 static inline void 464 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 465 { 466 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 467 continue; 468 } 469 470 static inline void 471 wait_for_idle(struct mach64_softc *sc) 472 { 473 wait_for_fifo(sc, 16); 474 while ((regr(sc, GUI_STAT) & 1) != 0) 475 continue; 476 } 477 478 static int 479 mach64_match(device_t parent, cfdata_t match, void *aux) 480 { 481 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 482 int i; 483 484 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 485 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 486 return 0; 487 488 for (i = 0; i < __arraycount(mach64_info); i++) 489 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 490 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 491 mach64_chip_rev = PCI_REVISION(pa->pa_class); 492 return 100; 493 } 494 495 return 0; 496 } 497 498 static void 499 mach64_attach(device_t parent, device_t self, void *aux) 500 { 501 struct mach64_softc *sc = device_private(self); 502 struct pci_attach_args *pa = aux; 503 struct rasops_info *ri; 504 prop_data_t edid_data; 505 #if defined(__sparc__) || defined(__powerpc__) 506 const struct videomode *mode = NULL; 507 #endif 508 char devinfo[256]; 509 int bar, id, expected_id; 510 int is_gx; 511 const char **memtype_names; 512 struct wsemuldisplaydev_attach_args aa; 513 long defattr; 514 int setmode, width, height; 515 pcireg_t screg; 516 uint32_t reg; 517 const pcireg_t enables = PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE; 518 519 sc->sc_dev = self; 520 sc->sc_pc = pa->pa_pc; 521 sc->sc_pcitag = pa->pa_tag; 522 sc->sc_dacw = -1; 523 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 524 sc->sc_nbus = pa->pa_bus; 525 sc->sc_ndev = pa->pa_device; 526 sc->sc_nfunc = pa->pa_function; 527 sc->sc_locked = 0; 528 sc->sc_iot = pa->pa_iot; 529 sc->sc_accessops.ioctl = mach64_ioctl; 530 sc->sc_accessops.mmap = mach64_mmap; 531 532 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 533 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 534 PCI_REVISION(pa->pa_class)); 535 aprint_naive(": Graphics processor\n"); 536 #ifdef MACHFB_DEBUG 537 printf(prop_dictionary_externalize(device_properties(self))); 538 #endif 539 540 /* enable memory and disable IO access */ 541 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 542 if ((screg & enables) != enables) { 543 screg |= enables; 544 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 545 PCI_COMMAND_STATUS_REG, screg); 546 } 547 for (bar = 0; bar < NBARS; bar++) { 548 reg = PCI_MAPREG_START + (bar * 4); 549 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 550 sc->sc_pcitag, reg); 551 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 552 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 553 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 554 sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc, 555 sc->sc_pcitag, reg) & 0xfffffff0; 556 } 557 printf("%s: aperture size %08x\n", device_xname(sc->sc_dev), 558 (uint32_t)sc->sc_apersize); 559 560 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 561 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 562 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 563 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 564 sc->sc_memt = pa->pa_memt; 565 566 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 567 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 568 panic("%s: failed to map aperture", device_xname(sc->sc_dev)); 569 } 570 sc->sc_aperture = (void *)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 571 572 /* If the BAR was never mapped, fix it up in MMIO. */ 573 if(sc->sc_regsize == 0) { 574 sc->sc_regsize = MACH64_REG_SIZE; 575 sc->sc_regbase = sc->sc_aperbase + MACH64_REG_OFF; 576 sc->sc_regphys = sc->sc_aperphys + MACH64_REG_OFF; 577 } 578 579 sc->sc_regt = sc->sc_memt; 580 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 581 sc->sc_regsize, &sc->sc_regh); 582 sc->sc_registers = (char *)sc->sc_aperture + 0x7ffc00; 583 584 mach64_init(sc); 585 586 aprint_normal_dev(sc->sc_dev, 587 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 588 (u_int)(sc->sc_apersize / (1024 * 1024)), 589 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 590 (u_int)sc->sc_regphys); 591 592 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 593 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 594 595 prop_dictionary_get_uint32(device_properties(self), "width", &width); 596 prop_dictionary_get_uint32(device_properties(self), "height", &height); 597 598 if ((edid_data = prop_dictionary_get(device_properties(self), "EDID")) 599 != NULL) { 600 struct edid_info ei; 601 602 sc->sc_edid_size = min(1024, prop_data_size(edid_data)); 603 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 604 memcpy(sc->sc_edid_data, prop_data_data_nocopy(edid_data), 605 sc->sc_edid_size); 606 607 edid_parse(sc->sc_edid_data, &ei); 608 609 #ifdef MACHFB_DEBUG 610 edid_print(&ei); 611 #endif 612 } 613 614 is_gx = 0; 615 switch(mach64_chip_id) { 616 case PCI_PRODUCT_ATI_MACH64_GX: 617 case PCI_PRODUCT_ATI_MACH64_CX: 618 is_gx = 1; 619 case PCI_PRODUCT_ATI_MACH64_CT: 620 sc->has_dsp = 0; 621 break; 622 case PCI_PRODUCT_ATI_MACH64_VT: 623 case PCI_PRODUCT_ATI_RAGE_II: 624 if((mach64_chip_rev & 0x07) == 0) { 625 sc->has_dsp = 0; 626 break; 627 } 628 /* Otherwise fall through. */ 629 default: 630 sc->has_dsp = 1; 631 } 632 633 memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names; 634 635 sc->memsize = mach64_get_memsize(sc); 636 if (sc->memsize == 8192) 637 /* The last page is used as register aperture. */ 638 sc->memsize -= 4; 639 if(is_gx) 640 sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07; 641 else 642 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 643 644 /* XXX is there any way to calculate reference frequency from 645 known values? */ 646 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 647 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 648 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 649 aprint_normal_dev(sc->sc_dev, "ref_freq=29.498MHz\n"); 650 sc->ref_freq = 29498; 651 } else 652 sc->ref_freq = 14318; 653 654 reg = regr(sc, CLOCK_CNTL); 655 printf("CLOCK_CNTL: %08x\n", reg); 656 sc->sc_clock = reg & 3; 657 printf("using clock %d\n", sc->sc_clock); 658 659 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 660 printf("ref_div: %d\n", sc->ref_div); 661 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 662 printf("mclk_fb_div: %d\n", sc->mclk_fb_div); 663 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 664 (sc->ref_div * 2); 665 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 666 (sc->mem_freq * sc->ref_div); 667 sc->ramdac_freq = mach64_get_max_ramdac(sc); 668 aprint_normal_dev(sc->sc_dev, 669 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 670 (u_long)sc->memsize, 671 memtype_names[sc->memtype], 672 sc->mem_freq / 1000, sc->mem_freq % 1000, 673 sc->ramdac_freq / 1000); 674 675 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 676 switch(mach64_chip_id) { 677 case PCI_PRODUCT_ATI_MACH64_GX: 678 expected_id = 0x00d7; 679 break; 680 case PCI_PRODUCT_ATI_MACH64_CX: 681 expected_id = 0x0057; 682 break; 683 default: 684 /* Most chip IDs match their PCI product ID. */ 685 expected_id = mach64_chip_id; 686 } 687 688 if (id != expected_id) { 689 aprint_error_dev(sc->sc_dev, 690 "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id); 691 return; 692 } 693 694 sc->sc_console = mach64_is_console(sc); 695 #ifdef DIAGNOSTIC 696 aprint_normal("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 697 #endif 698 #if defined(__sparc__) || defined(__powerpc__) 699 if (sc->sc_console) { 700 if (mode != NULL) { 701 memcpy(&default_mode, mode, sizeof(struct videomode)); 702 setmode = 1; 703 } else { 704 mach64_get_mode(sc, &default_mode); 705 setmode = 0; 706 } 707 sc->sc_my_mode = &default_mode; 708 } else { 709 /* fill in default_mode if it's empty */ 710 mach64_get_mode(sc, &default_mode); 711 if (default_mode.dot_clock == 0) { 712 memcpy(&default_mode, &mach64_modes[4], 713 sizeof(default_mode)); 714 } 715 sc->sc_my_mode = &default_mode; 716 setmode = 1; 717 } 718 #else 719 if (default_mode.dot_clock == 0) { 720 memcpy(&default_mode, &mach64_modes[0], 721 sizeof(default_mode)); 722 } 723 sc->sc_my_mode = &mach64_modes[0]; 724 setmode = 1; 725 #endif 726 727 sc->bits_per_pixel = 8; 728 sc->virt_x = sc->sc_my_mode->hdisplay; 729 sc->virt_y = sc->sc_my_mode->vdisplay; 730 sc->max_x = sc->virt_x - 1; 731 sc->max_y = (sc->memsize * 1024) / 732 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 733 734 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 735 736 mach64_init_engine(sc); 737 738 if (setmode) 739 mach64_modeswitch(sc, sc->sc_my_mode); 740 741 aprint_normal_dev(sc->sc_dev, 742 "initial resolution %dx%d at %d bpp\n", 743 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 744 sc->bits_per_pixel); 745 746 #ifdef __sparc__ 747 machfb_fbattach(sc); 748 #endif 749 750 wsfont_init(); 751 752 sc->sc_bg = WS_DEFAULT_BG; 753 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &sc->sc_accessops); 754 sc->vd.init_screen = mach64_init_screen; 755 756 mach64_init_lut(sc); 757 mach64_clearscreen(sc); 758 machfb_blank(sc, 0); /* unblank the screen */ 759 760 if (sc->sc_console) { 761 762 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 763 &defattr); 764 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 765 766 ri = &mach64_console_screen.scr_ri; 767 mach64_defaultscreen.textops = &ri->ri_ops; 768 mach64_defaultscreen.capabilities = ri->ri_caps; 769 mach64_defaultscreen.nrows = ri->ri_rows; 770 mach64_defaultscreen.ncols = ri->ri_cols; 771 772 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 773 vcons_replay_msgbuf(&mach64_console_screen); 774 } else { 775 /* 776 * since we're not the console we can postpone the rest 777 * until someone actually allocates a screen for us 778 */ 779 mach64_modeswitch(sc, sc->sc_my_mode); 780 } 781 782 aa.console = sc->sc_console; 783 aa.scrdata = &mach64_screenlist; 784 aa.accessops = &sc->sc_accessops; 785 aa.accesscookie = &sc->vd; 786 787 config_found(self, &aa, wsemuldisplaydevprint); 788 789 config_found_ia(self, "drm", aux, machfb_drm_print); 790 } 791 792 static int 793 machfb_drm_print(void *aux, const char *pnp) 794 { 795 if (pnp) 796 aprint_normal("direct rendering for %s", pnp); 797 return (UNSUPP); 798 } 799 800 static void 801 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 802 long *defattr) 803 { 804 struct mach64_softc *sc = cookie; 805 struct rasops_info *ri = &scr->scr_ri; 806 807 /* XXX for now */ 808 #define setmode 0 809 810 ri->ri_depth = sc->bits_per_pixel; 811 ri->ri_width = sc->sc_my_mode->hdisplay; 812 ri->ri_height = sc->sc_my_mode->vdisplay; 813 ri->ri_stride = ri->ri_width; 814 ri->ri_flg = RI_CENTER; 815 set_address(ri, sc->sc_aperture); 816 817 #ifdef VCONS_DRAW_INTR 818 scr->scr_flags |= VCONS_DONT_READ; 819 #endif 820 821 if (existing) { 822 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 823 panic("%s: failed to switch video mode", 824 device_xname(sc->sc_dev)); 825 } 826 } 827 828 rasops_init(ri, 0, 0); 829 ri->ri_caps = WSSCREEN_WSCOLORS; 830 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 831 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 832 833 /* enable acceleration */ 834 ri->ri_hw = scr; 835 ri->ri_ops.copyrows = mach64_copyrows; 836 ri->ri_ops.copycols = mach64_copycols; 837 ri->ri_ops.eraserows = mach64_eraserows; 838 ri->ri_ops.erasecols = mach64_erasecols; 839 ri->ri_ops.cursor = mach64_cursor; 840 ri->ri_ops.putchar = mach64_putchar; 841 } 842 843 static void 844 mach64_init(struct mach64_softc *sc) 845 { 846 uint32_t *p32, saved_value; 847 uint8_t *p; 848 int need_swap; 849 850 /* 851 * Test whether the aperture is byte swapped or not 852 */ 853 p32 = (uint32_t*)sc->sc_aperture; 854 saved_value = *p32; 855 p = (uint8_t*)(u_long)sc->sc_aperture; 856 *p32 = 0x12345678; 857 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 858 need_swap = 0; 859 else 860 need_swap = 1; 861 if (need_swap) { 862 sc->sc_aperture = (char *)sc->sc_aperture + 0x800000; 863 #if 0 864 /* what the fsck is this for? */ 865 sc->sc_aperbase += 0x800000; 866 sc->sc_apersize -= 0x800000; 867 #endif 868 } 869 *p32 = saved_value; 870 871 sc->sc_blanked = 0; 872 } 873 874 static int 875 mach64_get_memsize(struct mach64_softc *sc) 876 { 877 int tmp, memsize; 878 int mem_tab[] = { 879 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 880 }; 881 tmp = regr(sc, MEM_CNTL); 882 #ifdef DIAGNOSTIC 883 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 884 #endif 885 if (sc->has_dsp) { 886 tmp &= 0x0000000f; 887 if (tmp < 8) 888 memsize = (tmp + 1) * 512; 889 else if (tmp < 12) 890 memsize = (tmp - 3) * 1024; 891 else 892 memsize = (tmp - 7) * 2048; 893 } else { 894 memsize = mem_tab[tmp & 0x07]; 895 } 896 897 return memsize; 898 } 899 900 static int 901 mach64_get_max_ramdac(struct mach64_softc *sc) 902 { 903 int i; 904 905 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 906 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 907 (mach64_chip_rev & 0x07)) 908 return 170000; 909 910 for (i = 0; i < __arraycount(mach64_info); i++) 911 if (mach64_chip_id == mach64_info[i].chip_id) 912 return mach64_info[i].ramdac_freq; 913 914 if (sc->bits_per_pixel == 8) 915 return 135000; 916 else 917 return 80000; 918 } 919 920 #if defined(__sparc__) || defined(__powerpc__) 921 static void 922 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 923 { 924 struct mach64_crtcregs crtc; 925 926 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 927 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 928 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 929 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 930 931 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 932 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 933 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 934 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 935 mode->hsync_start; 936 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 937 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 938 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 939 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 940 941 #ifdef MACHFB_DEBUG 942 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 943 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 944 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 945 #endif 946 } 947 #endif 948 949 static int 950 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 951 struct videomode *mode) 952 { 953 954 if (mode->dot_clock > sc->ramdac_freq) 955 /* Clock too high. */ 956 return 1; 957 958 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 959 ((mode->htotal >> 3) - 1); 960 crtc->h_sync_strt_wid = 961 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 962 ((mode->hsync_start >> 3) - 1); 963 964 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 965 (mode->vtotal - 1); 966 crtc->v_sync_strt_wid = 967 ((mode->vsync_end - mode->vsync_start) << 16) | 968 (mode->vsync_start - 1); 969 970 if (mode->flags & VID_NVSYNC) 971 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 972 973 switch (sc->bits_per_pixel) { 974 case 8: 975 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 976 break; 977 case 16: 978 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 979 break; 980 case 32: 981 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 982 break; 983 } 984 985 crtc->gen_cntl = 0; 986 if (mode->flags & VID_INTERLACE) 987 crtc->gen_cntl |= CRTC_INTERLACE_EN; 988 989 if (mode->flags & VID_CSYNC) 990 crtc->gen_cntl |= CRTC_CSYNC_EN; 991 992 crtc->dot_clock = mode->dot_clock; 993 994 return 0; 995 } 996 997 static void 998 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 999 { 1000 1001 mach64_set_pll(sc, crtc->dot_clock); 1002 1003 if (sc->has_dsp) 1004 mach64_set_dsp(sc); 1005 #if 1 1006 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 1007 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1008 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 1009 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1010 1011 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 1012 1013 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1014 1015 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 1016 /* XXX this unconditionally enables composite sync on SPARC */ 1017 #ifdef __sparc__ 1018 CRTC_CSYNC_EN | 1019 #endif 1020 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 1021 #endif 1022 } 1023 1024 static int 1025 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 1026 { 1027 struct mach64_crtcregs crtc; 1028 1029 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 1030 1031 if (mach64_calc_crtcregs(sc, &crtc, mode)) 1032 return 1; 1033 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 1034 if (crtc.dot_clock == 0) { 1035 aprint_error("%s: preposterous dot clock (%d)\n", 1036 device_xname(sc->sc_dev), crtc.dot_clock); 1037 return 1; 1038 } 1039 mach64_set_crtcregs(sc, &crtc); 1040 return 0; 1041 } 1042 1043 static void 1044 mach64_reset_engine(struct mach64_softc *sc) 1045 { 1046 1047 /* Reset engine.*/ 1048 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1049 1050 /* Enable engine. */ 1051 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1052 1053 /* Ensure engine is not locked up by clearing any FIFO or 1054 host errors. */ 1055 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1056 BUS_FIFO_ERR_ACK); 1057 } 1058 1059 static void 1060 mach64_init_engine(struct mach64_softc *sc) 1061 { 1062 uint32_t pitch_value; 1063 1064 pitch_value = sc->virt_x; 1065 1066 if (sc->bits_per_pixel == 24) 1067 pitch_value *= 3; 1068 1069 mach64_reset_engine(sc); 1070 1071 wait_for_fifo(sc, 14); 1072 1073 regw(sc, CONTEXT_MASK, 0xffffffff); 1074 1075 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 1076 1077 /* make sure the visible area starts where we're going to draw */ 1078 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1079 1080 regw(sc, DST_Y_X, 0); 1081 regw(sc, DST_HEIGHT, 0); 1082 regw(sc, DST_BRES_ERR, 0); 1083 regw(sc, DST_BRES_INC, 0); 1084 regw(sc, DST_BRES_DEC, 0); 1085 1086 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1087 DST_Y_TOP_TO_BOTTOM); 1088 1089 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 1090 1091 regw(sc, SRC_Y_X, 0); 1092 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1093 regw(sc, SRC_Y_X_START, 0); 1094 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1095 1096 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1097 1098 wait_for_fifo(sc, 13); 1099 regw(sc, HOST_CNTL, 0); 1100 1101 regw(sc, PAT_REG0, 0); 1102 regw(sc, PAT_REG1, 0); 1103 regw(sc, PAT_CNTL, 0); 1104 1105 regw(sc, SC_LEFT, 0); 1106 regw(sc, SC_TOP, 0); 1107 regw(sc, SC_BOTTOM, sc->sc_my_mode->vdisplay - 1); 1108 regw(sc, SC_RIGHT, pitch_value - 1); 1109 1110 regw(sc, DP_BKGD_CLR, WS_DEFAULT_BG); 1111 regw(sc, DP_FRGD_CLR, WS_DEFAULT_FG); 1112 regw(sc, DP_WRITE_MASK, 0xffffffff); 1113 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1114 1115 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1116 1117 wait_for_fifo(sc, 3); 1118 regw(sc, CLR_CMP_CLR, 0); 1119 regw(sc, CLR_CMP_MASK, 0xffffffff); 1120 regw(sc, CLR_CMP_CNTL, 0); 1121 1122 wait_for_fifo(sc, 2); 1123 switch (sc->bits_per_pixel) { 1124 case 8: 1125 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP); 1126 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1127 /* We want 8 bit per channel */ 1128 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1129 break; 1130 case 32: 1131 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP); 1132 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1133 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1134 break; 1135 } 1136 1137 wait_for_fifo(sc, 5); 1138 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1139 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1140 1141 wait_for_idle(sc); 1142 } 1143 1144 #if 0 1145 static void 1146 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1147 { 1148 int offset; 1149 1150 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1151 1152 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1153 offset); 1154 } 1155 #endif 1156 1157 static void 1158 mach64_set_dsp(struct mach64_softc *sc) 1159 { 1160 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1161 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1162 uint32_t xclks_per_qw, y; 1163 uint32_t fifo_off, fifo_on; 1164 1165 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1166 1167 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1168 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1169 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1170 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1171 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1172 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1173 dsp_loop_latency = 0; 1174 fifo_depth = 24; 1175 } else { 1176 dsp_loop_latency = 2; 1177 fifo_depth = 32; 1178 } 1179 1180 dsp_precision = 0; 1181 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1182 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1183 y = (xclks_per_qw * fifo_depth) >> 11; 1184 while (y) { 1185 y >>= 1; 1186 dsp_precision++; 1187 } 1188 dsp_precision -= 5; 1189 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1190 1191 switch (sc->memtype) { 1192 case DRAM: 1193 case EDO_DRAM: 1194 case PSEUDO_EDO: 1195 if (sc->memsize > 1024) { 1196 page_size = 9; 1197 dsp_loop_latency += 6; 1198 } else { 1199 page_size = 10; 1200 if (sc->memtype == DRAM) 1201 dsp_loop_latency += 8; 1202 else 1203 dsp_loop_latency += 7; 1204 } 1205 break; 1206 case SDRAM: 1207 case SGRAM: 1208 if (sc->memsize > 1024) { 1209 page_size = 8; 1210 dsp_loop_latency += 8; 1211 } else { 1212 page_size = 10; 1213 dsp_loop_latency += 9; 1214 } 1215 break; 1216 default: 1217 page_size = 10; 1218 dsp_loop_latency += 9; 1219 break; 1220 } 1221 1222 if (xclks_per_qw >= (page_size << 11)) 1223 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1224 else 1225 fifo_on = (3 * page_size + 2) << 6; 1226 1227 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1228 dsp_on = fifo_on >> dsp_precision; 1229 dsp_off = fifo_off >> dsp_precision; 1230 1231 #ifdef MACHFB_DEBUG 1232 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1233 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1234 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1235 "mclk_post_div = %d, vclk_post_div = %d\n", 1236 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1237 sc->mclk_fb_div, sc->vclk_fb_div, 1238 sc->mclk_post_div, sc->vclk_post_div); 1239 #endif 1240 1241 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1242 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1243 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1244 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1245 } 1246 1247 static void 1248 mach64_set_pll(struct mach64_softc *sc, int clock) 1249 { 1250 uint32_t q, clockreg; 1251 int clockshift = sc->sc_clock << 1; 1252 uint8_t reg, vclk_ctl; 1253 1254 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1255 #ifdef MACHFB_DEBUG 1256 printf("q = %d\n", q); 1257 #endif 1258 if (q > 25500) { 1259 printf("Warning: q > 25500\n"); 1260 q = 25500; 1261 sc->vclk_post_div = 1; 1262 sc->log2_vclk_post_div = 0; 1263 } else if (q > 12750) { 1264 sc->vclk_post_div = 1; 1265 sc->log2_vclk_post_div = 0; 1266 } else if (q > 6350) { 1267 sc->vclk_post_div = 2; 1268 sc->log2_vclk_post_div = 1; 1269 } else if (q > 3150) { 1270 sc->vclk_post_div = 4; 1271 sc->log2_vclk_post_div = 2; 1272 } else if (q >= 1600) { 1273 sc->vclk_post_div = 8; 1274 sc->log2_vclk_post_div = 3; 1275 } else { 1276 printf("Warning: q < 1600\n"); 1277 sc->vclk_post_div = 8; 1278 sc->log2_vclk_post_div = 3; 1279 } 1280 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1281 printf("post_div: %d log2_post_div: %d mclk_div: %d\n", sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1282 1283 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1284 printf("vclk_ctl: %02x\n", vclk_ctl); 1285 vclk_ctl |= PLL_VCLK_RESET; 1286 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1287 1288 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1289 reg = regrb_pll(sc, VCLK_POST_DIV); 1290 reg &= ~(3 << clockshift); 1291 reg |= (sc->log2_vclk_post_div << clockshift); 1292 regwb_pll(sc, VCLK_POST_DIV, reg); 1293 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1294 1295 vclk_ctl &= ~PLL_VCLK_RESET; 1296 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1297 1298 clockreg = regr(sc, CLOCK_CNTL); 1299 clockreg &= ~CLOCK_SEL; 1300 clockreg |= sc->sc_clock | CLOCK_STROBE; 1301 regw(sc, CLOCK_CNTL, clockreg); 1302 } 1303 1304 static void 1305 mach64_init_lut(struct mach64_softc *sc) 1306 { 1307 int i, idx; 1308 1309 idx = 0; 1310 for (i = 0; i < 256; i++) { 1311 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1], 1312 rasops_cmap[idx + 2]); 1313 idx += 3; 1314 } 1315 } 1316 1317 static int 1318 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1319 uint8_t b) 1320 { 1321 sc->sc_cmap_red[index] = r; 1322 sc->sc_cmap_green[index] = g; 1323 sc->sc_cmap_blue[index] = b; 1324 /* 1325 * writing the dac index takes a while, in theory we can poll some 1326 * register to see when it's ready - but we better avoid writing it 1327 * unnecessarily 1328 */ 1329 if (index != sc->sc_dacw) { 1330 regwb(sc, DAC_MASK, 0xff); 1331 regwb(sc, DAC_WINDEX, index); 1332 } 1333 sc->sc_dacw = index + 1; 1334 regwb(sc, DAC_DATA, r); 1335 regwb(sc, DAC_DATA, g); 1336 regwb(sc, DAC_DATA, b); 1337 return 0; 1338 } 1339 1340 static int 1341 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1342 { 1343 uint index = cm->index; 1344 uint count = cm->count; 1345 int i, error; 1346 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1347 uint8_t *r, *g, *b; 1348 1349 if (cm->index >= 256 || cm->count > 256 || 1350 (cm->index + cm->count) > 256) 1351 return EINVAL; 1352 error = copyin(cm->red, &rbuf[index], count); 1353 if (error) 1354 return error; 1355 error = copyin(cm->green, &gbuf[index], count); 1356 if (error) 1357 return error; 1358 error = copyin(cm->blue, &bbuf[index], count); 1359 if (error) 1360 return error; 1361 1362 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1363 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1364 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1365 1366 r = &sc->sc_cmap_red[index]; 1367 g = &sc->sc_cmap_green[index]; 1368 b = &sc->sc_cmap_blue[index]; 1369 1370 for (i = 0; i < count; i++) { 1371 mach64_putpalreg(sc, index, *r, *g, *b); 1372 index++; 1373 r++, g++, b++; 1374 } 1375 return 0; 1376 } 1377 1378 static int 1379 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1380 { 1381 u_int index = cm->index; 1382 u_int count = cm->count; 1383 int error; 1384 1385 if (index >= 255 || count > 256 || index + count > 256) 1386 return EINVAL; 1387 1388 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1389 if (error) 1390 return error; 1391 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1392 if (error) 1393 return error; 1394 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1395 if (error) 1396 return error; 1397 1398 return 0; 1399 } 1400 1401 static int 1402 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1403 { 1404 struct mach64_crtcregs regs; 1405 1406 if (mach64_calc_crtcregs(sc, ®s, 1407 (struct videomode *)des->modecookie)) 1408 return 1; 1409 1410 mach64_set_crtcregs(sc, ®s); 1411 return 0; 1412 } 1413 1414 static int 1415 mach64_is_console(struct mach64_softc *sc) 1416 { 1417 bool console = 0; 1418 1419 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1420 "is_console", &console); 1421 return console; 1422 } 1423 1424 /* 1425 * wsdisplay_emulops 1426 */ 1427 1428 static void 1429 mach64_cursor(void *cookie, int on, int row, int col) 1430 { 1431 struct rasops_info *ri = cookie; 1432 struct vcons_screen *scr = ri->ri_hw; 1433 struct mach64_softc *sc = scr->scr_cookie; 1434 int x, y, wi, he; 1435 1436 wi = ri->ri_font->fontwidth; 1437 he = ri->ri_font->fontheight; 1438 1439 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1440 x = ri->ri_ccol * wi + ri->ri_xorigin; 1441 y = ri->ri_crow * he + ri->ri_yorigin; 1442 if (ri->ri_flg & RI_CURSOR) { 1443 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1444 0xff); 1445 ri->ri_flg &= ~RI_CURSOR; 1446 } 1447 ri->ri_crow = row; 1448 ri->ri_ccol = col; 1449 if (on) { 1450 x = ri->ri_ccol * wi + ri->ri_xorigin; 1451 y = ri->ri_crow * he + ri->ri_yorigin; 1452 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1453 0xff); 1454 ri->ri_flg |= RI_CURSOR; 1455 } 1456 } else { 1457 scr->scr_ri.ri_crow = row; 1458 scr->scr_ri.ri_ccol = col; 1459 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1460 } 1461 } 1462 1463 #if 0 1464 static int 1465 mach64_mapchar(void *cookie, int uni, u_int *index) 1466 { 1467 return 0; 1468 } 1469 #endif 1470 1471 static void 1472 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1473 { 1474 struct rasops_info *ri = cookie; 1475 struct wsdisplay_font *font = PICK_FONT(ri, c); 1476 struct vcons_screen *scr = ri->ri_hw; 1477 struct mach64_softc *sc = scr->scr_cookie; 1478 1479 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1480 int fg, bg, uc; 1481 uint8_t *data; 1482 int x, y, wi, he; 1483 wi = font->fontwidth; 1484 he = font->fontheight; 1485 1486 if (!CHAR_IN_FONT(c, font)) 1487 return; 1488 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1489 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f]; 1490 x = ri->ri_xorigin + col * wi; 1491 y = ri->ri_yorigin + row * he; 1492 if (c == 0x20) { 1493 mach64_rectfill(sc, x, y, wi, he, bg); 1494 } else { 1495 uc = c - font->firstchar; 1496 data = (uint8_t *)font->data + uc * 1497 ri->ri_fontscale; 1498 1499 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1500 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1501 } 1502 } 1503 } 1504 1505 1506 static void 1507 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1508 { 1509 struct rasops_info *ri = cookie; 1510 struct vcons_screen *scr = ri->ri_hw; 1511 struct mach64_softc *sc = scr->scr_cookie; 1512 int32_t xs, xd, y, width, height; 1513 1514 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1515 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1516 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1517 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1518 width = ri->ri_font->fontwidth * ncols; 1519 height = ri->ri_font->fontheight; 1520 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff); 1521 } 1522 } 1523 1524 static void 1525 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1526 { 1527 struct rasops_info *ri = cookie; 1528 struct vcons_screen *scr = ri->ri_hw; 1529 struct mach64_softc *sc = scr->scr_cookie; 1530 int32_t x, y, width, height, fg, bg, ul; 1531 1532 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1533 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1534 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1535 width = ri->ri_font->fontwidth * ncols; 1536 height = ri->ri_font->fontheight; 1537 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1538 1539 mach64_rectfill(sc, x, y, width, height, bg); 1540 } 1541 } 1542 1543 static void 1544 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1545 { 1546 struct rasops_info *ri = cookie; 1547 struct vcons_screen *scr = ri->ri_hw; 1548 struct mach64_softc *sc = scr->scr_cookie; 1549 int32_t x, ys, yd, width, height; 1550 1551 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1552 x = ri->ri_xorigin; 1553 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1554 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1555 width = ri->ri_emuwidth; 1556 height = ri->ri_font->fontheight*nrows; 1557 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff); 1558 } 1559 } 1560 1561 static void 1562 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1563 { 1564 struct rasops_info *ri = cookie; 1565 struct vcons_screen *scr = ri->ri_hw; 1566 struct mach64_softc *sc = scr->scr_cookie; 1567 int32_t x, y, width, height, fg, bg, ul; 1568 1569 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1570 x = ri->ri_xorigin; 1571 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1572 width = ri->ri_emuwidth; 1573 height = ri->ri_font->fontheight * nrows; 1574 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1575 1576 mach64_rectfill(sc, x, y, width, height, bg); 1577 } 1578 } 1579 1580 static void 1581 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1582 { 1583 uint32_t dest_ctl = 0; 1584 1585 wait_for_idle(sc); 1586 regw(sc, DP_WRITE_MASK, mask); /* XXX only good for 8 bit */ 1587 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1588 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1589 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1590 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1591 if (yd < ys) { 1592 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1593 } else { 1594 ys += height - 1; 1595 yd += height - 1; 1596 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1597 } 1598 if (xd < xs) { 1599 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1600 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1601 } else { 1602 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1603 xs += width - 1; 1604 xd += width - 1; 1605 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1606 } 1607 regw(sc, DST_CNTL, dest_ctl); 1608 1609 regw(sc, SRC_Y_X, (xs << 16) | ys); 1610 regw(sc, SRC_WIDTH1, width); 1611 regw(sc, DST_Y_X, (xd << 16) | yd); 1612 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1613 } 1614 1615 static void 1616 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1617 int height, uint32_t fg, uint32_t bg) 1618 { 1619 wait_for_idle(sc); 1620 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1621 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1622 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1623 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1624 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1625 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1626 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1627 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1628 regw(sc, DP_BKGD_CLR, bg); 1629 regw(sc, DP_FRGD_CLR, fg); 1630 regw(sc, SRC_Y_X, 0); 1631 regw(sc, SRC_WIDTH1, width); 1632 regw(sc, DST_Y_X, (xd << 16) | yd); 1633 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1634 /* now feed the data into the chip */ 1635 } 1636 1637 static void 1638 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1639 { 1640 int i; 1641 uint32_t latch = 0, bork; 1642 int shift = 0; 1643 int reg = 0; 1644 1645 for (i = 0; i < count; i++) { 1646 bork = data[i]; 1647 latch |= (bork << shift); 1648 if (shift == 24) { 1649 regw(sc, HOST_DATA0 + reg, latch); 1650 latch = 0; 1651 shift = 0; 1652 reg = (reg + 4) & 0x3c; 1653 } else 1654 shift += 8; 1655 } 1656 if (shift != 0) /* 24 */ 1657 regw(sc, HOST_DATA0 + reg, latch); 1658 } 1659 1660 1661 static void 1662 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1663 int colour) 1664 { 1665 wait_for_idle(sc); 1666 regw(sc, DP_WRITE_MASK, 0xff); 1667 regw(sc, DP_FRGD_CLR, colour); 1668 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1669 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1670 regw(sc, DP_MIX, MIX_SRC << 16); 1671 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1672 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1673 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1674 1675 regw(sc, SRC_Y_X, (x << 16) | y); 1676 regw(sc, SRC_WIDTH1, width); 1677 regw(sc, DST_Y_X, (x << 16) | y); 1678 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1679 } 1680 1681 static void 1682 mach64_clearscreen(struct mach64_softc *sc) 1683 { 1684 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1685 } 1686 1687 1688 #if 0 1689 static void 1690 mach64_showpal(struct mach64_softc *sc) 1691 { 1692 int i, x = 0; 1693 1694 for (i = 0; i < 16; i++) { 1695 mach64_rectfill(sc, x, 0, 64, 64, i); 1696 x += 64; 1697 } 1698 } 1699 #endif 1700 1701 /* 1702 * wsdisplay_accessops 1703 */ 1704 1705 static int 1706 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1707 struct lwp *l) 1708 { 1709 struct vcons_data *vd = v; 1710 struct mach64_softc *sc = vd->cookie; 1711 struct wsdisplay_fbinfo *wdf; 1712 struct vcons_screen *ms = vd->active; 1713 1714 switch (cmd) { 1715 case WSDISPLAYIO_GTYPE: 1716 /* XXX is this the right type to return? */ 1717 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1718 return 0; 1719 1720 case WSDISPLAYIO_LINEBYTES: 1721 *(u_int *)data = sc->virt_x * sc->bits_per_pixel / 8; 1722 return 0; 1723 1724 case WSDISPLAYIO_GINFO: 1725 wdf = (void *)data; 1726 wdf->height = sc->virt_y; 1727 wdf->width = sc->virt_x; 1728 wdf->depth = sc->bits_per_pixel; 1729 wdf->cmsize = 256; 1730 return 0; 1731 1732 case WSDISPLAYIO_GETCMAP: 1733 return mach64_getcmap(sc, 1734 (struct wsdisplay_cmap *)data); 1735 1736 case WSDISPLAYIO_PUTCMAP: 1737 return mach64_putcmap(sc, 1738 (struct wsdisplay_cmap *)data); 1739 1740 /* PCI config read/write passthrough. */ 1741 case PCI_IOC_CFGREAD: 1742 case PCI_IOC_CFGWRITE: 1743 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1744 cmd, data, flag, l); 1745 1746 case WSDISPLAYIO_GET_BUSID: 1747 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1748 sc->sc_pcitag, data); 1749 1750 case WSDISPLAYIO_SMODE: { 1751 int new_mode = *(int*)data; 1752 if (new_mode != sc->sc_mode) { 1753 sc->sc_mode = new_mode; 1754 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1755 && (ms != NULL)) 1756 { 1757 /* restore initial video mode */ 1758 mach64_init(sc); 1759 mach64_init_engine(sc); 1760 mach64_init_lut(sc); 1761 mach64_modeswitch(sc, sc->sc_my_mode); 1762 vcons_redraw_screen(ms); 1763 } 1764 } 1765 } 1766 return 0; 1767 case WSDISPLAYIO_GET_EDID: { 1768 struct wsdisplayio_edid_info *d = data; 1769 return wsdisplayio_get_edid(sc->sc_dev, d); 1770 } 1771 } 1772 return EPASSTHROUGH; 1773 } 1774 1775 static paddr_t 1776 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1777 { 1778 struct vcons_data *vd = v; 1779 struct mach64_softc *sc = vd->cookie; 1780 paddr_t pa; 1781 pcireg_t reg; 1782 1783 #ifndef __sparc64__ 1784 /* 1785 *'regular' framebuffer mmap()ing 1786 * disabled on sparc64 because some ATI firmware likes to map some PCI 1787 * resources to addresses that would collide with this ( like some Rage 1788 * IIc which uses 0x2000 for the 2nd register block ) 1789 * Other 64bit architectures might run into similar problems. 1790 */ 1791 if (offset<sc->sc_apersize) { 1792 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, offset, 1793 prot, BUS_SPACE_MAP_LINEAR); 1794 return pa; 1795 } 1796 #endif 1797 1798 /* 1799 * restrict all other mappings to processes with superuser privileges 1800 * or the kernel itself 1801 */ 1802 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1803 NULL) != 0) { 1804 return -1; 1805 } 1806 1807 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1808 if (reg != sc->sc_regphys) { 1809 #ifdef DIAGNOSTIC 1810 printf("%s: BAR 0x18 changed! (%x %x)\n", 1811 device_xname(sc->sc_dev), (uint32_t)sc->sc_regphys, 1812 (uint32_t)reg); 1813 #endif 1814 sc->sc_regphys = reg; 1815 } 1816 1817 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1818 if (reg != sc->sc_aperphys) { 1819 #ifdef DIAGNOSTIC 1820 printf("%s: BAR 0x10 changed! (%x %x)\n", 1821 device_xname(sc->sc_dev), (uint32_t)sc->sc_aperphys, 1822 (uint32_t)reg); 1823 #endif 1824 sc->sc_aperphys = reg; 1825 } 1826 1827 if ((offset >= sc->sc_aperphys) && 1828 (offset < (sc->sc_aperphys + sc->sc_apersize))) { 1829 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1830 BUS_SPACE_MAP_LINEAR); 1831 return pa; 1832 } 1833 1834 if ((offset >= sc->sc_regphys) && 1835 (offset < (sc->sc_regphys + sc->sc_regsize))) { 1836 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1837 BUS_SPACE_MAP_LINEAR); 1838 return pa; 1839 } 1840 1841 if ((offset >= sc->sc_rom.vb_base) && 1842 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 1843 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1844 BUS_SPACE_MAP_LINEAR); 1845 return pa; 1846 } 1847 1848 #ifdef PCI_MAGIC_IO_RANGE 1849 if ((offset >= PCI_MAGIC_IO_RANGE) && 1850 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 1851 return bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1852 0, prot, BUS_SPACE_MAP_LINEAR); 1853 } 1854 #endif 1855 1856 return -1; 1857 } 1858 1859 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1860 static void 1861 set_address(struct rasops_info *ri, void *fb) 1862 { 1863 #ifdef notdef 1864 printf(" %d %d %d\n", ri->ri_xorigin, ri->ri_yorigin, ri->ri_stride); 1865 #endif 1866 ri->ri_bits = (void *)((char *)fb + ri->ri_stride * ri->ri_yorigin + 1867 ri->ri_xorigin); 1868 } 1869 1870 #if 0 1871 static int 1872 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1873 { 1874 1875 return 0; 1876 } 1877 #endif 1878 1879 void 1880 machfb_blank(struct mach64_softc *sc, int blank) 1881 { 1882 uint32_t reg; 1883 1884 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1885 1886 switch (blank) 1887 { 1888 case 0: 1889 reg = regr(sc, CRTC_GEN_CNTL); 1890 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1891 sc->sc_blanked = 0; 1892 break; 1893 case 1: 1894 reg = regr(sc, CRTC_GEN_CNTL); 1895 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1896 sc->sc_blanked = 1; 1897 break; 1898 default: 1899 break; 1900 } 1901 } 1902 1903 /* framebuffer device support */ 1904 #ifdef __sparc__ 1905 1906 static void 1907 machfb_unblank(device_t dev) 1908 { 1909 struct mach64_softc *sc = device_private(dev); 1910 1911 machfb_blank(sc, 0); 1912 } 1913 1914 static void 1915 machfb_fbattach(struct mach64_softc *sc) 1916 { 1917 struct fbdevice *fb = &sc->sc_fb; 1918 1919 fb->fb_device = sc->sc_dev; 1920 fb->fb_driver = &machfb_fbdriver; 1921 1922 fb->fb_type.fb_cmsize = 256; 1923 fb->fb_type.fb_size = sc->memsize; 1924 1925 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 1926 fb->fb_flags = sc->sc_dev->dv_cfdata->cf_flags & FB_USERMASK; 1927 fb->fb_type.fb_depth = sc->bits_per_pixel; 1928 fb->fb_type.fb_width = sc->virt_x; 1929 fb->fb_type.fb_height = sc->virt_y; 1930 1931 fb->fb_pixels = sc->sc_aperture; 1932 fb_attach(fb, sc->sc_console); 1933 } 1934 1935 int 1936 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 1937 { 1938 struct mach64_softc *sc; 1939 1940 sc = device_lookup_private(&machfb_cd, minor(dev)); 1941 if (sc == NULL) 1942 return ENXIO; 1943 sc->sc_locked = 1; 1944 1945 #ifdef MACHFB_DEBUG 1946 printf("machfb_fbopen(%d)\n", minor(dev)); 1947 #endif 1948 return 0; 1949 } 1950 1951 int 1952 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 1953 { 1954 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1955 1956 #ifdef MACHFB_DEBUG 1957 printf("machfb_fbclose()\n"); 1958 #endif 1959 mach64_init_engine(sc); 1960 mach64_init_lut(sc); 1961 sc->sc_locked = 0; 1962 return 0; 1963 } 1964 1965 int 1966 machfb_fbioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1967 { 1968 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1969 1970 #ifdef MACHFB_DEBUG 1971 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 1972 #endif 1973 switch (cmd) { 1974 case FBIOGTYPE: 1975 *(struct fbtype *)data = sc->sc_fb.fb_type; 1976 break; 1977 1978 case FBIOGATTR: 1979 #define fba ((struct fbgattr *)data) 1980 fba->real_type = sc->sc_fb.fb_type.fb_type; 1981 fba->owner = 0; /* XXX ??? */ 1982 fba->fbtype = sc->sc_fb.fb_type; 1983 fba->sattr.flags = 0; 1984 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 1985 fba->sattr.dev_specific[0] = sc->sc_nbus; 1986 fba->sattr.dev_specific[1] = sc->sc_ndev; 1987 fba->sattr.dev_specific[2] = sc->sc_nfunc; 1988 fba->sattr.dev_specific[3] = -1; 1989 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 1990 fba->emu_types[1] = -1; 1991 #undef fba 1992 break; 1993 1994 #if 0 1995 case FBIOGETCMAP: 1996 #define p ((struct fbcmap *)data) 1997 return bt_getcmap(p, &sc->sc_cmap, 256, 1); 1998 1999 case FBIOPUTCMAP: 2000 /* copy to software map */ 2001 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 2002 if (error) 2003 return error; 2004 /* now blast them into the chip */ 2005 /* XXX should use retrace interrupt */ 2006 cg6_loadcmap(sc, p->index, p->count); 2007 #undef p 2008 break; 2009 #endif 2010 case FBIOGVIDEO: 2011 *(int *)data = sc->sc_blanked; 2012 break; 2013 2014 case FBIOSVIDEO: 2015 machfb_blank(sc, *(int *)data); 2016 break; 2017 2018 #if 0 2019 case FBIOGCURSOR: 2020 break; 2021 2022 case FBIOSCURSOR: 2023 break; 2024 2025 case FBIOGCURPOS: 2026 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 2027 break; 2028 2029 case FBIOSCURPOS: 2030 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 2031 break; 2032 2033 case FBIOGCURMAX: 2034 /* max cursor size is 32x32 */ 2035 ((struct fbcurpos *)data)->x = 32; 2036 ((struct fbcurpos *)data)->y = 32; 2037 break; 2038 #endif 2039 case PCI_IOC_CFGREAD: 2040 case PCI_IOC_CFGWRITE: { 2041 int ret; 2042 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 2043 cmd, data, flags, l); 2044 2045 #ifdef MACHFB_DEBUG 2046 printf("pci_devioctl: %d\n", ret); 2047 #endif 2048 return ret; 2049 } 2050 2051 case WSDISPLAYIO_GET_BUSID: 2052 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 2053 sc->sc_pcitag, data); 2054 2055 default: 2056 return ENOTTY; 2057 } 2058 #ifdef MACHFB_DEBUG 2059 printf("machfb_fbioctl done\n"); 2060 #endif 2061 return 0; 2062 } 2063 2064 paddr_t 2065 machfb_fbmmap(dev_t dev, off_t off, int prot) 2066 { 2067 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 2068 2069 if (sc != NULL) 2070 return mach64_mmap(&sc->vd, NULL, off, prot); 2071 2072 return 0; 2073 } 2074 2075 #endif /* __sparc__ */ 2076
Indexes created Thu Oct 02 14:10:14 GMT 2025