machfb.c revision 1.76
1 /* $NetBSD: machfb.c,v 1.76 2012/06/14 00:15:07 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.76 2012/06/14 00:15:07 macallan Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #ifdef __sparc__ 58 #include <dev/sun/fbio.h> 59 #include <dev/sun/fbvar.h> 60 #include <sys/conf.h> 61 #else 62 #include <dev/wscons/wsdisplayvar.h> 63 #endif 64 65 #include <dev/wscons/wsconsio.h> 66 #include <dev/wsfont/wsfont.h> 67 #include <dev/rasops/rasops.h> 68 #include <dev/pci/wsdisplay_pci.h> 69 70 #include <dev/wscons/wsdisplay_vconsvar.h> 71 72 #include "opt_wsemul.h" 73 #include "opt_machfb.h" 74 75 #define MACH64_REG_SIZE 1024 76 #define MACH64_REG_OFF 0x7ffc00 77 78 #define NBARS 3 /* number of Mach64 PCI BARs */ 79 80 struct vga_bar { 81 bus_addr_t vb_base; 82 pcireg_t vb_busaddr; 83 bus_size_t vb_size; 84 pcireg_t vb_type; 85 int vb_flags; 86 }; 87 88 struct mach64_softc { 89 device_t sc_dev; 90 #ifdef __sparc__ 91 struct fbdevice sc_fb; 92 #endif 93 pci_chipset_tag_t sc_pc; 94 pcitag_t sc_pcitag; 95 96 struct vga_bar sc_bars[NBARS]; 97 struct vga_bar sc_rom; 98 99 #define sc_aperbase sc_bars[0].vb_base 100 #define sc_apersize sc_bars[0].vb_size 101 #define sc_aperphys sc_bars[0].vb_busaddr 102 103 #define sc_iobase sc_bars[1].vb_base 104 #define sc_iosize sc_bars[1].vb_size 105 106 #define sc_regbase sc_bars[2].vb_base 107 #define sc_regsize sc_bars[2].vb_size 108 #define sc_regphys sc_bars[2].vb_busaddr 109 110 bus_space_tag_t sc_regt; 111 bus_space_tag_t sc_memt; 112 bus_space_tag_t sc_iot; 113 bus_space_handle_t sc_regh; 114 bus_space_handle_t sc_memh; 115 void *sc_aperture; /* mapped aperture vaddr */ 116 void *sc_registers; /* mapped registers vaddr */ 117 118 uint32_t sc_nbus, sc_ndev, sc_nfunc; 119 size_t memsize; 120 int memtype; 121 122 int sc_mode; 123 int sc_bg; 124 int sc_locked; 125 126 int has_dsp; 127 int bits_per_pixel; 128 int max_x; 129 int max_y; 130 int virt_x; 131 int virt_y; 132 int color_depth; 133 134 int mem_freq; 135 int ramdac_freq; 136 int ref_freq; 137 138 int ref_div; 139 int log2_vclk_post_div; 140 int vclk_post_div; 141 int vclk_fb_div; 142 int mclk_post_div; 143 int mclk_fb_div; 144 int sc_clock; /* which clock to use */ 145 146 struct videomode *sc_my_mode; 147 int sc_edid_size; 148 uint8_t sc_edid_data[1024]; 149 150 u_char sc_cmap_red[256]; 151 u_char sc_cmap_green[256]; 152 u_char sc_cmap_blue[256]; 153 int sc_dacw, sc_blanked, sc_console; 154 struct vcons_data vd; 155 struct wsdisplay_accessops sc_accessops; 156 }; 157 158 struct mach64_crtcregs { 159 uint32_t h_total_disp; 160 uint32_t h_sync_strt_wid; 161 uint32_t v_total_disp; 162 uint32_t v_sync_strt_wid; 163 uint32_t gen_cntl; 164 uint32_t clock_cntl; 165 uint32_t color_depth; 166 uint32_t dot_clock; 167 }; 168 169 static struct { 170 uint16_t chip_id; 171 uint32_t ramdac_freq; 172 } const mach64_info[] = { 173 { PCI_PRODUCT_ATI_MACH64_GX, 135000 }, 174 { PCI_PRODUCT_ATI_MACH64_CX, 135000 }, 175 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 176 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 185 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 186 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 189 #if 0 190 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 192 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 193 #endif 194 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 195 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 196 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 197 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 198 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 199 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 200 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 201 }; 202 203 static int mach64_chip_id, mach64_chip_rev; 204 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 205 206 static const char *mach64_gx_memtype_names[] = { 207 "DRAM", "VRAM", "VRAM", "DRAM", 208 "DRAM", "VRAM", "VRAM", "(unknown type)" 209 }; 210 211 static const char *mach64_memtype_names[] = { 212 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 213 "(unknown type)" 214 }; 215 216 static struct videomode mach64_modes[] = { 217 /* 640x400 @ 70 Hz, 31.5 kHz */ 218 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0, NULL, }, 219 /* 640x480 @ 72 Hz, 36.5 kHz */ 220 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0, NULL, }, 221 /* 800x600 @ 72 Hz, 48.0 kHz */ 222 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 223 VID_PHSYNC | VID_PVSYNC, NULL, }, 224 /* 1024x768 @ 70 Hz, 56.5 kHz */ 225 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 226 VID_NHSYNC | VID_NVSYNC, NULL, }, 227 /* 1152x864 @ 70 Hz, 62.4 kHz */ 228 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0, NULL, }, 229 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 230 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 231 VID_NHSYNC | VID_NVSYNC, NULL, } 232 }; 233 234 extern const u_char rasops_cmap[768]; 235 236 static int mach64_match(device_t, cfdata_t, void *); 237 static void mach64_attach(device_t, device_t, void *); 238 239 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 240 NULL, NULL); 241 242 static void mach64_init(struct mach64_softc *); 243 static int mach64_get_memsize(struct mach64_softc *); 244 static int mach64_get_max_ramdac(struct mach64_softc *); 245 246 #if defined(__sparc__) || defined(__powerpc__) 247 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 248 #endif 249 250 static int mach64_calc_crtcregs(struct mach64_softc *, 251 struct mach64_crtcregs *, 252 struct videomode *); 253 static void mach64_set_crtcregs(struct mach64_softc *, 254 struct mach64_crtcregs *); 255 256 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 257 static void mach64_set_dsp(struct mach64_softc *); 258 static void mach64_set_pll(struct mach64_softc *, int); 259 static void mach64_reset_engine(struct mach64_softc *); 260 static void mach64_init_engine(struct mach64_softc *); 261 #if 0 262 static void mach64_adjust_frame(struct mach64_softc *, int, int); 263 #endif 264 static void mach64_init_lut(struct mach64_softc *); 265 266 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 267 static int mach64_set_screentype(struct mach64_softc *, 268 const struct wsscreen_descr *); 269 static int mach64_is_console(struct mach64_softc *); 270 271 static void mach64_cursor(void *, int, int, int); 272 #if 0 273 static int mach64_mapchar(void *, int, u_int *); 274 #endif 275 static void mach64_putchar(void *, int, int, u_int, long); 276 static void mach64_copycols(void *, int, int, int, int); 277 static void mach64_erasecols(void *, int, int, int, long); 278 static void mach64_copyrows(void *, int, int, int); 279 static void mach64_eraserows(void *, int, int, long); 280 static void mach64_clearscreen(struct mach64_softc *); 281 282 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 283 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 284 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 285 uint8_t, uint8_t); 286 static void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, 287 int, int, int) ; 288 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 289 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 290 uint32_t, uint32_t); 291 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 292 #if 0 293 static void mach64_showpal(struct mach64_softc *); 294 #endif 295 296 static void set_address(struct rasops_info *, void *); 297 static void machfb_blank(struct mach64_softc *, int); 298 static int machfb_drm_print(void *, const char *); 299 300 static struct wsscreen_descr mach64_defaultscreen = { 301 "default", 302 80, 30, 303 NULL, 304 8, 16, 305 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 306 &default_mode 307 }, mach64_80x25_screen = { 308 "80x25", 80, 25, 309 NULL, 310 8, 16, 311 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 312 &mach64_modes[0] 313 }, mach64_80x30_screen = { 314 "80x30", 80, 30, 315 NULL, 316 8, 16, 317 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 318 &mach64_modes[1] 319 }, mach64_80x40_screen = { 320 "80x40", 80, 40, 321 NULL, 322 8, 10, 323 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 324 &mach64_modes[0] 325 }, mach64_80x50_screen = { 326 "80x50", 80, 50, 327 NULL, 328 8, 8, 329 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 330 &mach64_modes[0] 331 }, mach64_100x37_screen = { 332 "100x37", 100, 37, 333 NULL, 334 8, 16, 335 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 336 &mach64_modes[2] 337 }, mach64_128x48_screen = { 338 "128x48", 128, 48, 339 NULL, 340 8, 16, 341 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 342 &mach64_modes[3] 343 }, mach64_144x54_screen = { 344 "144x54", 144, 54, 345 NULL, 346 8, 16, 347 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 348 &mach64_modes[4] 349 }, mach64_160x64_screen = { 350 "160x54", 160, 64, 351 NULL, 352 8, 16, 353 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 354 &mach64_modes[5] 355 }; 356 357 static const struct wsscreen_descr *_mach64_scrlist[] = { 358 &mach64_defaultscreen, 359 &mach64_80x25_screen, 360 &mach64_80x30_screen, 361 &mach64_80x40_screen, 362 &mach64_80x50_screen, 363 &mach64_100x37_screen, 364 &mach64_128x48_screen, 365 &mach64_144x54_screen, 366 &mach64_160x64_screen 367 }; 368 369 static struct wsscreen_list mach64_screenlist = { 370 __arraycount(_mach64_scrlist), 371 _mach64_scrlist 372 }; 373 374 static int mach64_ioctl(void *, void *, u_long, void *, int, 375 struct lwp *); 376 static paddr_t mach64_mmap(void *, void *, off_t, int); 377 378 #if 0 379 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 380 #endif 381 382 383 static struct vcons_screen mach64_console_screen; 384 385 /* framebuffer device, SPARC-only so far */ 386 #ifdef __sparc__ 387 388 static void machfb_unblank(device_t); 389 static void machfb_fbattach(struct mach64_softc *); 390 391 extern struct cfdriver machfb_cd; 392 393 dev_type_open(machfb_fbopen); 394 dev_type_close(machfb_fbclose); 395 dev_type_ioctl(machfb_fbioctl); 396 dev_type_mmap(machfb_fbmmap); 397 398 /* frame buffer generic driver */ 399 static struct fbdriver machfb_fbdriver = { 400 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 401 machfb_fbmmap, nokqfilter 402 }; 403 404 #endif /* __sparc__ */ 405 406 /* 407 * Inline functions for getting access to register aperture. 408 */ 409 410 static inline uint32_t 411 regr(struct mach64_softc *sc, uint32_t index) 412 { 413 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 414 } 415 416 static inline uint8_t 417 regrb(struct mach64_softc *sc, uint32_t index) 418 { 419 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 420 } 421 422 static inline void 423 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 424 { 425 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 426 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 427 BUS_SPACE_BARRIER_WRITE); 428 } 429 430 static inline void 431 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 432 { 433 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 434 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 435 BUS_SPACE_BARRIER_WRITE); 436 } 437 438 static inline void 439 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 440 { 441 uint32_t reg; 442 443 reg = regr(sc, CLOCK_CNTL); 444 reg |= PLL_WR_EN; 445 regw(sc, CLOCK_CNTL, reg); 446 reg &= ~(PLL_ADDR | PLL_DATA); 447 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 448 reg |= data << PLL_DATA_SHIFT; 449 reg |= CLOCK_STROBE; 450 regw(sc, CLOCK_CNTL, reg); 451 reg &= ~PLL_WR_EN; 452 regw(sc, CLOCK_CNTL, reg); 453 } 454 455 static inline uint8_t 456 regrb_pll(struct mach64_softc *sc, uint32_t index) 457 { 458 459 regwb(sc, CLOCK_CNTL + 1, index << 2); 460 return regrb(sc, CLOCK_CNTL + 2); 461 } 462 463 static inline void 464 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 465 { 466 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 467 continue; 468 } 469 470 static inline void 471 wait_for_idle(struct mach64_softc *sc) 472 { 473 wait_for_fifo(sc, 16); 474 while ((regr(sc, GUI_STAT) & 1) != 0) 475 continue; 476 } 477 478 static int 479 mach64_match(device_t parent, cfdata_t match, void *aux) 480 { 481 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 482 int i; 483 484 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 485 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 486 return 0; 487 488 for (i = 0; i < __arraycount(mach64_info); i++) 489 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 490 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 491 mach64_chip_rev = PCI_REVISION(pa->pa_class); 492 return 100; 493 } 494 495 return 0; 496 } 497 498 static void 499 mach64_attach(device_t parent, device_t self, void *aux) 500 { 501 struct mach64_softc *sc = device_private(self); 502 struct pci_attach_args *pa = aux; 503 struct rasops_info *ri; 504 prop_data_t edid_data; 505 #if defined(__sparc__) || defined(__powerpc__) 506 const struct videomode *mode = NULL; 507 #endif 508 int bar, id, expected_id; 509 int is_gx; 510 const char **memtype_names; 511 struct wsemuldisplaydev_attach_args aa; 512 long defattr; 513 int setmode, width, height; 514 pcireg_t screg; 515 uint32_t reg; 516 const pcireg_t enables = PCI_COMMAND_MEM_ENABLE; 517 518 sc->sc_dev = self; 519 sc->sc_pc = pa->pa_pc; 520 sc->sc_pcitag = pa->pa_tag; 521 sc->sc_dacw = -1; 522 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 523 sc->sc_nbus = pa->pa_bus; 524 sc->sc_ndev = pa->pa_device; 525 sc->sc_nfunc = pa->pa_function; 526 sc->sc_locked = 0; 527 sc->sc_iot = pa->pa_iot; 528 sc->sc_accessops.ioctl = mach64_ioctl; 529 sc->sc_accessops.mmap = mach64_mmap; 530 531 pci_aprint_devinfo(pa, "Graphics processor"); 532 #ifdef MACHFB_DEBUG 533 printf(prop_dictionary_externalize(device_properties(self))); 534 #endif 535 536 /* enable memory access */ 537 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 538 if ((screg & enables) != enables) { 539 screg |= enables; 540 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 541 PCI_COMMAND_STATUS_REG, screg); 542 } 543 for (bar = 0; bar < NBARS; bar++) { 544 reg = PCI_MAPREG_START + (bar * 4); 545 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 546 sc->sc_pcitag, reg); 547 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 548 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 549 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 550 sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc, 551 sc->sc_pcitag, reg) & 0xfffffff0; 552 } 553 aprint_debug_dev(sc->sc_dev, "aperture size %08x\n", 554 (uint32_t)sc->sc_apersize); 555 556 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 557 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 558 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 559 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 560 sc->sc_memt = pa->pa_memt; 561 562 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 563 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 564 panic("%s: failed to map aperture", device_xname(sc->sc_dev)); 565 } 566 sc->sc_aperture = (void *)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 567 568 /* If the BAR was never mapped, fix it up in MMIO. */ 569 if(sc->sc_regsize == 0) { 570 sc->sc_regsize = MACH64_REG_SIZE; 571 sc->sc_regbase = sc->sc_aperbase + MACH64_REG_OFF; 572 sc->sc_regphys = sc->sc_aperphys + MACH64_REG_OFF; 573 } 574 575 sc->sc_regt = sc->sc_memt; 576 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 577 sc->sc_regsize, &sc->sc_regh); 578 sc->sc_registers = (char *)sc->sc_aperture + 0x7ffc00; 579 580 mach64_init(sc); 581 582 aprint_normal_dev(sc->sc_dev, 583 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 584 (u_int)(sc->sc_apersize / (1024 * 1024)), 585 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 586 (u_int)sc->sc_regphys); 587 588 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 589 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 590 591 prop_dictionary_get_uint32(device_properties(self), "width", &width); 592 prop_dictionary_get_uint32(device_properties(self), "height", &height); 593 594 if ((edid_data = prop_dictionary_get(device_properties(self), "EDID")) 595 != NULL) { 596 struct edid_info ei; 597 598 sc->sc_edid_size = min(1024, prop_data_size(edid_data)); 599 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 600 memcpy(sc->sc_edid_data, prop_data_data_nocopy(edid_data), 601 sc->sc_edid_size); 602 603 edid_parse(sc->sc_edid_data, &ei); 604 605 #ifdef MACHFB_DEBUG 606 edid_print(&ei); 607 #endif 608 } 609 610 is_gx = 0; 611 switch(mach64_chip_id) { 612 case PCI_PRODUCT_ATI_MACH64_GX: 613 case PCI_PRODUCT_ATI_MACH64_CX: 614 is_gx = 1; 615 case PCI_PRODUCT_ATI_MACH64_CT: 616 sc->has_dsp = 0; 617 break; 618 case PCI_PRODUCT_ATI_MACH64_VT: 619 case PCI_PRODUCT_ATI_RAGE_II: 620 if((mach64_chip_rev & 0x07) == 0) { 621 sc->has_dsp = 0; 622 break; 623 } 624 /* Otherwise fall through. */ 625 default: 626 sc->has_dsp = 1; 627 } 628 629 memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names; 630 631 sc->memsize = mach64_get_memsize(sc); 632 if (sc->memsize == 8192) 633 /* The last page is used as register aperture. */ 634 sc->memsize -= 4; 635 if(is_gx) 636 sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07; 637 else 638 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 639 640 /* 641 * XXX is there any way to calculate reference frequency from 642 * known values? 643 */ 644 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 645 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 646 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 647 aprint_normal_dev(sc->sc_dev, "ref_freq=29.498MHz\n"); 648 sc->ref_freq = 29498; 649 } else 650 sc->ref_freq = 14318; 651 652 reg = regr(sc, CLOCK_CNTL); 653 aprint_debug("CLOCK_CNTL: %08x\n", reg); 654 sc->sc_clock = reg & 3; 655 aprint_debug("using clock %d\n", sc->sc_clock); 656 657 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 658 aprint_debug("ref_div: %d\n", sc->ref_div); 659 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 660 aprint_debug("mclk_fb_div: %d\n", sc->mclk_fb_div); 661 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 662 (sc->ref_div * 2); 663 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 664 (sc->mem_freq * sc->ref_div); 665 sc->ramdac_freq = mach64_get_max_ramdac(sc); 666 aprint_normal_dev(sc->sc_dev, 667 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 668 (u_long)sc->memsize, 669 memtype_names[sc->memtype], 670 sc->mem_freq / 1000, sc->mem_freq % 1000, 671 sc->ramdac_freq / 1000); 672 673 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 674 switch(mach64_chip_id) { 675 case PCI_PRODUCT_ATI_MACH64_GX: 676 expected_id = 0x00d7; 677 break; 678 case PCI_PRODUCT_ATI_MACH64_CX: 679 expected_id = 0x0057; 680 break; 681 default: 682 /* Most chip IDs match their PCI product ID. */ 683 expected_id = mach64_chip_id; 684 } 685 686 if (id != expected_id) { 687 aprint_error_dev(sc->sc_dev, 688 "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id); 689 return; 690 } 691 692 sc->sc_console = mach64_is_console(sc); 693 aprint_debug("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 694 #if defined(__sparc__) || defined(__powerpc__) 695 if (sc->sc_console) { 696 if (mode != NULL) { 697 memcpy(&default_mode, mode, sizeof(struct videomode)); 698 setmode = 1; 699 } else { 700 mach64_get_mode(sc, &default_mode); 701 setmode = 0; 702 } 703 sc->sc_my_mode = &default_mode; 704 } else { 705 /* fill in default_mode if it's empty */ 706 mach64_get_mode(sc, &default_mode); 707 if (default_mode.dot_clock == 0) { 708 memcpy(&default_mode, &mach64_modes[4], 709 sizeof(default_mode)); 710 } 711 sc->sc_my_mode = &default_mode; 712 setmode = 1; 713 } 714 #else 715 if (default_mode.dot_clock == 0) { 716 memcpy(&default_mode, &mach64_modes[0], 717 sizeof(default_mode)); 718 } 719 sc->sc_my_mode = &mach64_modes[0]; 720 setmode = 1; 721 #endif 722 723 sc->bits_per_pixel = 8; 724 sc->virt_x = sc->sc_my_mode->hdisplay; 725 sc->virt_y = sc->sc_my_mode->vdisplay; 726 sc->max_x = sc->virt_x - 1; 727 sc->max_y = (sc->memsize * 1024) / 728 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 729 730 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 731 732 mach64_init_engine(sc); 733 734 if (setmode) 735 mach64_modeswitch(sc, sc->sc_my_mode); 736 737 aprint_normal_dev(sc->sc_dev, 738 "initial resolution %dx%d at %d bpp\n", 739 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 740 sc->bits_per_pixel); 741 742 #ifdef __sparc__ 743 machfb_fbattach(sc); 744 #endif 745 746 wsfont_init(); 747 748 sc->sc_bg = WS_DEFAULT_BG; 749 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &sc->sc_accessops); 750 sc->vd.init_screen = mach64_init_screen; 751 752 mach64_init_lut(sc); 753 mach64_clearscreen(sc); 754 machfb_blank(sc, 0); /* unblank the screen */ 755 756 if (sc->sc_console) { 757 758 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 759 &defattr); 760 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 761 762 ri = &mach64_console_screen.scr_ri; 763 mach64_defaultscreen.textops = &ri->ri_ops; 764 mach64_defaultscreen.capabilities = ri->ri_caps; 765 mach64_defaultscreen.nrows = ri->ri_rows; 766 mach64_defaultscreen.ncols = ri->ri_cols; 767 768 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 769 vcons_replay_msgbuf(&mach64_console_screen); 770 } else { 771 /* 772 * since we're not the console we can postpone the rest 773 * until someone actually allocates a screen for us 774 */ 775 mach64_modeswitch(sc, sc->sc_my_mode); 776 } 777 778 aa.console = sc->sc_console; 779 aa.scrdata = &mach64_screenlist; 780 aa.accessops = &sc->sc_accessops; 781 aa.accesscookie = &sc->vd; 782 783 config_found(self, &aa, wsemuldisplaydevprint); 784 785 config_found_ia(self, "drm", aux, machfb_drm_print); 786 } 787 788 static int 789 machfb_drm_print(void *aux, const char *pnp) 790 { 791 if (pnp) 792 aprint_normal("direct rendering for %s", pnp); 793 return (UNSUPP); 794 } 795 796 static void 797 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 798 long *defattr) 799 { 800 struct mach64_softc *sc = cookie; 801 struct rasops_info *ri = &scr->scr_ri; 802 803 /* XXX for now */ 804 #define setmode 0 805 806 ri->ri_depth = sc->bits_per_pixel; 807 ri->ri_width = sc->sc_my_mode->hdisplay; 808 ri->ri_height = sc->sc_my_mode->vdisplay; 809 ri->ri_stride = ri->ri_width; 810 ri->ri_flg = RI_CENTER; 811 set_address(ri, sc->sc_aperture); 812 813 #ifdef VCONS_DRAW_INTR 814 scr->scr_flags |= VCONS_DONT_READ; 815 #endif 816 817 if (existing) { 818 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 819 panic("%s: failed to switch video mode", 820 device_xname(sc->sc_dev)); 821 } 822 } 823 824 rasops_init(ri, 0, 0); 825 ri->ri_caps = WSSCREEN_WSCOLORS; 826 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 827 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 828 829 /* enable acceleration */ 830 ri->ri_hw = scr; 831 ri->ri_ops.copyrows = mach64_copyrows; 832 ri->ri_ops.copycols = mach64_copycols; 833 ri->ri_ops.eraserows = mach64_eraserows; 834 ri->ri_ops.erasecols = mach64_erasecols; 835 ri->ri_ops.cursor = mach64_cursor; 836 ri->ri_ops.putchar = mach64_putchar; 837 } 838 839 static void 840 mach64_init(struct mach64_softc *sc) 841 { 842 uint32_t *p32, saved_value; 843 uint8_t *p; 844 int need_swap; 845 846 /* 847 * Test whether the aperture is byte swapped or not 848 */ 849 p32 = (uint32_t*)sc->sc_aperture; 850 saved_value = *p32; 851 p = (uint8_t*)(u_long)sc->sc_aperture; 852 *p32 = 0x12345678; 853 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 854 need_swap = 0; 855 else 856 need_swap = 1; 857 if (need_swap) { 858 sc->sc_aperture = (char *)sc->sc_aperture + 0x800000; 859 #if 0 860 /* what the fsck is this for? */ 861 sc->sc_aperbase += 0x800000; 862 sc->sc_apersize -= 0x800000; 863 #endif 864 } 865 *p32 = saved_value; 866 867 sc->sc_blanked = 0; 868 } 869 870 static int 871 mach64_get_memsize(struct mach64_softc *sc) 872 { 873 int tmp, memsize; 874 int mem_tab[] = { 875 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 876 }; 877 tmp = regr(sc, MEM_CNTL); 878 #ifdef DIAGNOSTIC 879 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 880 #endif 881 if (sc->has_dsp) { 882 tmp &= 0x0000000f; 883 if (tmp < 8) 884 memsize = (tmp + 1) * 512; 885 else if (tmp < 12) 886 memsize = (tmp - 3) * 1024; 887 else 888 memsize = (tmp - 7) * 2048; 889 } else { 890 memsize = mem_tab[tmp & 0x07]; 891 } 892 893 return memsize; 894 } 895 896 static int 897 mach64_get_max_ramdac(struct mach64_softc *sc) 898 { 899 int i; 900 901 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 902 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 903 (mach64_chip_rev & 0x07)) 904 return 170000; 905 906 for (i = 0; i < __arraycount(mach64_info); i++) 907 if (mach64_chip_id == mach64_info[i].chip_id) 908 return mach64_info[i].ramdac_freq; 909 910 if (sc->bits_per_pixel == 8) 911 return 135000; 912 else 913 return 80000; 914 } 915 916 #if defined(__sparc__) || defined(__powerpc__) 917 static void 918 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 919 { 920 struct mach64_crtcregs crtc; 921 922 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 923 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 924 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 925 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 926 927 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 928 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 929 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 930 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 931 mode->hsync_start; 932 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 933 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 934 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 935 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 936 937 #ifdef MACHFB_DEBUG 938 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 939 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 940 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 941 #endif 942 } 943 #endif 944 945 static int 946 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 947 struct videomode *mode) 948 { 949 950 if (mode->dot_clock > sc->ramdac_freq) 951 /* Clock too high. */ 952 return 1; 953 954 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 955 ((mode->htotal >> 3) - 1); 956 crtc->h_sync_strt_wid = 957 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 958 ((mode->hsync_start >> 3) - 1); 959 960 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 961 (mode->vtotal - 1); 962 crtc->v_sync_strt_wid = 963 ((mode->vsync_end - mode->vsync_start) << 16) | 964 (mode->vsync_start - 1); 965 966 if (mode->flags & VID_NVSYNC) 967 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 968 969 switch (sc->bits_per_pixel) { 970 case 8: 971 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 972 break; 973 case 16: 974 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 975 break; 976 case 32: 977 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 978 break; 979 } 980 981 crtc->gen_cntl = 0; 982 if (mode->flags & VID_INTERLACE) 983 crtc->gen_cntl |= CRTC_INTERLACE_EN; 984 985 if (mode->flags & VID_CSYNC) 986 crtc->gen_cntl |= CRTC_CSYNC_EN; 987 988 crtc->dot_clock = mode->dot_clock; 989 990 return 0; 991 } 992 993 static void 994 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 995 { 996 997 mach64_set_pll(sc, crtc->dot_clock); 998 999 if (sc->has_dsp) 1000 mach64_set_dsp(sc); 1001 1002 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 1003 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1004 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 1005 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1006 1007 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 1008 1009 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1010 1011 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 1012 /* XXX this unconditionally enables composite sync on SPARC */ 1013 #ifdef __sparc__ 1014 CRTC_CSYNC_EN | 1015 #endif 1016 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 1017 } 1018 1019 static int 1020 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 1021 { 1022 struct mach64_crtcregs crtc; 1023 1024 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 1025 1026 if (mach64_calc_crtcregs(sc, &crtc, mode)) 1027 return 1; 1028 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 1029 if (crtc.dot_clock == 0) { 1030 aprint_error("%s: preposterous dot clock (%d)\n", 1031 device_xname(sc->sc_dev), crtc.dot_clock); 1032 return 1; 1033 } 1034 mach64_set_crtcregs(sc, &crtc); 1035 return 0; 1036 } 1037 1038 static void 1039 mach64_reset_engine(struct mach64_softc *sc) 1040 { 1041 1042 /* Reset engine.*/ 1043 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1044 1045 /* Enable engine. */ 1046 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1047 1048 /* Ensure engine is not locked up by clearing any FIFO or 1049 host errors. */ 1050 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1051 BUS_FIFO_ERR_ACK); 1052 } 1053 1054 static void 1055 mach64_init_engine(struct mach64_softc *sc) 1056 { 1057 uint32_t pitch_value; 1058 1059 pitch_value = sc->virt_x; 1060 1061 if (sc->bits_per_pixel == 24) 1062 pitch_value *= 3; 1063 1064 mach64_reset_engine(sc); 1065 1066 wait_for_fifo(sc, 14); 1067 1068 regw(sc, CONTEXT_MASK, 0xffffffff); 1069 1070 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 1071 1072 /* make sure the visible area starts where we're going to draw */ 1073 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1074 1075 regw(sc, DST_Y_X, 0); 1076 regw(sc, DST_HEIGHT, 0); 1077 regw(sc, DST_BRES_ERR, 0); 1078 regw(sc, DST_BRES_INC, 0); 1079 regw(sc, DST_BRES_DEC, 0); 1080 1081 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1082 DST_Y_TOP_TO_BOTTOM); 1083 1084 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 1085 1086 regw(sc, SRC_Y_X, 0); 1087 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1088 regw(sc, SRC_Y_X_START, 0); 1089 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1090 1091 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1092 1093 wait_for_fifo(sc, 13); 1094 regw(sc, HOST_CNTL, 0); 1095 1096 regw(sc, PAT_REG0, 0); 1097 regw(sc, PAT_REG1, 0); 1098 regw(sc, PAT_CNTL, 0); 1099 1100 regw(sc, SC_LEFT, 0); 1101 regw(sc, SC_TOP, 0); 1102 regw(sc, SC_BOTTOM, sc->sc_my_mode->vdisplay - 1); 1103 regw(sc, SC_RIGHT, pitch_value - 1); 1104 1105 regw(sc, DP_BKGD_CLR, WS_DEFAULT_BG); 1106 regw(sc, DP_FRGD_CLR, WS_DEFAULT_FG); 1107 regw(sc, DP_WRITE_MASK, 0xffffffff); 1108 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1109 1110 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1111 1112 wait_for_fifo(sc, 3); 1113 regw(sc, CLR_CMP_CLR, 0); 1114 regw(sc, CLR_CMP_MASK, 0xffffffff); 1115 regw(sc, CLR_CMP_CNTL, 0); 1116 1117 wait_for_fifo(sc, 2); 1118 switch (sc->bits_per_pixel) { 1119 case 8: 1120 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP); 1121 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1122 /* We want 8 bit per channel */ 1123 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1124 break; 1125 case 32: 1126 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP); 1127 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1128 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1129 break; 1130 } 1131 1132 wait_for_fifo(sc, 5); 1133 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1134 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1135 1136 wait_for_idle(sc); 1137 } 1138 1139 #if 0 1140 static void 1141 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1142 { 1143 int offset; 1144 1145 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1146 1147 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1148 offset); 1149 } 1150 #endif 1151 1152 static void 1153 mach64_set_dsp(struct mach64_softc *sc) 1154 { 1155 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1156 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1157 uint32_t xclks_per_qw, y; 1158 uint32_t fifo_off, fifo_on; 1159 1160 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1161 1162 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1163 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1164 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1165 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1166 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1167 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1168 dsp_loop_latency = 0; 1169 fifo_depth = 24; 1170 } else { 1171 dsp_loop_latency = 2; 1172 fifo_depth = 32; 1173 } 1174 1175 dsp_precision = 0; 1176 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1177 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1178 y = (xclks_per_qw * fifo_depth) >> 11; 1179 while (y) { 1180 y >>= 1; 1181 dsp_precision++; 1182 } 1183 dsp_precision -= 5; 1184 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1185 1186 switch (sc->memtype) { 1187 case DRAM: 1188 case EDO_DRAM: 1189 case PSEUDO_EDO: 1190 if (sc->memsize > 1024) { 1191 page_size = 9; 1192 dsp_loop_latency += 6; 1193 } else { 1194 page_size = 10; 1195 if (sc->memtype == DRAM) 1196 dsp_loop_latency += 8; 1197 else 1198 dsp_loop_latency += 7; 1199 } 1200 break; 1201 case SDRAM: 1202 case SGRAM: 1203 if (sc->memsize > 1024) { 1204 page_size = 8; 1205 dsp_loop_latency += 8; 1206 } else { 1207 page_size = 10; 1208 dsp_loop_latency += 9; 1209 } 1210 break; 1211 default: 1212 page_size = 10; 1213 dsp_loop_latency += 9; 1214 break; 1215 } 1216 1217 if (xclks_per_qw >= (page_size << 11)) 1218 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1219 else 1220 fifo_on = (3 * page_size + 2) << 6; 1221 1222 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1223 dsp_on = fifo_on >> dsp_precision; 1224 dsp_off = fifo_off >> dsp_precision; 1225 1226 #ifdef MACHFB_DEBUG 1227 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1228 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1229 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1230 "mclk_post_div = %d, vclk_post_div = %d\n", 1231 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1232 sc->mclk_fb_div, sc->vclk_fb_div, 1233 sc->mclk_post_div, sc->vclk_post_div); 1234 #endif 1235 1236 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1237 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1238 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1239 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1240 } 1241 1242 static void 1243 mach64_set_pll(struct mach64_softc *sc, int clock) 1244 { 1245 uint32_t q, clockreg; 1246 int clockshift = sc->sc_clock << 1; 1247 uint8_t reg, vclk_ctl; 1248 1249 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1250 #ifdef MACHFB_DEBUG 1251 printf("q = %d\n", q); 1252 #endif 1253 if (q > 25500) { 1254 aprint_error_dev(sc->sc_dev, "Warning: q > 25500\n"); 1255 q = 25500; 1256 sc->vclk_post_div = 1; 1257 sc->log2_vclk_post_div = 0; 1258 } else if (q > 12750) { 1259 sc->vclk_post_div = 1; 1260 sc->log2_vclk_post_div = 0; 1261 } else if (q > 6350) { 1262 sc->vclk_post_div = 2; 1263 sc->log2_vclk_post_div = 1; 1264 } else if (q > 3150) { 1265 sc->vclk_post_div = 4; 1266 sc->log2_vclk_post_div = 2; 1267 } else if (q >= 1600) { 1268 sc->vclk_post_div = 8; 1269 sc->log2_vclk_post_div = 3; 1270 } else { 1271 aprint_error_dev(sc->sc_dev, "Warning: q < 1600\n"); 1272 sc->vclk_post_div = 8; 1273 sc->log2_vclk_post_div = 3; 1274 } 1275 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1276 aprint_debug("post_div: %d log2_post_div: %d mclk_div: %d\n", 1277 sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1278 1279 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1280 aprint_debug("vclk_ctl: %02x\n", vclk_ctl); 1281 vclk_ctl |= PLL_VCLK_RESET; 1282 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1283 1284 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1285 reg = regrb_pll(sc, VCLK_POST_DIV); 1286 reg &= ~(3 << clockshift); 1287 reg |= (sc->log2_vclk_post_div << clockshift); 1288 regwb_pll(sc, VCLK_POST_DIV, reg); 1289 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1290 1291 vclk_ctl &= ~PLL_VCLK_RESET; 1292 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1293 1294 clockreg = regr(sc, CLOCK_CNTL); 1295 clockreg &= ~CLOCK_SEL; 1296 clockreg |= sc->sc_clock | CLOCK_STROBE; 1297 regw(sc, CLOCK_CNTL, clockreg); 1298 } 1299 1300 static void 1301 mach64_init_lut(struct mach64_softc *sc) 1302 { 1303 int i, idx; 1304 1305 idx = 0; 1306 for (i = 0; i < 256; i++) { 1307 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1], 1308 rasops_cmap[idx + 2]); 1309 idx += 3; 1310 } 1311 } 1312 1313 static int 1314 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1315 uint8_t b) 1316 { 1317 sc->sc_cmap_red[index] = r; 1318 sc->sc_cmap_green[index] = g; 1319 sc->sc_cmap_blue[index] = b; 1320 /* 1321 * writing the dac index takes a while, in theory we can poll some 1322 * register to see when it's ready - but we better avoid writing it 1323 * unnecessarily 1324 */ 1325 if (index != sc->sc_dacw) { 1326 regwb(sc, DAC_MASK, 0xff); 1327 regwb(sc, DAC_WINDEX, index); 1328 } 1329 sc->sc_dacw = index + 1; 1330 regwb(sc, DAC_DATA, r); 1331 regwb(sc, DAC_DATA, g); 1332 regwb(sc, DAC_DATA, b); 1333 return 0; 1334 } 1335 1336 static int 1337 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1338 { 1339 uint index = cm->index; 1340 uint count = cm->count; 1341 int i, error; 1342 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1343 uint8_t *r, *g, *b; 1344 1345 if (cm->index >= 256 || cm->count > 256 || 1346 (cm->index + cm->count) > 256) 1347 return EINVAL; 1348 error = copyin(cm->red, &rbuf[index], count); 1349 if (error) 1350 return error; 1351 error = copyin(cm->green, &gbuf[index], count); 1352 if (error) 1353 return error; 1354 error = copyin(cm->blue, &bbuf[index], count); 1355 if (error) 1356 return error; 1357 1358 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1359 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1360 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1361 1362 r = &sc->sc_cmap_red[index]; 1363 g = &sc->sc_cmap_green[index]; 1364 b = &sc->sc_cmap_blue[index]; 1365 1366 for (i = 0; i < count; i++) { 1367 mach64_putpalreg(sc, index, *r, *g, *b); 1368 index++; 1369 r++, g++, b++; 1370 } 1371 return 0; 1372 } 1373 1374 static int 1375 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1376 { 1377 u_int index = cm->index; 1378 u_int count = cm->count; 1379 int error; 1380 1381 if (index >= 255 || count > 256 || index + count > 256) 1382 return EINVAL; 1383 1384 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1385 if (error) 1386 return error; 1387 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1388 if (error) 1389 return error; 1390 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1391 if (error) 1392 return error; 1393 1394 return 0; 1395 } 1396 1397 static int 1398 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1399 { 1400 struct mach64_crtcregs regs; 1401 1402 if (mach64_calc_crtcregs(sc, ®s, 1403 (struct videomode *)des->modecookie)) 1404 return 1; 1405 1406 mach64_set_crtcregs(sc, ®s); 1407 return 0; 1408 } 1409 1410 static int 1411 mach64_is_console(struct mach64_softc *sc) 1412 { 1413 bool console = 0; 1414 1415 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1416 "is_console", &console); 1417 return console; 1418 } 1419 1420 /* 1421 * wsdisplay_emulops 1422 */ 1423 1424 static void 1425 mach64_cursor(void *cookie, int on, int row, int col) 1426 { 1427 struct rasops_info *ri = cookie; 1428 struct vcons_screen *scr = ri->ri_hw; 1429 struct mach64_softc *sc = scr->scr_cookie; 1430 int x, y, wi, he; 1431 1432 wi = ri->ri_font->fontwidth; 1433 he = ri->ri_font->fontheight; 1434 1435 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1436 x = ri->ri_ccol * wi + ri->ri_xorigin; 1437 y = ri->ri_crow * he + ri->ri_yorigin; 1438 if (ri->ri_flg & RI_CURSOR) { 1439 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1440 0xff); 1441 ri->ri_flg &= ~RI_CURSOR; 1442 } 1443 ri->ri_crow = row; 1444 ri->ri_ccol = col; 1445 if (on) { 1446 x = ri->ri_ccol * wi + ri->ri_xorigin; 1447 y = ri->ri_crow * he + ri->ri_yorigin; 1448 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1449 0xff); 1450 ri->ri_flg |= RI_CURSOR; 1451 } 1452 } else { 1453 scr->scr_ri.ri_crow = row; 1454 scr->scr_ri.ri_ccol = col; 1455 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1456 } 1457 } 1458 1459 #if 0 1460 static int 1461 mach64_mapchar(void *cookie, int uni, u_int *index) 1462 { 1463 return 0; 1464 } 1465 #endif 1466 1467 static void 1468 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1469 { 1470 struct rasops_info *ri = cookie; 1471 struct wsdisplay_font *font = PICK_FONT(ri, c); 1472 struct vcons_screen *scr = ri->ri_hw; 1473 struct mach64_softc *sc = scr->scr_cookie; 1474 1475 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1476 int fg, bg, uc; 1477 uint8_t *data; 1478 int x, y, wi, he; 1479 wi = font->fontwidth; 1480 he = font->fontheight; 1481 1482 if (!CHAR_IN_FONT(c, font)) 1483 return; 1484 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1485 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f]; 1486 x = ri->ri_xorigin + col * wi; 1487 y = ri->ri_yorigin + row * he; 1488 if (c == 0x20) { 1489 mach64_rectfill(sc, x, y, wi, he, bg); 1490 } else { 1491 uc = c - font->firstchar; 1492 data = (uint8_t *)font->data + uc * 1493 ri->ri_fontscale; 1494 1495 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1496 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1497 } 1498 } 1499 } 1500 1501 1502 static void 1503 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1504 { 1505 struct rasops_info *ri = cookie; 1506 struct vcons_screen *scr = ri->ri_hw; 1507 struct mach64_softc *sc = scr->scr_cookie; 1508 int32_t xs, xd, y, width, height; 1509 1510 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1511 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1512 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1513 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1514 width = ri->ri_font->fontwidth * ncols; 1515 height = ri->ri_font->fontheight; 1516 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff); 1517 } 1518 } 1519 1520 static void 1521 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1522 { 1523 struct rasops_info *ri = cookie; 1524 struct vcons_screen *scr = ri->ri_hw; 1525 struct mach64_softc *sc = scr->scr_cookie; 1526 int32_t x, y, width, height, fg, bg, ul; 1527 1528 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1529 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1530 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1531 width = ri->ri_font->fontwidth * ncols; 1532 height = ri->ri_font->fontheight; 1533 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1534 1535 mach64_rectfill(sc, x, y, width, height, bg); 1536 } 1537 } 1538 1539 static void 1540 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1541 { 1542 struct rasops_info *ri = cookie; 1543 struct vcons_screen *scr = ri->ri_hw; 1544 struct mach64_softc *sc = scr->scr_cookie; 1545 int32_t x, ys, yd, width, height; 1546 1547 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1548 x = ri->ri_xorigin; 1549 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1550 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1551 width = ri->ri_emuwidth; 1552 height = ri->ri_font->fontheight*nrows; 1553 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff); 1554 } 1555 } 1556 1557 static void 1558 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1559 { 1560 struct rasops_info *ri = cookie; 1561 struct vcons_screen *scr = ri->ri_hw; 1562 struct mach64_softc *sc = scr->scr_cookie; 1563 int32_t x, y, width, height, fg, bg, ul; 1564 1565 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1566 x = ri->ri_xorigin; 1567 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1568 width = ri->ri_emuwidth; 1569 height = ri->ri_font->fontheight * nrows; 1570 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1571 1572 mach64_rectfill(sc, x, y, width, height, bg); 1573 } 1574 } 1575 1576 static void 1577 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1578 { 1579 uint32_t dest_ctl = 0; 1580 1581 wait_for_idle(sc); 1582 regw(sc, DP_WRITE_MASK, mask); /* XXX only good for 8 bit */ 1583 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1584 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1585 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1586 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1587 if (yd < ys) { 1588 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1589 } else { 1590 ys += height - 1; 1591 yd += height - 1; 1592 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1593 } 1594 if (xd < xs) { 1595 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1596 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1597 } else { 1598 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1599 xs += width - 1; 1600 xd += width - 1; 1601 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1602 } 1603 regw(sc, DST_CNTL, dest_ctl); 1604 1605 regw(sc, SRC_Y_X, (xs << 16) | ys); 1606 regw(sc, SRC_WIDTH1, width); 1607 regw(sc, DST_Y_X, (xd << 16) | yd); 1608 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1609 } 1610 1611 static void 1612 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1613 int height, uint32_t fg, uint32_t bg) 1614 { 1615 wait_for_idle(sc); 1616 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1617 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1618 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1619 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1620 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1621 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1622 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1623 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1624 regw(sc, DP_BKGD_CLR, bg); 1625 regw(sc, DP_FRGD_CLR, fg); 1626 regw(sc, SRC_Y_X, 0); 1627 regw(sc, SRC_WIDTH1, width); 1628 regw(sc, DST_Y_X, (xd << 16) | yd); 1629 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1630 /* now feed the data into the chip */ 1631 } 1632 1633 static void 1634 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1635 { 1636 int i; 1637 uint32_t latch = 0, bork; 1638 int shift = 0; 1639 int reg = 0; 1640 1641 for (i = 0; i < count; i++) { 1642 bork = data[i]; 1643 latch |= (bork << shift); 1644 if (shift == 24) { 1645 regw(sc, HOST_DATA0 + reg, latch); 1646 latch = 0; 1647 shift = 0; 1648 reg = (reg + 4) & 0x3c; 1649 } else 1650 shift += 8; 1651 } 1652 if (shift != 0) /* 24 */ 1653 regw(sc, HOST_DATA0 + reg, latch); 1654 } 1655 1656 1657 static void 1658 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1659 int colour) 1660 { 1661 wait_for_idle(sc); 1662 regw(sc, DP_WRITE_MASK, 0xff); 1663 regw(sc, DP_FRGD_CLR, colour); 1664 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1665 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1666 regw(sc, DP_MIX, MIX_SRC << 16); 1667 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1668 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1669 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1670 1671 regw(sc, SRC_Y_X, (x << 16) | y); 1672 regw(sc, SRC_WIDTH1, width); 1673 regw(sc, DST_Y_X, (x << 16) | y); 1674 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1675 } 1676 1677 static void 1678 mach64_clearscreen(struct mach64_softc *sc) 1679 { 1680 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1681 } 1682 1683 1684 #if 0 1685 static void 1686 mach64_showpal(struct mach64_softc *sc) 1687 { 1688 int i, x = 0; 1689 1690 for (i = 0; i < 16; i++) { 1691 mach64_rectfill(sc, x, 0, 64, 64, i); 1692 x += 64; 1693 } 1694 } 1695 #endif 1696 1697 /* 1698 * wsdisplay_accessops 1699 */ 1700 1701 static int 1702 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1703 struct lwp *l) 1704 { 1705 struct vcons_data *vd = v; 1706 struct mach64_softc *sc = vd->cookie; 1707 struct wsdisplay_fbinfo *wdf; 1708 struct vcons_screen *ms = vd->active; 1709 1710 switch (cmd) { 1711 case WSDISPLAYIO_GTYPE: 1712 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1713 return 0; 1714 1715 case WSDISPLAYIO_LINEBYTES: 1716 *(u_int *)data = sc->virt_x * sc->bits_per_pixel / 8; 1717 return 0; 1718 1719 case WSDISPLAYIO_GINFO: 1720 wdf = (void *)data; 1721 wdf->height = sc->virt_y; 1722 wdf->width = sc->virt_x; 1723 wdf->depth = sc->bits_per_pixel; 1724 wdf->cmsize = 256; 1725 return 0; 1726 1727 case WSDISPLAYIO_GETCMAP: 1728 return mach64_getcmap(sc, 1729 (struct wsdisplay_cmap *)data); 1730 1731 case WSDISPLAYIO_PUTCMAP: 1732 return mach64_putcmap(sc, 1733 (struct wsdisplay_cmap *)data); 1734 1735 /* PCI config read/write passthrough. */ 1736 case PCI_IOC_CFGREAD: 1737 case PCI_IOC_CFGWRITE: 1738 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1739 cmd, data, flag, l); 1740 1741 case WSDISPLAYIO_GET_BUSID: 1742 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1743 sc->sc_pcitag, data); 1744 1745 case WSDISPLAYIO_SMODE: { 1746 int new_mode = *(int*)data; 1747 if (new_mode != sc->sc_mode) { 1748 sc->sc_mode = new_mode; 1749 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1750 && (ms != NULL)) 1751 { 1752 /* restore initial video mode */ 1753 mach64_init(sc); 1754 mach64_init_engine(sc); 1755 mach64_init_lut(sc); 1756 mach64_modeswitch(sc, sc->sc_my_mode); 1757 vcons_redraw_screen(ms); 1758 } 1759 } 1760 } 1761 return 0; 1762 case WSDISPLAYIO_GET_EDID: { 1763 struct wsdisplayio_edid_info *d = data; 1764 return wsdisplayio_get_edid(sc->sc_dev, d); 1765 } 1766 } 1767 return EPASSTHROUGH; 1768 } 1769 1770 static paddr_t 1771 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1772 { 1773 struct vcons_data *vd = v; 1774 struct mach64_softc *sc = vd->cookie; 1775 paddr_t pa; 1776 pcireg_t reg; 1777 1778 #ifndef __sparc64__ 1779 /* 1780 *'regular' framebuffer mmap()ing 1781 * disabled on sparc64 because some ATI firmware likes to map some PCI 1782 * resources to addresses that would collide with this ( like some Rage 1783 * IIc which uses 0x2000 for the 2nd register block ) 1784 * Other 64bit architectures might run into similar problems. 1785 */ 1786 if (offset<sc->sc_apersize) { 1787 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, offset, 1788 prot, BUS_SPACE_MAP_LINEAR); 1789 return pa; 1790 } 1791 #endif 1792 1793 /* 1794 * restrict all other mappings to processes with superuser privileges 1795 * or the kernel itself 1796 */ 1797 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1798 NULL, NULL, NULL, NULL) != 0) { 1799 return -1; 1800 } 1801 1802 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1803 if (reg != sc->sc_regphys) { 1804 #ifdef DIAGNOSTIC 1805 printf("%s: BAR 0x18 changed! (%x %x)\n", 1806 device_xname(sc->sc_dev), (uint32_t)sc->sc_regphys, 1807 (uint32_t)reg); 1808 #endif 1809 sc->sc_regphys = reg; 1810 } 1811 1812 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1813 if (reg != sc->sc_aperphys) { 1814 #ifdef DIAGNOSTIC 1815 printf("%s: BAR 0x10 changed! (%x %x)\n", 1816 device_xname(sc->sc_dev), (uint32_t)sc->sc_aperphys, 1817 (uint32_t)reg); 1818 #endif 1819 sc->sc_aperphys = reg; 1820 } 1821 1822 if ((offset >= sc->sc_aperphys) && 1823 (offset < (sc->sc_aperphys + sc->sc_apersize))) { 1824 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1825 BUS_SPACE_MAP_LINEAR); 1826 return pa; 1827 } 1828 1829 if ((offset >= sc->sc_regphys) && 1830 (offset < (sc->sc_regphys + sc->sc_regsize))) { 1831 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1832 BUS_SPACE_MAP_LINEAR); 1833 return pa; 1834 } 1835 1836 if ((offset >= sc->sc_rom.vb_base) && 1837 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 1838 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1839 BUS_SPACE_MAP_LINEAR); 1840 return pa; 1841 } 1842 1843 #ifdef PCI_MAGIC_IO_RANGE 1844 if ((offset >= PCI_MAGIC_IO_RANGE) && 1845 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 1846 return bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1847 0, prot, BUS_SPACE_MAP_LINEAR); 1848 } 1849 #endif 1850 1851 return -1; 1852 } 1853 1854 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1855 static void 1856 set_address(struct rasops_info *ri, void *fb) 1857 { 1858 #ifdef notdef 1859 printf(" %d %d %d\n", ri->ri_xorigin, ri->ri_yorigin, ri->ri_stride); 1860 #endif 1861 ri->ri_bits = (void *)((char *)fb + ri->ri_stride * ri->ri_yorigin + 1862 ri->ri_xorigin); 1863 } 1864 1865 #if 0 1866 static int 1867 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1868 { 1869 1870 return 0; 1871 } 1872 #endif 1873 1874 void 1875 machfb_blank(struct mach64_softc *sc, int blank) 1876 { 1877 uint32_t reg; 1878 1879 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1880 1881 switch (blank) 1882 { 1883 case 0: 1884 reg = regr(sc, CRTC_GEN_CNTL); 1885 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1886 sc->sc_blanked = 0; 1887 break; 1888 case 1: 1889 reg = regr(sc, CRTC_GEN_CNTL); 1890 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1891 sc->sc_blanked = 1; 1892 break; 1893 default: 1894 break; 1895 } 1896 } 1897 1898 /* framebuffer device support */ 1899 #ifdef __sparc__ 1900 1901 static void 1902 machfb_unblank(device_t dev) 1903 { 1904 struct mach64_softc *sc = device_private(dev); 1905 1906 machfb_blank(sc, 0); 1907 } 1908 1909 static void 1910 machfb_fbattach(struct mach64_softc *sc) 1911 { 1912 struct fbdevice *fb = &sc->sc_fb; 1913 1914 fb->fb_device = sc->sc_dev; 1915 fb->fb_driver = &machfb_fbdriver; 1916 1917 fb->fb_type.fb_cmsize = 256; 1918 fb->fb_type.fb_size = sc->memsize; 1919 1920 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 1921 fb->fb_flags = sc->sc_dev->dv_cfdata->cf_flags & FB_USERMASK; 1922 fb->fb_type.fb_depth = sc->bits_per_pixel; 1923 fb->fb_type.fb_width = sc->virt_x; 1924 fb->fb_type.fb_height = sc->virt_y; 1925 1926 fb->fb_pixels = sc->sc_aperture; 1927 fb_attach(fb, sc->sc_console); 1928 } 1929 1930 int 1931 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 1932 { 1933 struct mach64_softc *sc; 1934 1935 sc = device_lookup_private(&machfb_cd, minor(dev)); 1936 if (sc == NULL) 1937 return ENXIO; 1938 sc->sc_locked = 1; 1939 1940 #ifdef MACHFB_DEBUG 1941 printf("machfb_fbopen(%d)\n", minor(dev)); 1942 #endif 1943 return 0; 1944 } 1945 1946 int 1947 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 1948 { 1949 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1950 1951 #ifdef MACHFB_DEBUG 1952 printf("machfb_fbclose()\n"); 1953 #endif 1954 mach64_init_engine(sc); 1955 mach64_init_lut(sc); 1956 sc->sc_locked = 0; 1957 return 0; 1958 } 1959 1960 int 1961 machfb_fbioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1962 { 1963 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1964 1965 #ifdef MACHFB_DEBUG 1966 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 1967 #endif 1968 switch (cmd) { 1969 case FBIOGTYPE: 1970 *(struct fbtype *)data = sc->sc_fb.fb_type; 1971 break; 1972 1973 case FBIOGATTR: 1974 #define fba ((struct fbgattr *)data) 1975 fba->real_type = sc->sc_fb.fb_type.fb_type; 1976 fba->owner = 0; /* XXX ??? */ 1977 fba->fbtype = sc->sc_fb.fb_type; 1978 fba->sattr.flags = 0; 1979 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 1980 fba->sattr.dev_specific[0] = sc->sc_nbus; 1981 fba->sattr.dev_specific[1] = sc->sc_ndev; 1982 fba->sattr.dev_specific[2] = sc->sc_nfunc; 1983 fba->sattr.dev_specific[3] = -1; 1984 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 1985 fba->emu_types[1] = -1; 1986 #undef fba 1987 break; 1988 1989 #if 0 1990 case FBIOGETCMAP: 1991 #define p ((struct fbcmap *)data) 1992 return bt_getcmap(p, &sc->sc_cmap, 256, 1); 1993 1994 case FBIOPUTCMAP: 1995 /* copy to software map */ 1996 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 1997 if (error) 1998 return error; 1999 /* now blast them into the chip */ 2000 /* XXX should use retrace interrupt */ 2001 cg6_loadcmap(sc, p->index, p->count); 2002 #undef p 2003 break; 2004 #endif 2005 case FBIOGVIDEO: 2006 *(int *)data = sc->sc_blanked; 2007 break; 2008 2009 case FBIOSVIDEO: 2010 machfb_blank(sc, *(int *)data); 2011 break; 2012 2013 #if 0 2014 case FBIOGCURSOR: 2015 break; 2016 2017 case FBIOSCURSOR: 2018 break; 2019 2020 case FBIOGCURPOS: 2021 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 2022 break; 2023 2024 case FBIOSCURPOS: 2025 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 2026 break; 2027 2028 case FBIOGCURMAX: 2029 /* max cursor size is 32x32 */ 2030 ((struct fbcurpos *)data)->x = 32; 2031 ((struct fbcurpos *)data)->y = 32; 2032 break; 2033 #endif 2034 case PCI_IOC_CFGREAD: 2035 case PCI_IOC_CFGWRITE: { 2036 int ret; 2037 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 2038 cmd, data, flags, l); 2039 2040 #ifdef MACHFB_DEBUG 2041 printf("pci_devioctl: %d\n", ret); 2042 #endif 2043 return ret; 2044 } 2045 2046 case WSDISPLAYIO_GET_BUSID: 2047 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 2048 sc->sc_pcitag, data); 2049 2050 default: 2051 return ENOTTY; 2052 } 2053 #ifdef MACHFB_DEBUG 2054 printf("machfb_fbioctl done\n"); 2055 #endif 2056 return 0; 2057 } 2058 2059 paddr_t 2060 machfb_fbmmap(dev_t dev, off_t off, int prot) 2061 { 2062 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 2063 2064 if (sc != NULL) 2065 return mach64_mmap(&sc->vd, NULL, off, prot); 2066 2067 return 0; 2068 } 2069 2070 #endif /* __sparc__ */ 2071
Indexes created Thu Oct 02 14:10:14 GMT 2025