machfb.c revision 1.81
1 /* $NetBSD: machfb.c,v 1.81 2012/08/15 17:02:41 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.81 2012/08/15 17:02:41 macallan Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #ifdef __sparc__ 58 #include <dev/sun/fbio.h> 59 #include <dev/sun/fbvar.h> 60 #include <sys/conf.h> 61 #else 62 #include <dev/wscons/wsdisplayvar.h> 63 #endif 64 65 #include <dev/wscons/wsconsio.h> 66 #include <dev/wsfont/wsfont.h> 67 #include <dev/rasops/rasops.h> 68 #include <dev/pci/wsdisplay_pci.h> 69 70 #include <dev/wscons/wsdisplay_vconsvar.h> 71 #include <dev/wscons/wsdisplay_glyphcachevar.h> 72 73 #include "opt_wsemul.h" 74 #include "opt_machfb.h" 75 76 #define MACH64_REG_SIZE 1024 77 #define MACH64_REG_OFF 0x7ff800 78 79 #define NBARS 3 /* number of Mach64 PCI BARs */ 80 81 struct vga_bar { 82 bus_addr_t vb_base; 83 bus_size_t vb_size; 84 pcireg_t vb_type; 85 int vb_flags; 86 }; 87 88 struct mach64_softc { 89 device_t sc_dev; 90 #ifdef __sparc__ 91 struct fbdevice sc_fb; 92 #endif 93 pci_chipset_tag_t sc_pc; 94 pcitag_t sc_pcitag; 95 96 struct vga_bar sc_bars[NBARS]; 97 struct vga_bar sc_rom; 98 99 #define sc_aperbase sc_bars[0].vb_base 100 #define sc_apersize sc_bars[0].vb_size 101 102 #define sc_iobase sc_bars[1].vb_base 103 #define sc_iosize sc_bars[1].vb_size 104 105 #define sc_regbase sc_bars[2].vb_base 106 #define sc_regsize sc_bars[2].vb_size 107 108 bus_space_tag_t sc_regt; 109 bus_space_tag_t sc_memt; 110 bus_space_tag_t sc_iot; 111 bus_space_handle_t sc_regh; 112 bus_space_handle_t sc_memh; 113 #if 0 114 void *sc_aperture; /* mapped aperture vaddr */ 115 void *sc_registers; /* mapped registers vaddr */ 116 #endif 117 uint32_t sc_nbus, sc_ndev, sc_nfunc; 118 size_t memsize; 119 int memtype; 120 121 int sc_mode; 122 int sc_bg; 123 int sc_locked; 124 125 int has_dsp; 126 int bits_per_pixel; 127 int max_x; 128 int max_y; 129 int virt_x; 130 int virt_y; 131 int color_depth; 132 133 int mem_freq; 134 int ramdac_freq; 135 int ref_freq; 136 137 int ref_div; 138 int log2_vclk_post_div; 139 int vclk_post_div; 140 int vclk_fb_div; 141 int mclk_post_div; 142 int mclk_fb_div; 143 int sc_clock; /* which clock to use */ 144 145 struct videomode *sc_my_mode; 146 int sc_edid_size; 147 uint8_t sc_edid_data[1024]; 148 149 u_char sc_cmap_red[256]; 150 u_char sc_cmap_green[256]; 151 u_char sc_cmap_blue[256]; 152 int sc_dacw, sc_blanked, sc_console; 153 struct vcons_data vd; 154 struct wsdisplay_accessops sc_accessops; 155 glyphcache sc_gc; 156 }; 157 158 struct mach64_crtcregs { 159 uint32_t h_total_disp; 160 uint32_t h_sync_strt_wid; 161 uint32_t v_total_disp; 162 uint32_t v_sync_strt_wid; 163 uint32_t gen_cntl; 164 uint32_t clock_cntl; 165 uint32_t color_depth; 166 uint32_t dot_clock; 167 }; 168 169 static struct { 170 uint16_t chip_id; 171 uint32_t ramdac_freq; 172 } const mach64_info[] = { 173 { PCI_PRODUCT_ATI_MACH64_GX, 135000 }, 174 { PCI_PRODUCT_ATI_MACH64_CX, 135000 }, 175 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 176 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 185 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 186 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 189 #if 0 190 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 192 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 193 #endif 194 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 195 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 196 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 197 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 198 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 199 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 200 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 201 }; 202 203 static int mach64_chip_id, mach64_chip_rev; 204 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 205 206 static const char *mach64_gx_memtype_names[] = { 207 "DRAM", "VRAM", "VRAM", "DRAM", 208 "DRAM", "VRAM", "VRAM", "(unknown type)" 209 }; 210 211 static const char *mach64_memtype_names[] = { 212 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 213 "(unknown type)" 214 }; 215 216 static struct videomode mach64_modes[] = { 217 /* 640x400 @ 70 Hz, 31.5 kHz */ 218 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0, NULL, }, 219 /* 640x480 @ 72 Hz, 36.5 kHz */ 220 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0, NULL, }, 221 /* 800x600 @ 72 Hz, 48.0 kHz */ 222 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 223 VID_PHSYNC | VID_PVSYNC, NULL, }, 224 /* 1024x768 @ 70 Hz, 56.5 kHz */ 225 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 226 VID_NHSYNC | VID_NVSYNC, NULL, }, 227 /* 1152x864 @ 70 Hz, 62.4 kHz */ 228 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0, NULL, }, 229 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 230 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 231 VID_NHSYNC | VID_NVSYNC, NULL, } 232 }; 233 234 extern const u_char rasops_cmap[768]; 235 236 static int mach64_match(device_t, cfdata_t, void *); 237 static void mach64_attach(device_t, device_t, void *); 238 239 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 240 NULL, NULL); 241 242 static void mach64_init(struct mach64_softc *); 243 static int mach64_get_memsize(struct mach64_softc *); 244 static int mach64_get_max_ramdac(struct mach64_softc *); 245 246 #if defined(__sparc__) || defined(__powerpc__) 247 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 248 #endif 249 250 static int mach64_calc_crtcregs(struct mach64_softc *, 251 struct mach64_crtcregs *, 252 struct videomode *); 253 static void mach64_set_crtcregs(struct mach64_softc *, 254 struct mach64_crtcregs *); 255 256 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 257 static void mach64_set_dsp(struct mach64_softc *); 258 static void mach64_set_pll(struct mach64_softc *, int); 259 static void mach64_reset_engine(struct mach64_softc *); 260 static void mach64_init_engine(struct mach64_softc *); 261 #if 0 262 static void mach64_adjust_frame(struct mach64_softc *, int, int); 263 #endif 264 static void mach64_init_lut(struct mach64_softc *); 265 266 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 267 static int mach64_set_screentype(struct mach64_softc *, 268 const struct wsscreen_descr *); 269 static int mach64_is_console(struct mach64_softc *); 270 271 static void mach64_cursor(void *, int, int, int); 272 #if 0 273 static int mach64_mapchar(void *, int, u_int *); 274 #endif 275 static void mach64_putchar_mono(void *, int, int, u_int, long); 276 static void mach64_putchar_aa8(void *, int, int, u_int, long); 277 static void mach64_copycols(void *, int, int, int, int); 278 static void mach64_erasecols(void *, int, int, int, long); 279 static void mach64_copyrows(void *, int, int, int); 280 static void mach64_eraserows(void *, int, int, long); 281 static void mach64_clearscreen(struct mach64_softc *); 282 283 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 284 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 285 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 286 uint8_t, uint8_t); 287 static void mach64_bitblt(void *, int, int, int, int, int, int, int); 288 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 289 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 290 uint32_t, uint32_t); 291 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 292 #if 0 293 static void mach64_showpal(struct mach64_softc *); 294 #endif 295 296 static void machfb_blank(struct mach64_softc *, int); 297 static int machfb_drm_print(void *, const char *); 298 299 static struct wsscreen_descr mach64_defaultscreen = { 300 "default", 301 80, 30, 302 NULL, 303 8, 16, 304 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 305 &default_mode 306 }, mach64_80x25_screen = { 307 "80x25", 80, 25, 308 NULL, 309 8, 16, 310 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 311 &mach64_modes[0] 312 }, mach64_80x30_screen = { 313 "80x30", 80, 30, 314 NULL, 315 8, 16, 316 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 317 &mach64_modes[1] 318 }, mach64_80x40_screen = { 319 "80x40", 80, 40, 320 NULL, 321 8, 10, 322 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 323 &mach64_modes[0] 324 }, mach64_80x50_screen = { 325 "80x50", 80, 50, 326 NULL, 327 8, 8, 328 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 329 &mach64_modes[0] 330 }, mach64_100x37_screen = { 331 "100x37", 100, 37, 332 NULL, 333 8, 16, 334 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 335 &mach64_modes[2] 336 }, mach64_128x48_screen = { 337 "128x48", 128, 48, 338 NULL, 339 8, 16, 340 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 341 &mach64_modes[3] 342 }, mach64_144x54_screen = { 343 "144x54", 144, 54, 344 NULL, 345 8, 16, 346 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 347 &mach64_modes[4] 348 }, mach64_160x64_screen = { 349 "160x54", 160, 64, 350 NULL, 351 8, 16, 352 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 353 &mach64_modes[5] 354 }; 355 356 static const struct wsscreen_descr *_mach64_scrlist[] = { 357 &mach64_defaultscreen, 358 &mach64_80x25_screen, 359 &mach64_80x30_screen, 360 &mach64_80x40_screen, 361 &mach64_80x50_screen, 362 &mach64_100x37_screen, 363 &mach64_128x48_screen, 364 &mach64_144x54_screen, 365 &mach64_160x64_screen 366 }; 367 368 static struct wsscreen_list mach64_screenlist = { 369 __arraycount(_mach64_scrlist), 370 _mach64_scrlist 371 }; 372 373 static int mach64_ioctl(void *, void *, u_long, void *, int, 374 struct lwp *); 375 static paddr_t mach64_mmap(void *, void *, off_t, int); 376 377 #if 0 378 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 379 #endif 380 381 382 static struct vcons_screen mach64_console_screen; 383 384 /* framebuffer device, SPARC-only so far */ 385 #ifdef __sparc__ 386 387 static void machfb_unblank(device_t); 388 static void machfb_fbattach(struct mach64_softc *); 389 390 extern struct cfdriver machfb_cd; 391 392 dev_type_open(machfb_fbopen); 393 dev_type_close(machfb_fbclose); 394 dev_type_ioctl(machfb_fbioctl); 395 dev_type_mmap(machfb_fbmmap); 396 397 /* frame buffer generic driver */ 398 static struct fbdriver machfb_fbdriver = { 399 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 400 machfb_fbmmap, nokqfilter 401 }; 402 403 #endif /* __sparc__ */ 404 405 /* 406 * Inline functions for getting access to register aperture. 407 */ 408 409 static inline uint32_t 410 regr(struct mach64_softc *sc, uint32_t index) 411 { 412 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index + 0x400); 413 } 414 415 static inline uint8_t 416 regrb(struct mach64_softc *sc, uint32_t index) 417 { 418 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index + 0x400); 419 } 420 421 static inline void 422 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 423 { 424 bus_space_write_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 425 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 426 BUS_SPACE_BARRIER_WRITE); 427 } 428 429 static inline void 430 regws(struct mach64_softc *sc, uint32_t index, uint32_t data) 431 { 432 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 433 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 4, 434 BUS_SPACE_BARRIER_WRITE); 435 } 436 437 static inline void 438 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 439 { 440 bus_space_write_1(sc->sc_regt, sc->sc_regh, index + 0x400, data); 441 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 1, 442 BUS_SPACE_BARRIER_WRITE); 443 } 444 445 static inline void 446 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 447 { 448 uint32_t reg; 449 450 reg = regr(sc, CLOCK_CNTL); 451 reg |= PLL_WR_EN; 452 regw(sc, CLOCK_CNTL, reg); 453 reg &= ~(PLL_ADDR | PLL_DATA); 454 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 455 reg |= data << PLL_DATA_SHIFT; 456 reg |= CLOCK_STROBE; 457 regw(sc, CLOCK_CNTL, reg); 458 reg &= ~PLL_WR_EN; 459 regw(sc, CLOCK_CNTL, reg); 460 } 461 462 static inline uint8_t 463 regrb_pll(struct mach64_softc *sc, uint32_t index) 464 { 465 466 regwb(sc, CLOCK_CNTL + 1, index << 2); 467 return regrb(sc, CLOCK_CNTL + 2); 468 } 469 470 static inline void 471 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 472 { 473 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 474 continue; 475 } 476 477 static inline void 478 wait_for_idle(struct mach64_softc *sc) 479 { 480 wait_for_fifo(sc, 16); 481 while ((regr(sc, GUI_STAT) & 1) != 0) 482 continue; 483 } 484 485 static int 486 mach64_match(device_t parent, cfdata_t match, void *aux) 487 { 488 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 489 int i; 490 491 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 492 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 493 return 0; 494 495 for (i = 0; i < __arraycount(mach64_info); i++) 496 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 497 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 498 mach64_chip_rev = PCI_REVISION(pa->pa_class); 499 return 100; 500 } 501 502 return 0; 503 } 504 505 static void 506 mach64_attach(device_t parent, device_t self, void *aux) 507 { 508 struct mach64_softc *sc = device_private(self); 509 struct pci_attach_args *pa = aux; 510 struct rasops_info *ri; 511 prop_data_t edid_data; 512 #if defined(__sparc__) || defined(__powerpc__) 513 const struct videomode *mode = NULL; 514 #endif 515 int bar, id, expected_id; 516 int is_gx; 517 const char **memtype_names; 518 struct wsemuldisplaydev_attach_args aa; 519 long defattr; 520 int setmode, width, height; 521 pcireg_t screg; 522 uint32_t reg; 523 const pcireg_t enables = PCI_COMMAND_MEM_ENABLE; 524 int use_mmio = FALSE; 525 526 sc->sc_dev = self; 527 sc->sc_pc = pa->pa_pc; 528 sc->sc_pcitag = pa->pa_tag; 529 sc->sc_dacw = -1; 530 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 531 sc->sc_nbus = pa->pa_bus; 532 sc->sc_ndev = pa->pa_device; 533 sc->sc_nfunc = pa->pa_function; 534 sc->sc_locked = 0; 535 sc->sc_iot = pa->pa_iot; 536 sc->sc_accessops.ioctl = mach64_ioctl; 537 sc->sc_accessops.mmap = mach64_mmap; 538 539 pci_aprint_devinfo(pa, "Graphics processor"); 540 #ifdef MACHFB_DEBUG 541 printf(prop_dictionary_externalize(device_properties(self))); 542 #endif 543 544 /* enable memory access */ 545 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 546 if ((screg & enables) != enables) { 547 screg |= enables; 548 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 549 PCI_COMMAND_STATUS_REG, screg); 550 } 551 for (bar = 0; bar < NBARS; bar++) { 552 reg = PCI_MAPREG_START + (bar * 4); 553 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 554 sc->sc_pcitag, reg); 555 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 556 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 557 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 558 } 559 aprint_debug_dev(sc->sc_dev, "aperture size %08x\n", 560 (uint32_t)sc->sc_apersize); 561 562 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 563 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 564 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 565 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 566 sc->sc_memt = pa->pa_memt; 567 568 /* use MMIO register aperture if available */ 569 if ((sc->sc_regbase != 0) && (sc->sc_regbase != 0xffffffff)) { 570 if (pci_mapreg_map(pa, MACH64_BAR_MMIO, PCI_MAPREG_TYPE_MEM, 0, 571 &sc->sc_regt, &sc->sc_regh, &sc->sc_regbase, 572 &sc->sc_regsize) == 0) { 573 574 /* 575 * the MMIO aperture maps both 1KB register blocks, but 576 * all register offsets are relative to the 2nd one so 577 * for now fix this up in MACH64_REG_OFF and the access 578 * functions 579 */ 580 aprint_normal_dev(sc->sc_dev, "using MMIO aperture\n"); 581 use_mmio = TRUE; 582 } 583 } 584 if (!use_mmio) { 585 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 586 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 587 panic("%s: failed to map aperture", 588 device_xname(sc->sc_dev)); 589 } 590 591 /* If the BAR was never mapped, fix it up in MMIO. */ 592 sc->sc_regsize = MACH64_REG_SIZE; 593 sc->sc_regbase = sc->sc_aperbase + MACH64_REG_OFF; 594 sc->sc_regt = sc->sc_memt; 595 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 596 sc->sc_regsize, &sc->sc_regh); 597 } 598 599 mach64_init(sc); 600 601 aprint_normal_dev(sc->sc_dev, 602 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 603 (u_int)(sc->sc_apersize / (1024 * 1024)), 604 (u_int)sc->sc_aperbase, (u_int)(sc->sc_regsize / 1024), 605 (u_int)sc->sc_regbase); 606 607 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 608 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 609 610 prop_dictionary_get_uint32(device_properties(self), "width", &width); 611 prop_dictionary_get_uint32(device_properties(self), "height", &height); 612 613 if ((edid_data = prop_dictionary_get(device_properties(self), "EDID")) 614 != NULL) { 615 struct edid_info ei; 616 617 sc->sc_edid_size = min(1024, prop_data_size(edid_data)); 618 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 619 memcpy(sc->sc_edid_data, prop_data_data_nocopy(edid_data), 620 sc->sc_edid_size); 621 622 edid_parse(sc->sc_edid_data, &ei); 623 624 #ifdef MACHFB_DEBUG 625 edid_print(&ei); 626 #endif 627 } 628 629 is_gx = 0; 630 switch(mach64_chip_id) { 631 case PCI_PRODUCT_ATI_MACH64_GX: 632 case PCI_PRODUCT_ATI_MACH64_CX: 633 is_gx = 1; 634 case PCI_PRODUCT_ATI_MACH64_CT: 635 sc->has_dsp = 0; 636 break; 637 case PCI_PRODUCT_ATI_MACH64_VT: 638 case PCI_PRODUCT_ATI_RAGE_II: 639 if((mach64_chip_rev & 0x07) == 0) { 640 sc->has_dsp = 0; 641 break; 642 } 643 /* Otherwise fall through. */ 644 default: 645 sc->has_dsp = 1; 646 } 647 648 memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names; 649 650 sc->memsize = mach64_get_memsize(sc); 651 652 if(is_gx) 653 sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07; 654 else 655 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 656 657 /* 658 * XXX is there any way to calculate reference frequency from 659 * known values? 660 */ 661 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 662 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 663 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 664 aprint_normal_dev(sc->sc_dev, "ref_freq=29.498MHz\n"); 665 sc->ref_freq = 29498; 666 } else 667 sc->ref_freq = 14318; 668 669 reg = regr(sc, CLOCK_CNTL); 670 aprint_debug("CLOCK_CNTL: %08x\n", reg); 671 sc->sc_clock = reg & 3; 672 aprint_debug("using clock %d\n", sc->sc_clock); 673 674 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 675 aprint_debug("ref_div: %d\n", sc->ref_div); 676 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 677 aprint_debug("mclk_fb_div: %d\n", sc->mclk_fb_div); 678 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 679 (sc->ref_div * 2); 680 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 681 (sc->mem_freq * sc->ref_div); 682 sc->ramdac_freq = mach64_get_max_ramdac(sc); 683 aprint_normal_dev(sc->sc_dev, 684 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 685 (u_long)sc->memsize, 686 memtype_names[sc->memtype], 687 sc->mem_freq / 1000, sc->mem_freq % 1000, 688 sc->ramdac_freq / 1000); 689 690 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 691 switch(mach64_chip_id) { 692 case PCI_PRODUCT_ATI_MACH64_GX: 693 expected_id = 0x00d7; 694 break; 695 case PCI_PRODUCT_ATI_MACH64_CX: 696 expected_id = 0x0057; 697 break; 698 default: 699 /* Most chip IDs match their PCI product ID. */ 700 expected_id = mach64_chip_id; 701 } 702 703 if (id != expected_id) { 704 aprint_error_dev(sc->sc_dev, 705 "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id); 706 return; 707 } 708 709 sc->sc_console = mach64_is_console(sc); 710 aprint_debug("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 711 #if defined(__sparc__) || defined(__powerpc__) 712 if (sc->sc_console) { 713 if (mode != NULL) { 714 memcpy(&default_mode, mode, sizeof(struct videomode)); 715 setmode = 1; 716 } else { 717 mach64_get_mode(sc, &default_mode); 718 setmode = 0; 719 } 720 sc->sc_my_mode = &default_mode; 721 } else { 722 /* fill in default_mode if it's empty */ 723 mach64_get_mode(sc, &default_mode); 724 if (default_mode.dot_clock == 0) { 725 memcpy(&default_mode, &mach64_modes[4], 726 sizeof(default_mode)); 727 } 728 sc->sc_my_mode = &default_mode; 729 setmode = 1; 730 } 731 #else 732 if (default_mode.dot_clock == 0) { 733 memcpy(&default_mode, &mach64_modes[0], 734 sizeof(default_mode)); 735 } 736 sc->sc_my_mode = &mach64_modes[0]; 737 setmode = 1; 738 #endif 739 740 sc->bits_per_pixel = 8; 741 sc->virt_x = sc->sc_my_mode->hdisplay; 742 sc->virt_y = sc->sc_my_mode->vdisplay; 743 sc->max_x = sc->virt_x - 1; 744 sc->max_y = (sc->memsize * 1024) / 745 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 746 747 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 748 749 mach64_init_engine(sc); 750 751 if (setmode) 752 mach64_modeswitch(sc, sc->sc_my_mode); 753 754 aprint_normal_dev(sc->sc_dev, 755 "initial resolution %dx%d at %d bpp\n", 756 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 757 sc->bits_per_pixel); 758 759 #ifdef __sparc__ 760 machfb_fbattach(sc); 761 #endif 762 763 wsfont_init(); 764 765 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &sc->sc_accessops); 766 sc->vd.init_screen = mach64_init_screen; 767 768 sc->sc_gc.gc_bitblt = mach64_bitblt; 769 sc->sc_gc.gc_blitcookie = sc; 770 sc->sc_gc.gc_rop = MIX_SRC; 771 772 ri = &mach64_console_screen.scr_ri; 773 if (sc->sc_console) { 774 775 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 776 &defattr); 777 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 778 779 mach64_defaultscreen.textops = &ri->ri_ops; 780 mach64_defaultscreen.capabilities = ri->ri_caps; 781 mach64_defaultscreen.nrows = ri->ri_rows; 782 mach64_defaultscreen.ncols = ri->ri_cols; 783 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 784 ((sc->memsize * 1024 * 1024) / sc->sc_my_mode->hdisplay) - 785 sc->sc_my_mode->vdisplay - 5, 786 sc->sc_my_mode->hdisplay, 787 ri->ri_font->fontwidth, 788 ri->ri_font->fontheight, 789 defattr); 790 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 791 } else { 792 /* 793 * since we're not the console we can postpone the rest 794 * until someone actually allocates a screen for us 795 */ 796 mach64_modeswitch(sc, sc->sc_my_mode); 797 if (mach64_console_screen.scr_ri.ri_rows == 0) { 798 /* do some minimal setup to avoid weirdnesses later */ 799 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 800 &defattr); 801 } 802 803 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 804 ((sc->memsize * 1024 * 1024) / sc->sc_my_mode->hdisplay) - 805 sc->sc_my_mode->vdisplay - 5, 806 sc->sc_my_mode->hdisplay, 807 ri->ri_font->fontwidth, 808 ri->ri_font->fontheight, 809 defattr); 810 } 811 812 sc->sc_bg = mach64_console_screen.scr_ri.ri_devcmap[WS_DEFAULT_BG]; 813 mach64_clearscreen(sc); 814 mach64_init_lut(sc); 815 816 if (sc->sc_console) 817 vcons_replay_msgbuf(&mach64_console_screen); 818 819 machfb_blank(sc, 0); /* unblank the screen */ 820 821 aa.console = sc->sc_console; 822 aa.scrdata = &mach64_screenlist; 823 aa.accessops = &sc->sc_accessops; 824 aa.accesscookie = &sc->vd; 825 826 config_found(self, &aa, wsemuldisplaydevprint); 827 if (use_mmio) { 828 /* 829 * Now that we took over, turn off the aperture registers if we 830 * don't use them. Can't do this earlier since on some hardware 831 * we use firmware calls as early console output which may in 832 * turn try to access these registers. 833 */ 834 reg = regr(sc, BUS_CNTL); 835 aprint_debug_dev(sc->sc_dev, "BUS_CNTL: %08x\n", reg); 836 reg |= BUS_APER_REG_DIS; 837 regw(sc, BUS_CNTL, reg); 838 } 839 config_found_ia(self, "drm", aux, machfb_drm_print); 840 } 841 842 static int 843 machfb_drm_print(void *aux, const char *pnp) 844 { 845 if (pnp) 846 aprint_normal("direct rendering for %s", pnp); 847 return (UNSUPP); 848 } 849 850 static void 851 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 852 long *defattr) 853 { 854 struct mach64_softc *sc = cookie; 855 struct rasops_info *ri = &scr->scr_ri; 856 857 /* XXX for now */ 858 #define setmode 0 859 860 ri->ri_depth = sc->bits_per_pixel; 861 ri->ri_width = sc->sc_my_mode->hdisplay; 862 ri->ri_height = sc->sc_my_mode->vdisplay; 863 ri->ri_stride = ri->ri_width; 864 ri->ri_flg = RI_CENTER; 865 if (ri->ri_depth == 8) 866 ri->ri_flg |= RI_8BIT_IS_RGB | RI_ENABLE_ALPHA; 867 868 #ifdef VCONS_DRAW_INTR 869 scr->scr_flags |= VCONS_DONT_READ; 870 #endif 871 872 if (existing) { 873 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 874 panic("%s: failed to switch video mode", 875 device_xname(sc->sc_dev)); 876 } 877 } 878 879 rasops_init(ri, 0, 0); 880 ri->ri_caps = WSSCREEN_WSCOLORS; 881 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 882 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 883 884 /* enable acceleration */ 885 ri->ri_hw = scr; 886 ri->ri_ops.copyrows = mach64_copyrows; 887 ri->ri_ops.copycols = mach64_copycols; 888 ri->ri_ops.eraserows = mach64_eraserows; 889 ri->ri_ops.erasecols = mach64_erasecols; 890 ri->ri_ops.cursor = mach64_cursor; 891 if (FONT_IS_ALPHA(ri->ri_font)) { 892 ri->ri_ops.putchar = mach64_putchar_aa8; 893 ri->ri_ops.allocattr(ri, WS_DEFAULT_FG, WS_DEFAULT_BG, 894 0, &sc->sc_gc.gc_attr); 895 } else 896 ri->ri_ops.putchar = mach64_putchar_mono; 897 } 898 899 static void 900 mach64_init(struct mach64_softc *sc) 901 { 902 sc->sc_blanked = 0; 903 } 904 905 static int 906 mach64_get_memsize(struct mach64_softc *sc) 907 { 908 int tmp, memsize; 909 int mem_tab[] = { 910 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 911 }; 912 tmp = regr(sc, MEM_CNTL); 913 #ifdef DIAGNOSTIC 914 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 915 #endif 916 if (sc->has_dsp) { 917 tmp &= 0x0000000f; 918 if (tmp < 8) 919 memsize = (tmp + 1) * 512; 920 else if (tmp < 12) 921 memsize = (tmp - 3) * 1024; 922 else 923 memsize = (tmp - 7) * 2048; 924 } else { 925 memsize = mem_tab[tmp & 0x07]; 926 } 927 928 return memsize; 929 } 930 931 static int 932 mach64_get_max_ramdac(struct mach64_softc *sc) 933 { 934 int i; 935 936 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 937 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 938 (mach64_chip_rev & 0x07)) 939 return 170000; 940 941 for (i = 0; i < __arraycount(mach64_info); i++) 942 if (mach64_chip_id == mach64_info[i].chip_id) 943 return mach64_info[i].ramdac_freq; 944 945 if (sc->bits_per_pixel == 8) 946 return 135000; 947 else 948 return 80000; 949 } 950 951 #if defined(__sparc__) || defined(__powerpc__) 952 static void 953 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 954 { 955 struct mach64_crtcregs crtc; 956 957 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 958 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 959 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 960 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 961 962 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 963 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 964 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 965 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 966 mode->hsync_start; 967 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 968 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 969 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 970 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 971 972 #ifdef MACHFB_DEBUG 973 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 974 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 975 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 976 #endif 977 } 978 #endif 979 980 static int 981 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 982 struct videomode *mode) 983 { 984 985 if (mode->dot_clock > sc->ramdac_freq) 986 /* Clock too high. */ 987 return 1; 988 989 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 990 ((mode->htotal >> 3) - 1); 991 crtc->h_sync_strt_wid = 992 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 993 ((mode->hsync_start >> 3) - 1); 994 995 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 996 (mode->vtotal - 1); 997 crtc->v_sync_strt_wid = 998 ((mode->vsync_end - mode->vsync_start) << 16) | 999 (mode->vsync_start - 1); 1000 1001 if (mode->flags & VID_NVSYNC) 1002 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 1003 1004 switch (sc->bits_per_pixel) { 1005 case 8: 1006 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 1007 break; 1008 case 16: 1009 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 1010 break; 1011 case 32: 1012 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 1013 break; 1014 } 1015 1016 crtc->gen_cntl = 0; 1017 if (mode->flags & VID_INTERLACE) 1018 crtc->gen_cntl |= CRTC_INTERLACE_EN; 1019 1020 if (mode->flags & VID_CSYNC) 1021 crtc->gen_cntl |= CRTC_CSYNC_EN; 1022 1023 crtc->dot_clock = mode->dot_clock; 1024 1025 return 0; 1026 } 1027 1028 static void 1029 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 1030 { 1031 1032 mach64_set_pll(sc, crtc->dot_clock); 1033 1034 if (sc->has_dsp) 1035 mach64_set_dsp(sc); 1036 1037 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 1038 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1039 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 1040 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1041 1042 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 1043 1044 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1045 1046 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 1047 /* XXX this unconditionally enables composite sync on SPARC */ 1048 #ifdef __sparc__ 1049 CRTC_CSYNC_EN | 1050 #endif 1051 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 1052 } 1053 1054 static int 1055 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 1056 { 1057 struct mach64_crtcregs crtc; 1058 1059 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 1060 1061 if (mach64_calc_crtcregs(sc, &crtc, mode)) 1062 return 1; 1063 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 1064 if (crtc.dot_clock == 0) { 1065 aprint_error("%s: preposterous dot clock (%d)\n", 1066 device_xname(sc->sc_dev), crtc.dot_clock); 1067 return 1; 1068 } 1069 mach64_set_crtcregs(sc, &crtc); 1070 return 0; 1071 } 1072 1073 static void 1074 mach64_reset_engine(struct mach64_softc *sc) 1075 { 1076 1077 /* Reset engine.*/ 1078 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1079 1080 /* Enable engine. */ 1081 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1082 1083 /* Ensure engine is not locked up by clearing any FIFO or 1084 host errors. */ 1085 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1086 BUS_FIFO_ERR_ACK); 1087 } 1088 1089 static void 1090 mach64_init_engine(struct mach64_softc *sc) 1091 { 1092 uint32_t pitch_value; 1093 1094 pitch_value = sc->virt_x; 1095 1096 if (sc->bits_per_pixel == 24) 1097 pitch_value *= 3; 1098 1099 mach64_reset_engine(sc); 1100 1101 wait_for_fifo(sc, 14); 1102 1103 regw(sc, CONTEXT_MASK, 0xffffffff); 1104 1105 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 1106 1107 /* make sure the visible area starts where we're going to draw */ 1108 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1109 1110 regw(sc, DST_Y_X, 0); 1111 regw(sc, DST_HEIGHT, 0); 1112 regw(sc, DST_BRES_ERR, 0); 1113 regw(sc, DST_BRES_INC, 0); 1114 regw(sc, DST_BRES_DEC, 0); 1115 1116 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1117 DST_Y_TOP_TO_BOTTOM); 1118 1119 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 1120 1121 regw(sc, SRC_Y_X, 0); 1122 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1123 regw(sc, SRC_Y_X_START, 0); 1124 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1125 1126 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1127 1128 wait_for_fifo(sc, 13); 1129 regw(sc, HOST_CNTL, 0); 1130 1131 regw(sc, PAT_REG0, 0); 1132 regw(sc, PAT_REG1, 0); 1133 regw(sc, PAT_CNTL, 0); 1134 1135 regw(sc, SC_LEFT, 0); 1136 regw(sc, SC_TOP, 0); 1137 regw(sc, SC_BOTTOM, 0x3fff); 1138 regw(sc, SC_RIGHT, pitch_value - 1); 1139 1140 regw(sc, DP_BKGD_CLR, WS_DEFAULT_BG); 1141 regw(sc, DP_FRGD_CLR, WS_DEFAULT_FG); 1142 regw(sc, DP_WRITE_MASK, 0xffffffff); 1143 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1144 1145 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1146 1147 wait_for_fifo(sc, 3); 1148 regw(sc, CLR_CMP_CLR, 0); 1149 regw(sc, CLR_CMP_MASK, 0xffffffff); 1150 regw(sc, CLR_CMP_CNTL, 0); 1151 1152 wait_for_fifo(sc, 3); 1153 switch (sc->bits_per_pixel) { 1154 case 8: 1155 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP); 1156 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1157 /* We want 8 bit per channel */ 1158 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1159 break; 1160 case 32: 1161 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP); 1162 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1163 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1164 break; 1165 } 1166 regw(sc, DP_WRITE_MASK, 0xff); 1167 1168 wait_for_fifo(sc, 5); 1169 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1170 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1171 1172 wait_for_idle(sc); 1173 } 1174 1175 #if 0 1176 static void 1177 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1178 { 1179 int offset; 1180 1181 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1182 1183 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1184 offset); 1185 } 1186 #endif 1187 1188 static void 1189 mach64_set_dsp(struct mach64_softc *sc) 1190 { 1191 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1192 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1193 uint32_t xclks_per_qw, y; 1194 uint32_t fifo_off, fifo_on; 1195 1196 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1197 1198 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1199 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1200 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1201 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1202 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1203 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1204 dsp_loop_latency = 0; 1205 fifo_depth = 24; 1206 } else { 1207 dsp_loop_latency = 2; 1208 fifo_depth = 32; 1209 } 1210 1211 dsp_precision = 0; 1212 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1213 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1214 y = (xclks_per_qw * fifo_depth) >> 11; 1215 while (y) { 1216 y >>= 1; 1217 dsp_precision++; 1218 } 1219 dsp_precision -= 5; 1220 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1221 1222 switch (sc->memtype) { 1223 case DRAM: 1224 case EDO_DRAM: 1225 case PSEUDO_EDO: 1226 if (sc->memsize > 1024) { 1227 page_size = 9; 1228 dsp_loop_latency += 6; 1229 } else { 1230 page_size = 10; 1231 if (sc->memtype == DRAM) 1232 dsp_loop_latency += 8; 1233 else 1234 dsp_loop_latency += 7; 1235 } 1236 break; 1237 case SDRAM: 1238 case SGRAM: 1239 if (sc->memsize > 1024) { 1240 page_size = 8; 1241 dsp_loop_latency += 8; 1242 } else { 1243 page_size = 10; 1244 dsp_loop_latency += 9; 1245 } 1246 break; 1247 default: 1248 page_size = 10; 1249 dsp_loop_latency += 9; 1250 break; 1251 } 1252 1253 if (xclks_per_qw >= (page_size << 11)) 1254 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1255 else 1256 fifo_on = (3 * page_size + 2) << 6; 1257 1258 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1259 dsp_on = fifo_on >> dsp_precision; 1260 dsp_off = fifo_off >> dsp_precision; 1261 1262 #ifdef MACHFB_DEBUG 1263 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1264 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1265 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1266 "mclk_post_div = %d, vclk_post_div = %d\n", 1267 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1268 sc->mclk_fb_div, sc->vclk_fb_div, 1269 sc->mclk_post_div, sc->vclk_post_div); 1270 #endif 1271 1272 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1273 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1274 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1275 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1276 } 1277 1278 static void 1279 mach64_set_pll(struct mach64_softc *sc, int clock) 1280 { 1281 uint32_t q, clockreg; 1282 int clockshift = sc->sc_clock << 1; 1283 uint8_t reg, vclk_ctl; 1284 1285 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1286 #ifdef MACHFB_DEBUG 1287 printf("q = %d\n", q); 1288 #endif 1289 if (q > 25500) { 1290 aprint_error_dev(sc->sc_dev, "Warning: q > 25500\n"); 1291 q = 25500; 1292 sc->vclk_post_div = 1; 1293 sc->log2_vclk_post_div = 0; 1294 } else if (q > 12750) { 1295 sc->vclk_post_div = 1; 1296 sc->log2_vclk_post_div = 0; 1297 } else if (q > 6350) { 1298 sc->vclk_post_div = 2; 1299 sc->log2_vclk_post_div = 1; 1300 } else if (q > 3150) { 1301 sc->vclk_post_div = 4; 1302 sc->log2_vclk_post_div = 2; 1303 } else if (q >= 1600) { 1304 sc->vclk_post_div = 8; 1305 sc->log2_vclk_post_div = 3; 1306 } else { 1307 aprint_error_dev(sc->sc_dev, "Warning: q < 1600\n"); 1308 sc->vclk_post_div = 8; 1309 sc->log2_vclk_post_div = 3; 1310 } 1311 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1312 aprint_debug("post_div: %d log2_post_div: %d mclk_div: %d\n", 1313 sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1314 1315 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1316 aprint_debug("vclk_ctl: %02x\n", vclk_ctl); 1317 vclk_ctl |= PLL_VCLK_RESET; 1318 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1319 1320 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1321 reg = regrb_pll(sc, VCLK_POST_DIV); 1322 reg &= ~(3 << clockshift); 1323 reg |= (sc->log2_vclk_post_div << clockshift); 1324 regwb_pll(sc, VCLK_POST_DIV, reg); 1325 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1326 1327 vclk_ctl &= ~PLL_VCLK_RESET; 1328 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1329 1330 clockreg = regr(sc, CLOCK_CNTL); 1331 clockreg &= ~CLOCK_SEL; 1332 clockreg |= sc->sc_clock | CLOCK_STROBE; 1333 regw(sc, CLOCK_CNTL, clockreg); 1334 } 1335 1336 static void 1337 mach64_init_lut(struct mach64_softc *sc) 1338 { 1339 uint8_t cmap[768]; 1340 int i, idx; 1341 1342 rasops_get_cmap(&mach64_console_screen.scr_ri, cmap, sizeof(cmap)); 1343 idx = 0; 1344 for (i = 0; i < 256; i++) { 1345 mach64_putpalreg(sc, i, cmap[idx], cmap[idx + 1], 1346 cmap[idx + 2]); 1347 idx += 3; 1348 } 1349 } 1350 1351 static int 1352 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1353 uint8_t b) 1354 { 1355 sc->sc_cmap_red[index] = r; 1356 sc->sc_cmap_green[index] = g; 1357 sc->sc_cmap_blue[index] = b; 1358 /* 1359 * writing the dac index takes a while, in theory we can poll some 1360 * register to see when it's ready - but we better avoid writing it 1361 * unnecessarily 1362 */ 1363 if (index != sc->sc_dacw) { 1364 regwb(sc, DAC_MASK, 0xff); 1365 regwb(sc, DAC_WINDEX, index); 1366 } 1367 sc->sc_dacw = index + 1; 1368 regwb(sc, DAC_DATA, r); 1369 regwb(sc, DAC_DATA, g); 1370 regwb(sc, DAC_DATA, b); 1371 return 0; 1372 } 1373 1374 static int 1375 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1376 { 1377 uint index = cm->index; 1378 uint count = cm->count; 1379 int i, error; 1380 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1381 uint8_t *r, *g, *b; 1382 1383 if (cm->index >= 256 || cm->count > 256 || 1384 (cm->index + cm->count) > 256) 1385 return EINVAL; 1386 error = copyin(cm->red, &rbuf[index], count); 1387 if (error) 1388 return error; 1389 error = copyin(cm->green, &gbuf[index], count); 1390 if (error) 1391 return error; 1392 error = copyin(cm->blue, &bbuf[index], count); 1393 if (error) 1394 return error; 1395 1396 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1397 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1398 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1399 1400 r = &sc->sc_cmap_red[index]; 1401 g = &sc->sc_cmap_green[index]; 1402 b = &sc->sc_cmap_blue[index]; 1403 1404 for (i = 0; i < count; i++) { 1405 mach64_putpalreg(sc, index, *r, *g, *b); 1406 index++; 1407 r++, g++, b++; 1408 } 1409 return 0; 1410 } 1411 1412 static int 1413 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1414 { 1415 u_int index = cm->index; 1416 u_int count = cm->count; 1417 int error; 1418 1419 if (index >= 255 || count > 256 || index + count > 256) 1420 return EINVAL; 1421 1422 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1423 if (error) 1424 return error; 1425 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1426 if (error) 1427 return error; 1428 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1429 if (error) 1430 return error; 1431 1432 return 0; 1433 } 1434 1435 static int 1436 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1437 { 1438 struct mach64_crtcregs regs; 1439 1440 if (mach64_calc_crtcregs(sc, ®s, 1441 (struct videomode *)des->modecookie)) 1442 return 1; 1443 1444 mach64_set_crtcregs(sc, ®s); 1445 return 0; 1446 } 1447 1448 static int 1449 mach64_is_console(struct mach64_softc *sc) 1450 { 1451 bool console = 0; 1452 1453 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1454 "is_console", &console); 1455 return console; 1456 } 1457 1458 /* 1459 * wsdisplay_emulops 1460 */ 1461 1462 static void 1463 mach64_cursor(void *cookie, int on, int row, int col) 1464 { 1465 struct rasops_info *ri = cookie; 1466 struct vcons_screen *scr = ri->ri_hw; 1467 struct mach64_softc *sc = scr->scr_cookie; 1468 int x, y, wi, he; 1469 1470 wi = ri->ri_font->fontwidth; 1471 he = ri->ri_font->fontheight; 1472 1473 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1474 x = ri->ri_ccol * wi + ri->ri_xorigin; 1475 y = ri->ri_crow * he + ri->ri_yorigin; 1476 if (ri->ri_flg & RI_CURSOR) { 1477 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1478 ri->ri_flg &= ~RI_CURSOR; 1479 } 1480 ri->ri_crow = row; 1481 ri->ri_ccol = col; 1482 if (on) { 1483 x = ri->ri_ccol * wi + ri->ri_xorigin; 1484 y = ri->ri_crow * he + ri->ri_yorigin; 1485 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1486 ri->ri_flg |= RI_CURSOR; 1487 } 1488 } else { 1489 scr->scr_ri.ri_crow = row; 1490 scr->scr_ri.ri_ccol = col; 1491 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1492 } 1493 } 1494 1495 #if 0 1496 static int 1497 mach64_mapchar(void *cookie, int uni, u_int *index) 1498 { 1499 return 0; 1500 } 1501 #endif 1502 1503 static void 1504 mach64_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1505 { 1506 struct rasops_info *ri = cookie; 1507 struct wsdisplay_font *font = PICK_FONT(ri, c); 1508 struct vcons_screen *scr = ri->ri_hw; 1509 struct mach64_softc *sc = scr->scr_cookie; 1510 1511 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1512 int fg, bg, uc; 1513 uint8_t *data; 1514 int x, y, wi, he; 1515 wi = font->fontwidth; 1516 he = font->fontheight; 1517 1518 if (!CHAR_IN_FONT(c, font)) 1519 return; 1520 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1521 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f]; 1522 x = ri->ri_xorigin + col * wi; 1523 y = ri->ri_yorigin + row * he; 1524 if (c == 0x20) { 1525 mach64_rectfill(sc, x, y, wi, he, bg); 1526 } else { 1527 uc = c - font->firstchar; 1528 data = (uint8_t *)font->data + uc * 1529 ri->ri_fontscale; 1530 1531 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1532 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1533 } 1534 } 1535 } 1536 1537 static void 1538 mach64_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 1539 { 1540 struct rasops_info *ri = cookie; 1541 struct wsdisplay_font *font = PICK_FONT(ri, c); 1542 struct vcons_screen *scr = ri->ri_hw; 1543 struct mach64_softc *sc = scr->scr_cookie; 1544 uint32_t bg, latch = 0, bg8, fg8, pixel; 1545 int i, x, y, wi, he, r, g, b, aval; 1546 int r1, g1, b1, r0, g0, b0, fgo, bgo; 1547 uint8_t *data8; 1548 int rv = 0, cnt = 0; 1549 1550 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1551 return; 1552 1553 if (!CHAR_IN_FONT(c, font)) 1554 return; 1555 1556 wi = font->fontwidth; 1557 he = font->fontheight; 1558 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1559 x = ri->ri_xorigin + col * wi; 1560 y = ri->ri_yorigin + row * he; 1561 1562 if (c == 0x20) { 1563 mach64_rectfill(sc, x, y, wi, he, bg); 1564 return; 1565 } 1566 1567 rv = glyphcache_try(&sc->sc_gc, c, x, y, attr); 1568 if (rv == GC_OK) 1569 return; 1570 1571 data8 = WSFONT_GLYPH(c, font); 1572 1573 wait_for_fifo(sc, 11); 1574 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1575 regw(sc, DP_SRC, MONO_SRC_ONE | BKGD_SRC_HOST | FRGD_SRC_HOST); 1576 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1577 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1578 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1579 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1580 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1581 regw(sc, SRC_Y_X, 0); 1582 regw(sc, SRC_WIDTH1, wi); 1583 regw(sc, DST_Y_X, (x << 16) | y); 1584 regw(sc, DST_HEIGHT_WIDTH, (wi << 16) | he); 1585 1586 /* 1587 * we need the RGB colours here, so get offsets into rasops_cmap 1588 */ 1589 fgo = ((attr >> 24) & 0xf) * 3; 1590 bgo = ((attr >> 16) & 0xf) * 3; 1591 1592 r0 = rasops_cmap[bgo]; 1593 r1 = rasops_cmap[fgo]; 1594 g0 = rasops_cmap[bgo + 1]; 1595 g1 = rasops_cmap[fgo + 1]; 1596 b0 = rasops_cmap[bgo + 2]; 1597 b1 = rasops_cmap[fgo + 2]; 1598 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 1599 bg8 = R3G3B2(r0, g0, b0); 1600 fg8 = R3G3B2(r1, g1, b1); 1601 1602 wait_for_fifo(sc, 10); 1603 1604 for (i = 0; i < ri->ri_fontscale; i++) { 1605 aval = *data8; 1606 if (aval == 0) { 1607 pixel = bg8; 1608 } else if (aval == 255) { 1609 pixel = fg8; 1610 } else { 1611 r = aval * r1 + (255 - aval) * r0; 1612 g = aval * g1 + (255 - aval) * g0; 1613 b = aval * b1 + (255 - aval) * b0; 1614 pixel = ((r & 0xe000) >> 8) | 1615 ((g & 0xe000) >> 11) | 1616 ((b & 0xc000) >> 14); 1617 } 1618 latch = (latch << 8) | pixel; 1619 /* write in 32bit chunks */ 1620 if ((i & 3) == 3) { 1621 regws(sc, HOST_DATA0, latch); 1622 /* 1623 * not strictly necessary, old data should be shifted 1624 * out 1625 */ 1626 latch = 0; 1627 cnt++; 1628 if (cnt > 8) { 1629 wait_for_fifo(sc, 10); 1630 cnt = 0; 1631 } 1632 } 1633 data8++; 1634 } 1635 /* if we have pixels left in latch write them out */ 1636 if ((i & 3) != 0) { 1637 latch = latch << ((4 - (i & 3)) << 3); 1638 regws(sc, HOST_DATA0, latch); 1639 } 1640 1641 if (rv == GC_ADD) { 1642 glyphcache_add(&sc->sc_gc, c, x, y); 1643 } 1644 } 1645 1646 static void 1647 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1648 { 1649 struct rasops_info *ri = cookie; 1650 struct vcons_screen *scr = ri->ri_hw; 1651 struct mach64_softc *sc = scr->scr_cookie; 1652 int32_t xs, xd, y, width, height; 1653 1654 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1655 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1656 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1657 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1658 width = ri->ri_font->fontwidth * ncols; 1659 height = ri->ri_font->fontheight; 1660 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC); 1661 } 1662 } 1663 1664 static void 1665 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1666 { 1667 struct rasops_info *ri = cookie; 1668 struct vcons_screen *scr = ri->ri_hw; 1669 struct mach64_softc *sc = scr->scr_cookie; 1670 int32_t x, y, width, height, fg, bg, ul; 1671 1672 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1673 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1674 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1675 width = ri->ri_font->fontwidth * ncols; 1676 height = ri->ri_font->fontheight; 1677 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1678 1679 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1680 } 1681 } 1682 1683 static void 1684 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1685 { 1686 struct rasops_info *ri = cookie; 1687 struct vcons_screen *scr = ri->ri_hw; 1688 struct mach64_softc *sc = scr->scr_cookie; 1689 int32_t x, ys, yd, width, height; 1690 1691 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1692 x = ri->ri_xorigin; 1693 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1694 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1695 width = ri->ri_emuwidth; 1696 height = ri->ri_font->fontheight*nrows; 1697 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC); 1698 } 1699 } 1700 1701 static void 1702 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1703 { 1704 struct rasops_info *ri = cookie; 1705 struct vcons_screen *scr = ri->ri_hw; 1706 struct mach64_softc *sc = scr->scr_cookie; 1707 int32_t x, y, width, height, fg, bg, ul; 1708 1709 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1710 x = ri->ri_xorigin; 1711 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1712 width = ri->ri_emuwidth; 1713 height = ri->ri_font->fontheight * nrows; 1714 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1715 1716 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1717 } 1718 } 1719 1720 static void 1721 mach64_bitblt(void *cookie, int xs, int ys, int xd, int yd, int width, int height, int rop) 1722 { 1723 struct mach64_softc *sc = cookie; 1724 uint32_t dest_ctl = 0; 1725 1726 wait_for_fifo(sc, 10); 1727 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1728 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1729 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1730 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1731 if (yd < ys) { 1732 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1733 } else { 1734 ys += height - 1; 1735 yd += height - 1; 1736 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1737 } 1738 if (xd < xs) { 1739 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1740 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1741 } else { 1742 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1743 xs += width - 1; 1744 xd += width - 1; 1745 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1746 } 1747 regw(sc, DST_CNTL, dest_ctl); 1748 1749 regw(sc, SRC_Y_X, (xs << 16) | ys); 1750 regw(sc, SRC_WIDTH1, width); 1751 regw(sc, DST_Y_X, (xd << 16) | yd); 1752 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1753 } 1754 1755 static void 1756 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1757 int height, uint32_t fg, uint32_t bg) 1758 { 1759 wait_for_idle(sc); 1760 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1761 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1762 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1763 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1764 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1765 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1766 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1767 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1768 regw(sc, DP_BKGD_CLR, bg); 1769 regw(sc, DP_FRGD_CLR, fg); 1770 regw(sc, SRC_Y_X, 0); 1771 regw(sc, SRC_WIDTH1, width); 1772 regw(sc, DST_Y_X, (xd << 16) | yd); 1773 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1774 /* now feed the data into the chip */ 1775 } 1776 1777 static void 1778 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1779 { 1780 int i; 1781 uint32_t latch = 0, bork; 1782 int shift = 0; 1783 int reg = 0; 1784 1785 for (i = 0; i < count; i++) { 1786 bork = data[i]; 1787 latch |= (bork << shift); 1788 if (shift == 24) { 1789 regw(sc, HOST_DATA0 + reg, latch); 1790 latch = 0; 1791 shift = 0; 1792 reg = (reg + 4) & 0x3c; 1793 } else 1794 shift += 8; 1795 } 1796 if (shift != 0) /* 24 */ 1797 regw(sc, HOST_DATA0 + reg, latch); 1798 } 1799 1800 1801 static void 1802 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1803 int colour) 1804 { 1805 wait_for_fifo(sc, 11); 1806 regw(sc, DP_FRGD_CLR, colour); 1807 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1808 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1809 regw(sc, DP_MIX, MIX_SRC << 16); 1810 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1811 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1812 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1813 1814 regw(sc, SRC_Y_X, (x << 16) | y); 1815 regw(sc, SRC_WIDTH1, width); 1816 regw(sc, DST_Y_X, (x << 16) | y); 1817 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1818 } 1819 1820 static void 1821 mach64_clearscreen(struct mach64_softc *sc) 1822 { 1823 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1824 } 1825 1826 1827 #if 0 1828 static void 1829 mach64_showpal(struct mach64_softc *sc) 1830 { 1831 int i, x = 0; 1832 1833 for (i = 0; i < 16; i++) { 1834 mach64_rectfill(sc, x, 0, 64, 64, i); 1835 x += 64; 1836 } 1837 } 1838 #endif 1839 1840 /* 1841 * wsdisplay_accessops 1842 */ 1843 1844 static int 1845 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1846 struct lwp *l) 1847 { 1848 struct vcons_data *vd = v; 1849 struct mach64_softc *sc = vd->cookie; 1850 struct wsdisplay_fbinfo *wdf; 1851 struct vcons_screen *ms = vd->active; 1852 1853 switch (cmd) { 1854 case WSDISPLAYIO_GTYPE: 1855 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1856 return 0; 1857 1858 case WSDISPLAYIO_LINEBYTES: 1859 *(u_int *)data = sc->virt_x * sc->bits_per_pixel / 8; 1860 return 0; 1861 1862 case WSDISPLAYIO_GINFO: 1863 wdf = (void *)data; 1864 wdf->height = sc->virt_y; 1865 wdf->width = sc->virt_x; 1866 wdf->depth = sc->bits_per_pixel; 1867 wdf->cmsize = 256; 1868 return 0; 1869 1870 case WSDISPLAYIO_GETCMAP: 1871 return mach64_getcmap(sc, 1872 (struct wsdisplay_cmap *)data); 1873 1874 case WSDISPLAYIO_PUTCMAP: 1875 return mach64_putcmap(sc, 1876 (struct wsdisplay_cmap *)data); 1877 1878 /* PCI config read/write passthrough. */ 1879 case PCI_IOC_CFGREAD: 1880 case PCI_IOC_CFGWRITE: 1881 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1882 cmd, data, flag, l); 1883 1884 case WSDISPLAYIO_GET_BUSID: 1885 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1886 sc->sc_pcitag, data); 1887 1888 case WSDISPLAYIO_SMODE: { 1889 int new_mode = *(int*)data; 1890 if (new_mode != sc->sc_mode) { 1891 sc->sc_mode = new_mode; 1892 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1893 && (ms != NULL)) 1894 { 1895 /* restore initial video mode */ 1896 mach64_init(sc); 1897 mach64_init_engine(sc); 1898 mach64_init_lut(sc); 1899 mach64_modeswitch(sc, sc->sc_my_mode); 1900 vcons_redraw_screen(ms); 1901 } 1902 } 1903 } 1904 return 0; 1905 case WSDISPLAYIO_GET_EDID: { 1906 struct wsdisplayio_edid_info *d = data; 1907 return wsdisplayio_get_edid(sc->sc_dev, d); 1908 } 1909 } 1910 return EPASSTHROUGH; 1911 } 1912 1913 static paddr_t 1914 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1915 { 1916 struct vcons_data *vd = v; 1917 struct mach64_softc *sc = vd->cookie; 1918 paddr_t pa; 1919 pcireg_t reg; 1920 1921 #ifndef __sparc64__ 1922 /* 1923 *'regular' framebuffer mmap()ing 1924 * disabled on sparc64 because some ATI firmware likes to map some PCI 1925 * resources to addresses that would collide with this ( like some Rage 1926 * IIc which uses 0x2000 for the 2nd register block ) 1927 * Other 64bit architectures might run into similar problems. 1928 */ 1929 if (offset<sc->sc_apersize) { 1930 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, offset, 1931 prot, BUS_SPACE_MAP_LINEAR); 1932 return pa; 1933 } 1934 #endif 1935 1936 /* 1937 * restrict all other mappings to processes with superuser privileges 1938 * or the kernel itself 1939 */ 1940 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1941 NULL, NULL, NULL, NULL) != 0) { 1942 return -1; 1943 } 1944 1945 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1946 if (reg != sc->sc_regbase) { 1947 #ifdef DIAGNOSTIC 1948 printf("%s: BAR 0x18 changed! (%x %x)\n", 1949 device_xname(sc->sc_dev), (uint32_t)sc->sc_regbase, 1950 (uint32_t)reg); 1951 #endif 1952 sc->sc_regbase = reg; 1953 } 1954 1955 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1956 if (reg != sc->sc_aperbase) { 1957 #ifdef DIAGNOSTIC 1958 printf("%s: BAR 0x10 changed! (%x %x)\n", 1959 device_xname(sc->sc_dev), (uint32_t)sc->sc_aperbase, 1960 (uint32_t)reg); 1961 #endif 1962 sc->sc_aperbase = reg; 1963 } 1964 1965 if ((offset >= sc->sc_aperbase) && 1966 (offset < (sc->sc_aperbase + sc->sc_apersize))) { 1967 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1968 BUS_SPACE_MAP_LINEAR); 1969 return pa; 1970 } 1971 1972 if ((offset >= sc->sc_regbase) && 1973 (offset < (sc->sc_regbase + sc->sc_regsize))) { 1974 pa = bus_space_mmap(sc->sc_regt, offset, 0, prot, 1975 BUS_SPACE_MAP_LINEAR); 1976 return pa; 1977 } 1978 1979 if ((offset >= sc->sc_rom.vb_base) && 1980 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 1981 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1982 BUS_SPACE_MAP_LINEAR); 1983 return pa; 1984 } 1985 1986 #ifdef PCI_MAGIC_IO_RANGE 1987 if ((offset >= PCI_MAGIC_IO_RANGE) && 1988 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 1989 return bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1990 0, prot, 0); 1991 } 1992 #endif 1993 1994 return -1; 1995 } 1996 1997 #if 0 1998 static int 1999 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 2000 { 2001 2002 return 0; 2003 } 2004 #endif 2005 2006 void 2007 machfb_blank(struct mach64_softc *sc, int blank) 2008 { 2009 uint32_t reg; 2010 2011 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 2012 2013 switch (blank) 2014 { 2015 case 0: 2016 reg = regr(sc, CRTC_GEN_CNTL); 2017 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 2018 sc->sc_blanked = 0; 2019 break; 2020 case 1: 2021 reg = regr(sc, CRTC_GEN_CNTL); 2022 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 2023 sc->sc_blanked = 1; 2024 break; 2025 default: 2026 break; 2027 } 2028 } 2029 2030 /* framebuffer device support */ 2031 #ifdef __sparc__ 2032 2033 static void 2034 machfb_unblank(device_t dev) 2035 { 2036 struct mach64_softc *sc = device_private(dev); 2037 2038 machfb_blank(sc, 0); 2039 } 2040 2041 static void 2042 machfb_fbattach(struct mach64_softc *sc) 2043 { 2044 struct fbdevice *fb = &sc->sc_fb; 2045 2046 fb->fb_device = sc->sc_dev; 2047 fb->fb_driver = &machfb_fbdriver; 2048 2049 fb->fb_type.fb_cmsize = 256; 2050 fb->fb_type.fb_size = sc->memsize; 2051 2052 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 2053 fb->fb_flags = sc->sc_dev->dv_cfdata->cf_flags & FB_USERMASK; 2054 fb->fb_type.fb_depth = sc->bits_per_pixel; 2055 fb->fb_type.fb_width = sc->virt_x; 2056 fb->fb_type.fb_height = sc->virt_y; 2057 2058 fb_attach(fb, sc->sc_console); 2059 } 2060 2061 int 2062 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 2063 { 2064 struct mach64_softc *sc; 2065 2066 sc = device_lookup_private(&machfb_cd, minor(dev)); 2067 if (sc == NULL) 2068 return ENXIO; 2069 sc->sc_locked = 1; 2070 2071 #ifdef MACHFB_DEBUG 2072 printf("machfb_fbopen(%d)\n", minor(dev)); 2073 #endif 2074 return 0; 2075 } 2076 2077 int 2078 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 2079 { 2080 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 2081 2082 #ifdef MACHFB_DEBUG 2083 printf("machfb_fbclose()\n"); 2084 #endif 2085 mach64_init_engine(sc); 2086 mach64_init_lut(sc); 2087 sc->sc_locked = 0; 2088 return 0; 2089 } 2090 2091 int 2092 machfb_fbioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 2093 { 2094 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 2095 2096 #ifdef MACHFB_DEBUG 2097 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 2098 #endif 2099 switch (cmd) { 2100 case FBIOGTYPE: 2101 *(struct fbtype *)data = sc->sc_fb.fb_type; 2102 break; 2103 2104 case FBIOGATTR: 2105 #define fba ((struct fbgattr *)data) 2106 fba->real_type = sc->sc_fb.fb_type.fb_type; 2107 fba->owner = 0; /* XXX ??? */ 2108 fba->fbtype = sc->sc_fb.fb_type; 2109 fba->sattr.flags = 0; 2110 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 2111 fba->sattr.dev_specific[0] = sc->sc_nbus; 2112 fba->sattr.dev_specific[1] = sc->sc_ndev; 2113 fba->sattr.dev_specific[2] = sc->sc_nfunc; 2114 fba->sattr.dev_specific[3] = -1; 2115 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 2116 fba->emu_types[1] = -1; 2117 #undef fba 2118 break; 2119 2120 #if 0 2121 case FBIOGETCMAP: 2122 #define p ((struct fbcmap *)data) 2123 return bt_getcmap(p, &sc->sc_cmap, 256, 1); 2124 2125 case FBIOPUTCMAP: 2126 /* copy to software map */ 2127 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 2128 if (error) 2129 return error; 2130 /* now blast them into the chip */ 2131 /* XXX should use retrace interrupt */ 2132 cg6_loadcmap(sc, p->index, p->count); 2133 #undef p 2134 break; 2135 #endif 2136 case FBIOGVIDEO: 2137 *(int *)data = sc->sc_blanked; 2138 break; 2139 2140 case FBIOSVIDEO: 2141 machfb_blank(sc, *(int *)data); 2142 break; 2143 2144 #if 0 2145 case FBIOGCURSOR: 2146 break; 2147 2148 case FBIOSCURSOR: 2149 break; 2150 2151 case FBIOGCURPOS: 2152 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 2153 break; 2154 2155 case FBIOSCURPOS: 2156 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 2157 break; 2158 2159 case FBIOGCURMAX: 2160 /* max cursor size is 32x32 */ 2161 ((struct fbcurpos *)data)->x = 32; 2162 ((struct fbcurpos *)data)->y = 32; 2163 break; 2164 #endif 2165 case PCI_IOC_CFGREAD: 2166 case PCI_IOC_CFGWRITE: { 2167 int ret; 2168 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 2169 cmd, data, flags, l); 2170 2171 #ifdef MACHFB_DEBUG 2172 printf("pci_devioctl: %d\n", ret); 2173 #endif 2174 return ret; 2175 } 2176 2177 case WSDISPLAYIO_GET_BUSID: 2178 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 2179 sc->sc_pcitag, data); 2180 2181 default: 2182 return ENOTTY; 2183 } 2184 #ifdef MACHFB_DEBUG 2185 printf("machfb_fbioctl done\n"); 2186 #endif 2187 return 0; 2188 } 2189 2190 paddr_t 2191 machfb_fbmmap(dev_t dev, off_t off, int prot) 2192 { 2193 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 2194 2195 if (sc != NULL) 2196 return mach64_mmap(&sc->vd, NULL, off, prot); 2197 2198 return 0; 2199 } 2200 2201 #endif /* __sparc__ */ 2202
Indexes created Fri Oct 03 02:09:57 GMT 2025