machfb.c revision 1.85
1 /* $NetBSD: machfb.c,v 1.85 2012/10/05 01:12:15 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.85 2012/10/05 01:12:15 macallan Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #ifdef __sparc__ 58 #include <dev/sun/fbio.h> 59 #include <dev/sun/fbvar.h> 60 #include <sys/conf.h> 61 #else 62 #include <dev/wscons/wsdisplayvar.h> 63 #endif 64 65 #include <dev/wscons/wsconsio.h> 66 #include <dev/wsfont/wsfont.h> 67 #include <dev/rasops/rasops.h> 68 #include <dev/pci/wsdisplay_pci.h> 69 70 #include <dev/wscons/wsdisplay_vconsvar.h> 71 #include <dev/wscons/wsdisplay_glyphcachevar.h> 72 73 #include "opt_wsemul.h" 74 #include "opt_machfb.h" 75 76 #define MACH64_REG_SIZE 0x800 77 #define MACH64_REG_OFF 0x7ff800 78 79 #define NBARS 3 /* number of Mach64 PCI BARs */ 80 81 struct vga_bar { 82 bus_addr_t vb_base; 83 bus_size_t vb_size; 84 pcireg_t vb_type; 85 int vb_flags; 86 }; 87 88 struct mach64_softc { 89 device_t sc_dev; 90 #ifdef __sparc__ 91 struct fbdevice sc_fb; 92 #endif 93 pci_chipset_tag_t sc_pc; 94 pcitag_t sc_pcitag; 95 96 struct vga_bar sc_bars[NBARS]; 97 struct vga_bar sc_rom; 98 99 #define sc_aperbase sc_bars[0].vb_base 100 #define sc_apersize sc_bars[0].vb_size 101 102 #define sc_iobase sc_bars[1].vb_base 103 #define sc_iosize sc_bars[1].vb_size 104 105 #define sc_regbase sc_bars[2].vb_base 106 #define sc_regsize sc_bars[2].vb_size 107 108 bus_space_tag_t sc_regt; 109 bus_space_tag_t sc_memt; 110 bus_space_tag_t sc_iot; 111 bus_space_handle_t sc_regh; 112 bus_space_handle_t sc_memh; 113 #if 0 114 void *sc_aperture; /* mapped aperture vaddr */ 115 void *sc_registers; /* mapped registers vaddr */ 116 #endif 117 uint32_t sc_nbus, sc_ndev, sc_nfunc; 118 size_t memsize; 119 int memtype; 120 121 int sc_mode; 122 int sc_bg; 123 int sc_locked; 124 125 int has_dsp; 126 int bits_per_pixel; 127 int max_x; 128 int max_y; 129 int virt_x; 130 int virt_y; 131 int color_depth; 132 133 int mem_freq; 134 int ramdac_freq; 135 int ref_freq; 136 137 int ref_div; 138 int log2_vclk_post_div; 139 int vclk_post_div; 140 int vclk_fb_div; 141 int mclk_post_div; 142 int mclk_fb_div; 143 int sc_clock; /* which clock to use */ 144 145 struct videomode *sc_my_mode; 146 int sc_edid_size; 147 uint8_t sc_edid_data[1024]; 148 149 u_char sc_cmap_red[256]; 150 u_char sc_cmap_green[256]; 151 u_char sc_cmap_blue[256]; 152 int sc_dacw, sc_blanked, sc_console; 153 struct vcons_data vd; 154 struct wsdisplay_accessops sc_accessops; 155 glyphcache sc_gc; 156 }; 157 158 struct mach64_crtcregs { 159 uint32_t h_total_disp; 160 uint32_t h_sync_strt_wid; 161 uint32_t v_total_disp; 162 uint32_t v_sync_strt_wid; 163 uint32_t gen_cntl; 164 uint32_t clock_cntl; 165 uint32_t color_depth; 166 uint32_t dot_clock; 167 }; 168 169 static struct { 170 uint16_t chip_id; 171 uint32_t ramdac_freq; 172 } const mach64_info[] = { 173 { PCI_PRODUCT_ATI_MACH64_GX, 135000 }, 174 { PCI_PRODUCT_ATI_MACH64_CX, 135000 }, 175 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 176 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 185 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 186 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 189 #if 0 190 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 192 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 193 #endif 194 { PCI_PRODUCT_ATI_RAGE_L_MOB_M1_PCI, 230000 }, 195 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 196 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 197 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 198 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 199 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 200 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 201 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 202 }; 203 204 static int mach64_chip_id, mach64_chip_rev; 205 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 206 207 static const char *mach64_gx_memtype_names[] = { 208 "DRAM", "VRAM", "VRAM", "DRAM", 209 "DRAM", "VRAM", "VRAM", "(unknown type)" 210 }; 211 212 static const char *mach64_memtype_names[] = { 213 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 214 "(unknown type)" 215 }; 216 217 static struct videomode mach64_modes[] = { 218 /* 640x400 @ 70 Hz, 31.5 kHz */ 219 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0, NULL, }, 220 /* 640x480 @ 72 Hz, 36.5 kHz */ 221 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0, NULL, }, 222 /* 800x600 @ 72 Hz, 48.0 kHz */ 223 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 224 VID_PHSYNC | VID_PVSYNC, NULL, }, 225 /* 1024x768 @ 70 Hz, 56.5 kHz */ 226 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 227 VID_NHSYNC | VID_NVSYNC, NULL, }, 228 /* 1152x864 @ 70 Hz, 62.4 kHz */ 229 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0, NULL, }, 230 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 231 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 232 VID_NHSYNC | VID_NVSYNC, NULL, } 233 }; 234 235 extern const u_char rasops_cmap[768]; 236 237 static int mach64_match(device_t, cfdata_t, void *); 238 static void mach64_attach(device_t, device_t, void *); 239 240 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 241 NULL, NULL); 242 243 static void mach64_init(struct mach64_softc *); 244 static int mach64_get_memsize(struct mach64_softc *); 245 static int mach64_get_max_ramdac(struct mach64_softc *); 246 247 #if defined(__sparc__) || defined(__powerpc__) 248 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 249 #endif 250 251 static int mach64_calc_crtcregs(struct mach64_softc *, 252 struct mach64_crtcregs *, 253 struct videomode *); 254 static void mach64_set_crtcregs(struct mach64_softc *, 255 struct mach64_crtcregs *); 256 257 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 258 static void mach64_set_dsp(struct mach64_softc *); 259 static void mach64_set_pll(struct mach64_softc *, int); 260 static void mach64_reset_engine(struct mach64_softc *); 261 static void mach64_init_engine(struct mach64_softc *); 262 #if 0 263 static void mach64_adjust_frame(struct mach64_softc *, int, int); 264 #endif 265 static void mach64_init_lut(struct mach64_softc *); 266 267 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 268 static int mach64_set_screentype(struct mach64_softc *, 269 const struct wsscreen_descr *); 270 static int mach64_is_console(struct mach64_softc *); 271 272 static void mach64_cursor(void *, int, int, int); 273 #if 0 274 static int mach64_mapchar(void *, int, u_int *); 275 #endif 276 static void mach64_putchar_mono(void *, int, int, u_int, long); 277 static void mach64_putchar_aa8(void *, int, int, u_int, long); 278 static void mach64_copycols(void *, int, int, int, int); 279 static void mach64_erasecols(void *, int, int, int, long); 280 static void mach64_copyrows(void *, int, int, int); 281 static void mach64_eraserows(void *, int, int, long); 282 static void mach64_clearscreen(struct mach64_softc *); 283 284 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 285 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 286 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 287 uint8_t, uint8_t); 288 static void mach64_bitblt(void *, int, int, int, int, int, int, int); 289 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 290 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 291 uint32_t, uint32_t); 292 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 293 #if 0 294 static void mach64_showpal(struct mach64_softc *); 295 #endif 296 297 static void machfb_blank(struct mach64_softc *, int); 298 static int machfb_drm_print(void *, const char *); 299 300 static struct wsscreen_descr mach64_defaultscreen = { 301 "default", 302 80, 30, 303 NULL, 304 8, 16, 305 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 306 &default_mode 307 }, mach64_80x25_screen = { 308 "80x25", 80, 25, 309 NULL, 310 8, 16, 311 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 312 &mach64_modes[0] 313 }, mach64_80x30_screen = { 314 "80x30", 80, 30, 315 NULL, 316 8, 16, 317 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 318 &mach64_modes[1] 319 }, mach64_80x40_screen = { 320 "80x40", 80, 40, 321 NULL, 322 8, 10, 323 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 324 &mach64_modes[0] 325 }, mach64_80x50_screen = { 326 "80x50", 80, 50, 327 NULL, 328 8, 8, 329 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 330 &mach64_modes[0] 331 }, mach64_100x37_screen = { 332 "100x37", 100, 37, 333 NULL, 334 8, 16, 335 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 336 &mach64_modes[2] 337 }, mach64_128x48_screen = { 338 "128x48", 128, 48, 339 NULL, 340 8, 16, 341 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 342 &mach64_modes[3] 343 }, mach64_144x54_screen = { 344 "144x54", 144, 54, 345 NULL, 346 8, 16, 347 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 348 &mach64_modes[4] 349 }, mach64_160x64_screen = { 350 "160x54", 160, 64, 351 NULL, 352 8, 16, 353 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 354 &mach64_modes[5] 355 }; 356 357 static const struct wsscreen_descr *_mach64_scrlist[] = { 358 &mach64_defaultscreen, 359 &mach64_80x25_screen, 360 &mach64_80x30_screen, 361 &mach64_80x40_screen, 362 &mach64_80x50_screen, 363 &mach64_100x37_screen, 364 &mach64_128x48_screen, 365 &mach64_144x54_screen, 366 &mach64_160x64_screen 367 }; 368 369 static struct wsscreen_list mach64_screenlist = { 370 __arraycount(_mach64_scrlist), 371 _mach64_scrlist 372 }; 373 374 static int mach64_ioctl(void *, void *, u_long, void *, int, 375 struct lwp *); 376 static paddr_t mach64_mmap(void *, void *, off_t, int); 377 378 #if 0 379 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 380 #endif 381 382 383 static struct vcons_screen mach64_console_screen; 384 385 /* framebuffer device, SPARC-only so far */ 386 #ifdef __sparc__ 387 388 static void machfb_unblank(device_t); 389 static void machfb_fbattach(struct mach64_softc *); 390 391 extern struct cfdriver machfb_cd; 392 393 dev_type_open(machfb_fbopen); 394 dev_type_close(machfb_fbclose); 395 dev_type_ioctl(machfb_fbioctl); 396 dev_type_mmap(machfb_fbmmap); 397 398 /* frame buffer generic driver */ 399 static struct fbdriver machfb_fbdriver = { 400 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 401 machfb_fbmmap, nokqfilter 402 }; 403 404 #endif /* __sparc__ */ 405 406 /* 407 * Inline functions for getting access to register aperture. 408 */ 409 410 static inline uint32_t 411 regr(struct mach64_softc *sc, uint32_t index) 412 { 413 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index + 0x400); 414 } 415 416 static inline uint8_t 417 regrb(struct mach64_softc *sc, uint32_t index) 418 { 419 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index + 0x400); 420 } 421 422 static inline void 423 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 424 { 425 bus_space_write_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 426 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 427 BUS_SPACE_BARRIER_WRITE); 428 } 429 430 static inline void 431 regws(struct mach64_softc *sc, uint32_t index, uint32_t data) 432 { 433 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 434 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 4, 435 BUS_SPACE_BARRIER_WRITE); 436 } 437 438 static inline void 439 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 440 { 441 bus_space_write_1(sc->sc_regt, sc->sc_regh, index + 0x400, data); 442 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 1, 443 BUS_SPACE_BARRIER_WRITE); 444 } 445 446 static inline void 447 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 448 { 449 uint32_t reg; 450 451 reg = regr(sc, CLOCK_CNTL); 452 reg |= PLL_WR_EN; 453 regw(sc, CLOCK_CNTL, reg); 454 reg &= ~(PLL_ADDR | PLL_DATA); 455 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 456 reg |= data << PLL_DATA_SHIFT; 457 reg |= CLOCK_STROBE; 458 regw(sc, CLOCK_CNTL, reg); 459 reg &= ~PLL_WR_EN; 460 regw(sc, CLOCK_CNTL, reg); 461 } 462 463 static inline uint8_t 464 regrb_pll(struct mach64_softc *sc, uint32_t index) 465 { 466 467 regwb(sc, CLOCK_CNTL + 1, index << 2); 468 return regrb(sc, CLOCK_CNTL + 2); 469 } 470 471 static inline void 472 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 473 { 474 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 475 continue; 476 } 477 478 static inline void 479 wait_for_idle(struct mach64_softc *sc) 480 { 481 wait_for_fifo(sc, 16); 482 while ((regr(sc, GUI_STAT) & 1) != 0) 483 continue; 484 } 485 486 static int 487 mach64_match(device_t parent, cfdata_t match, void *aux) 488 { 489 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 490 int i; 491 492 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 493 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 494 return 0; 495 496 for (i = 0; i < __arraycount(mach64_info); i++) 497 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 498 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 499 mach64_chip_rev = PCI_REVISION(pa->pa_class); 500 return 100; 501 } 502 503 return 0; 504 } 505 506 static void 507 mach64_attach(device_t parent, device_t self, void *aux) 508 { 509 struct mach64_softc *sc = device_private(self); 510 struct pci_attach_args *pa = aux; 511 struct rasops_info *ri; 512 prop_data_t edid_data; 513 #if defined(__sparc__) || defined(__powerpc__) 514 const struct videomode *mode = NULL; 515 #endif 516 int bar, id, expected_id; 517 int is_gx; 518 const char **memtype_names; 519 struct wsemuldisplaydev_attach_args aa; 520 long defattr; 521 int setmode, width, height; 522 pcireg_t screg; 523 uint32_t reg; 524 const pcireg_t enables = PCI_COMMAND_MEM_ENABLE; 525 int use_mmio = FALSE; 526 527 sc->sc_dev = self; 528 sc->sc_pc = pa->pa_pc; 529 sc->sc_pcitag = pa->pa_tag; 530 sc->sc_dacw = -1; 531 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 532 sc->sc_nbus = pa->pa_bus; 533 sc->sc_ndev = pa->pa_device; 534 sc->sc_nfunc = pa->pa_function; 535 sc->sc_locked = 0; 536 sc->sc_iot = pa->pa_iot; 537 sc->sc_accessops.ioctl = mach64_ioctl; 538 sc->sc_accessops.mmap = mach64_mmap; 539 540 pci_aprint_devinfo(pa, "Graphics processor"); 541 #ifdef MACHFB_DEBUG 542 printf(prop_dictionary_externalize(device_properties(self))); 543 #endif 544 545 /* enable memory access */ 546 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 547 if ((screg & enables) != enables) { 548 screg |= enables; 549 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 550 PCI_COMMAND_STATUS_REG, screg); 551 } 552 for (bar = 0; bar < NBARS; bar++) { 553 reg = PCI_MAPREG_START + (bar * 4); 554 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 555 sc->sc_pcitag, reg); 556 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 557 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 558 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 559 } 560 aprint_debug_dev(sc->sc_dev, "aperture size %08x\n", 561 (uint32_t)sc->sc_apersize); 562 563 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 564 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 565 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 566 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 567 sc->sc_memt = pa->pa_memt; 568 569 /* use MMIO register aperture if available */ 570 if ((sc->sc_regbase != 0) && (sc->sc_regbase != 0xffffffff)) { 571 if (pci_mapreg_map(pa, MACH64_BAR_MMIO, PCI_MAPREG_TYPE_MEM, 0, 572 &sc->sc_regt, &sc->sc_regh, &sc->sc_regbase, 573 &sc->sc_regsize) == 0) { 574 575 /* 576 * the MMIO aperture maps both 1KB register blocks, but 577 * all register offsets are relative to the 2nd one so 578 * for now fix this up in MACH64_REG_OFF and the access 579 * functions 580 */ 581 aprint_normal_dev(sc->sc_dev, "using MMIO aperture\n"); 582 use_mmio = TRUE; 583 } 584 } 585 if (!use_mmio) { 586 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 587 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 588 panic("%s: failed to map aperture", 589 device_xname(sc->sc_dev)); 590 } 591 592 sc->sc_regt = sc->sc_memt; 593 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 594 MACH64_REG_SIZE, &sc->sc_regh); 595 } 596 597 mach64_init(sc); 598 599 aprint_normal_dev(sc->sc_dev, 600 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 601 (u_int)(sc->sc_apersize / (1024 * 1024)), 602 (u_int)sc->sc_aperbase, (u_int)(sc->sc_regsize / 1024), 603 (u_int)sc->sc_regbase); 604 605 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 606 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 607 608 prop_dictionary_get_uint32(device_properties(self), "width", &width); 609 prop_dictionary_get_uint32(device_properties(self), "height", &height); 610 611 if ((edid_data = prop_dictionary_get(device_properties(self), "EDID")) 612 != NULL) { 613 struct edid_info ei; 614 615 sc->sc_edid_size = min(1024, prop_data_size(edid_data)); 616 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 617 memcpy(sc->sc_edid_data, prop_data_data_nocopy(edid_data), 618 sc->sc_edid_size); 619 620 edid_parse(sc->sc_edid_data, &ei); 621 622 #ifdef MACHFB_DEBUG 623 edid_print(&ei); 624 #endif 625 } 626 627 is_gx = 0; 628 switch(mach64_chip_id) { 629 case PCI_PRODUCT_ATI_MACH64_GX: 630 case PCI_PRODUCT_ATI_MACH64_CX: 631 is_gx = 1; 632 case PCI_PRODUCT_ATI_MACH64_CT: 633 sc->has_dsp = 0; 634 break; 635 case PCI_PRODUCT_ATI_MACH64_VT: 636 case PCI_PRODUCT_ATI_RAGE_II: 637 if((mach64_chip_rev & 0x07) == 0) { 638 sc->has_dsp = 0; 639 break; 640 } 641 /* Otherwise fall through. */ 642 default: 643 sc->has_dsp = 1; 644 } 645 646 memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names; 647 648 sc->memsize = mach64_get_memsize(sc); 649 650 if(is_gx) 651 sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07; 652 else 653 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 654 655 /* 656 * XXX is there any way to calculate reference frequency from 657 * known values? 658 */ 659 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 660 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 661 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 662 aprint_normal_dev(sc->sc_dev, "ref_freq=29.498MHz\n"); 663 sc->ref_freq = 29498; 664 } else 665 sc->ref_freq = 14318; 666 667 reg = regr(sc, CLOCK_CNTL); 668 aprint_debug("CLOCK_CNTL: %08x\n", reg); 669 sc->sc_clock = reg & 3; 670 aprint_debug("using clock %d\n", sc->sc_clock); 671 672 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 673 aprint_debug("ref_div: %d\n", sc->ref_div); 674 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 675 aprint_debug("mclk_fb_div: %d\n", sc->mclk_fb_div); 676 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 677 (sc->ref_div * 2); 678 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 679 (sc->mem_freq * sc->ref_div); 680 sc->ramdac_freq = mach64_get_max_ramdac(sc); 681 aprint_normal_dev(sc->sc_dev, 682 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 683 (u_long)sc->memsize, 684 memtype_names[sc->memtype], 685 sc->mem_freq / 1000, sc->mem_freq % 1000, 686 sc->ramdac_freq / 1000); 687 688 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 689 switch(mach64_chip_id) { 690 case PCI_PRODUCT_ATI_MACH64_GX: 691 expected_id = 0x00d7; 692 break; 693 case PCI_PRODUCT_ATI_MACH64_CX: 694 expected_id = 0x0057; 695 break; 696 default: 697 /* Most chip IDs match their PCI product ID. */ 698 expected_id = mach64_chip_id; 699 } 700 701 if (id != expected_id) { 702 aprint_error_dev(sc->sc_dev, 703 "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id); 704 return; 705 } 706 707 sc->sc_console = mach64_is_console(sc); 708 aprint_debug("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 709 #if defined(__sparc__) || defined(__powerpc__) 710 if (sc->sc_console) { 711 if (mode != NULL) { 712 memcpy(&default_mode, mode, sizeof(struct videomode)); 713 setmode = 1; 714 } else { 715 mach64_get_mode(sc, &default_mode); 716 setmode = 0; 717 } 718 sc->sc_my_mode = &default_mode; 719 } else { 720 /* fill in default_mode if it's empty */ 721 mach64_get_mode(sc, &default_mode); 722 if (default_mode.dot_clock == 0) { 723 memcpy(&default_mode, &mach64_modes[4], 724 sizeof(default_mode)); 725 } 726 sc->sc_my_mode = &default_mode; 727 setmode = 1; 728 } 729 #else 730 if (default_mode.dot_clock == 0) { 731 memcpy(&default_mode, &mach64_modes[0], 732 sizeof(default_mode)); 733 } 734 sc->sc_my_mode = &mach64_modes[0]; 735 setmode = 1; 736 #endif 737 738 sc->bits_per_pixel = 8; 739 sc->virt_x = sc->sc_my_mode->hdisplay; 740 sc->virt_y = sc->sc_my_mode->vdisplay; 741 sc->max_x = sc->virt_x - 1; 742 sc->max_y = (sc->memsize * 1024) / 743 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 744 745 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 746 747 mach64_init_engine(sc); 748 749 if (setmode) 750 mach64_modeswitch(sc, sc->sc_my_mode); 751 752 aprint_normal_dev(sc->sc_dev, 753 "initial resolution %dx%d at %d bpp\n", 754 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 755 sc->bits_per_pixel); 756 757 #ifdef __sparc__ 758 machfb_fbattach(sc); 759 #endif 760 761 wsfont_init(); 762 763 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &sc->sc_accessops); 764 sc->vd.init_screen = mach64_init_screen; 765 766 sc->sc_gc.gc_bitblt = mach64_bitblt; 767 sc->sc_gc.gc_blitcookie = sc; 768 sc->sc_gc.gc_rop = MIX_SRC; 769 770 ri = &mach64_console_screen.scr_ri; 771 if (sc->sc_console) { 772 773 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 774 &defattr); 775 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 776 777 mach64_defaultscreen.textops = &ri->ri_ops; 778 mach64_defaultscreen.capabilities = ri->ri_caps; 779 mach64_defaultscreen.nrows = ri->ri_rows; 780 mach64_defaultscreen.ncols = ri->ri_cols; 781 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 782 ((sc->memsize * 1024) / sc->sc_my_mode->hdisplay) - 783 sc->sc_my_mode->vdisplay - 5, 784 sc->sc_my_mode->hdisplay, 785 ri->ri_font->fontwidth, 786 ri->ri_font->fontheight, 787 defattr); 788 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 789 } else { 790 /* 791 * since we're not the console we can postpone the rest 792 * until someone actually allocates a screen for us 793 */ 794 mach64_modeswitch(sc, sc->sc_my_mode); 795 if (mach64_console_screen.scr_ri.ri_rows == 0) { 796 /* do some minimal setup to avoid weirdnesses later */ 797 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 798 &defattr); 799 } 800 801 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 802 ((sc->memsize * 1024) / sc->sc_my_mode->hdisplay) - 803 sc->sc_my_mode->vdisplay - 5, 804 sc->sc_my_mode->hdisplay, 805 ri->ri_font->fontwidth, 806 ri->ri_font->fontheight, 807 defattr); 808 } 809 810 sc->sc_bg = mach64_console_screen.scr_ri.ri_devcmap[WS_DEFAULT_BG]; 811 mach64_clearscreen(sc); 812 mach64_init_lut(sc); 813 814 if (sc->sc_console) 815 vcons_replay_msgbuf(&mach64_console_screen); 816 817 machfb_blank(sc, 0); /* unblank the screen */ 818 819 aa.console = sc->sc_console; 820 aa.scrdata = &mach64_screenlist; 821 aa.accessops = &sc->sc_accessops; 822 aa.accesscookie = &sc->vd; 823 824 config_found(self, &aa, wsemuldisplaydevprint); 825 if (use_mmio) { 826 /* 827 * Now that we took over, turn off the aperture registers if we 828 * don't use them. Can't do this earlier since on some hardware 829 * we use firmware calls as early console output which may in 830 * turn try to access these registers. 831 */ 832 reg = regr(sc, BUS_CNTL); 833 aprint_debug_dev(sc->sc_dev, "BUS_CNTL: %08x\n", reg); 834 reg |= BUS_APER_REG_DIS; 835 regw(sc, BUS_CNTL, reg); 836 } 837 config_found_ia(self, "drm", aux, machfb_drm_print); 838 } 839 840 static int 841 machfb_drm_print(void *aux, const char *pnp) 842 { 843 if (pnp) 844 aprint_normal("direct rendering for %s", pnp); 845 return (UNSUPP); 846 } 847 848 static void 849 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 850 long *defattr) 851 { 852 struct mach64_softc *sc = cookie; 853 struct rasops_info *ri = &scr->scr_ri; 854 855 /* XXX for now */ 856 #define setmode 0 857 858 ri->ri_depth = sc->bits_per_pixel; 859 ri->ri_width = sc->sc_my_mode->hdisplay; 860 ri->ri_height = sc->sc_my_mode->vdisplay; 861 ri->ri_stride = ri->ri_width; 862 ri->ri_flg = RI_CENTER; 863 if (ri->ri_depth == 8) 864 ri->ri_flg |= RI_8BIT_IS_RGB | RI_ENABLE_ALPHA; 865 866 #ifdef VCONS_DRAW_INTR 867 scr->scr_flags |= VCONS_DONT_READ; 868 #endif 869 870 if (existing) { 871 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 872 panic("%s: failed to switch video mode", 873 device_xname(sc->sc_dev)); 874 } 875 } 876 877 rasops_init(ri, 0, 0); 878 ri->ri_caps = WSSCREEN_WSCOLORS; 879 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 880 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 881 882 /* enable acceleration */ 883 ri->ri_hw = scr; 884 ri->ri_ops.copyrows = mach64_copyrows; 885 ri->ri_ops.copycols = mach64_copycols; 886 ri->ri_ops.eraserows = mach64_eraserows; 887 ri->ri_ops.erasecols = mach64_erasecols; 888 ri->ri_ops.cursor = mach64_cursor; 889 if (FONT_IS_ALPHA(ri->ri_font)) { 890 ri->ri_ops.putchar = mach64_putchar_aa8; 891 } else 892 ri->ri_ops.putchar = mach64_putchar_mono; 893 } 894 895 static void 896 mach64_init(struct mach64_softc *sc) 897 { 898 sc->sc_blanked = 0; 899 } 900 901 static int 902 mach64_get_memsize(struct mach64_softc *sc) 903 { 904 int tmp, memsize; 905 int mem_tab[] = { 906 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 907 }; 908 tmp = regr(sc, MEM_CNTL); 909 #ifdef DIAGNOSTIC 910 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 911 #endif 912 if (sc->has_dsp) { 913 tmp &= 0x0000000f; 914 if (tmp < 8) 915 memsize = (tmp + 1) * 512; 916 else if (tmp < 12) 917 memsize = (tmp - 3) * 1024; 918 else 919 memsize = (tmp - 7) * 2048; 920 } else { 921 memsize = mem_tab[tmp & 0x07]; 922 } 923 924 return memsize; 925 } 926 927 static int 928 mach64_get_max_ramdac(struct mach64_softc *sc) 929 { 930 int i; 931 932 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 933 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 934 (mach64_chip_rev & 0x07)) 935 return 170000; 936 937 for (i = 0; i < __arraycount(mach64_info); i++) 938 if (mach64_chip_id == mach64_info[i].chip_id) 939 return mach64_info[i].ramdac_freq; 940 941 if (sc->bits_per_pixel == 8) 942 return 135000; 943 else 944 return 80000; 945 } 946 947 #if defined(__sparc__) || defined(__powerpc__) 948 static void 949 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 950 { 951 struct mach64_crtcregs crtc; 952 953 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 954 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 955 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 956 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 957 958 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 959 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 960 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 961 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 962 mode->hsync_start; 963 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 964 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 965 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 966 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 967 968 #ifdef MACHFB_DEBUG 969 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 970 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 971 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 972 #endif 973 } 974 #endif 975 976 static int 977 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 978 struct videomode *mode) 979 { 980 981 if (mode->dot_clock > sc->ramdac_freq) 982 /* Clock too high. */ 983 return 1; 984 985 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 986 ((mode->htotal >> 3) - 1); 987 crtc->h_sync_strt_wid = 988 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 989 ((mode->hsync_start >> 3) - 1); 990 991 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 992 (mode->vtotal - 1); 993 crtc->v_sync_strt_wid = 994 ((mode->vsync_end - mode->vsync_start) << 16) | 995 (mode->vsync_start - 1); 996 997 if (mode->flags & VID_NVSYNC) 998 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 999 1000 switch (sc->bits_per_pixel) { 1001 case 8: 1002 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 1003 break; 1004 case 16: 1005 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 1006 break; 1007 case 32: 1008 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 1009 break; 1010 } 1011 1012 crtc->gen_cntl = 0; 1013 if (mode->flags & VID_INTERLACE) 1014 crtc->gen_cntl |= CRTC_INTERLACE_EN; 1015 1016 if (mode->flags & VID_CSYNC) 1017 crtc->gen_cntl |= CRTC_CSYNC_EN; 1018 1019 crtc->dot_clock = mode->dot_clock; 1020 1021 return 0; 1022 } 1023 1024 static void 1025 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 1026 { 1027 1028 mach64_set_pll(sc, crtc->dot_clock); 1029 1030 if (sc->has_dsp) 1031 mach64_set_dsp(sc); 1032 1033 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 1034 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1035 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 1036 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1037 1038 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 1039 1040 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1041 1042 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 1043 /* XXX this unconditionally enables composite sync on SPARC */ 1044 #ifdef __sparc__ 1045 CRTC_CSYNC_EN | 1046 #endif 1047 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 1048 } 1049 1050 static int 1051 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 1052 { 1053 struct mach64_crtcregs crtc; 1054 1055 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 1056 1057 if (mach64_calc_crtcregs(sc, &crtc, mode)) 1058 return 1; 1059 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 1060 if (crtc.dot_clock == 0) { 1061 aprint_error("%s: preposterous dot clock (%d)\n", 1062 device_xname(sc->sc_dev), crtc.dot_clock); 1063 return 1; 1064 } 1065 mach64_set_crtcregs(sc, &crtc); 1066 return 0; 1067 } 1068 1069 static void 1070 mach64_reset_engine(struct mach64_softc *sc) 1071 { 1072 1073 /* Reset engine.*/ 1074 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1075 1076 /* Enable engine. */ 1077 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1078 1079 /* Ensure engine is not locked up by clearing any FIFO or 1080 host errors. */ 1081 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1082 BUS_FIFO_ERR_ACK); 1083 } 1084 1085 static void 1086 mach64_init_engine(struct mach64_softc *sc) 1087 { 1088 uint32_t pitch_value; 1089 1090 pitch_value = sc->virt_x; 1091 1092 if (sc->bits_per_pixel == 24) 1093 pitch_value *= 3; 1094 1095 mach64_reset_engine(sc); 1096 1097 wait_for_fifo(sc, 14); 1098 1099 regw(sc, CONTEXT_MASK, 0xffffffff); 1100 1101 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 1102 1103 /* make sure the visible area starts where we're going to draw */ 1104 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1105 1106 regw(sc, DST_Y_X, 0); 1107 regw(sc, DST_HEIGHT, 0); 1108 regw(sc, DST_BRES_ERR, 0); 1109 regw(sc, DST_BRES_INC, 0); 1110 regw(sc, DST_BRES_DEC, 0); 1111 1112 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1113 DST_Y_TOP_TO_BOTTOM); 1114 1115 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 1116 1117 regw(sc, SRC_Y_X, 0); 1118 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1119 regw(sc, SRC_Y_X_START, 0); 1120 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1121 1122 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1123 1124 wait_for_fifo(sc, 13); 1125 regw(sc, HOST_CNTL, 0); 1126 1127 regw(sc, PAT_REG0, 0); 1128 regw(sc, PAT_REG1, 0); 1129 regw(sc, PAT_CNTL, 0); 1130 1131 regw(sc, SC_LEFT, 0); 1132 regw(sc, SC_TOP, 0); 1133 regw(sc, SC_BOTTOM, 0x3fff); 1134 regw(sc, SC_RIGHT, pitch_value - 1); 1135 1136 regw(sc, DP_BKGD_CLR, WS_DEFAULT_BG); 1137 regw(sc, DP_FRGD_CLR, WS_DEFAULT_FG); 1138 regw(sc, DP_WRITE_MASK, 0xffffffff); 1139 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1140 1141 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1142 1143 wait_for_fifo(sc, 3); 1144 regw(sc, CLR_CMP_CLR, 0); 1145 regw(sc, CLR_CMP_MASK, 0xffffffff); 1146 regw(sc, CLR_CMP_CNTL, 0); 1147 1148 wait_for_fifo(sc, 3); 1149 switch (sc->bits_per_pixel) { 1150 case 8: 1151 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP); 1152 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1153 /* We want 8 bit per channel */ 1154 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1155 break; 1156 case 32: 1157 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP); 1158 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1159 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1160 break; 1161 } 1162 regw(sc, DP_WRITE_MASK, 0xff); 1163 1164 wait_for_fifo(sc, 5); 1165 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1166 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1167 1168 wait_for_idle(sc); 1169 } 1170 1171 #if 0 1172 static void 1173 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1174 { 1175 int offset; 1176 1177 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1178 1179 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1180 offset); 1181 } 1182 #endif 1183 1184 static void 1185 mach64_set_dsp(struct mach64_softc *sc) 1186 { 1187 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1188 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1189 uint32_t xclks_per_qw, y; 1190 uint32_t fifo_off, fifo_on; 1191 1192 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1193 1194 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1195 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1196 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1197 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1198 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1199 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1200 dsp_loop_latency = 0; 1201 fifo_depth = 24; 1202 } else { 1203 dsp_loop_latency = 2; 1204 fifo_depth = 32; 1205 } 1206 1207 dsp_precision = 0; 1208 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1209 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1210 y = (xclks_per_qw * fifo_depth) >> 11; 1211 while (y) { 1212 y >>= 1; 1213 dsp_precision++; 1214 } 1215 dsp_precision -= 5; 1216 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1217 1218 switch (sc->memtype) { 1219 case DRAM: 1220 case EDO_DRAM: 1221 case PSEUDO_EDO: 1222 if (sc->memsize > 1024) { 1223 page_size = 9; 1224 dsp_loop_latency += 6; 1225 } else { 1226 page_size = 10; 1227 if (sc->memtype == DRAM) 1228 dsp_loop_latency += 8; 1229 else 1230 dsp_loop_latency += 7; 1231 } 1232 break; 1233 case SDRAM: 1234 case SGRAM: 1235 if (sc->memsize > 1024) { 1236 page_size = 8; 1237 dsp_loop_latency += 8; 1238 } else { 1239 page_size = 10; 1240 dsp_loop_latency += 9; 1241 } 1242 break; 1243 default: 1244 page_size = 10; 1245 dsp_loop_latency += 9; 1246 break; 1247 } 1248 1249 if (xclks_per_qw >= (page_size << 11)) 1250 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1251 else 1252 fifo_on = (3 * page_size + 2) << 6; 1253 1254 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1255 dsp_on = fifo_on >> dsp_precision; 1256 dsp_off = fifo_off >> dsp_precision; 1257 1258 #ifdef MACHFB_DEBUG 1259 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1260 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1261 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1262 "mclk_post_div = %d, vclk_post_div = %d\n", 1263 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1264 sc->mclk_fb_div, sc->vclk_fb_div, 1265 sc->mclk_post_div, sc->vclk_post_div); 1266 #endif 1267 1268 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1269 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1270 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1271 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1272 } 1273 1274 static void 1275 mach64_set_pll(struct mach64_softc *sc, int clock) 1276 { 1277 uint32_t q, clockreg; 1278 int clockshift = sc->sc_clock << 1; 1279 uint8_t reg, vclk_ctl; 1280 1281 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1282 #ifdef MACHFB_DEBUG 1283 printf("q = %d\n", q); 1284 #endif 1285 if (q > 25500) { 1286 aprint_error_dev(sc->sc_dev, "Warning: q > 25500\n"); 1287 q = 25500; 1288 sc->vclk_post_div = 1; 1289 sc->log2_vclk_post_div = 0; 1290 } else if (q > 12750) { 1291 sc->vclk_post_div = 1; 1292 sc->log2_vclk_post_div = 0; 1293 } else if (q > 6350) { 1294 sc->vclk_post_div = 2; 1295 sc->log2_vclk_post_div = 1; 1296 } else if (q > 3150) { 1297 sc->vclk_post_div = 4; 1298 sc->log2_vclk_post_div = 2; 1299 } else if (q >= 1600) { 1300 sc->vclk_post_div = 8; 1301 sc->log2_vclk_post_div = 3; 1302 } else { 1303 aprint_error_dev(sc->sc_dev, "Warning: q < 1600\n"); 1304 sc->vclk_post_div = 8; 1305 sc->log2_vclk_post_div = 3; 1306 } 1307 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1308 aprint_debug("post_div: %d log2_post_div: %d mclk_div: %d\n", 1309 sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1310 1311 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1312 aprint_debug("vclk_ctl: %02x\n", vclk_ctl); 1313 vclk_ctl |= PLL_VCLK_RESET; 1314 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1315 1316 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1317 reg = regrb_pll(sc, VCLK_POST_DIV); 1318 reg &= ~(3 << clockshift); 1319 reg |= (sc->log2_vclk_post_div << clockshift); 1320 regwb_pll(sc, VCLK_POST_DIV, reg); 1321 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1322 1323 vclk_ctl &= ~PLL_VCLK_RESET; 1324 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1325 1326 clockreg = regr(sc, CLOCK_CNTL); 1327 clockreg &= ~CLOCK_SEL; 1328 clockreg |= sc->sc_clock | CLOCK_STROBE; 1329 regw(sc, CLOCK_CNTL, clockreg); 1330 } 1331 1332 static void 1333 mach64_init_lut(struct mach64_softc *sc) 1334 { 1335 uint8_t cmap[768]; 1336 int i, idx; 1337 1338 rasops_get_cmap(&mach64_console_screen.scr_ri, cmap, sizeof(cmap)); 1339 idx = 0; 1340 for (i = 0; i < 256; i++) { 1341 mach64_putpalreg(sc, i, cmap[idx], cmap[idx + 1], 1342 cmap[idx + 2]); 1343 idx += 3; 1344 } 1345 } 1346 1347 static int 1348 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1349 uint8_t b) 1350 { 1351 sc->sc_cmap_red[index] = r; 1352 sc->sc_cmap_green[index] = g; 1353 sc->sc_cmap_blue[index] = b; 1354 /* 1355 * writing the dac index takes a while, in theory we can poll some 1356 * register to see when it's ready - but we better avoid writing it 1357 * unnecessarily 1358 */ 1359 if (index != sc->sc_dacw) { 1360 regwb(sc, DAC_MASK, 0xff); 1361 regwb(sc, DAC_WINDEX, index); 1362 } 1363 sc->sc_dacw = index + 1; 1364 regwb(sc, DAC_DATA, r); 1365 regwb(sc, DAC_DATA, g); 1366 regwb(sc, DAC_DATA, b); 1367 return 0; 1368 } 1369 1370 static int 1371 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1372 { 1373 uint index = cm->index; 1374 uint count = cm->count; 1375 int i, error; 1376 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1377 uint8_t *r, *g, *b; 1378 1379 if (cm->index >= 256 || cm->count > 256 || 1380 (cm->index + cm->count) > 256) 1381 return EINVAL; 1382 error = copyin(cm->red, &rbuf[index], count); 1383 if (error) 1384 return error; 1385 error = copyin(cm->green, &gbuf[index], count); 1386 if (error) 1387 return error; 1388 error = copyin(cm->blue, &bbuf[index], count); 1389 if (error) 1390 return error; 1391 1392 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1393 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1394 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1395 1396 r = &sc->sc_cmap_red[index]; 1397 g = &sc->sc_cmap_green[index]; 1398 b = &sc->sc_cmap_blue[index]; 1399 1400 for (i = 0; i < count; i++) { 1401 mach64_putpalreg(sc, index, *r, *g, *b); 1402 index++; 1403 r++, g++, b++; 1404 } 1405 return 0; 1406 } 1407 1408 static int 1409 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1410 { 1411 u_int index = cm->index; 1412 u_int count = cm->count; 1413 int error; 1414 1415 if (index >= 255 || count > 256 || index + count > 256) 1416 return EINVAL; 1417 1418 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1419 if (error) 1420 return error; 1421 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1422 if (error) 1423 return error; 1424 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1425 if (error) 1426 return error; 1427 1428 return 0; 1429 } 1430 1431 static int 1432 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1433 { 1434 struct mach64_crtcregs regs; 1435 1436 if (mach64_calc_crtcregs(sc, ®s, 1437 (struct videomode *)des->modecookie)) 1438 return 1; 1439 1440 mach64_set_crtcregs(sc, ®s); 1441 return 0; 1442 } 1443 1444 static int 1445 mach64_is_console(struct mach64_softc *sc) 1446 { 1447 bool console = 0; 1448 1449 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1450 "is_console", &console); 1451 return console; 1452 } 1453 1454 /* 1455 * wsdisplay_emulops 1456 */ 1457 1458 static void 1459 mach64_cursor(void *cookie, int on, int row, int col) 1460 { 1461 struct rasops_info *ri = cookie; 1462 struct vcons_screen *scr = ri->ri_hw; 1463 struct mach64_softc *sc = scr->scr_cookie; 1464 int x, y, wi, he; 1465 1466 wi = ri->ri_font->fontwidth; 1467 he = ri->ri_font->fontheight; 1468 1469 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1470 x = ri->ri_ccol * wi + ri->ri_xorigin; 1471 y = ri->ri_crow * he + ri->ri_yorigin; 1472 if (ri->ri_flg & RI_CURSOR) { 1473 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1474 ri->ri_flg &= ~RI_CURSOR; 1475 } 1476 ri->ri_crow = row; 1477 ri->ri_ccol = col; 1478 if (on) { 1479 x = ri->ri_ccol * wi + ri->ri_xorigin; 1480 y = ri->ri_crow * he + ri->ri_yorigin; 1481 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1482 ri->ri_flg |= RI_CURSOR; 1483 } 1484 } else { 1485 scr->scr_ri.ri_crow = row; 1486 scr->scr_ri.ri_ccol = col; 1487 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1488 } 1489 } 1490 1491 #if 0 1492 static int 1493 mach64_mapchar(void *cookie, int uni, u_int *index) 1494 { 1495 return 0; 1496 } 1497 #endif 1498 1499 static void 1500 mach64_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1501 { 1502 struct rasops_info *ri = cookie; 1503 struct wsdisplay_font *font = PICK_FONT(ri, c); 1504 struct vcons_screen *scr = ri->ri_hw; 1505 struct mach64_softc *sc = scr->scr_cookie; 1506 1507 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1508 int fg, bg, uc; 1509 uint8_t *data; 1510 int x, y, wi, he; 1511 wi = font->fontwidth; 1512 he = font->fontheight; 1513 1514 if (!CHAR_IN_FONT(c, font)) 1515 return; 1516 bg = ri->ri_devcmap[(attr >> 16) & 0x0f]; 1517 fg = ri->ri_devcmap[(attr >> 24) & 0x0f]; 1518 x = ri->ri_xorigin + col * wi; 1519 y = ri->ri_yorigin + row * he; 1520 if (c == 0x20) { 1521 mach64_rectfill(sc, x, y, wi, he, bg); 1522 } else { 1523 uc = c - font->firstchar; 1524 data = (uint8_t *)font->data + uc * 1525 ri->ri_fontscale; 1526 1527 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1528 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1529 } 1530 } 1531 } 1532 1533 static void 1534 mach64_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 1535 { 1536 struct rasops_info *ri = cookie; 1537 struct wsdisplay_font *font = PICK_FONT(ri, c); 1538 struct vcons_screen *scr = ri->ri_hw; 1539 struct mach64_softc *sc = scr->scr_cookie; 1540 uint32_t bg, latch = 0, bg8, fg8, pixel; 1541 int i, x, y, wi, he, r, g, b, aval; 1542 int r1, g1, b1, r0, g0, b0, fgo, bgo; 1543 uint8_t *data8; 1544 int rv = 0, cnt = 0; 1545 1546 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1547 return; 1548 1549 if (!CHAR_IN_FONT(c, font)) 1550 return; 1551 1552 wi = font->fontwidth; 1553 he = font->fontheight; 1554 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1555 x = ri->ri_xorigin + col * wi; 1556 y = ri->ri_yorigin + row * he; 1557 1558 if (c == 0x20) { 1559 mach64_rectfill(sc, x, y, wi, he, bg); 1560 return; 1561 } 1562 1563 rv = glyphcache_try(&sc->sc_gc, c, x, y, attr); 1564 if (rv == GC_OK) 1565 return; 1566 1567 data8 = WSFONT_GLYPH(c, font); 1568 1569 wait_for_fifo(sc, 11); 1570 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1571 regw(sc, DP_SRC, MONO_SRC_ONE | BKGD_SRC_HOST | FRGD_SRC_HOST); 1572 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1573 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1574 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1575 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1576 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1577 regw(sc, SRC_Y_X, 0); 1578 regw(sc, SRC_WIDTH1, wi); 1579 regw(sc, DST_Y_X, (x << 16) | y); 1580 regw(sc, DST_HEIGHT_WIDTH, (wi << 16) | he); 1581 1582 /* 1583 * we need the RGB colours here, so get offsets into rasops_cmap 1584 */ 1585 fgo = ((attr >> 24) & 0xf) * 3; 1586 bgo = ((attr >> 16) & 0xf) * 3; 1587 1588 r0 = rasops_cmap[bgo]; 1589 r1 = rasops_cmap[fgo]; 1590 g0 = rasops_cmap[bgo + 1]; 1591 g1 = rasops_cmap[fgo + 1]; 1592 b0 = rasops_cmap[bgo + 2]; 1593 b1 = rasops_cmap[fgo + 2]; 1594 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 1595 bg8 = R3G3B2(r0, g0, b0); 1596 fg8 = R3G3B2(r1, g1, b1); 1597 1598 wait_for_fifo(sc, 10); 1599 1600 for (i = 0; i < ri->ri_fontscale; i++) { 1601 aval = *data8; 1602 if (aval == 0) { 1603 pixel = bg8; 1604 } else if (aval == 255) { 1605 pixel = fg8; 1606 } else { 1607 r = aval * r1 + (255 - aval) * r0; 1608 g = aval * g1 + (255 - aval) * g0; 1609 b = aval * b1 + (255 - aval) * b0; 1610 pixel = ((r & 0xe000) >> 8) | 1611 ((g & 0xe000) >> 11) | 1612 ((b & 0xc000) >> 14); 1613 } 1614 latch = (latch << 8) | pixel; 1615 /* write in 32bit chunks */ 1616 if ((i & 3) == 3) { 1617 regws(sc, HOST_DATA0, latch); 1618 /* 1619 * not strictly necessary, old data should be shifted 1620 * out 1621 */ 1622 latch = 0; 1623 cnt++; 1624 if (cnt > 8) { 1625 wait_for_fifo(sc, 10); 1626 cnt = 0; 1627 } 1628 } 1629 data8++; 1630 } 1631 /* if we have pixels left in latch write them out */ 1632 if ((i & 3) != 0) { 1633 latch = latch << ((4 - (i & 3)) << 3); 1634 regws(sc, HOST_DATA0, latch); 1635 } 1636 1637 if (rv == GC_ADD) { 1638 glyphcache_add(&sc->sc_gc, c, x, y); 1639 } 1640 } 1641 1642 static void 1643 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1644 { 1645 struct rasops_info *ri = cookie; 1646 struct vcons_screen *scr = ri->ri_hw; 1647 struct mach64_softc *sc = scr->scr_cookie; 1648 int32_t xs, xd, y, width, height; 1649 1650 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1651 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1652 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1653 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1654 width = ri->ri_font->fontwidth * ncols; 1655 height = ri->ri_font->fontheight; 1656 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC); 1657 } 1658 } 1659 1660 static void 1661 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1662 { 1663 struct rasops_info *ri = cookie; 1664 struct vcons_screen *scr = ri->ri_hw; 1665 struct mach64_softc *sc = scr->scr_cookie; 1666 int32_t x, y, width, height, fg, bg, ul; 1667 1668 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1669 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1670 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1671 width = ri->ri_font->fontwidth * ncols; 1672 height = ri->ri_font->fontheight; 1673 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1674 1675 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1676 } 1677 } 1678 1679 static void 1680 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1681 { 1682 struct rasops_info *ri = cookie; 1683 struct vcons_screen *scr = ri->ri_hw; 1684 struct mach64_softc *sc = scr->scr_cookie; 1685 int32_t x, ys, yd, width, height; 1686 1687 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1688 x = ri->ri_xorigin; 1689 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1690 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1691 width = ri->ri_emuwidth; 1692 height = ri->ri_font->fontheight*nrows; 1693 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC); 1694 } 1695 } 1696 1697 static void 1698 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1699 { 1700 struct rasops_info *ri = cookie; 1701 struct vcons_screen *scr = ri->ri_hw; 1702 struct mach64_softc *sc = scr->scr_cookie; 1703 int32_t x, y, width, height, fg, bg, ul; 1704 1705 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1706 x = ri->ri_xorigin; 1707 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1708 width = ri->ri_emuwidth; 1709 height = ri->ri_font->fontheight * nrows; 1710 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1711 1712 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1713 } 1714 } 1715 1716 static void 1717 mach64_bitblt(void *cookie, int xs, int ys, int xd, int yd, int width, int height, int rop) 1718 { 1719 struct mach64_softc *sc = cookie; 1720 uint32_t dest_ctl = 0; 1721 1722 wait_for_fifo(sc, 10); 1723 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1724 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1725 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1726 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1727 if (yd < ys) { 1728 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1729 } else { 1730 ys += height - 1; 1731 yd += height - 1; 1732 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1733 } 1734 if (xd < xs) { 1735 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1736 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1737 } else { 1738 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1739 xs += width - 1; 1740 xd += width - 1; 1741 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1742 } 1743 regw(sc, DST_CNTL, dest_ctl); 1744 1745 regw(sc, SRC_Y_X, (xs << 16) | ys); 1746 regw(sc, SRC_WIDTH1, width); 1747 regw(sc, DST_Y_X, (xd << 16) | yd); 1748 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1749 } 1750 1751 static void 1752 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1753 int height, uint32_t fg, uint32_t bg) 1754 { 1755 wait_for_idle(sc); 1756 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1757 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1758 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1759 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1760 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1761 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1762 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1763 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1764 regw(sc, DP_BKGD_CLR, bg); 1765 regw(sc, DP_FRGD_CLR, fg); 1766 regw(sc, SRC_Y_X, 0); 1767 regw(sc, SRC_WIDTH1, width); 1768 regw(sc, DST_Y_X, (xd << 16) | yd); 1769 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1770 /* now feed the data into the chip */ 1771 } 1772 1773 static void 1774 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1775 { 1776 int i; 1777 uint32_t latch = 0, bork; 1778 int shift = 0; 1779 int reg = 0; 1780 1781 for (i = 0; i < count; i++) { 1782 bork = data[i]; 1783 latch |= (bork << shift); 1784 if (shift == 24) { 1785 regw(sc, HOST_DATA0 + reg, latch); 1786 latch = 0; 1787 shift = 0; 1788 reg = (reg + 4) & 0x3c; 1789 } else 1790 shift += 8; 1791 } 1792 if (shift != 0) /* 24 */ 1793 regw(sc, HOST_DATA0 + reg, latch); 1794 } 1795 1796 1797 static void 1798 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1799 int colour) 1800 { 1801 wait_for_fifo(sc, 11); 1802 regw(sc, DP_FRGD_CLR, colour); 1803 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1804 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1805 regw(sc, DP_MIX, MIX_SRC << 16); 1806 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1807 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1808 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1809 1810 regw(sc, SRC_Y_X, (x << 16) | y); 1811 regw(sc, SRC_WIDTH1, width); 1812 regw(sc, DST_Y_X, (x << 16) | y); 1813 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1814 } 1815 1816 static void 1817 mach64_clearscreen(struct mach64_softc *sc) 1818 { 1819 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1820 } 1821 1822 1823 #if 0 1824 static void 1825 mach64_showpal(struct mach64_softc *sc) 1826 { 1827 int i, x = 0; 1828 1829 for (i = 0; i < 16; i++) { 1830 mach64_rectfill(sc, x, 0, 64, 64, i); 1831 x += 64; 1832 } 1833 } 1834 #endif 1835 1836 /* 1837 * wsdisplay_accessops 1838 */ 1839 1840 static int 1841 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1842 struct lwp *l) 1843 { 1844 struct vcons_data *vd = v; 1845 struct mach64_softc *sc = vd->cookie; 1846 struct wsdisplay_fbinfo *wdf; 1847 struct vcons_screen *ms = vd->active; 1848 1849 switch (cmd) { 1850 case WSDISPLAYIO_GTYPE: 1851 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1852 return 0; 1853 1854 case WSDISPLAYIO_LINEBYTES: 1855 *(u_int *)data = sc->virt_x * sc->bits_per_pixel / 8; 1856 return 0; 1857 1858 case WSDISPLAYIO_GINFO: 1859 wdf = (void *)data; 1860 wdf->height = sc->virt_y; 1861 wdf->width = sc->virt_x; 1862 wdf->depth = sc->bits_per_pixel; 1863 wdf->cmsize = 256; 1864 return 0; 1865 1866 case WSDISPLAYIO_GETCMAP: 1867 return mach64_getcmap(sc, 1868 (struct wsdisplay_cmap *)data); 1869 1870 case WSDISPLAYIO_PUTCMAP: 1871 return mach64_putcmap(sc, 1872 (struct wsdisplay_cmap *)data); 1873 1874 /* PCI config read/write passthrough. */ 1875 case PCI_IOC_CFGREAD: 1876 case PCI_IOC_CFGWRITE: 1877 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1878 cmd, data, flag, l); 1879 1880 case WSDISPLAYIO_GET_BUSID: 1881 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1882 sc->sc_pcitag, data); 1883 1884 case WSDISPLAYIO_SMODE: { 1885 int new_mode = *(int*)data; 1886 if (new_mode != sc->sc_mode) { 1887 sc->sc_mode = new_mode; 1888 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1889 && (ms != NULL)) 1890 { 1891 /* restore initial video mode */ 1892 mach64_init(sc); 1893 mach64_init_engine(sc); 1894 mach64_init_lut(sc); 1895 mach64_modeswitch(sc, sc->sc_my_mode); 1896 mach64_clearscreen(sc); 1897 glyphcache_wipe(&sc->sc_gc); 1898 vcons_redraw_screen(ms); 1899 } 1900 } 1901 } 1902 return 0; 1903 case WSDISPLAYIO_GET_EDID: { 1904 struct wsdisplayio_edid_info *d = data; 1905 return wsdisplayio_get_edid(sc->sc_dev, d); 1906 } 1907 } 1908 return EPASSTHROUGH; 1909 } 1910 1911 static paddr_t 1912 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1913 { 1914 struct vcons_data *vd = v; 1915 struct mach64_softc *sc = vd->cookie; 1916 paddr_t pa; 1917 #if 0 1918 pcireg_t reg; 1919 #endif 1920 #ifndef __sparc64__ 1921 /* 1922 *'regular' framebuffer mmap()ing 1923 * disabled on sparc64 because some ATI firmware likes to map some PCI 1924 * resources to addresses that would collide with this ( like some Rage 1925 * IIc which uses 0x2000 for the 2nd register block ) 1926 * Other 64bit architectures might run into similar problems. 1927 */ 1928 if (offset < (sc->memsize * 1024)) { 1929 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, offset, 1930 prot, BUS_SPACE_MAP_LINEAR); 1931 return pa; 1932 } 1933 #endif 1934 /* 1935 * restrict all other mappings to processes with superuser privileges 1936 * or the kernel itself 1937 */ 1938 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1939 NULL, NULL, NULL, NULL) != 0) { 1940 return -1; 1941 } 1942 #if 0 1943 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1944 if (reg != sc->sc_regbase) { 1945 #ifdef DIAGNOSTIC 1946 printf("%s: BAR 0x18 changed! (%x %x)\n", 1947 device_xname(sc->sc_dev), (uint32_t)sc->sc_regbase, 1948 (uint32_t)reg); 1949 #endif 1950 sc->sc_regbase = reg; 1951 } 1952 1953 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1954 if (reg != sc->sc_aperbase) { 1955 #ifdef DIAGNOSTIC 1956 printf("%s: BAR 0x10 changed! (%x %x)\n", 1957 device_xname(sc->sc_dev), (uint32_t)sc->sc_aperbase, 1958 (uint32_t)reg); 1959 #endif 1960 sc->sc_aperbase = reg; 1961 } 1962 #endif 1963 if ((offset >= sc->sc_aperbase) && 1964 (offset < (sc->sc_aperbase + sc->sc_apersize))) { 1965 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1966 BUS_SPACE_MAP_LINEAR); 1967 return pa; 1968 } 1969 1970 if ((offset >= sc->sc_regbase) && 1971 (offset < (sc->sc_regbase + sc->sc_regsize))) { 1972 pa = bus_space_mmap(sc->sc_regt, offset, 0, prot, 1973 BUS_SPACE_MAP_LINEAR); 1974 return pa; 1975 } 1976 1977 if ((offset >= sc->sc_rom.vb_base) && 1978 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 1979 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1980 BUS_SPACE_MAP_LINEAR); 1981 return pa; 1982 } 1983 1984 #ifdef PCI_MAGIC_IO_RANGE 1985 if ((offset >= PCI_MAGIC_IO_RANGE) && 1986 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 1987 return bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1988 0, prot, 0); 1989 } 1990 #endif 1991 return -1; 1992 } 1993 1994 #if 0 1995 static int 1996 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1997 { 1998 1999 return 0; 2000 } 2001 #endif 2002 2003 void 2004 machfb_blank(struct mach64_softc *sc, int blank) 2005 { 2006 uint32_t reg; 2007 2008 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 2009 2010 switch (blank) 2011 { 2012 case 0: 2013 reg = regr(sc, CRTC_GEN_CNTL); 2014 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 2015 sc->sc_blanked = 0; 2016 break; 2017 case 1: 2018 reg = regr(sc, CRTC_GEN_CNTL); 2019 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 2020 sc->sc_blanked = 1; 2021 break; 2022 default: 2023 break; 2024 } 2025 } 2026 2027 /* framebuffer device support */ 2028 #ifdef __sparc__ 2029 2030 static void 2031 machfb_unblank(device_t dev) 2032 { 2033 struct mach64_softc *sc = device_private(dev); 2034 2035 machfb_blank(sc, 0); 2036 } 2037 2038 static void 2039 machfb_fbattach(struct mach64_softc *sc) 2040 { 2041 struct fbdevice *fb = &sc->sc_fb; 2042 2043 fb->fb_device = sc->sc_dev; 2044 fb->fb_driver = &machfb_fbdriver; 2045 2046 fb->fb_type.fb_cmsize = 256; 2047 fb->fb_type.fb_size = sc->memsize; 2048 2049 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 2050 fb->fb_flags = sc->sc_dev->dv_cfdata->cf_flags & FB_USERMASK; 2051 fb->fb_type.fb_depth = sc->bits_per_pixel; 2052 fb->fb_type.fb_width = sc->virt_x; 2053 fb->fb_type.fb_height = sc->virt_y; 2054 2055 fb_attach(fb, sc->sc_console); 2056 } 2057 2058 int 2059 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 2060 { 2061 struct mach64_softc *sc; 2062 2063 sc = device_lookup_private(&machfb_cd, minor(dev)); 2064 if (sc == NULL) 2065 return ENXIO; 2066 sc->sc_locked = 1; 2067 2068 #ifdef MACHFB_DEBUG 2069 printf("machfb_fbopen(%d)\n", minor(dev)); 2070 #endif 2071 return 0; 2072 } 2073 2074 int 2075 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 2076 { 2077 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 2078 2079 #ifdef MACHFB_DEBUG 2080 printf("machfb_fbclose()\n"); 2081 #endif 2082 mach64_init_engine(sc); 2083 mach64_init_lut(sc); 2084 sc->sc_locked = 0; 2085 return 0; 2086 } 2087 2088 int 2089 machfb_fbioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 2090 { 2091 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 2092 2093 #ifdef MACHFB_DEBUG 2094 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 2095 #endif 2096 switch (cmd) { 2097 case FBIOGTYPE: 2098 *(struct fbtype *)data = sc->sc_fb.fb_type; 2099 break; 2100 2101 case FBIOGATTR: 2102 #define fba ((struct fbgattr *)data) 2103 fba->real_type = sc->sc_fb.fb_type.fb_type; 2104 fba->owner = 0; /* XXX ??? */ 2105 fba->fbtype = sc->sc_fb.fb_type; 2106 fba->sattr.flags = 0; 2107 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 2108 fba->sattr.dev_specific[0] = sc->sc_nbus; 2109 fba->sattr.dev_specific[1] = sc->sc_ndev; 2110 fba->sattr.dev_specific[2] = sc->sc_nfunc; 2111 fba->sattr.dev_specific[3] = -1; 2112 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 2113 fba->emu_types[1] = -1; 2114 #undef fba 2115 break; 2116 2117 #if 0 2118 case FBIOGETCMAP: 2119 #define p ((struct fbcmap *)data) 2120 return bt_getcmap(p, &sc->sc_cmap, 256, 1); 2121 2122 case FBIOPUTCMAP: 2123 /* copy to software map */ 2124 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 2125 if (error) 2126 return error; 2127 /* now blast them into the chip */ 2128 /* XXX should use retrace interrupt */ 2129 cg6_loadcmap(sc, p->index, p->count); 2130 #undef p 2131 break; 2132 #endif 2133 case FBIOGVIDEO: 2134 *(int *)data = sc->sc_blanked; 2135 break; 2136 2137 case FBIOSVIDEO: 2138 machfb_blank(sc, *(int *)data); 2139 break; 2140 2141 #if 0 2142 case FBIOGCURSOR: 2143 break; 2144 2145 case FBIOSCURSOR: 2146 break; 2147 2148 case FBIOGCURPOS: 2149 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 2150 break; 2151 2152 case FBIOSCURPOS: 2153 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 2154 break; 2155 2156 case FBIOGCURMAX: 2157 /* max cursor size is 32x32 */ 2158 ((struct fbcurpos *)data)->x = 32; 2159 ((struct fbcurpos *)data)->y = 32; 2160 break; 2161 #endif 2162 case PCI_IOC_CFGREAD: 2163 case PCI_IOC_CFGWRITE: { 2164 int ret; 2165 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 2166 cmd, data, flags, l); 2167 2168 #ifdef MACHFB_DEBUG 2169 printf("pci_devioctl: %d\n", ret); 2170 #endif 2171 return ret; 2172 } 2173 2174 case WSDISPLAYIO_GET_BUSID: 2175 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 2176 sc->sc_pcitag, data); 2177 2178 default: 2179 return ENOTTY; 2180 } 2181 #ifdef MACHFB_DEBUG 2182 printf("machfb_fbioctl done\n"); 2183 #endif 2184 return 0; 2185 } 2186 2187 paddr_t 2188 machfb_fbmmap(dev_t dev, off_t off, int prot) 2189 { 2190 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 2191 2192 if (sc != NULL) 2193 return mach64_mmap(&sc->vd, NULL, off, prot); 2194 2195 return 0; 2196 } 2197 2198 #endif /* __sparc__ */ 2199
Indexes created Thu Oct 02 14:10:14 GMT 2025