machfb.c revision 1.96
1 /* $NetBSD: machfb.c,v 1.96 2019/02/03 12:39:38 tnn Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.96 2019/02/03 12:39:38 tnn Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #include <dev/wscons/wsdisplayvar.h> 58 59 #include <dev/wscons/wsconsio.h> 60 #include <dev/wsfont/wsfont.h> 61 #include <dev/rasops/rasops.h> 62 #include <dev/pci/wsdisplay_pci.h> 63 64 #include <dev/wscons/wsdisplay_vconsvar.h> 65 #include <dev/wscons/wsdisplay_glyphcachevar.h> 66 67 #include "opt_wsemul.h" 68 #include "opt_machfb.h" 69 #include "opt_glyphcache.h" 70 71 #define MACH64_REG_SIZE 0x800 72 #define MACH64_REG_OFF 0x7ff800 73 74 #define NBARS 3 /* number of Mach64 PCI BARs */ 75 76 struct vga_bar { 77 bus_addr_t vb_base; 78 bus_size_t vb_size; 79 pcireg_t vb_type; 80 int vb_flags; 81 }; 82 83 struct mach64_softc { 84 device_t sc_dev; 85 pci_chipset_tag_t sc_pc; 86 pcitag_t sc_pcitag; 87 88 struct vga_bar sc_bars[NBARS]; 89 struct vga_bar sc_rom; 90 91 #define sc_aperbase sc_bars[0].vb_base 92 #define sc_apersize sc_bars[0].vb_size 93 94 #define sc_iobase sc_bars[1].vb_base 95 #define sc_iosize sc_bars[1].vb_size 96 97 #define sc_regbase sc_bars[2].vb_base 98 #define sc_regsize sc_bars[2].vb_size 99 100 bus_space_tag_t sc_regt; 101 bus_space_tag_t sc_memt; 102 bus_space_tag_t sc_iot; 103 bus_space_handle_t sc_regh; 104 bus_space_handle_t sc_memh; 105 #if 0 106 void *sc_aperture; /* mapped aperture vaddr */ 107 void *sc_registers; /* mapped registers vaddr */ 108 #endif 109 uint32_t sc_nbus, sc_ndev, sc_nfunc; 110 size_t memsize; 111 int memtype; 112 113 int sc_mode; 114 int sc_bg; 115 int sc_locked; 116 117 int has_dsp; 118 int bits_per_pixel; 119 int max_x; 120 int max_y; 121 int virt_x; 122 int virt_y; 123 int color_depth; 124 125 int mem_freq; 126 int ramdac_freq; 127 int ref_freq; 128 int vclk_freq; 129 130 int ref_div; 131 int log2_vclk_post_div; 132 int vclk_post_div; 133 int vclk_fb_div; 134 int mclk_post_div; 135 int mclk_fb_div; 136 int sc_clock; /* which clock to use */ 137 int minref, m; 138 139 struct videomode *sc_my_mode; 140 int sc_edid_size; 141 uint8_t sc_edid_data[1024]; 142 struct edid_info sc_ei; 143 144 u_char sc_cmap_red[256]; 145 u_char sc_cmap_green[256]; 146 u_char sc_cmap_blue[256]; 147 int sc_dacw, sc_blanked, sc_console; 148 struct vcons_data vd; 149 struct wsdisplay_accessops sc_accessops; 150 glyphcache sc_gc; 151 }; 152 153 struct mach64_crtcregs { 154 uint32_t h_total_disp; 155 uint32_t h_sync_strt_wid; 156 uint32_t v_total_disp; 157 uint32_t v_sync_strt_wid; 158 uint32_t gen_cntl; 159 uint32_t clock_cntl; 160 uint32_t color_depth; 161 uint32_t dot_clock; 162 }; 163 164 static struct { 165 uint16_t chip_id; 166 uint32_t ramdac_freq; 167 } const mach64_info[] = { 168 { PCI_PRODUCT_ATI_MACH64_GX, 135000 }, 169 { PCI_PRODUCT_ATI_MACH64_CX, 135000 }, 170 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 171 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 172 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 173 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 174 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 175 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 176 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 180 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 181 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 184 #if 0 185 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 186 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 188 #endif 189 { PCI_PRODUCT_ATI_RAGE_L_MOB_M1_PCI, 230000 }, 190 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 192 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 193 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 194 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 195 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 196 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 197 }; 198 199 static int mach64_chip_id, mach64_chip_rev; 200 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 201 202 static const char *mach64_gx_memtype_names[] = { 203 "DRAM", "VRAM", "VRAM", "DRAM", 204 "DRAM", "VRAM", "VRAM", "(unknown type)" 205 }; 206 207 static const char *mach64_memtype_names[] = { 208 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 209 "(unknown type)" 210 }; 211 212 extern const u_char rasops_cmap[768]; 213 214 static int mach64_match(device_t, cfdata_t, void *); 215 static void mach64_attach(device_t, device_t, void *); 216 217 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, 218 mach64_attach, NULL, NULL); 219 220 static void mach64_init(struct mach64_softc *); 221 static int mach64_get_memsize(struct mach64_softc *); 222 static int mach64_get_max_ramdac(struct mach64_softc *); 223 224 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 225 226 static int mach64_calc_crtcregs(struct mach64_softc *, 227 struct mach64_crtcregs *, 228 struct videomode *); 229 static void mach64_set_crtcregs(struct mach64_softc *, 230 struct mach64_crtcregs *); 231 232 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 233 static void mach64_set_dsp(struct mach64_softc *); 234 static void mach64_set_pll(struct mach64_softc *, int); 235 static void mach64_reset_engine(struct mach64_softc *); 236 static void mach64_init_engine(struct mach64_softc *); 237 #if 0 238 static void mach64_adjust_frame(struct mach64_softc *, int, int); 239 #endif 240 static void mach64_init_lut(struct mach64_softc *); 241 242 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 243 static int mach64_is_console(struct mach64_softc *); 244 245 static void mach64_cursor(void *, int, int, int); 246 #if 0 247 static int mach64_mapchar(void *, int, u_int *); 248 #endif 249 static void mach64_putchar_mono(void *, int, int, u_int, long); 250 static void mach64_putchar_aa8(void *, int, int, u_int, long); 251 static void mach64_copycols(void *, int, int, int, int); 252 static void mach64_erasecols(void *, int, int, int, long); 253 static void mach64_copyrows(void *, int, int, int); 254 static void mach64_eraserows(void *, int, int, long); 255 static void mach64_clearscreen(struct mach64_softc *); 256 257 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 258 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 259 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 260 uint8_t, uint8_t); 261 static void mach64_bitblt(void *, int, int, int, int, int, int, int); 262 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 263 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 264 uint32_t, uint32_t); 265 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 266 #if 0 267 static void mach64_showpal(struct mach64_softc *); 268 #endif 269 270 static void machfb_blank(struct mach64_softc *, int); 271 static int machfb_drm_print(void *, const char *); 272 273 static struct wsscreen_descr mach64_defaultscreen = { 274 "default", 275 80, 30, 276 NULL, 277 8, 16, 278 WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE 279 | WSSCREEN_RESIZE , 280 NULL 281 }; 282 283 static const struct wsscreen_descr *_mach64_scrlist[] = { 284 &mach64_defaultscreen, 285 }; 286 287 static struct wsscreen_list mach64_screenlist = { 288 __arraycount(_mach64_scrlist), 289 _mach64_scrlist 290 }; 291 292 static int mach64_ioctl(void *, void *, u_long, void *, int, 293 struct lwp *); 294 static paddr_t mach64_mmap(void *, void *, off_t, int); 295 296 static struct vcons_screen mach64_console_screen; 297 298 /* 299 * Inline functions for getting access to register aperture. 300 */ 301 302 static inline uint32_t 303 regr(struct mach64_softc *sc, uint32_t index) 304 { 305 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index + 0x400); 306 } 307 308 static inline uint8_t 309 regrb(struct mach64_softc *sc, uint32_t index) 310 { 311 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index + 0x400); 312 } 313 314 static inline void 315 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 316 { 317 bus_space_write_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 318 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 319 BUS_SPACE_BARRIER_WRITE); 320 } 321 322 static inline void 323 regws(struct mach64_softc *sc, uint32_t index, uint32_t data) 324 { 325 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 326 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 4, 327 BUS_SPACE_BARRIER_WRITE); 328 } 329 330 static inline void 331 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 332 { 333 bus_space_write_1(sc->sc_regt, sc->sc_regh, index + 0x400, data); 334 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 1, 335 BUS_SPACE_BARRIER_WRITE); 336 } 337 338 static inline void 339 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 340 { 341 uint32_t reg; 342 343 reg = regr(sc, CLOCK_CNTL); 344 reg |= PLL_WR_EN; 345 regw(sc, CLOCK_CNTL, reg); 346 reg &= ~(PLL_ADDR | PLL_DATA); 347 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 348 reg |= data << PLL_DATA_SHIFT; 349 reg |= CLOCK_STROBE; 350 regw(sc, CLOCK_CNTL, reg); 351 reg &= ~PLL_WR_EN; 352 regw(sc, CLOCK_CNTL, reg); 353 } 354 355 static inline uint8_t 356 regrb_pll(struct mach64_softc *sc, uint32_t index) 357 { 358 359 regwb(sc, CLOCK_CNTL + 1, index << 2); 360 return regrb(sc, CLOCK_CNTL + 2); 361 } 362 363 static inline void 364 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 365 { 366 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 367 continue; 368 } 369 370 static inline void 371 wait_for_idle(struct mach64_softc *sc) 372 { 373 wait_for_fifo(sc, 16); 374 while ((regr(sc, GUI_STAT) & 1) != 0) 375 continue; 376 } 377 378 static int 379 mach64_match(device_t parent, cfdata_t match, void *aux) 380 { 381 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 382 int i; 383 384 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 385 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 386 return 0; 387 388 for (i = 0; i < __arraycount(mach64_info); i++) 389 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 390 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 391 mach64_chip_rev = PCI_REVISION(pa->pa_class); 392 return 100; 393 } 394 395 return 0; 396 } 397 398 static void 399 mach64_attach(device_t parent, device_t self, void *aux) 400 { 401 struct mach64_softc *sc = device_private(self); 402 struct pci_attach_args *pa = aux; 403 struct rasops_info *ri; 404 prop_data_t edid_data; 405 const struct videomode *mode = NULL; 406 int bar, id, expected_id; 407 int is_gx; 408 const char **memtype_names; 409 struct wsemuldisplaydev_attach_args aa; 410 long defattr; 411 int setmode = 0, width, height; 412 pcireg_t screg; 413 uint32_t reg; 414 const pcireg_t enables = PCI_COMMAND_MEM_ENABLE; 415 int use_mmio = FALSE; 416 417 sc->sc_dev = self; 418 sc->sc_pc = pa->pa_pc; 419 sc->sc_pcitag = pa->pa_tag; 420 sc->sc_dacw = -1; 421 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 422 sc->sc_nbus = pa->pa_bus; 423 sc->sc_ndev = pa->pa_device; 424 sc->sc_nfunc = pa->pa_function; 425 sc->sc_locked = 0; 426 sc->sc_iot = pa->pa_iot; 427 sc->sc_accessops.ioctl = mach64_ioctl; 428 sc->sc_accessops.mmap = mach64_mmap; 429 430 pci_aprint_devinfo(pa, "Graphics processor"); 431 #ifdef MACHFB_DEBUG 432 printf(prop_dictionary_externalize(device_properties(self))); 433 #endif 434 435 /* enable memory access */ 436 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 437 if ((screg & enables) != enables) { 438 screg |= enables; 439 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 440 PCI_COMMAND_STATUS_REG, screg); 441 } 442 for (bar = 0; bar < NBARS; bar++) { 443 reg = PCI_MAPREG_START + (bar * 4); 444 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 445 sc->sc_pcitag, reg); 446 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 447 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 448 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 449 } 450 aprint_debug_dev(sc->sc_dev, "aperture size %08x\n", 451 (uint32_t)sc->sc_apersize); 452 453 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 454 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 455 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 456 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 457 sc->sc_memt = pa->pa_memt; 458 459 /* use MMIO register aperture if available */ 460 if ((sc->sc_regbase != 0) && (sc->sc_regbase != 0xffffffff)) { 461 if (pci_mapreg_map(pa, MACH64_BAR_MMIO, PCI_MAPREG_TYPE_MEM, 462 0, &sc->sc_regt, &sc->sc_regh, &sc->sc_regbase, 463 &sc->sc_regsize) == 0) { 464 465 /* 466 * the MMIO aperture maps both 1KB register blocks, but 467 * all register offsets are relative to the 2nd one so 468 * for now fix this up in MACH64_REG_OFF and the access 469 * functions 470 */ 471 aprint_normal_dev(sc->sc_dev, "using MMIO aperture\n"); 472 use_mmio = TRUE; 473 } 474 } 475 if (!use_mmio) { 476 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, 477 sc->sc_apersize, BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 478 panic("%s: failed to map aperture", 479 device_xname(sc->sc_dev)); 480 } 481 482 sc->sc_regt = sc->sc_memt; 483 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 484 MACH64_REG_SIZE, &sc->sc_regh); 485 } 486 487 mach64_init(sc); 488 489 aprint_normal_dev(sc->sc_dev, 490 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 491 (u_int)(sc->sc_apersize / (1024 * 1024)), 492 (u_int)sc->sc_aperbase, (u_int)(sc->sc_regsize / 1024), 493 (u_int)sc->sc_regbase); 494 495 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 496 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 497 498 prop_dictionary_get_uint32(device_properties(self), "width", &width); 499 prop_dictionary_get_uint32(device_properties(self), "height", &height); 500 501 memset(&sc->sc_ei, 0, sizeof(sc->sc_ei)); 502 if ((edid_data = prop_dictionary_get(device_properties(self), "EDID")) 503 != NULL) { 504 505 sc->sc_edid_size = uimin(1024, prop_data_size(edid_data)); 506 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 507 memcpy(sc->sc_edid_data, prop_data_data_nocopy(edid_data), 508 sc->sc_edid_size); 509 510 edid_parse(sc->sc_edid_data, &sc->sc_ei); 511 512 #ifdef MACHFB_DEBUG 513 edid_print(&sc->sc_ei); 514 #endif 515 } 516 517 is_gx = 0; 518 switch(mach64_chip_id) { 519 case PCI_PRODUCT_ATI_MACH64_GX: 520 case PCI_PRODUCT_ATI_MACH64_CX: 521 is_gx = 1; 522 case PCI_PRODUCT_ATI_MACH64_CT: 523 sc->has_dsp = 0; 524 break; 525 case PCI_PRODUCT_ATI_MACH64_VT: 526 case PCI_PRODUCT_ATI_RAGE_II: 527 if((mach64_chip_rev & 0x07) == 0) { 528 sc->has_dsp = 0; 529 break; 530 } 531 /* Otherwise fall through. */ 532 default: 533 sc->has_dsp = 1; 534 } 535 536 memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names; 537 538 sc->memsize = mach64_get_memsize(sc); 539 540 if(is_gx) 541 sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07; 542 else 543 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 544 545 /* 546 * XXX is there any way to calculate reference frequency from 547 * known values? 548 */ 549 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 550 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 551 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 552 aprint_normal_dev(sc->sc_dev, "ref_freq=29.498MHz\n"); 553 sc->ref_freq = 29498; 554 } else 555 sc->ref_freq = 14318; 556 557 reg = regr(sc, CLOCK_CNTL); 558 aprint_debug("CLOCK_CNTL: %08x\n", reg); 559 sc->sc_clock = reg & 3; 560 aprint_debug("using clock %d\n", sc->sc_clock); 561 562 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 563 aprint_error("ref_div: %d\n", sc->ref_div); 564 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 565 aprint_error("mclk_fb_div: %d\n", sc->mclk_fb_div); 566 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 567 (sc->ref_div * 2); 568 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 569 (sc->mem_freq * sc->ref_div); 570 sc->ramdac_freq = mach64_get_max_ramdac(sc); 571 { 572 sc->minref = sc->ramdac_freq / 510; 573 sc->m = sc->ref_freq / sc->minref; 574 aprint_error("minref: %d m: %d\n", sc->minref, sc->m); 575 } 576 aprint_normal_dev(sc->sc_dev, 577 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 578 (u_long)sc->memsize, 579 memtype_names[sc->memtype], 580 sc->mem_freq / 1000, sc->mem_freq % 1000, 581 sc->ramdac_freq / 1000); 582 583 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 584 switch(mach64_chip_id) { 585 case PCI_PRODUCT_ATI_MACH64_GX: 586 expected_id = 0x00d7; 587 break; 588 case PCI_PRODUCT_ATI_MACH64_CX: 589 expected_id = 0x0057; 590 break; 591 default: 592 /* Most chip IDs match their PCI product ID. */ 593 expected_id = mach64_chip_id; 594 } 595 596 if (id != expected_id) { 597 aprint_error_dev(sc->sc_dev, 598 "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id); 599 return; 600 } 601 602 sc->sc_console = mach64_is_console(sc); 603 aprint_debug("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 604 605 #define MODE_IS_VALID(m) ((sc->ramdac_freq >= (m)->dot_clock) && \ 606 ((m)->hdisplay <= 11280)) 607 608 /* no mode setting support on ancient chips with external clocks */ 609 setmode = 0; 610 if (!is_gx) { 611 /* 612 * Now pick a mode. 613 */ 614 if ((sc->sc_ei.edid_preferred_mode != NULL)) { 615 struct videomode *m = sc->sc_ei.edid_preferred_mode; 616 if (MODE_IS_VALID(m)) { 617 memcpy(&default_mode, m, 618 sizeof(struct videomode)); 619 setmode = 1; 620 } else { 621 aprint_error_dev(sc->sc_dev, 622 "unable to use preferred mode\n"); 623 } 624 } 625 /* 626 * if we can't use the preferred mode go look for the 627 * best one we can support 628 */ 629 if (setmode == 0) { 630 struct videomode *m = sc->sc_ei.edid_modes; 631 632 mode = NULL; 633 sort_modes(sc->sc_ei.edid_modes, 634 &sc->sc_ei.edid_preferred_mode, 635 sc->sc_ei.edid_nmodes); 636 for (int n = 0; n < sc->sc_ei.edid_nmodes; n++) 637 if (MODE_IS_VALID(&m[n])) { 638 mode = &m[n]; 639 break; 640 } 641 if (mode != NULL) { 642 memcpy(&default_mode, mode, 643 sizeof(struct videomode)); 644 setmode = 1; 645 } 646 } 647 /* got nothing? try to pick one based on firmware parameters */ 648 if (setmode == 0 && width > 0 && height > 0) { 649 /* no EDID data? */ 650 mode = pick_mode_by_ref(width, height, 60); 651 memcpy(&default_mode, mode, sizeof(struct videomode)); 652 setmode = 1; 653 } 654 /* still nothing? Grab the default */ 655 if (setmode == 0) { 656 mode = pick_mode_by_ref(1024, 768, 60); 657 memcpy(&default_mode, mode, sizeof(struct videomode)); 658 setmode = 1; 659 } 660 } else { 661 /* make sure my_mode points at something sensible */ 662 mach64_get_mode(sc, &default_mode); 663 if (default_mode.dot_clock == 0) { 664 memcpy(&default_mode, pick_mode_by_ref(width, height, 60), 665 sizeof(default_mode)); 666 } 667 } 668 sc->sc_my_mode = &default_mode; 669 670 sc->bits_per_pixel = 8; 671 sc->virt_x = sc->sc_my_mode->hdisplay; 672 sc->virt_y = sc->sc_my_mode->vdisplay; 673 sc->max_x = sc->virt_x - 1; 674 sc->max_y = (sc->memsize * 1024) / 675 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 676 677 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 678 679 mach64_init_engine(sc); 680 681 if (setmode) 682 mach64_modeswitch(sc, sc->sc_my_mode); 683 684 aprint_normal_dev(sc->sc_dev, 685 "initial resolution %dx%d at %d bpp\n", 686 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 687 sc->bits_per_pixel); 688 689 wsfont_init(); 690 691 #ifdef GLYPHCACHE_DEBUG 692 /* shrink the screen so we can see part of the glyph cache */ 693 sc->sc_my_mode->vdisplay -= 200; 694 #endif 695 696 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &sc->sc_accessops); 697 sc->vd.init_screen = mach64_init_screen; 698 sc->vd.show_screen_cookie = &sc->sc_gc; 699 sc->vd.show_screen_cb = glyphcache_adapt; 700 701 sc->sc_gc.gc_bitblt = mach64_bitblt; 702 sc->sc_gc.gc_blitcookie = sc; 703 sc->sc_gc.gc_rop = MIX_SRC; 704 705 ri = &mach64_console_screen.scr_ri; 706 if (sc->sc_console) { 707 708 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 709 &defattr); 710 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 711 712 mach64_defaultscreen.textops = &ri->ri_ops; 713 mach64_defaultscreen.capabilities = ri->ri_caps; 714 mach64_defaultscreen.nrows = ri->ri_rows; 715 mach64_defaultscreen.ncols = ri->ri_cols; 716 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 717 ((sc->memsize * 1024) / sc->sc_my_mode->hdisplay) - 718 sc->sc_my_mode->vdisplay - 5, 719 sc->sc_my_mode->hdisplay, 720 ri->ri_font->fontwidth, 721 ri->ri_font->fontheight, 722 defattr); 723 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 724 } else { 725 /* 726 * since we're not the console we can postpone the rest 727 * until someone actually allocates a screen for us 728 */ 729 mach64_modeswitch(sc, sc->sc_my_mode); 730 if (mach64_console_screen.scr_ri.ri_rows == 0) { 731 /* do some minimal setup to avoid weirdnesses later */ 732 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 733 &defattr); 734 } else 735 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 736 737 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 738 ((sc->memsize * 1024) / sc->sc_my_mode->hdisplay) - 739 sc->sc_my_mode->vdisplay - 5, 740 sc->sc_my_mode->hdisplay, 741 ri->ri_font->fontwidth, 742 ri->ri_font->fontheight, 743 defattr); 744 } 745 746 sc->sc_bg = mach64_console_screen.scr_ri.ri_devcmap[WS_DEFAULT_BG]; 747 mach64_clearscreen(sc); 748 mach64_init_lut(sc); 749 750 if (sc->sc_console) 751 vcons_replay_msgbuf(&mach64_console_screen); 752 753 machfb_blank(sc, 0); /* unblank the screen */ 754 755 aa.console = sc->sc_console; 756 aa.scrdata = &mach64_screenlist; 757 aa.accessops = &sc->sc_accessops; 758 aa.accesscookie = &sc->vd; 759 760 config_found(self, &aa, wsemuldisplaydevprint); 761 #if 0 762 /* XXX 763 * turns out some firmware doesn't turn these back on when needed 764 * so we need to turn them off only when mapping vram in 765 * WSDISPLAYIO_MODE_DUMB would overlap ( unlikely but far from 766 * impossible ) 767 */ 768 if (use_mmio) { 769 /* 770 * Now that we took over, turn off the aperture registers if we 771 * don't use them. Can't do this earlier since on some hardware 772 * we use firmware calls as early console output which may in 773 * turn try to access these registers. 774 */ 775 reg = regr(sc, BUS_CNTL); 776 aprint_debug_dev(sc->sc_dev, "BUS_CNTL: %08x\n", reg); 777 reg |= BUS_APER_REG_DIS; 778 regw(sc, BUS_CNTL, reg); 779 } 780 #endif 781 config_found_ia(self, "drm", aux, machfb_drm_print); 782 } 783 784 static int 785 machfb_drm_print(void *aux, const char *pnp) 786 { 787 if (pnp) 788 aprint_normal("direct rendering for %s", pnp); 789 return (UNSUPP); 790 } 791 792 static void 793 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 794 long *defattr) 795 { 796 struct mach64_softc *sc = cookie; 797 struct rasops_info *ri = &scr->scr_ri; 798 799 ri->ri_depth = sc->bits_per_pixel; 800 ri->ri_width = sc->sc_my_mode->hdisplay; 801 ri->ri_height = sc->sc_my_mode->vdisplay; 802 ri->ri_stride = ri->ri_width; 803 ri->ri_flg = RI_CENTER | RI_FULLCLEAR; 804 if (ri->ri_depth == 8) 805 ri->ri_flg |= RI_8BIT_IS_RGB | RI_ENABLE_ALPHA | 806 RI_PREFER_ALPHA; 807 808 #ifdef VCONS_DRAW_INTR 809 scr->scr_flags |= VCONS_DONT_READ; 810 #endif 811 scr->scr_flags |= VCONS_LOADFONT; 812 813 rasops_init(ri, 0, 0); 814 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE | 815 WSSCREEN_RESIZE; 816 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 817 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 818 819 /* enable acceleration */ 820 ri->ri_hw = scr; 821 ri->ri_ops.copyrows = mach64_copyrows; 822 ri->ri_ops.copycols = mach64_copycols; 823 ri->ri_ops.eraserows = mach64_eraserows; 824 ri->ri_ops.erasecols = mach64_erasecols; 825 ri->ri_ops.cursor = mach64_cursor; 826 if (FONT_IS_ALPHA(ri->ri_font)) { 827 ri->ri_ops.putchar = mach64_putchar_aa8; 828 } else 829 ri->ri_ops.putchar = mach64_putchar_mono; 830 } 831 832 static void 833 mach64_init(struct mach64_softc *sc) 834 { 835 sc->sc_blanked = 0; 836 } 837 838 static int 839 mach64_get_memsize(struct mach64_softc *sc) 840 { 841 int tmp, memsize; 842 int mem_tab[] = { 843 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 844 }; 845 tmp = regr(sc, MEM_CNTL); 846 #ifdef DIAGNOSTIC 847 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 848 #endif 849 if (sc->has_dsp) { 850 tmp &= 0x0000000f; 851 if (tmp < 8) 852 memsize = (tmp + 1) * 512; 853 else if (tmp < 12) 854 memsize = (tmp - 3) * 1024; 855 else 856 memsize = (tmp - 7) * 2048; 857 } else { 858 memsize = mem_tab[tmp & 0x07]; 859 } 860 861 return memsize; 862 } 863 864 static int 865 mach64_get_max_ramdac(struct mach64_softc *sc) 866 { 867 int i; 868 869 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 870 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 871 (mach64_chip_rev & 0x07)) 872 return 170000; 873 874 for (i = 0; i < __arraycount(mach64_info); i++) 875 if (mach64_chip_id == mach64_info[i].chip_id) 876 return mach64_info[i].ramdac_freq; 877 878 if (sc->bits_per_pixel == 8) 879 return 135000; 880 else 881 return 80000; 882 } 883 884 static void 885 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 886 { 887 struct mach64_crtcregs crtc; 888 889 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 890 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 891 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 892 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 893 894 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 895 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 896 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 897 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 898 mode->hsync_start; 899 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 900 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 901 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 902 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 903 904 #ifdef MACHFB_DEBUG 905 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 906 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 907 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 908 #endif 909 } 910 911 static int 912 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 913 struct videomode *mode) 914 { 915 916 if (mode->dot_clock > sc->ramdac_freq) 917 /* Clock too high. */ 918 return 1; 919 920 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 921 ((mode->htotal >> 3) - 1); 922 crtc->h_sync_strt_wid = 923 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 924 ((mode->hsync_start >> 3) - 1); 925 926 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 927 (mode->vtotal - 1); 928 crtc->v_sync_strt_wid = 929 ((mode->vsync_end - mode->vsync_start) << 16) | 930 (mode->vsync_start - 1); 931 932 if (mode->flags & VID_NVSYNC) 933 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 934 935 switch (sc->bits_per_pixel) { 936 case 8: 937 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 938 break; 939 case 16: 940 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 941 break; 942 case 32: 943 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 944 break; 945 } 946 947 crtc->gen_cntl = 0; 948 if (mode->flags & VID_INTERLACE) 949 crtc->gen_cntl |= CRTC_INTERLACE_EN; 950 951 if (mode->flags & VID_CSYNC) 952 crtc->gen_cntl |= CRTC_CSYNC_EN; 953 954 crtc->dot_clock = mode->dot_clock; 955 956 return 0; 957 } 958 959 static void 960 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 961 { 962 963 mach64_set_pll(sc, crtc->dot_clock); 964 965 if (sc->has_dsp) 966 mach64_set_dsp(sc); 967 968 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 969 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 970 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 971 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 972 973 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 974 975 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 976 977 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 978 /* XXX this unconditionally enables composite sync on SPARC */ 979 #ifdef __sparc__ 980 CRTC_CSYNC_EN | 981 #endif 982 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 983 } 984 985 static int 986 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 987 { 988 struct mach64_crtcregs crtc; 989 990 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 991 992 if (mach64_calc_crtcregs(sc, &crtc, mode)) 993 return 1; 994 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 995 if (crtc.dot_clock == 0) { 996 aprint_error("%s: preposterous dot clock (%d)\n", 997 device_xname(sc->sc_dev), crtc.dot_clock); 998 return 1; 999 } 1000 mach64_set_crtcregs(sc, &crtc); 1001 return 0; 1002 } 1003 1004 static void 1005 mach64_reset_engine(struct mach64_softc *sc) 1006 { 1007 1008 /* Reset engine.*/ 1009 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1010 1011 /* Enable engine. */ 1012 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1013 1014 /* Ensure engine is not locked up by clearing any FIFO or 1015 host errors. */ 1016 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1017 BUS_FIFO_ERR_ACK); 1018 } 1019 1020 static void 1021 mach64_init_engine(struct mach64_softc *sc) 1022 { 1023 uint32_t pitch_value; 1024 1025 pitch_value = sc->virt_x; 1026 1027 if (sc->bits_per_pixel == 24) 1028 pitch_value *= 3; 1029 1030 mach64_reset_engine(sc); 1031 1032 wait_for_fifo(sc, 14); 1033 1034 regw(sc, CONTEXT_MASK, 0xffffffff); 1035 1036 regw(sc, DST_OFF_PITCH, (pitch_value >> 3) << 22); 1037 1038 /* make sure the visible area starts where we're going to draw */ 1039 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1040 1041 regw(sc, DST_Y_X, 0); 1042 regw(sc, DST_HEIGHT, 0); 1043 regw(sc, DST_BRES_ERR, 0); 1044 regw(sc, DST_BRES_INC, 0); 1045 regw(sc, DST_BRES_DEC, 0); 1046 1047 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1048 DST_Y_TOP_TO_BOTTOM); 1049 1050 regw(sc, SRC_OFF_PITCH, (pitch_value >> 3) << 22); 1051 1052 regw(sc, SRC_Y_X, 0); 1053 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1054 regw(sc, SRC_Y_X_START, 0); 1055 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1056 1057 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1058 1059 wait_for_fifo(sc, 13); 1060 regw(sc, HOST_CNTL, 0); 1061 1062 regw(sc, PAT_REG0, 0); 1063 regw(sc, PAT_REG1, 0); 1064 regw(sc, PAT_CNTL, 0); 1065 1066 regw(sc, SC_LEFT, 0); 1067 regw(sc, SC_TOP, 0); 1068 regw(sc, SC_BOTTOM, 0x3fff); 1069 regw(sc, SC_RIGHT, pitch_value - 1); 1070 1071 regw(sc, DP_BKGD_CLR, WS_DEFAULT_BG); 1072 regw(sc, DP_FRGD_CLR, WS_DEFAULT_FG); 1073 regw(sc, DP_WRITE_MASK, 0xffffffff); 1074 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1075 1076 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1077 1078 wait_for_fifo(sc, 3); 1079 regw(sc, CLR_CMP_CLR, 0); 1080 regw(sc, CLR_CMP_MASK, 0xffffffff); 1081 regw(sc, CLR_CMP_CNTL, 0); 1082 1083 wait_for_fifo(sc, 3); 1084 switch (sc->bits_per_pixel) { 1085 case 8: 1086 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP); 1087 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1088 /* We want 8 bit per channel */ 1089 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1090 break; 1091 case 32: 1092 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP); 1093 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1094 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1095 break; 1096 } 1097 regw(sc, DP_WRITE_MASK, 0xff); 1098 1099 wait_for_fifo(sc, 5); 1100 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1101 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1102 1103 wait_for_idle(sc); 1104 } 1105 1106 #if 0 1107 static void 1108 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1109 { 1110 int offset; 1111 1112 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1113 1114 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1115 offset); 1116 } 1117 #endif 1118 1119 static void 1120 mach64_set_dsp(struct mach64_softc *sc) 1121 { 1122 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1123 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1124 uint32_t xclks_per_qw, xclks_per_qw_m, y; 1125 uint32_t fifo_off, fifo_on; 1126 1127 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1128 1129 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1130 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1131 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1132 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1133 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1134 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1135 dsp_loop_latency = 0; 1136 fifo_depth = 24; 1137 } else { 1138 dsp_loop_latency = 2; 1139 fifo_depth = 32; 1140 } 1141 1142 dsp_precision = 0; 1143 1144 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1145 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1146 1147 xclks_per_qw_m = (sc->mem_freq * 64 << 4) / 1148 (sc->vclk_freq * sc->bits_per_pixel); 1149 printf("xclks_per_qw %d %d\n", xclks_per_qw >> 7, xclks_per_qw_m); 1150 y = (xclks_per_qw * fifo_depth) >> 11; 1151 1152 while (y) { 1153 y >>= 1; 1154 dsp_precision++; 1155 } 1156 dsp_precision -= 5; 1157 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1158 1159 switch (sc->memtype) { 1160 case DRAM: 1161 case EDO_DRAM: 1162 case PSEUDO_EDO: 1163 if (sc->memsize > 1024) { 1164 page_size = 9; 1165 dsp_loop_latency += 6; 1166 } else { 1167 page_size = 10; 1168 if (sc->memtype == DRAM) 1169 dsp_loop_latency += 8; 1170 else 1171 dsp_loop_latency += 7; 1172 } 1173 break; 1174 case SDRAM: 1175 if (sc->memsize > 1024) { 1176 page_size = 8; 1177 dsp_loop_latency += 8; 1178 } else { 1179 page_size = 10; 1180 dsp_loop_latency += 9; 1181 } 1182 break; 1183 case SGRAM: 1184 page_size = 8; 1185 dsp_loop_latency = 8; 1186 break; 1187 default: 1188 page_size = 10; 1189 dsp_loop_latency += 9; 1190 break; 1191 } 1192 1193 if (xclks_per_qw >= (page_size << 11)) 1194 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1195 else 1196 fifo_on = (3 * page_size + 2) << 6; 1197 1198 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1199 dsp_on = fifo_on >> dsp_precision; 1200 dsp_off = fifo_off >> dsp_precision; 1201 1202 #ifdef MACHFB_DEBUG 1203 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1204 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1205 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1206 "mclk_post_div = %d, vclk_post_div = %d\n", 1207 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1208 sc->mclk_fb_div, sc->vclk_fb_div, 1209 sc->mclk_post_div, sc->vclk_post_div); 1210 #endif 1211 1212 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1213 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1214 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1215 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1216 } 1217 1218 static void 1219 mach64_set_pll(struct mach64_softc *sc, int clock) 1220 { 1221 uint32_t q, clockreg; 1222 int clockshift = sc->sc_clock << 1; 1223 uint8_t reg, vclk_ctl; 1224 1225 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1226 #ifdef MACHFB_DEBUG 1227 printf("q = %d\n", q); 1228 #endif 1229 if (q > 25500) { 1230 aprint_error_dev(sc->sc_dev, "Warning: q > 25500\n"); 1231 q = 25500; 1232 sc->vclk_post_div = 1; 1233 sc->log2_vclk_post_div = 0; 1234 } else if (q > 12750) { 1235 sc->vclk_post_div = 1; 1236 sc->log2_vclk_post_div = 0; 1237 } else if (q > 6350) { 1238 sc->vclk_post_div = 2; 1239 sc->log2_vclk_post_div = 1; 1240 } else if (q > 3150) { 1241 sc->vclk_post_div = 4; 1242 sc->log2_vclk_post_div = 2; 1243 } else if (q >= 1600) { 1244 sc->vclk_post_div = 8; 1245 sc->log2_vclk_post_div = 3; 1246 } else { 1247 aprint_error_dev(sc->sc_dev, "Warning: q < 1600\n"); 1248 sc->vclk_post_div = 8; 1249 sc->log2_vclk_post_div = 3; 1250 } 1251 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1252 aprint_error("post_div: %d log2_post_div: %d mclk_div: %d\n", 1253 sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1254 1255 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1256 aprint_debug("vclk_ctl: %02x\n", vclk_ctl); 1257 vclk_ctl |= PLL_VCLK_RESET; 1258 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1259 1260 aprint_error("target: %d output: %d\n", clock, 1261 (2 * sc->ref_freq * sc->vclk_fb_div) / 1262 (sc->ref_div * sc->vclk_post_div)); 1263 1264 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1265 reg = regrb_pll(sc, VCLK_POST_DIV); 1266 reg &= ~(3 << clockshift); 1267 reg |= (sc->log2_vclk_post_div << clockshift); 1268 regwb_pll(sc, VCLK_POST_DIV, reg); 1269 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1270 1271 vclk_ctl &= ~PLL_VCLK_RESET; 1272 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1273 1274 clockreg = regr(sc, CLOCK_CNTL); 1275 clockreg &= ~CLOCK_SEL; 1276 clockreg |= sc->sc_clock | CLOCK_STROBE; 1277 regw(sc, CLOCK_CNTL, clockreg); 1278 sc->vclk_freq = clock; 1279 } 1280 1281 static void 1282 mach64_init_lut(struct mach64_softc *sc) 1283 { 1284 uint8_t cmap[768]; 1285 int i, idx; 1286 1287 rasops_get_cmap(&mach64_console_screen.scr_ri, cmap, sizeof(cmap)); 1288 idx = 0; 1289 for (i = 0; i < 256; i++) { 1290 mach64_putpalreg(sc, i, cmap[idx], cmap[idx + 1], 1291 cmap[idx + 2]); 1292 idx += 3; 1293 } 1294 } 1295 1296 static int 1297 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1298 uint8_t b) 1299 { 1300 sc->sc_cmap_red[index] = r; 1301 sc->sc_cmap_green[index] = g; 1302 sc->sc_cmap_blue[index] = b; 1303 /* 1304 * writing the dac index takes a while, in theory we can poll some 1305 * register to see when it's ready - but we better avoid writing it 1306 * unnecessarily 1307 */ 1308 if (index != sc->sc_dacw) { 1309 regwb(sc, DAC_MASK, 0xff); 1310 regwb(sc, DAC_WINDEX, index); 1311 } 1312 sc->sc_dacw = index + 1; 1313 regwb(sc, DAC_DATA, r); 1314 regwb(sc, DAC_DATA, g); 1315 regwb(sc, DAC_DATA, b); 1316 return 0; 1317 } 1318 1319 static int 1320 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1321 { 1322 uint index = cm->index; 1323 uint count = cm->count; 1324 int i, error; 1325 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1326 uint8_t *r, *g, *b; 1327 1328 if (cm->index >= 256 || cm->count > 256 || 1329 (cm->index + cm->count) > 256) 1330 return EINVAL; 1331 error = copyin(cm->red, &rbuf[index], count); 1332 if (error) 1333 return error; 1334 error = copyin(cm->green, &gbuf[index], count); 1335 if (error) 1336 return error; 1337 error = copyin(cm->blue, &bbuf[index], count); 1338 if (error) 1339 return error; 1340 1341 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1342 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1343 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1344 1345 r = &sc->sc_cmap_red[index]; 1346 g = &sc->sc_cmap_green[index]; 1347 b = &sc->sc_cmap_blue[index]; 1348 1349 for (i = 0; i < count; i++) { 1350 mach64_putpalreg(sc, index, *r, *g, *b); 1351 index++; 1352 r++, g++, b++; 1353 } 1354 return 0; 1355 } 1356 1357 static int 1358 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1359 { 1360 u_int index = cm->index; 1361 u_int count = cm->count; 1362 int error; 1363 1364 if (index >= 255 || count > 256 || index + count > 256) 1365 return EINVAL; 1366 1367 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1368 if (error) 1369 return error; 1370 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1371 if (error) 1372 return error; 1373 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1374 if (error) 1375 return error; 1376 1377 return 0; 1378 } 1379 1380 static int 1381 mach64_is_console(struct mach64_softc *sc) 1382 { 1383 bool console = 0; 1384 1385 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1386 "is_console", &console); 1387 return console; 1388 } 1389 1390 /* 1391 * wsdisplay_emulops 1392 */ 1393 1394 static void 1395 mach64_cursor(void *cookie, int on, int row, int col) 1396 { 1397 struct rasops_info *ri = cookie; 1398 struct vcons_screen *scr = ri->ri_hw; 1399 struct mach64_softc *sc = scr->scr_cookie; 1400 int x, y, wi, he; 1401 1402 wi = ri->ri_font->fontwidth; 1403 he = ri->ri_font->fontheight; 1404 1405 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1406 x = ri->ri_ccol * wi + ri->ri_xorigin; 1407 y = ri->ri_crow * he + ri->ri_yorigin; 1408 if (ri->ri_flg & RI_CURSOR) { 1409 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1410 ri->ri_flg &= ~RI_CURSOR; 1411 } 1412 ri->ri_crow = row; 1413 ri->ri_ccol = col; 1414 if (on) { 1415 x = ri->ri_ccol * wi + ri->ri_xorigin; 1416 y = ri->ri_crow * he + ri->ri_yorigin; 1417 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1418 ri->ri_flg |= RI_CURSOR; 1419 } 1420 } else { 1421 scr->scr_ri.ri_crow = row; 1422 scr->scr_ri.ri_ccol = col; 1423 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1424 } 1425 } 1426 1427 #if 0 1428 static int 1429 mach64_mapchar(void *cookie, int uni, u_int *index) 1430 { 1431 return 0; 1432 } 1433 #endif 1434 1435 static void 1436 mach64_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1437 { 1438 struct rasops_info *ri = cookie; 1439 struct wsdisplay_font *font = PICK_FONT(ri, c); 1440 struct vcons_screen *scr = ri->ri_hw; 1441 struct mach64_softc *sc = scr->scr_cookie; 1442 1443 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1444 int fg, bg, uc; 1445 uint8_t *data; 1446 int x, y, wi, he; 1447 wi = font->fontwidth; 1448 he = font->fontheight; 1449 1450 if (!CHAR_IN_FONT(c, font)) 1451 return; 1452 bg = ri->ri_devcmap[(attr >> 16) & 0x0f]; 1453 fg = ri->ri_devcmap[(attr >> 24) & 0x0f]; 1454 x = ri->ri_xorigin + col * wi; 1455 y = ri->ri_yorigin + row * he; 1456 if (c == 0x20) { 1457 mach64_rectfill(sc, x, y, wi, he, bg); 1458 } else { 1459 uc = c - font->firstchar; 1460 data = (uint8_t *)font->data + uc * 1461 ri->ri_fontscale; 1462 1463 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1464 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1465 } 1466 if (attr & 1) 1467 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1468 } 1469 } 1470 1471 static void 1472 mach64_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 1473 { 1474 struct rasops_info *ri = cookie; 1475 struct wsdisplay_font *font = PICK_FONT(ri, c); 1476 struct vcons_screen *scr = ri->ri_hw; 1477 struct mach64_softc *sc = scr->scr_cookie; 1478 uint32_t bg, fg, latch = 0, bg8, fg8, pixel; 1479 int i, x, y, wi, he, r, g, b, aval; 1480 int r1, g1, b1, r0, g0, b0, fgo, bgo; 1481 uint8_t *data8; 1482 int rv = 0, cnt = 0; 1483 1484 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1485 return; 1486 1487 if (!CHAR_IN_FONT(c, font)) 1488 return; 1489 1490 wi = font->fontwidth; 1491 he = font->fontheight; 1492 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1493 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f]; 1494 x = ri->ri_xorigin + col * wi; 1495 y = ri->ri_yorigin + row * he; 1496 1497 if (c == 0x20) { 1498 mach64_rectfill(sc, x, y, wi, he, bg); 1499 if (attr & 1) 1500 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1501 return; 1502 } 1503 1504 rv = glyphcache_try(&sc->sc_gc, c, x, y, attr); 1505 if (rv == GC_OK) 1506 return; 1507 1508 data8 = WSFONT_GLYPH(c, font); 1509 1510 wait_for_fifo(sc, 11); 1511 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1512 regw(sc, DP_SRC, MONO_SRC_ONE | BKGD_SRC_HOST | FRGD_SRC_HOST); 1513 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1514 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1515 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1516 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1517 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1518 regw(sc, SRC_Y_X, 0); 1519 regw(sc, SRC_WIDTH1, wi); 1520 regw(sc, DST_Y_X, (x << 16) | y); 1521 regw(sc, DST_HEIGHT_WIDTH, (wi << 16) | he); 1522 1523 /* 1524 * we need the RGB colours here, so get offsets into rasops_cmap 1525 */ 1526 fgo = ((attr >> 24) & 0xf) * 3; 1527 bgo = ((attr >> 16) & 0xf) * 3; 1528 1529 r0 = rasops_cmap[bgo]; 1530 r1 = rasops_cmap[fgo]; 1531 g0 = rasops_cmap[bgo + 1]; 1532 g1 = rasops_cmap[fgo + 1]; 1533 b0 = rasops_cmap[bgo + 2]; 1534 b1 = rasops_cmap[fgo + 2]; 1535 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 1536 bg8 = R3G3B2(r0, g0, b0); 1537 fg8 = R3G3B2(r1, g1, b1); 1538 1539 wait_for_fifo(sc, 10); 1540 1541 for (i = 0; i < ri->ri_fontscale; i++) { 1542 aval = *data8; 1543 if (aval == 0) { 1544 pixel = bg8; 1545 } else if (aval == 255) { 1546 pixel = fg8; 1547 } else { 1548 r = aval * r1 + (255 - aval) * r0; 1549 g = aval * g1 + (255 - aval) * g0; 1550 b = aval * b1 + (255 - aval) * b0; 1551 pixel = ((r & 0xe000) >> 8) | 1552 ((g & 0xe000) >> 11) | 1553 ((b & 0xc000) >> 14); 1554 } 1555 latch = (latch << 8) | pixel; 1556 /* write in 32bit chunks */ 1557 if ((i & 3) == 3) { 1558 regws(sc, HOST_DATA0, latch); 1559 /* 1560 * not strictly necessary, old data should be shifted 1561 * out 1562 */ 1563 latch = 0; 1564 cnt++; 1565 if (cnt > 8) { 1566 wait_for_fifo(sc, 10); 1567 cnt = 0; 1568 } 1569 } 1570 data8++; 1571 } 1572 /* if we have pixels left in latch write them out */ 1573 if ((i & 3) != 0) { 1574 latch = latch << ((4 - (i & 3)) << 3); 1575 regws(sc, HOST_DATA0, latch); 1576 } 1577 1578 if (rv == GC_ADD) { 1579 glyphcache_add(&sc->sc_gc, c, x, y); 1580 } else if (attr & 1) { 1581 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1582 } 1583 1584 } 1585 1586 static void 1587 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1588 { 1589 struct rasops_info *ri = cookie; 1590 struct vcons_screen *scr = ri->ri_hw; 1591 struct mach64_softc *sc = scr->scr_cookie; 1592 int32_t xs, xd, y, width, height; 1593 1594 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1595 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1596 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1597 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1598 width = ri->ri_font->fontwidth * ncols; 1599 height = ri->ri_font->fontheight; 1600 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC); 1601 } 1602 } 1603 1604 static void 1605 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1606 { 1607 struct rasops_info *ri = cookie; 1608 struct vcons_screen *scr = ri->ri_hw; 1609 struct mach64_softc *sc = scr->scr_cookie; 1610 int32_t x, y, width, height, fg, bg, ul; 1611 1612 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1613 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1614 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1615 width = ri->ri_font->fontwidth * ncols; 1616 height = ri->ri_font->fontheight; 1617 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1618 1619 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1620 } 1621 } 1622 1623 static void 1624 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1625 { 1626 struct rasops_info *ri = cookie; 1627 struct vcons_screen *scr = ri->ri_hw; 1628 struct mach64_softc *sc = scr->scr_cookie; 1629 int32_t x, ys, yd, width, height; 1630 1631 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1632 x = ri->ri_xorigin; 1633 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1634 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1635 width = ri->ri_emuwidth; 1636 height = ri->ri_font->fontheight*nrows; 1637 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC); 1638 } 1639 } 1640 1641 static void 1642 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1643 { 1644 struct rasops_info *ri = cookie; 1645 struct vcons_screen *scr = ri->ri_hw; 1646 struct mach64_softc *sc = scr->scr_cookie; 1647 int32_t x, y, width, height, fg, bg, ul; 1648 1649 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1650 if ((row == 0) && (nrows == ri->ri_rows)) { 1651 /* clear full screen */ 1652 x = 0; 1653 y = 0; 1654 width = sc->virt_x; 1655 height = sc->virt_y; 1656 } else { 1657 x = ri->ri_xorigin; 1658 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1659 width = ri->ri_emuwidth; 1660 height = ri->ri_font->fontheight * nrows; 1661 } 1662 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1663 1664 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1665 } 1666 } 1667 1668 static void 1669 mach64_bitblt(void *cookie, int xs, int ys, int xd, int yd, int width, 1670 int height, int rop) 1671 { 1672 struct mach64_softc *sc = cookie; 1673 uint32_t dest_ctl = 0; 1674 1675 #if 0 1676 wait_for_idle(sc); 1677 #else 1678 wait_for_fifo(sc, 10); 1679 #endif 1680 1681 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1682 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1683 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1684 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1685 if (yd < ys) { 1686 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1687 } else { 1688 ys += height - 1; 1689 yd += height - 1; 1690 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1691 } 1692 if (xd < xs) { 1693 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1694 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1695 } else { 1696 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1697 xs += width - 1; 1698 xd += width - 1; 1699 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1700 } 1701 regw(sc, DST_CNTL, dest_ctl); 1702 1703 regw(sc, SRC_Y_X, (xs << 16) | ys); 1704 regw(sc, SRC_WIDTH1, width); 1705 regw(sc, DST_Y_X, (xd << 16) | yd); 1706 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1707 } 1708 1709 static void 1710 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1711 int height, uint32_t fg, uint32_t bg) 1712 { 1713 wait_for_idle(sc); 1714 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1715 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1716 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1717 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1718 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1719 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1720 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1721 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1722 regw(sc, DP_BKGD_CLR, bg); 1723 regw(sc, DP_FRGD_CLR, fg); 1724 regw(sc, SRC_Y_X, 0); 1725 regw(sc, SRC_WIDTH1, width); 1726 regw(sc, DST_Y_X, (xd << 16) | yd); 1727 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1728 /* now feed the data into the chip */ 1729 } 1730 1731 static void 1732 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1733 { 1734 int i; 1735 uint32_t latch = 0, bork; 1736 int shift = 0; 1737 int reg = 0; 1738 1739 for (i = 0; i < count; i++) { 1740 bork = data[i]; 1741 latch |= (bork << shift); 1742 if (shift == 24) { 1743 regw(sc, HOST_DATA0 + reg, latch); 1744 latch = 0; 1745 shift = 0; 1746 reg = (reg + 4) & 0x3c; 1747 } else 1748 shift += 8; 1749 } 1750 if (shift != 0) /* 24 */ 1751 regw(sc, HOST_DATA0 + reg, latch); 1752 } 1753 1754 1755 static void 1756 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1757 int colour) 1758 { 1759 wait_for_fifo(sc, 11); 1760 regw(sc, DP_FRGD_CLR, colour); 1761 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1762 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1763 regw(sc, DP_MIX, MIX_SRC << 16); 1764 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1765 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1766 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1767 1768 regw(sc, SRC_Y_X, (x << 16) | y); 1769 regw(sc, SRC_WIDTH1, width); 1770 regw(sc, DST_Y_X, (x << 16) | y); 1771 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1772 } 1773 1774 static void 1775 mach64_clearscreen(struct mach64_softc *sc) 1776 { 1777 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1778 } 1779 1780 1781 #if 0 1782 static void 1783 mach64_showpal(struct mach64_softc *sc) 1784 { 1785 int i, x = 0; 1786 1787 for (i = 0; i < 16; i++) { 1788 mach64_rectfill(sc, x, 0, 64, 64, i); 1789 x += 64; 1790 } 1791 } 1792 #endif 1793 1794 /* 1795 * wsdisplay_accessops 1796 */ 1797 1798 static int 1799 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1800 struct lwp *l) 1801 { 1802 struct vcons_data *vd = v; 1803 struct mach64_softc *sc = vd->cookie; 1804 struct wsdisplay_fbinfo *wdf; 1805 struct vcons_screen *ms = vd->active; 1806 1807 switch (cmd) { 1808 case WSDISPLAYIO_GTYPE: 1809 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1810 return 0; 1811 1812 case WSDISPLAYIO_LINEBYTES: 1813 *(u_int *)data = sc->virt_x * sc->bits_per_pixel / 8; 1814 return 0; 1815 1816 case WSDISPLAYIO_GINFO: 1817 wdf = (void *)data; 1818 wdf->height = sc->virt_y; 1819 wdf->width = sc->virt_x; 1820 wdf->depth = sc->bits_per_pixel; 1821 wdf->cmsize = 256; 1822 return 0; 1823 1824 case WSDISPLAYIO_GETCMAP: 1825 return mach64_getcmap(sc, 1826 (struct wsdisplay_cmap *)data); 1827 1828 case WSDISPLAYIO_PUTCMAP: 1829 return mach64_putcmap(sc, 1830 (struct wsdisplay_cmap *)data); 1831 1832 /* PCI config read/write passthrough. */ 1833 case PCI_IOC_CFGREAD: 1834 case PCI_IOC_CFGWRITE: 1835 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1836 cmd, data, flag, l); 1837 1838 case WSDISPLAYIO_GET_BUSID: 1839 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1840 sc->sc_pcitag, data); 1841 1842 case WSDISPLAYIO_SMODE: { 1843 int new_mode = *(int*)data; 1844 if (new_mode != sc->sc_mode) { 1845 sc->sc_mode = new_mode; 1846 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1847 && (ms != NULL)) 1848 { 1849 /* restore initial video mode */ 1850 mach64_init(sc); 1851 mach64_init_engine(sc); 1852 mach64_init_lut(sc); 1853 mach64_modeswitch(sc, sc->sc_my_mode); 1854 mach64_clearscreen(sc); 1855 glyphcache_wipe(&sc->sc_gc); 1856 vcons_redraw_screen(ms); 1857 } 1858 } 1859 } 1860 return 0; 1861 case WSDISPLAYIO_GET_EDID: { 1862 struct wsdisplayio_edid_info *d = data; 1863 return wsdisplayio_get_edid(sc->sc_dev, d); 1864 } 1865 1866 case WSDISPLAYIO_GET_FBINFO: { 1867 struct wsdisplayio_fbinfo *fbi = data; 1868 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1869 } 1870 } 1871 return EPASSTHROUGH; 1872 } 1873 1874 static paddr_t 1875 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1876 { 1877 struct vcons_data *vd = v; 1878 struct mach64_softc *sc = vd->cookie; 1879 paddr_t pa; 1880 1881 if (sc->sc_mode == WSDISPLAYIO_MODE_DUMBFB) { 1882 /* 1883 *'regular' framebuffer mmap()ing 1884 */ 1885 if (offset < (sc->memsize * 1024)) { 1886 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, 1887 offset, prot, BUS_SPACE_MAP_LINEAR); 1888 return pa; 1889 } 1890 } else if (sc->sc_mode == WSDISPLAYIO_MODE_MAPPED) { 1891 /* 1892 * restrict all other mappings to processes with superuser 1893 * privileges 1894 */ 1895 if (kauth_authorize_machdep(kauth_cred_get(), 1896 KAUTH_MACHDEP_UNMANAGEDMEM, 1897 NULL, NULL, NULL, NULL) != 0) { 1898 return -1; 1899 } 1900 if ((offset >= sc->sc_aperbase) && 1901 (offset < (sc->sc_aperbase + sc->sc_apersize))) { 1902 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1903 BUS_SPACE_MAP_LINEAR); 1904 return pa; 1905 } 1906 1907 if ((offset >= sc->sc_regbase) && 1908 (offset < (sc->sc_regbase + sc->sc_regsize))) { 1909 pa = bus_space_mmap(sc->sc_regt, offset, 0, prot, 1910 BUS_SPACE_MAP_LINEAR); 1911 return pa; 1912 } 1913 1914 if ((offset >= sc->sc_rom.vb_base) && 1915 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 1916 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1917 BUS_SPACE_MAP_LINEAR); 1918 return pa; 1919 } 1920 1921 #ifdef PCI_MAGIC_IO_RANGE 1922 if ((offset >= PCI_MAGIC_IO_RANGE) && 1923 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 1924 return bus_space_mmap(sc->sc_iot, 1925 offset - PCI_MAGIC_IO_RANGE, 0, prot, 0); 1926 } 1927 #endif 1928 } 1929 return -1; 1930 } 1931 1932 #if 0 1933 static int 1934 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1935 { 1936 1937 return 0; 1938 } 1939 #endif 1940 1941 void 1942 machfb_blank(struct mach64_softc *sc, int blank) 1943 { 1944 uint32_t reg; 1945 1946 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1947 1948 switch (blank) 1949 { 1950 case 0: 1951 reg = regr(sc, CRTC_GEN_CNTL); 1952 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1953 sc->sc_blanked = 0; 1954 break; 1955 case 1: 1956 reg = regr(sc, CRTC_GEN_CNTL); 1957 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1958 sc->sc_blanked = 1; 1959 break; 1960 default: 1961 break; 1962 } 1963 } 1964
Indexes created Thu Oct 02 14:10:14 GMT 2025