machfb.c revision 1.97
1 /* $NetBSD: machfb.c,v 1.97 2019/02/05 06:12:39 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.97 2019/02/05 06:12:39 mrg Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #include <dev/wscons/wsdisplayvar.h> 58 59 #include <dev/wscons/wsconsio.h> 60 #include <dev/wsfont/wsfont.h> 61 #include <dev/rasops/rasops.h> 62 #include <dev/pci/wsdisplay_pci.h> 63 64 #include <dev/wscons/wsdisplay_vconsvar.h> 65 #include <dev/wscons/wsdisplay_glyphcachevar.h> 66 67 #include "opt_wsemul.h" 68 #include "opt_machfb.h" 69 #include "opt_glyphcache.h" 70 71 #define MACH64_REG_SIZE 0x800 72 #define MACH64_REG_OFF 0x7ff800 73 74 #define NBARS 3 /* number of Mach64 PCI BARs */ 75 76 struct vga_bar { 77 bus_addr_t vb_base; 78 bus_size_t vb_size; 79 pcireg_t vb_type; 80 int vb_flags; 81 }; 82 83 struct mach64_softc { 84 device_t sc_dev; 85 pci_chipset_tag_t sc_pc; 86 pcitag_t sc_pcitag; 87 88 struct vga_bar sc_bars[NBARS]; 89 struct vga_bar sc_rom; 90 91 #define sc_aperbase sc_bars[0].vb_base 92 #define sc_apersize sc_bars[0].vb_size 93 94 #define sc_iobase sc_bars[1].vb_base 95 #define sc_iosize sc_bars[1].vb_size 96 97 #define sc_regbase sc_bars[2].vb_base 98 #define sc_regsize sc_bars[2].vb_size 99 100 bus_space_tag_t sc_regt; 101 bus_space_tag_t sc_memt; 102 bus_space_tag_t sc_iot; 103 bus_space_handle_t sc_regh; 104 bus_space_handle_t sc_memh; 105 #if 0 106 void *sc_aperture; /* mapped aperture vaddr */ 107 void *sc_registers; /* mapped registers vaddr */ 108 #endif 109 uint32_t sc_nbus, sc_ndev, sc_nfunc; 110 size_t memsize; 111 int memtype; 112 113 int sc_mode; 114 int sc_bg; 115 int sc_locked; 116 117 int has_dsp; 118 int bits_per_pixel; 119 int max_x; 120 int max_y; 121 int virt_x; 122 int virt_y; 123 int color_depth; 124 125 int mem_freq; 126 int ramdac_freq; 127 int ref_freq; 128 int vclk_freq; 129 130 int ref_div; 131 int log2_vclk_post_div; 132 int vclk_post_div; 133 int vclk_fb_div; 134 int mclk_post_div; 135 int mclk_fb_div; 136 int sc_clock; /* which clock to use */ 137 int minref, m; 138 139 struct videomode *sc_my_mode; 140 int sc_edid_size; 141 uint8_t sc_edid_data[1024]; 142 struct edid_info sc_ei; 143 144 u_char sc_cmap_red[256]; 145 u_char sc_cmap_green[256]; 146 u_char sc_cmap_blue[256]; 147 int sc_dacw, sc_blanked, sc_console; 148 struct vcons_data vd; 149 struct wsdisplay_accessops sc_accessops; 150 glyphcache sc_gc; 151 }; 152 153 struct mach64_crtcregs { 154 uint32_t h_total_disp; 155 uint32_t h_sync_strt_wid; 156 uint32_t v_total_disp; 157 uint32_t v_sync_strt_wid; 158 uint32_t gen_cntl; 159 uint32_t clock_cntl; 160 uint32_t color_depth; 161 uint32_t dot_clock; 162 }; 163 164 static struct { 165 uint16_t chip_id; 166 uint32_t ramdac_freq; 167 } const mach64_info[] = { 168 { PCI_PRODUCT_ATI_MACH64_GX, 135000 }, 169 { PCI_PRODUCT_ATI_MACH64_CX, 135000 }, 170 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 171 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 172 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 173 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 174 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 175 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 176 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 180 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 181 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 184 #if 0 185 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 186 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 188 #endif 189 { PCI_PRODUCT_ATI_RAGE_L_MOB_M1_PCI, 230000 }, 190 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 192 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 193 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 194 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 195 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 196 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 197 }; 198 199 static int mach64_chip_id, mach64_chip_rev; 200 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 201 202 static const char *mach64_gx_memtype_names[] = { 203 "DRAM", "VRAM", "VRAM", "DRAM", 204 "DRAM", "VRAM", "VRAM", "(unknown type)" 205 }; 206 207 static const char *mach64_memtype_names[] = { 208 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 209 "(unknown type)" 210 }; 211 212 extern const u_char rasops_cmap[768]; 213 214 static int mach64_match(device_t, cfdata_t, void *); 215 static void mach64_attach(device_t, device_t, void *); 216 217 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, 218 mach64_attach, NULL, NULL); 219 220 static void mach64_init(struct mach64_softc *); 221 static int mach64_get_memsize(struct mach64_softc *); 222 static int mach64_get_max_ramdac(struct mach64_softc *); 223 224 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 225 226 static int mach64_calc_crtcregs(struct mach64_softc *, 227 struct mach64_crtcregs *, 228 struct videomode *); 229 static void mach64_set_crtcregs(struct mach64_softc *, 230 struct mach64_crtcregs *); 231 232 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 233 static void mach64_set_dsp(struct mach64_softc *); 234 static void mach64_set_pll(struct mach64_softc *, int); 235 static void mach64_reset_engine(struct mach64_softc *); 236 static void mach64_init_engine(struct mach64_softc *); 237 #if 0 238 static void mach64_adjust_frame(struct mach64_softc *, int, int); 239 #endif 240 static void mach64_init_lut(struct mach64_softc *); 241 242 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 243 static int mach64_is_console(struct mach64_softc *); 244 245 static void mach64_cursor(void *, int, int, int); 246 #if 0 247 static int mach64_mapchar(void *, int, u_int *); 248 #endif 249 static void mach64_putchar_mono(void *, int, int, u_int, long); 250 static void mach64_putchar_aa8(void *, int, int, u_int, long); 251 static void mach64_copycols(void *, int, int, int, int); 252 static void mach64_erasecols(void *, int, int, int, long); 253 static void mach64_copyrows(void *, int, int, int); 254 static void mach64_eraserows(void *, int, int, long); 255 static void mach64_clearscreen(struct mach64_softc *); 256 257 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 258 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 259 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 260 uint8_t, uint8_t); 261 static void mach64_bitblt(void *, int, int, int, int, int, int, int); 262 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 263 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 264 uint32_t, uint32_t); 265 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 266 #if 0 267 static void mach64_showpal(struct mach64_softc *); 268 #endif 269 270 static void machfb_blank(struct mach64_softc *, int); 271 static int machfb_drm_print(void *, const char *); 272 273 static struct wsscreen_descr mach64_defaultscreen = { 274 "default", 275 80, 30, 276 NULL, 277 8, 16, 278 WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE 279 | WSSCREEN_RESIZE , 280 NULL 281 }; 282 283 static const struct wsscreen_descr *_mach64_scrlist[] = { 284 &mach64_defaultscreen, 285 }; 286 287 static struct wsscreen_list mach64_screenlist = { 288 __arraycount(_mach64_scrlist), 289 _mach64_scrlist 290 }; 291 292 static int mach64_ioctl(void *, void *, u_long, void *, int, 293 struct lwp *); 294 static paddr_t mach64_mmap(void *, void *, off_t, int); 295 296 static struct vcons_screen mach64_console_screen; 297 298 /* 299 * Inline functions for getting access to register aperture. 300 */ 301 302 static inline uint32_t 303 regr(struct mach64_softc *sc, uint32_t index) 304 { 305 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index + 0x400); 306 } 307 308 static inline uint8_t 309 regrb(struct mach64_softc *sc, uint32_t index) 310 { 311 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index + 0x400); 312 } 313 314 static inline void 315 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 316 { 317 bus_space_write_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 318 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 319 BUS_SPACE_BARRIER_WRITE); 320 } 321 322 static inline void 323 regws(struct mach64_softc *sc, uint32_t index, uint32_t data) 324 { 325 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, index + 0x400, data); 326 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 4, 327 BUS_SPACE_BARRIER_WRITE); 328 } 329 330 static inline void 331 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 332 { 333 bus_space_write_1(sc->sc_regt, sc->sc_regh, index + 0x400, data); 334 bus_space_barrier(sc->sc_regt, sc->sc_regh, index + 0x400, 1, 335 BUS_SPACE_BARRIER_WRITE); 336 } 337 338 static inline void 339 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 340 { 341 uint32_t reg; 342 343 reg = regr(sc, CLOCK_CNTL); 344 reg |= PLL_WR_EN; 345 regw(sc, CLOCK_CNTL, reg); 346 reg &= ~(PLL_ADDR | PLL_DATA); 347 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 348 reg |= data << PLL_DATA_SHIFT; 349 reg |= CLOCK_STROBE; 350 regw(sc, CLOCK_CNTL, reg); 351 reg &= ~PLL_WR_EN; 352 regw(sc, CLOCK_CNTL, reg); 353 } 354 355 static inline uint8_t 356 regrb_pll(struct mach64_softc *sc, uint32_t index) 357 { 358 359 regwb(sc, CLOCK_CNTL + 1, index << 2); 360 return regrb(sc, CLOCK_CNTL + 2); 361 } 362 363 static inline void 364 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 365 { 366 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 367 continue; 368 } 369 370 static inline void 371 wait_for_idle(struct mach64_softc *sc) 372 { 373 wait_for_fifo(sc, 16); 374 while ((regr(sc, GUI_STAT) & 1) != 0) 375 continue; 376 } 377 378 static int 379 mach64_match(device_t parent, cfdata_t match, void *aux) 380 { 381 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 382 int i; 383 384 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 385 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 386 return 0; 387 388 for (i = 0; i < __arraycount(mach64_info); i++) 389 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 390 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 391 mach64_chip_rev = PCI_REVISION(pa->pa_class); 392 return 100; 393 } 394 395 return 0; 396 } 397 398 static void 399 mach64_attach(device_t parent, device_t self, void *aux) 400 { 401 struct mach64_softc *sc = device_private(self); 402 struct pci_attach_args *pa = aux; 403 struct rasops_info *ri; 404 prop_data_t edid_data; 405 const struct videomode *mode = NULL; 406 int bar, id, expected_id; 407 int is_gx; 408 const char **memtype_names; 409 struct wsemuldisplaydev_attach_args aa; 410 long defattr; 411 int setmode = 0, width, height; 412 pcireg_t screg; 413 uint32_t reg; 414 const pcireg_t enables = PCI_COMMAND_MEM_ENABLE; 415 int use_mmio = FALSE; 416 417 sc->sc_dev = self; 418 sc->sc_pc = pa->pa_pc; 419 sc->sc_pcitag = pa->pa_tag; 420 sc->sc_dacw = -1; 421 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 422 sc->sc_nbus = pa->pa_bus; 423 sc->sc_ndev = pa->pa_device; 424 sc->sc_nfunc = pa->pa_function; 425 sc->sc_locked = 0; 426 sc->sc_iot = pa->pa_iot; 427 sc->sc_accessops.ioctl = mach64_ioctl; 428 sc->sc_accessops.mmap = mach64_mmap; 429 430 pci_aprint_devinfo(pa, "Graphics processor"); 431 #ifdef MACHFB_DEBUG 432 printf(prop_dictionary_externalize(device_properties(self))); 433 #endif 434 435 /* enable memory access */ 436 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 437 if ((screg & enables) != enables) { 438 screg |= enables; 439 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 440 PCI_COMMAND_STATUS_REG, screg); 441 } 442 for (bar = 0; bar < NBARS; bar++) { 443 reg = PCI_MAPREG_START + (bar * 4); 444 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 445 sc->sc_pcitag, reg); 446 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 447 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 448 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 449 } 450 aprint_debug_dev(sc->sc_dev, "aperture size %08x\n", 451 (uint32_t)sc->sc_apersize); 452 453 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 454 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 455 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 456 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 457 sc->sc_memt = pa->pa_memt; 458 459 /* use MMIO register aperture if available */ 460 if ((sc->sc_regbase != 0) && (sc->sc_regbase != 0xffffffff)) { 461 if (pci_mapreg_map(pa, MACH64_BAR_MMIO, PCI_MAPREG_TYPE_MEM, 462 0, &sc->sc_regt, &sc->sc_regh, &sc->sc_regbase, 463 &sc->sc_regsize) == 0) { 464 465 /* 466 * the MMIO aperture maps both 1KB register blocks, but 467 * all register offsets are relative to the 2nd one so 468 * for now fix this up in MACH64_REG_OFF and the access 469 * functions 470 */ 471 aprint_normal_dev(sc->sc_dev, "using MMIO aperture\n"); 472 use_mmio = TRUE; 473 } 474 } 475 if (!use_mmio) { 476 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, 477 sc->sc_apersize, BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 478 panic("%s: failed to map aperture", 479 device_xname(sc->sc_dev)); 480 } 481 482 sc->sc_regt = sc->sc_memt; 483 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 484 MACH64_REG_SIZE, &sc->sc_regh); 485 } 486 487 mach64_init(sc); 488 489 aprint_normal_dev(sc->sc_dev, 490 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 491 (u_int)(sc->sc_apersize / (1024 * 1024)), 492 (u_int)sc->sc_aperbase, (u_int)(sc->sc_regsize / 1024), 493 (u_int)sc->sc_regbase); 494 495 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 496 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 497 498 prop_dictionary_get_uint32(device_properties(self), "width", &width); 499 prop_dictionary_get_uint32(device_properties(self), "height", &height); 500 501 memset(&sc->sc_ei, 0, sizeof(sc->sc_ei)); 502 if ((edid_data = prop_dictionary_get(device_properties(self), "EDID")) 503 != NULL) { 504 505 sc->sc_edid_size = uimin(1024, prop_data_size(edid_data)); 506 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 507 memcpy(sc->sc_edid_data, prop_data_data_nocopy(edid_data), 508 sc->sc_edid_size); 509 510 edid_parse(sc->sc_edid_data, &sc->sc_ei); 511 512 #ifdef MACHFB_DEBUG 513 edid_print(&sc->sc_ei); 514 #endif 515 } 516 517 is_gx = 0; 518 switch(mach64_chip_id) { 519 case PCI_PRODUCT_ATI_MACH64_GX: 520 case PCI_PRODUCT_ATI_MACH64_CX: 521 is_gx = 1; 522 /* FALLTHROUGH */ 523 case PCI_PRODUCT_ATI_MACH64_CT: 524 sc->has_dsp = 0; 525 break; 526 case PCI_PRODUCT_ATI_MACH64_VT: 527 case PCI_PRODUCT_ATI_RAGE_II: 528 if((mach64_chip_rev & 0x07) == 0) { 529 sc->has_dsp = 0; 530 break; 531 } 532 /* FALLTHROUGH */ 533 default: 534 sc->has_dsp = 1; 535 } 536 537 memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names; 538 539 sc->memsize = mach64_get_memsize(sc); 540 541 if(is_gx) 542 sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07; 543 else 544 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 545 546 /* 547 * XXX is there any way to calculate reference frequency from 548 * known values? 549 */ 550 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 551 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 552 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 553 aprint_normal_dev(sc->sc_dev, "ref_freq=29.498MHz\n"); 554 sc->ref_freq = 29498; 555 } else 556 sc->ref_freq = 14318; 557 558 reg = regr(sc, CLOCK_CNTL); 559 aprint_debug("CLOCK_CNTL: %08x\n", reg); 560 sc->sc_clock = reg & 3; 561 aprint_debug("using clock %d\n", sc->sc_clock); 562 563 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 564 aprint_error("ref_div: %d\n", sc->ref_div); 565 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 566 aprint_error("mclk_fb_div: %d\n", sc->mclk_fb_div); 567 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 568 (sc->ref_div * 2); 569 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 570 (sc->mem_freq * sc->ref_div); 571 sc->ramdac_freq = mach64_get_max_ramdac(sc); 572 { 573 sc->minref = sc->ramdac_freq / 510; 574 sc->m = sc->ref_freq / sc->minref; 575 aprint_error("minref: %d m: %d\n", sc->minref, sc->m); 576 } 577 aprint_normal_dev(sc->sc_dev, 578 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 579 (u_long)sc->memsize, 580 memtype_names[sc->memtype], 581 sc->mem_freq / 1000, sc->mem_freq % 1000, 582 sc->ramdac_freq / 1000); 583 584 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 585 switch(mach64_chip_id) { 586 case PCI_PRODUCT_ATI_MACH64_GX: 587 expected_id = 0x00d7; 588 break; 589 case PCI_PRODUCT_ATI_MACH64_CX: 590 expected_id = 0x0057; 591 break; 592 default: 593 /* Most chip IDs match their PCI product ID. */ 594 expected_id = mach64_chip_id; 595 } 596 597 if (id != expected_id) { 598 aprint_error_dev(sc->sc_dev, 599 "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id); 600 return; 601 } 602 603 sc->sc_console = mach64_is_console(sc); 604 aprint_debug("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 605 606 #define MODE_IS_VALID(m) ((sc->ramdac_freq >= (m)->dot_clock) && \ 607 ((m)->hdisplay <= 11280)) 608 609 /* no mode setting support on ancient chips with external clocks */ 610 setmode = 0; 611 if (!is_gx) { 612 /* 613 * Now pick a mode. 614 */ 615 if ((sc->sc_ei.edid_preferred_mode != NULL)) { 616 struct videomode *m = sc->sc_ei.edid_preferred_mode; 617 if (MODE_IS_VALID(m)) { 618 memcpy(&default_mode, m, 619 sizeof(struct videomode)); 620 setmode = 1; 621 } else { 622 aprint_error_dev(sc->sc_dev, 623 "unable to use preferred mode\n"); 624 } 625 } 626 /* 627 * if we can't use the preferred mode go look for the 628 * best one we can support 629 */ 630 if (setmode == 0) { 631 struct videomode *m = sc->sc_ei.edid_modes; 632 633 mode = NULL; 634 sort_modes(sc->sc_ei.edid_modes, 635 &sc->sc_ei.edid_preferred_mode, 636 sc->sc_ei.edid_nmodes); 637 for (int n = 0; n < sc->sc_ei.edid_nmodes; n++) 638 if (MODE_IS_VALID(&m[n])) { 639 mode = &m[n]; 640 break; 641 } 642 if (mode != NULL) { 643 memcpy(&default_mode, mode, 644 sizeof(struct videomode)); 645 setmode = 1; 646 } 647 } 648 /* got nothing? try to pick one based on firmware parameters */ 649 if (setmode == 0 && width > 0 && height > 0) { 650 /* no EDID data? */ 651 mode = pick_mode_by_ref(width, height, 60); 652 memcpy(&default_mode, mode, sizeof(struct videomode)); 653 setmode = 1; 654 } 655 /* still nothing? Grab the default */ 656 if (setmode == 0) { 657 mode = pick_mode_by_ref(1024, 768, 60); 658 memcpy(&default_mode, mode, sizeof(struct videomode)); 659 setmode = 1; 660 } 661 } else { 662 /* make sure my_mode points at something sensible */ 663 mach64_get_mode(sc, &default_mode); 664 if (default_mode.dot_clock == 0) { 665 memcpy(&default_mode, pick_mode_by_ref(width, height, 60), 666 sizeof(default_mode)); 667 } 668 } 669 sc->sc_my_mode = &default_mode; 670 671 sc->bits_per_pixel = 8; 672 sc->virt_x = sc->sc_my_mode->hdisplay; 673 sc->virt_y = sc->sc_my_mode->vdisplay; 674 sc->max_x = sc->virt_x - 1; 675 sc->max_y = (sc->memsize * 1024) / 676 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 677 678 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 679 680 mach64_init_engine(sc); 681 682 if (setmode) 683 mach64_modeswitch(sc, sc->sc_my_mode); 684 685 aprint_normal_dev(sc->sc_dev, 686 "initial resolution %dx%d at %d bpp\n", 687 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 688 sc->bits_per_pixel); 689 690 wsfont_init(); 691 692 #ifdef GLYPHCACHE_DEBUG 693 /* shrink the screen so we can see part of the glyph cache */ 694 sc->sc_my_mode->vdisplay -= 200; 695 #endif 696 697 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &sc->sc_accessops); 698 sc->vd.init_screen = mach64_init_screen; 699 sc->vd.show_screen_cookie = &sc->sc_gc; 700 sc->vd.show_screen_cb = glyphcache_adapt; 701 702 sc->sc_gc.gc_bitblt = mach64_bitblt; 703 sc->sc_gc.gc_blitcookie = sc; 704 sc->sc_gc.gc_rop = MIX_SRC; 705 706 ri = &mach64_console_screen.scr_ri; 707 if (sc->sc_console) { 708 709 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 710 &defattr); 711 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 712 713 mach64_defaultscreen.textops = &ri->ri_ops; 714 mach64_defaultscreen.capabilities = ri->ri_caps; 715 mach64_defaultscreen.nrows = ri->ri_rows; 716 mach64_defaultscreen.ncols = ri->ri_cols; 717 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 718 ((sc->memsize * 1024) / sc->sc_my_mode->hdisplay) - 719 sc->sc_my_mode->vdisplay - 5, 720 sc->sc_my_mode->hdisplay, 721 ri->ri_font->fontwidth, 722 ri->ri_font->fontheight, 723 defattr); 724 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 725 } else { 726 /* 727 * since we're not the console we can postpone the rest 728 * until someone actually allocates a screen for us 729 */ 730 mach64_modeswitch(sc, sc->sc_my_mode); 731 if (mach64_console_screen.scr_ri.ri_rows == 0) { 732 /* do some minimal setup to avoid weirdnesses later */ 733 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 734 &defattr); 735 } else 736 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 737 738 glyphcache_init(&sc->sc_gc, sc->sc_my_mode->vdisplay + 5, 739 ((sc->memsize * 1024) / sc->sc_my_mode->hdisplay) - 740 sc->sc_my_mode->vdisplay - 5, 741 sc->sc_my_mode->hdisplay, 742 ri->ri_font->fontwidth, 743 ri->ri_font->fontheight, 744 defattr); 745 } 746 747 sc->sc_bg = mach64_console_screen.scr_ri.ri_devcmap[WS_DEFAULT_BG]; 748 mach64_clearscreen(sc); 749 mach64_init_lut(sc); 750 751 if (sc->sc_console) 752 vcons_replay_msgbuf(&mach64_console_screen); 753 754 machfb_blank(sc, 0); /* unblank the screen */ 755 756 aa.console = sc->sc_console; 757 aa.scrdata = &mach64_screenlist; 758 aa.accessops = &sc->sc_accessops; 759 aa.accesscookie = &sc->vd; 760 761 config_found(self, &aa, wsemuldisplaydevprint); 762 #if 0 763 /* XXX 764 * turns out some firmware doesn't turn these back on when needed 765 * so we need to turn them off only when mapping vram in 766 * WSDISPLAYIO_MODE_DUMB would overlap ( unlikely but far from 767 * impossible ) 768 */ 769 if (use_mmio) { 770 /* 771 * Now that we took over, turn off the aperture registers if we 772 * don't use them. Can't do this earlier since on some hardware 773 * we use firmware calls as early console output which may in 774 * turn try to access these registers. 775 */ 776 reg = regr(sc, BUS_CNTL); 777 aprint_debug_dev(sc->sc_dev, "BUS_CNTL: %08x\n", reg); 778 reg |= BUS_APER_REG_DIS; 779 regw(sc, BUS_CNTL, reg); 780 } 781 #endif 782 config_found_ia(self, "drm", aux, machfb_drm_print); 783 } 784 785 static int 786 machfb_drm_print(void *aux, const char *pnp) 787 { 788 if (pnp) 789 aprint_normal("direct rendering for %s", pnp); 790 return (UNSUPP); 791 } 792 793 static void 794 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 795 long *defattr) 796 { 797 struct mach64_softc *sc = cookie; 798 struct rasops_info *ri = &scr->scr_ri; 799 800 ri->ri_depth = sc->bits_per_pixel; 801 ri->ri_width = sc->sc_my_mode->hdisplay; 802 ri->ri_height = sc->sc_my_mode->vdisplay; 803 ri->ri_stride = ri->ri_width; 804 ri->ri_flg = RI_CENTER | RI_FULLCLEAR; 805 if (ri->ri_depth == 8) 806 ri->ri_flg |= RI_8BIT_IS_RGB | RI_ENABLE_ALPHA | 807 RI_PREFER_ALPHA; 808 809 #ifdef VCONS_DRAW_INTR 810 scr->scr_flags |= VCONS_DONT_READ; 811 #endif 812 scr->scr_flags |= VCONS_LOADFONT; 813 814 rasops_init(ri, 0, 0); 815 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE | 816 WSSCREEN_RESIZE; 817 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 818 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 819 820 /* enable acceleration */ 821 ri->ri_hw = scr; 822 ri->ri_ops.copyrows = mach64_copyrows; 823 ri->ri_ops.copycols = mach64_copycols; 824 ri->ri_ops.eraserows = mach64_eraserows; 825 ri->ri_ops.erasecols = mach64_erasecols; 826 ri->ri_ops.cursor = mach64_cursor; 827 if (FONT_IS_ALPHA(ri->ri_font)) { 828 ri->ri_ops.putchar = mach64_putchar_aa8; 829 } else 830 ri->ri_ops.putchar = mach64_putchar_mono; 831 } 832 833 static void 834 mach64_init(struct mach64_softc *sc) 835 { 836 sc->sc_blanked = 0; 837 } 838 839 static int 840 mach64_get_memsize(struct mach64_softc *sc) 841 { 842 int tmp, memsize; 843 int mem_tab[] = { 844 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 845 }; 846 tmp = regr(sc, MEM_CNTL); 847 #ifdef DIAGNOSTIC 848 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 849 #endif 850 if (sc->has_dsp) { 851 tmp &= 0x0000000f; 852 if (tmp < 8) 853 memsize = (tmp + 1) * 512; 854 else if (tmp < 12) 855 memsize = (tmp - 3) * 1024; 856 else 857 memsize = (tmp - 7) * 2048; 858 } else { 859 memsize = mem_tab[tmp & 0x07]; 860 } 861 862 return memsize; 863 } 864 865 static int 866 mach64_get_max_ramdac(struct mach64_softc *sc) 867 { 868 int i; 869 870 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 871 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 872 (mach64_chip_rev & 0x07)) 873 return 170000; 874 875 for (i = 0; i < __arraycount(mach64_info); i++) 876 if (mach64_chip_id == mach64_info[i].chip_id) 877 return mach64_info[i].ramdac_freq; 878 879 if (sc->bits_per_pixel == 8) 880 return 135000; 881 else 882 return 80000; 883 } 884 885 static void 886 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 887 { 888 struct mach64_crtcregs crtc; 889 890 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 891 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 892 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 893 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 894 895 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 896 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 897 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 898 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 899 mode->hsync_start; 900 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 901 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 902 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 903 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 904 905 #ifdef MACHFB_DEBUG 906 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 907 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 908 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 909 #endif 910 } 911 912 static int 913 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 914 struct videomode *mode) 915 { 916 917 if (mode->dot_clock > sc->ramdac_freq) 918 /* Clock too high. */ 919 return 1; 920 921 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 922 ((mode->htotal >> 3) - 1); 923 crtc->h_sync_strt_wid = 924 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 925 ((mode->hsync_start >> 3) - 1); 926 927 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 928 (mode->vtotal - 1); 929 crtc->v_sync_strt_wid = 930 ((mode->vsync_end - mode->vsync_start) << 16) | 931 (mode->vsync_start - 1); 932 933 if (mode->flags & VID_NVSYNC) 934 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 935 936 switch (sc->bits_per_pixel) { 937 case 8: 938 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 939 break; 940 case 16: 941 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 942 break; 943 case 32: 944 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 945 break; 946 } 947 948 crtc->gen_cntl = 0; 949 if (mode->flags & VID_INTERLACE) 950 crtc->gen_cntl |= CRTC_INTERLACE_EN; 951 952 if (mode->flags & VID_CSYNC) 953 crtc->gen_cntl |= CRTC_CSYNC_EN; 954 955 crtc->dot_clock = mode->dot_clock; 956 957 return 0; 958 } 959 960 static void 961 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 962 { 963 964 mach64_set_pll(sc, crtc->dot_clock); 965 966 if (sc->has_dsp) 967 mach64_set_dsp(sc); 968 969 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 970 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 971 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 972 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 973 974 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 975 976 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 977 978 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 979 /* XXX this unconditionally enables composite sync on SPARC */ 980 #ifdef __sparc__ 981 CRTC_CSYNC_EN | 982 #endif 983 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 984 } 985 986 static int 987 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 988 { 989 struct mach64_crtcregs crtc; 990 991 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 992 993 if (mach64_calc_crtcregs(sc, &crtc, mode)) 994 return 1; 995 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 996 if (crtc.dot_clock == 0) { 997 aprint_error("%s: preposterous dot clock (%d)\n", 998 device_xname(sc->sc_dev), crtc.dot_clock); 999 return 1; 1000 } 1001 mach64_set_crtcregs(sc, &crtc); 1002 return 0; 1003 } 1004 1005 static void 1006 mach64_reset_engine(struct mach64_softc *sc) 1007 { 1008 1009 /* Reset engine.*/ 1010 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1011 1012 /* Enable engine. */ 1013 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1014 1015 /* Ensure engine is not locked up by clearing any FIFO or 1016 host errors. */ 1017 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1018 BUS_FIFO_ERR_ACK); 1019 } 1020 1021 static void 1022 mach64_init_engine(struct mach64_softc *sc) 1023 { 1024 uint32_t pitch_value; 1025 1026 pitch_value = sc->virt_x; 1027 1028 if (sc->bits_per_pixel == 24) 1029 pitch_value *= 3; 1030 1031 mach64_reset_engine(sc); 1032 1033 wait_for_fifo(sc, 14); 1034 1035 regw(sc, CONTEXT_MASK, 0xffffffff); 1036 1037 regw(sc, DST_OFF_PITCH, (pitch_value >> 3) << 22); 1038 1039 /* make sure the visible area starts where we're going to draw */ 1040 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1041 1042 regw(sc, DST_Y_X, 0); 1043 regw(sc, DST_HEIGHT, 0); 1044 regw(sc, DST_BRES_ERR, 0); 1045 regw(sc, DST_BRES_INC, 0); 1046 regw(sc, DST_BRES_DEC, 0); 1047 1048 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1049 DST_Y_TOP_TO_BOTTOM); 1050 1051 regw(sc, SRC_OFF_PITCH, (pitch_value >> 3) << 22); 1052 1053 regw(sc, SRC_Y_X, 0); 1054 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1055 regw(sc, SRC_Y_X_START, 0); 1056 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1057 1058 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1059 1060 wait_for_fifo(sc, 13); 1061 regw(sc, HOST_CNTL, 0); 1062 1063 regw(sc, PAT_REG0, 0); 1064 regw(sc, PAT_REG1, 0); 1065 regw(sc, PAT_CNTL, 0); 1066 1067 regw(sc, SC_LEFT, 0); 1068 regw(sc, SC_TOP, 0); 1069 regw(sc, SC_BOTTOM, 0x3fff); 1070 regw(sc, SC_RIGHT, pitch_value - 1); 1071 1072 regw(sc, DP_BKGD_CLR, WS_DEFAULT_BG); 1073 regw(sc, DP_FRGD_CLR, WS_DEFAULT_FG); 1074 regw(sc, DP_WRITE_MASK, 0xffffffff); 1075 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1076 1077 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1078 1079 wait_for_fifo(sc, 3); 1080 regw(sc, CLR_CMP_CLR, 0); 1081 regw(sc, CLR_CMP_MASK, 0xffffffff); 1082 regw(sc, CLR_CMP_CNTL, 0); 1083 1084 wait_for_fifo(sc, 3); 1085 switch (sc->bits_per_pixel) { 1086 case 8: 1087 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP); 1088 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1089 /* We want 8 bit per channel */ 1090 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1091 break; 1092 case 32: 1093 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP); 1094 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1095 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1096 break; 1097 } 1098 regw(sc, DP_WRITE_MASK, 0xff); 1099 1100 wait_for_fifo(sc, 5); 1101 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1102 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1103 1104 wait_for_idle(sc); 1105 } 1106 1107 #if 0 1108 static void 1109 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1110 { 1111 int offset; 1112 1113 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1114 1115 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1116 offset); 1117 } 1118 #endif 1119 1120 static void 1121 mach64_set_dsp(struct mach64_softc *sc) 1122 { 1123 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1124 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1125 uint32_t xclks_per_qw, xclks_per_qw_m, y; 1126 uint32_t fifo_off, fifo_on; 1127 1128 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1129 1130 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1131 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1132 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1133 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1134 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1135 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1136 dsp_loop_latency = 0; 1137 fifo_depth = 24; 1138 } else { 1139 dsp_loop_latency = 2; 1140 fifo_depth = 32; 1141 } 1142 1143 dsp_precision = 0; 1144 1145 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1146 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1147 1148 xclks_per_qw_m = (sc->mem_freq * 64 << 4) / 1149 (sc->vclk_freq * sc->bits_per_pixel); 1150 printf("xclks_per_qw %d %d\n", xclks_per_qw >> 7, xclks_per_qw_m); 1151 y = (xclks_per_qw * fifo_depth) >> 11; 1152 1153 while (y) { 1154 y >>= 1; 1155 dsp_precision++; 1156 } 1157 dsp_precision -= 5; 1158 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1159 1160 switch (sc->memtype) { 1161 case DRAM: 1162 case EDO_DRAM: 1163 case PSEUDO_EDO: 1164 if (sc->memsize > 1024) { 1165 page_size = 9; 1166 dsp_loop_latency += 6; 1167 } else { 1168 page_size = 10; 1169 if (sc->memtype == DRAM) 1170 dsp_loop_latency += 8; 1171 else 1172 dsp_loop_latency += 7; 1173 } 1174 break; 1175 case SDRAM: 1176 if (sc->memsize > 1024) { 1177 page_size = 8; 1178 dsp_loop_latency += 8; 1179 } else { 1180 page_size = 10; 1181 dsp_loop_latency += 9; 1182 } 1183 break; 1184 case SGRAM: 1185 page_size = 8; 1186 dsp_loop_latency = 8; 1187 break; 1188 default: 1189 page_size = 10; 1190 dsp_loop_latency += 9; 1191 break; 1192 } 1193 1194 if (xclks_per_qw >= (page_size << 11)) 1195 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1196 else 1197 fifo_on = (3 * page_size + 2) << 6; 1198 1199 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1200 dsp_on = fifo_on >> dsp_precision; 1201 dsp_off = fifo_off >> dsp_precision; 1202 1203 #ifdef MACHFB_DEBUG 1204 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1205 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1206 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1207 "mclk_post_div = %d, vclk_post_div = %d\n", 1208 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1209 sc->mclk_fb_div, sc->vclk_fb_div, 1210 sc->mclk_post_div, sc->vclk_post_div); 1211 #endif 1212 1213 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1214 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1215 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1216 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1217 } 1218 1219 static void 1220 mach64_set_pll(struct mach64_softc *sc, int clock) 1221 { 1222 uint32_t q, clockreg; 1223 int clockshift = sc->sc_clock << 1; 1224 uint8_t reg, vclk_ctl; 1225 1226 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1227 #ifdef MACHFB_DEBUG 1228 printf("q = %d\n", q); 1229 #endif 1230 if (q > 25500) { 1231 aprint_error_dev(sc->sc_dev, "Warning: q > 25500\n"); 1232 q = 25500; 1233 sc->vclk_post_div = 1; 1234 sc->log2_vclk_post_div = 0; 1235 } else if (q > 12750) { 1236 sc->vclk_post_div = 1; 1237 sc->log2_vclk_post_div = 0; 1238 } else if (q > 6350) { 1239 sc->vclk_post_div = 2; 1240 sc->log2_vclk_post_div = 1; 1241 } else if (q > 3150) { 1242 sc->vclk_post_div = 4; 1243 sc->log2_vclk_post_div = 2; 1244 } else if (q >= 1600) { 1245 sc->vclk_post_div = 8; 1246 sc->log2_vclk_post_div = 3; 1247 } else { 1248 aprint_error_dev(sc->sc_dev, "Warning: q < 1600\n"); 1249 sc->vclk_post_div = 8; 1250 sc->log2_vclk_post_div = 3; 1251 } 1252 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1253 aprint_error("post_div: %d log2_post_div: %d mclk_div: %d\n", 1254 sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1255 1256 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1257 aprint_debug("vclk_ctl: %02x\n", vclk_ctl); 1258 vclk_ctl |= PLL_VCLK_RESET; 1259 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1260 1261 aprint_error("target: %d output: %d\n", clock, 1262 (2 * sc->ref_freq * sc->vclk_fb_div) / 1263 (sc->ref_div * sc->vclk_post_div)); 1264 1265 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1266 reg = regrb_pll(sc, VCLK_POST_DIV); 1267 reg &= ~(3 << clockshift); 1268 reg |= (sc->log2_vclk_post_div << clockshift); 1269 regwb_pll(sc, VCLK_POST_DIV, reg); 1270 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1271 1272 vclk_ctl &= ~PLL_VCLK_RESET; 1273 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1274 1275 clockreg = regr(sc, CLOCK_CNTL); 1276 clockreg &= ~CLOCK_SEL; 1277 clockreg |= sc->sc_clock | CLOCK_STROBE; 1278 regw(sc, CLOCK_CNTL, clockreg); 1279 sc->vclk_freq = clock; 1280 } 1281 1282 static void 1283 mach64_init_lut(struct mach64_softc *sc) 1284 { 1285 uint8_t cmap[768]; 1286 int i, idx; 1287 1288 rasops_get_cmap(&mach64_console_screen.scr_ri, cmap, sizeof(cmap)); 1289 idx = 0; 1290 for (i = 0; i < 256; i++) { 1291 mach64_putpalreg(sc, i, cmap[idx], cmap[idx + 1], 1292 cmap[idx + 2]); 1293 idx += 3; 1294 } 1295 } 1296 1297 static int 1298 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1299 uint8_t b) 1300 { 1301 sc->sc_cmap_red[index] = r; 1302 sc->sc_cmap_green[index] = g; 1303 sc->sc_cmap_blue[index] = b; 1304 /* 1305 * writing the dac index takes a while, in theory we can poll some 1306 * register to see when it's ready - but we better avoid writing it 1307 * unnecessarily 1308 */ 1309 if (index != sc->sc_dacw) { 1310 regwb(sc, DAC_MASK, 0xff); 1311 regwb(sc, DAC_WINDEX, index); 1312 } 1313 sc->sc_dacw = index + 1; 1314 regwb(sc, DAC_DATA, r); 1315 regwb(sc, DAC_DATA, g); 1316 regwb(sc, DAC_DATA, b); 1317 return 0; 1318 } 1319 1320 static int 1321 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1322 { 1323 uint index = cm->index; 1324 uint count = cm->count; 1325 int i, error; 1326 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1327 uint8_t *r, *g, *b; 1328 1329 if (cm->index >= 256 || cm->count > 256 || 1330 (cm->index + cm->count) > 256) 1331 return EINVAL; 1332 error = copyin(cm->red, &rbuf[index], count); 1333 if (error) 1334 return error; 1335 error = copyin(cm->green, &gbuf[index], count); 1336 if (error) 1337 return error; 1338 error = copyin(cm->blue, &bbuf[index], count); 1339 if (error) 1340 return error; 1341 1342 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1343 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1344 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1345 1346 r = &sc->sc_cmap_red[index]; 1347 g = &sc->sc_cmap_green[index]; 1348 b = &sc->sc_cmap_blue[index]; 1349 1350 for (i = 0; i < count; i++) { 1351 mach64_putpalreg(sc, index, *r, *g, *b); 1352 index++; 1353 r++, g++, b++; 1354 } 1355 return 0; 1356 } 1357 1358 static int 1359 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1360 { 1361 u_int index = cm->index; 1362 u_int count = cm->count; 1363 int error; 1364 1365 if (index >= 255 || count > 256 || index + count > 256) 1366 return EINVAL; 1367 1368 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1369 if (error) 1370 return error; 1371 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1372 if (error) 1373 return error; 1374 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1375 if (error) 1376 return error; 1377 1378 return 0; 1379 } 1380 1381 static int 1382 mach64_is_console(struct mach64_softc *sc) 1383 { 1384 bool console = 0; 1385 1386 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1387 "is_console", &console); 1388 return console; 1389 } 1390 1391 /* 1392 * wsdisplay_emulops 1393 */ 1394 1395 static void 1396 mach64_cursor(void *cookie, int on, int row, int col) 1397 { 1398 struct rasops_info *ri = cookie; 1399 struct vcons_screen *scr = ri->ri_hw; 1400 struct mach64_softc *sc = scr->scr_cookie; 1401 int x, y, wi, he; 1402 1403 wi = ri->ri_font->fontwidth; 1404 he = ri->ri_font->fontheight; 1405 1406 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1407 x = ri->ri_ccol * wi + ri->ri_xorigin; 1408 y = ri->ri_crow * he + ri->ri_yorigin; 1409 if (ri->ri_flg & RI_CURSOR) { 1410 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1411 ri->ri_flg &= ~RI_CURSOR; 1412 } 1413 ri->ri_crow = row; 1414 ri->ri_ccol = col; 1415 if (on) { 1416 x = ri->ri_ccol * wi + ri->ri_xorigin; 1417 y = ri->ri_crow * he + ri->ri_yorigin; 1418 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC); 1419 ri->ri_flg |= RI_CURSOR; 1420 } 1421 } else { 1422 scr->scr_ri.ri_crow = row; 1423 scr->scr_ri.ri_ccol = col; 1424 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1425 } 1426 } 1427 1428 #if 0 1429 static int 1430 mach64_mapchar(void *cookie, int uni, u_int *index) 1431 { 1432 return 0; 1433 } 1434 #endif 1435 1436 static void 1437 mach64_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1438 { 1439 struct rasops_info *ri = cookie; 1440 struct wsdisplay_font *font = PICK_FONT(ri, c); 1441 struct vcons_screen *scr = ri->ri_hw; 1442 struct mach64_softc *sc = scr->scr_cookie; 1443 1444 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1445 int fg, bg, uc; 1446 uint8_t *data; 1447 int x, y, wi, he; 1448 wi = font->fontwidth; 1449 he = font->fontheight; 1450 1451 if (!CHAR_IN_FONT(c, font)) 1452 return; 1453 bg = ri->ri_devcmap[(attr >> 16) & 0x0f]; 1454 fg = ri->ri_devcmap[(attr >> 24) & 0x0f]; 1455 x = ri->ri_xorigin + col * wi; 1456 y = ri->ri_yorigin + row * he; 1457 if (c == 0x20) { 1458 mach64_rectfill(sc, x, y, wi, he, bg); 1459 } else { 1460 uc = c - font->firstchar; 1461 data = (uint8_t *)font->data + uc * 1462 ri->ri_fontscale; 1463 1464 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1465 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1466 } 1467 if (attr & 1) 1468 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1469 } 1470 } 1471 1472 static void 1473 mach64_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 1474 { 1475 struct rasops_info *ri = cookie; 1476 struct wsdisplay_font *font = PICK_FONT(ri, c); 1477 struct vcons_screen *scr = ri->ri_hw; 1478 struct mach64_softc *sc = scr->scr_cookie; 1479 uint32_t bg, fg, latch = 0, bg8, fg8, pixel; 1480 int i, x, y, wi, he, r, g, b, aval; 1481 int r1, g1, b1, r0, g0, b0, fgo, bgo; 1482 uint8_t *data8; 1483 int rv = 0, cnt = 0; 1484 1485 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1486 return; 1487 1488 if (!CHAR_IN_FONT(c, font)) 1489 return; 1490 1491 wi = font->fontwidth; 1492 he = font->fontheight; 1493 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1494 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f]; 1495 x = ri->ri_xorigin + col * wi; 1496 y = ri->ri_yorigin + row * he; 1497 1498 if (c == 0x20) { 1499 mach64_rectfill(sc, x, y, wi, he, bg); 1500 if (attr & 1) 1501 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1502 return; 1503 } 1504 1505 rv = glyphcache_try(&sc->sc_gc, c, x, y, attr); 1506 if (rv == GC_OK) 1507 return; 1508 1509 data8 = WSFONT_GLYPH(c, font); 1510 1511 wait_for_fifo(sc, 11); 1512 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1513 regw(sc, DP_SRC, MONO_SRC_ONE | BKGD_SRC_HOST | FRGD_SRC_HOST); 1514 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1515 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1516 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1517 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1518 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1519 regw(sc, SRC_Y_X, 0); 1520 regw(sc, SRC_WIDTH1, wi); 1521 regw(sc, DST_Y_X, (x << 16) | y); 1522 regw(sc, DST_HEIGHT_WIDTH, (wi << 16) | he); 1523 1524 /* 1525 * we need the RGB colours here, so get offsets into rasops_cmap 1526 */ 1527 fgo = ((attr >> 24) & 0xf) * 3; 1528 bgo = ((attr >> 16) & 0xf) * 3; 1529 1530 r0 = rasops_cmap[bgo]; 1531 r1 = rasops_cmap[fgo]; 1532 g0 = rasops_cmap[bgo + 1]; 1533 g1 = rasops_cmap[fgo + 1]; 1534 b0 = rasops_cmap[bgo + 2]; 1535 b1 = rasops_cmap[fgo + 2]; 1536 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 1537 bg8 = R3G3B2(r0, g0, b0); 1538 fg8 = R3G3B2(r1, g1, b1); 1539 1540 wait_for_fifo(sc, 10); 1541 1542 for (i = 0; i < ri->ri_fontscale; i++) { 1543 aval = *data8; 1544 if (aval == 0) { 1545 pixel = bg8; 1546 } else if (aval == 255) { 1547 pixel = fg8; 1548 } else { 1549 r = aval * r1 + (255 - aval) * r0; 1550 g = aval * g1 + (255 - aval) * g0; 1551 b = aval * b1 + (255 - aval) * b0; 1552 pixel = ((r & 0xe000) >> 8) | 1553 ((g & 0xe000) >> 11) | 1554 ((b & 0xc000) >> 14); 1555 } 1556 latch = (latch << 8) | pixel; 1557 /* write in 32bit chunks */ 1558 if ((i & 3) == 3) { 1559 regws(sc, HOST_DATA0, latch); 1560 /* 1561 * not strictly necessary, old data should be shifted 1562 * out 1563 */ 1564 latch = 0; 1565 cnt++; 1566 if (cnt > 8) { 1567 wait_for_fifo(sc, 10); 1568 cnt = 0; 1569 } 1570 } 1571 data8++; 1572 } 1573 /* if we have pixels left in latch write them out */ 1574 if ((i & 3) != 0) { 1575 latch = latch << ((4 - (i & 3)) << 3); 1576 regws(sc, HOST_DATA0, latch); 1577 } 1578 1579 if (rv == GC_ADD) { 1580 glyphcache_add(&sc->sc_gc, c, x, y); 1581 } else if (attr & 1) { 1582 mach64_rectfill(sc, x, y + he - 2, wi, 1, fg); 1583 } 1584 1585 } 1586 1587 static void 1588 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1589 { 1590 struct rasops_info *ri = cookie; 1591 struct vcons_screen *scr = ri->ri_hw; 1592 struct mach64_softc *sc = scr->scr_cookie; 1593 int32_t xs, xd, y, width, height; 1594 1595 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1596 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1597 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1598 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1599 width = ri->ri_font->fontwidth * ncols; 1600 height = ri->ri_font->fontheight; 1601 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC); 1602 } 1603 } 1604 1605 static void 1606 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1607 { 1608 struct rasops_info *ri = cookie; 1609 struct vcons_screen *scr = ri->ri_hw; 1610 struct mach64_softc *sc = scr->scr_cookie; 1611 int32_t x, y, width, height, fg, bg, ul; 1612 1613 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1614 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1615 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1616 width = ri->ri_font->fontwidth * ncols; 1617 height = ri->ri_font->fontheight; 1618 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1619 1620 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1621 } 1622 } 1623 1624 static void 1625 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1626 { 1627 struct rasops_info *ri = cookie; 1628 struct vcons_screen *scr = ri->ri_hw; 1629 struct mach64_softc *sc = scr->scr_cookie; 1630 int32_t x, ys, yd, width, height; 1631 1632 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1633 x = ri->ri_xorigin; 1634 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1635 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1636 width = ri->ri_emuwidth; 1637 height = ri->ri_font->fontheight*nrows; 1638 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC); 1639 } 1640 } 1641 1642 static void 1643 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1644 { 1645 struct rasops_info *ri = cookie; 1646 struct vcons_screen *scr = ri->ri_hw; 1647 struct mach64_softc *sc = scr->scr_cookie; 1648 int32_t x, y, width, height, fg, bg, ul; 1649 1650 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1651 if ((row == 0) && (nrows == ri->ri_rows)) { 1652 /* clear full screen */ 1653 x = 0; 1654 y = 0; 1655 width = sc->virt_x; 1656 height = sc->virt_y; 1657 } else { 1658 x = ri->ri_xorigin; 1659 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1660 width = ri->ri_emuwidth; 1661 height = ri->ri_font->fontheight * nrows; 1662 } 1663 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1664 1665 mach64_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1666 } 1667 } 1668 1669 static void 1670 mach64_bitblt(void *cookie, int xs, int ys, int xd, int yd, int width, 1671 int height, int rop) 1672 { 1673 struct mach64_softc *sc = cookie; 1674 uint32_t dest_ctl = 0; 1675 1676 #if 0 1677 wait_for_idle(sc); 1678 #else 1679 wait_for_fifo(sc, 10); 1680 #endif 1681 1682 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1683 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1684 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1685 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1686 if (yd < ys) { 1687 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1688 } else { 1689 ys += height - 1; 1690 yd += height - 1; 1691 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1692 } 1693 if (xd < xs) { 1694 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1695 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1696 } else { 1697 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1698 xs += width - 1; 1699 xd += width - 1; 1700 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1701 } 1702 regw(sc, DST_CNTL, dest_ctl); 1703 1704 regw(sc, SRC_Y_X, (xs << 16) | ys); 1705 regw(sc, SRC_WIDTH1, width); 1706 regw(sc, DST_Y_X, (xd << 16) | yd); 1707 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1708 } 1709 1710 static void 1711 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1712 int height, uint32_t fg, uint32_t bg) 1713 { 1714 wait_for_idle(sc); 1715 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1716 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1717 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1718 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1719 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1720 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1721 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1722 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1723 regw(sc, DP_BKGD_CLR, bg); 1724 regw(sc, DP_FRGD_CLR, fg); 1725 regw(sc, SRC_Y_X, 0); 1726 regw(sc, SRC_WIDTH1, width); 1727 regw(sc, DST_Y_X, (xd << 16) | yd); 1728 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1729 /* now feed the data into the chip */ 1730 } 1731 1732 static void 1733 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1734 { 1735 int i; 1736 uint32_t latch = 0, bork; 1737 int shift = 0; 1738 int reg = 0; 1739 1740 for (i = 0; i < count; i++) { 1741 bork = data[i]; 1742 latch |= (bork << shift); 1743 if (shift == 24) { 1744 regw(sc, HOST_DATA0 + reg, latch); 1745 latch = 0; 1746 shift = 0; 1747 reg = (reg + 4) & 0x3c; 1748 } else 1749 shift += 8; 1750 } 1751 if (shift != 0) /* 24 */ 1752 regw(sc, HOST_DATA0 + reg, latch); 1753 } 1754 1755 1756 static void 1757 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1758 int colour) 1759 { 1760 wait_for_fifo(sc, 11); 1761 regw(sc, DP_FRGD_CLR, colour); 1762 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1763 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1764 regw(sc, DP_MIX, MIX_SRC << 16); 1765 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1766 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1767 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1768 1769 regw(sc, SRC_Y_X, (x << 16) | y); 1770 regw(sc, SRC_WIDTH1, width); 1771 regw(sc, DST_Y_X, (x << 16) | y); 1772 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1773 } 1774 1775 static void 1776 mach64_clearscreen(struct mach64_softc *sc) 1777 { 1778 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1779 } 1780 1781 1782 #if 0 1783 static void 1784 mach64_showpal(struct mach64_softc *sc) 1785 { 1786 int i, x = 0; 1787 1788 for (i = 0; i < 16; i++) { 1789 mach64_rectfill(sc, x, 0, 64, 64, i); 1790 x += 64; 1791 } 1792 } 1793 #endif 1794 1795 /* 1796 * wsdisplay_accessops 1797 */ 1798 1799 static int 1800 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1801 struct lwp *l) 1802 { 1803 struct vcons_data *vd = v; 1804 struct mach64_softc *sc = vd->cookie; 1805 struct wsdisplay_fbinfo *wdf; 1806 struct vcons_screen *ms = vd->active; 1807 1808 switch (cmd) { 1809 case WSDISPLAYIO_GTYPE: 1810 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1811 return 0; 1812 1813 case WSDISPLAYIO_LINEBYTES: 1814 *(u_int *)data = sc->virt_x * sc->bits_per_pixel / 8; 1815 return 0; 1816 1817 case WSDISPLAYIO_GINFO: 1818 wdf = (void *)data; 1819 wdf->height = sc->virt_y; 1820 wdf->width = sc->virt_x; 1821 wdf->depth = sc->bits_per_pixel; 1822 wdf->cmsize = 256; 1823 return 0; 1824 1825 case WSDISPLAYIO_GETCMAP: 1826 return mach64_getcmap(sc, 1827 (struct wsdisplay_cmap *)data); 1828 1829 case WSDISPLAYIO_PUTCMAP: 1830 return mach64_putcmap(sc, 1831 (struct wsdisplay_cmap *)data); 1832 1833 /* PCI config read/write passthrough. */ 1834 case PCI_IOC_CFGREAD: 1835 case PCI_IOC_CFGWRITE: 1836 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1837 cmd, data, flag, l); 1838 1839 case WSDISPLAYIO_GET_BUSID: 1840 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1841 sc->sc_pcitag, data); 1842 1843 case WSDISPLAYIO_SMODE: { 1844 int new_mode = *(int*)data; 1845 if (new_mode != sc->sc_mode) { 1846 sc->sc_mode = new_mode; 1847 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1848 && (ms != NULL)) 1849 { 1850 /* restore initial video mode */ 1851 mach64_init(sc); 1852 mach64_init_engine(sc); 1853 mach64_init_lut(sc); 1854 mach64_modeswitch(sc, sc->sc_my_mode); 1855 mach64_clearscreen(sc); 1856 glyphcache_wipe(&sc->sc_gc); 1857 vcons_redraw_screen(ms); 1858 } 1859 } 1860 } 1861 return 0; 1862 case WSDISPLAYIO_GET_EDID: { 1863 struct wsdisplayio_edid_info *d = data; 1864 return wsdisplayio_get_edid(sc->sc_dev, d); 1865 } 1866 1867 case WSDISPLAYIO_GET_FBINFO: { 1868 struct wsdisplayio_fbinfo *fbi = data; 1869 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1870 } 1871 } 1872 return EPASSTHROUGH; 1873 } 1874 1875 static paddr_t 1876 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1877 { 1878 struct vcons_data *vd = v; 1879 struct mach64_softc *sc = vd->cookie; 1880 paddr_t pa; 1881 1882 if (sc->sc_mode == WSDISPLAYIO_MODE_DUMBFB) { 1883 /* 1884 *'regular' framebuffer mmap()ing 1885 */ 1886 if (offset < (sc->memsize * 1024)) { 1887 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, 1888 offset, prot, BUS_SPACE_MAP_LINEAR); 1889 return pa; 1890 } 1891 } else if (sc->sc_mode == WSDISPLAYIO_MODE_MAPPED) { 1892 /* 1893 * restrict all other mappings to processes with superuser 1894 * privileges 1895 */ 1896 if (kauth_authorize_machdep(kauth_cred_get(), 1897 KAUTH_MACHDEP_UNMANAGEDMEM, 1898 NULL, NULL, NULL, NULL) != 0) { 1899 return -1; 1900 } 1901 if ((offset >= sc->sc_aperbase) && 1902 (offset < (sc->sc_aperbase + sc->sc_apersize))) { 1903 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1904 BUS_SPACE_MAP_LINEAR); 1905 return pa; 1906 } 1907 1908 if ((offset >= sc->sc_regbase) && 1909 (offset < (sc->sc_regbase + sc->sc_regsize))) { 1910 pa = bus_space_mmap(sc->sc_regt, offset, 0, prot, 1911 BUS_SPACE_MAP_LINEAR); 1912 return pa; 1913 } 1914 1915 if ((offset >= sc->sc_rom.vb_base) && 1916 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 1917 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1918 BUS_SPACE_MAP_LINEAR); 1919 return pa; 1920 } 1921 1922 #ifdef PCI_MAGIC_IO_RANGE 1923 if ((offset >= PCI_MAGIC_IO_RANGE) && 1924 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 1925 return bus_space_mmap(sc->sc_iot, 1926 offset - PCI_MAGIC_IO_RANGE, 0, prot, 0); 1927 } 1928 #endif 1929 } 1930 return -1; 1931 } 1932 1933 #if 0 1934 static int 1935 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1936 { 1937 1938 return 0; 1939 } 1940 #endif 1941 1942 void 1943 machfb_blank(struct mach64_softc *sc, int blank) 1944 { 1945 uint32_t reg; 1946 1947 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1948 1949 switch (blank) 1950 { 1951 case 0: 1952 reg = regr(sc, CRTC_GEN_CNTL); 1953 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1954 sc->sc_blanked = 0; 1955 break; 1956 case 1: 1957 reg = regr(sc, CRTC_GEN_CNTL); 1958 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1959 sc->sc_blanked = 1; 1960 break; 1961 default: 1962 break; 1963 } 1964 } 1965
Indexes created Thu Oct 02 14:10:14 GMT 2025