machfbreg.h revision 1.1
1 /* $NetBSD: machfbreg.h,v 1.1 2002/10/24 18:15:57 junyoung Exp $ */ 2 3 /* 4 * Copyright 1992,1993,1994,1995,1996,1997 by Kevin E. Martin, Chapel Hill, North Carolina. 5 * 6 * Permission to use, copy, modify, distribute, and sell this software and 7 * its documentation for any purpose is hereby granted without fee, 8 * provided that the above copyright notice appear in all copies and that 9 * both that copyright notice and this permission notice appear in 10 * supporting documentation, and that the name of Kevin E. Martin not be 11 * used in advertising or publicity pertaining to distribution of the 12 * software without specific, written prior permission. Kevin E. Martin 13 * makes no representations about the suitability of this software for any 14 * purpose. It is provided "as is" without express or implied warranty. 15 * 16 * KEVIN E. MARTIN, RICKARD E. FAITH, AND TIAGO GONS DISCLAIM ALL 17 * WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL THE 19 * AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR 20 * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, 21 * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, 22 * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS 23 * SOFTWARE. 24 * 25 * Modified for the Mach-8 by Rickard E. Faith (faith (at) cs.unc.edu) 26 * Modified for the Mach32 by Kevin E. Martin (martin (at) cs.unc.edu) 27 * Modified for the Mach64 by Kevin E. Martin (martin (at) cs.unc.edu) 28 */ 29 30 /* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */ 31 32 #define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 00 */ 33 #define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 01 */ 34 #define CRTC_V_TOTAL_DISP 0x0008 /* Dword offset 02 */ 35 #define CRTC_V_SYNC_STRT_WID 0x000C /* Dword offset 03 */ 36 #define CRTC_VLINE_CRNT_VLINE 0x0010 /* Dword offset 04 */ 37 #define CRTC_OFF_PITCH 0x0014 /* Dword offset 05 */ 38 #define CRTC_INT_CNTL 0x0018 /* Dword offset 06 */ 39 #define CRTC_GEN_CNTL 0x001C /* Dword offset 07 */ 40 41 #define DSP_CONFIG 0x0020 /* Dword offset 08 */ 42 #define DSP_ON_OFF 0x0024 /* Dword offset 09 */ 43 44 #define SHARED_CNTL 0x0038 /* Dword offset 0E */ 45 46 #define OVR_CLR 0x0040 /* Dword offset 10 */ 47 #define OVR_WID_LEFT_RIGHT 0x0044 /* Dword offset 11 */ 48 #define OVR_WID_TOP_BOTTOM 0x0048 /* Dword offset 12 */ 49 50 #define CUR_CLR0 0x0060 /* Dword offset 18 */ 51 #define CUR_CLR1 0x0064 /* Dword offset 19 */ 52 #define CUR_OFFSET 0x0068 /* Dword offset 1A */ 53 #define CUR_HORZ_VERT_POSN 0x006C /* Dword offset 1B */ 54 #define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 1C */ 55 56 #define HW_DEBUG 0x007C /* Dword offset 1F */ 57 58 #define SCRATCH_REG0 0x0080 /* Dword offset 20 */ 59 #define SCRATCH_REG1 0x0084 /* Dword offset 21 */ 60 61 #define CLOCK_CNTL 0x0090 /* Dword offset 24 */ 62 63 #define BUS_CNTL 0x00A0 /* Dword offset 28 */ 64 65 #define LCD_INDEX 0x00A4 /* Dword offset 29 (LTPro) */ 66 #define LCD_DATA 0x00A8 /* Dword offset 2A (LTPro) */ 67 68 #define MEM_CNTL 0x00B0 /* Dword offset 2C */ 69 70 #define MEM_VGA_WP_SEL 0x00B4 /* Dword offset 2D */ 71 #define MEM_VGA_RP_SEL 0x00B8 /* Dword offset 2E */ 72 73 #define DAC_REGS 0x00C0 /* Dword offset 30 */ 74 #define DAC_WINDEX 0x00C0 /* Dword offset 30 */ 75 #define DAC_DATA 0x00C1 /* Dword offset 30 */ 76 #define DAC_MASK 0x00C2 /* Dword offset 30 */ 77 #define DAC_RINDEX 0x00C3 /* Dword offset 30 */ 78 #define DAC_CNTL 0x00C4 /* Dword offset 31 */ 79 80 #define HORZ_STRETCHING 0x00C8 /* Dword offset 32 (LT) */ 81 #define VERT_STRETCHING 0x00CC /* Dword offset 33 (LT) */ 82 83 #define GEN_TEST_CNTL 0x00D0 /* Dword offset 34 */ 84 85 #define LCD_GEN_CNTL 0x00D4 /* Dword offset 35 (LT) */ 86 #define POWER_MANAGEMENT 0x00D8 /* Dword offset 36 (LT) */ 87 88 #define CONFIG_CNTL 0x00DC /* Dword offset 37 (CT, ET, VT) */ 89 #define CONFIG_CHIP_ID 0x00E0 /* Dword offset 38 */ 90 #define CONFIG_STAT0 0x00E4 /* Dword offset 39 */ 91 #define CONFIG_STAT1 0x00E8 /* Dword offset 3A */ 92 93 94 /* GUI MEMORY MAPPED Registers */ 95 96 #define DST_OFF_PITCH 0x0100 /* Dword offset 40 */ 97 #define DST_X 0x0104 /* Dword offset 41 */ 98 #define DST_Y 0x0108 /* Dword offset 42 */ 99 #define DST_Y_X 0x010C /* Dword offset 43 */ 100 #define DST_WIDTH 0x0110 /* Dword offset 44 */ 101 #define DST_HEIGHT 0x0114 /* Dword offset 45 */ 102 #define DST_HEIGHT_WIDTH 0x0118 /* Dword offset 46 */ 103 #define DST_X_WIDTH 0x011C /* Dword offset 47 */ 104 #define DST_BRES_LNTH 0x0120 /* Dword offset 48 */ 105 #define DST_BRES_ERR 0x0124 /* Dword offset 49 */ 106 #define DST_BRES_INC 0x0128 /* Dword offset 4A */ 107 #define DST_BRES_DEC 0x012C /* Dword offset 4B */ 108 #define DST_CNTL 0x0130 /* Dword offset 4C */ 109 110 #define SRC_OFF_PITCH 0x0180 /* Dword offset 60 */ 111 #define SRC_X 0x0184 /* Dword offset 61 */ 112 #define SRC_Y 0x0188 /* Dword offset 62 */ 113 #define SRC_Y_X 0x018C /* Dword offset 63 */ 114 #define SRC_WIDTH1 0x0190 /* Dword offset 64 */ 115 #define SRC_HEIGHT1 0x0194 /* Dword offset 65 */ 116 #define SRC_HEIGHT1_WIDTH1 0x0198 /* Dword offset 66 */ 117 #define SRC_X_START 0x019C /* Dword offset 67 */ 118 #define SRC_Y_START 0x01A0 /* Dword offset 68 */ 119 #define SRC_Y_X_START 0x01A4 /* Dword offset 69 */ 120 #define SRC_WIDTH2 0x01A8 /* Dword offset 6A */ 121 #define SRC_HEIGHT2 0x01AC /* Dword offset 6B */ 122 #define SRC_HEIGHT2_WIDTH2 0x01B0 /* Dword offset 6C */ 123 #define SRC_CNTL 0x01B4 /* Dword offset 6D */ 124 125 #define HOST_DATA0 0x0200 /* Dword offset 80 */ 126 #define HOST_DATA1 0x0204 /* Dword offset 81 */ 127 #define HOST_DATA2 0x0208 /* Dword offset 82 */ 128 #define HOST_DATA3 0x020C /* Dword offset 83 */ 129 #define HOST_DATA4 0x0210 /* Dword offset 84 */ 130 #define HOST_DATA5 0x0214 /* Dword offset 85 */ 131 #define HOST_DATA6 0x0218 /* Dword offset 86 */ 132 #define HOST_DATA7 0x021C /* Dword offset 87 */ 133 #define HOST_DATA8 0x0220 /* Dword offset 88 */ 134 #define HOST_DATA9 0x0224 /* Dword offset 89 */ 135 #define HOST_DATAA 0x0228 /* Dword offset 8A */ 136 #define HOST_DATAB 0x022C /* Dword offset 8B */ 137 #define HOST_DATAC 0x0230 /* Dword offset 8C */ 138 #define HOST_DATAD 0x0234 /* Dword offset 8D */ 139 #define HOST_DATAE 0x0238 /* Dword offset 8E */ 140 #define HOST_DATAF 0x023C /* Dword offset 8F */ 141 #define HOST_CNTL 0x0240 /* Dword offset 90 */ 142 143 #define PAT_REG0 0x0280 /* Dword offset A0 */ 144 #define PAT_REG1 0x0284 /* Dword offset A1 */ 145 #define PAT_CNTL 0x0288 /* Dword offset A2 */ 146 147 #define SC_LEFT 0x02A0 /* Dword offset A8 */ 148 #define SC_RIGHT 0x02A4 /* Dword offset A9 */ 149 #define SC_LEFT_RIGHT 0x02A8 /* Dword offset AA */ 150 #define SC_TOP 0x02AC /* Dword offset AB */ 151 #define SC_BOTTOM 0x02B0 /* Dword offset AC */ 152 #define SC_TOP_BOTTOM 0x02B4 /* Dword offset AD */ 153 154 #define DP_BKGD_CLR 0x02C0 /* Dword offset B0 */ 155 #define DP_FRGD_CLR 0x02C4 /* Dword offset B1 */ 156 #define DP_WRITE_MASK 0x02C8 /* Dword offset B2 */ 157 #define DP_CHAIN_MASK 0x02CC /* Dword offset B3 */ 158 #define DP_PIX_WIDTH 0x02D0 /* Dword offset B4 */ 159 #define DP_MIX 0x02D4 /* Dword offset B5 */ 160 #define DP_SRC 0x02D8 /* Dword offset B6 */ 161 162 #define CLR_CMP_CLR 0x0300 /* Dword offset C0 */ 163 #define CLR_CMP_MASK 0x0304 /* Dword offset C1 */ 164 #define CLR_CMP_CNTL 0x0308 /* Dword offset C2 */ 165 166 #define FIFO_STAT 0x0310 /* Dword offset C4 */ 167 168 #define CONTEXT_MASK 0x0320 /* Dword offset C8 */ 169 #define CONTEXT_LOAD_CNTL 0x032C /* Dword offset CB */ 170 171 #define GUI_TRAJ_CNTL 0x0330 /* Dword offset CC */ 172 #define GUI_STAT 0x0338 /* Dword offset CE */ 173 174 175 /* CRTC control values */ 176 177 #define CRTC_HSYNC_NEG 0x00200000 178 #define CRTC_VSYNC_NEG 0x00200000 179 180 #define CRTC_DBL_SCAN_EN 0x00000001 181 #define CRTC_INTERLACE_EN 0x00000002 182 #define CRTC_HSYNC_DIS 0x00000004 183 #define CRTC_VSYNC_DIS 0x00000008 184 #define CRTC_CSYNC_EN 0x00000010 185 #define CRTC_PIX_BY_2_EN 0x00000020 186 187 #define CRTC_PIX_WIDTH 0x00000700 188 #define CRTC_PIX_WIDTH_4BPP 0x00000100 189 #define CRTC_PIX_WIDTH_8BPP 0x00000200 190 #define CRTC_PIX_WIDTH_15BPP 0x00000300 191 #define CRTC_PIX_WIDTH_16BPP 0x00000400 192 #define CRTC_PIX_WIDTH_24BPP 0x00000500 193 #define CRTC_PIX_WIDTH_32BPP 0x00000600 194 195 #define CRTC_BYTE_PIX_ORDER 0x00000800 196 #define CRTC_PIX_ORDER_MSN_LSN 0x00000000 197 #define CRTC_PIX_ORDER_LSN_MSN 0x00000800 198 199 #define CRTC_FIFO_LWM 0x000f0000 200 #define CRTC_LOCK_REGS 0x00400000 201 #define CRTC_EXT_DISP_EN 0x01000000 202 #define CRTC_EXT_EN 0x02000000 203 204 #define CRTC_CRNT_VLINE 0x07f00000 205 #define CRTC_VBLANK 0x00000001 206 207 /* DAC control values */ 208 209 #define DAC_EXT_SEL_RS2 0x01 210 #define DAC_EXT_SEL_RS3 0x02 211 #define DAC_8BIT_EN 0x00000100 212 #define DAC_PIX_DLY_MASK 0x00000600 213 #define DAC_PIX_DLY_0NS 0x00000000 214 #define DAC_PIX_DLY_2NS 0x00000200 215 #define DAC_PIX_DLY_4NS 0x00000400 216 #define DAC_BLANK_ADJ_MASK 0x00001800 217 #define DAC_BLANK_ADJ_0 0x00000000 218 #define DAC_BLANK_ADJ_1 0x00000800 219 #define DAC_BLANK_ADJ_2 0x00001000 220 221 222 /* Mix control values */ 223 224 #define MIX_NOT_DST 0x0000 225 #define MIX_0 0x0001 226 #define MIX_1 0x0002 227 #define MIX_DST 0x0003 228 #define MIX_NOT_SRC 0x0004 229 #define MIX_XOR 0x0005 230 #define MIX_XNOR 0x0006 231 #define MIX_SRC 0x0007 232 #define MIX_NAND 0x0008 233 #define MIX_NOT_SRC_OR_DST 0x0009 234 #define MIX_SRC_OR_NOT_DST 0x000a 235 #define MIX_OR 0x000b 236 #define MIX_AND 0x000c 237 #define MIX_SRC_AND_NOT_DST 0x000d 238 #define MIX_NOT_SRC_AND_DST 0x000e 239 #define MIX_NOR 0x000f 240 241 /* Maximum engine dimensions */ 242 #define ENGINE_MIN_X 0 243 #define ENGINE_MIN_Y 0 244 #define ENGINE_MAX_X 4095 245 #define ENGINE_MAX_Y 16383 246 247 /* Mach64 engine bit constants - these are typically ORed together */ 248 249 /* HW_DEBUG register constants */ 250 /* For RagePro only... */ 251 #define AUTO_FF_DIS 0x000001000 252 #define AUTO_BLKWRT_DIS 0x000002000 253 254 /* BUS_CNTL register constants */ 255 #define BUS_FIFO_ERR_ACK 0x00200000 256 #define BUS_HOST_ERR_ACK 0x00800000 257 #define BUS_APER_REG_DIS 0x00000010 258 259 /* GEN_TEST_CNTL register constants */ 260 #define GEN_OVR_OUTPUT_EN 0x20 261 #define HWCURSOR_ENABLE 0x80 262 #define GUI_ENGINE_ENABLE 0x100 263 #define BLOCK_WRITE_ENABLE 0x200 264 265 /* DSP_CONFIG register constants */ 266 #define DSP_XCLKS_PER_QW 0x00003fff 267 #define DSP_LOOP_LATENCY 0x000f0000 268 #define DSP_PRECISION 0x00700000 269 270 /* DSP_ON_OFF register constants */ 271 #define DSP_OFF 0x000007ff 272 #define DSP_ON 0x07ff0000 273 274 /* SHARED_CNTL register constants */ 275 #define CTD_FIFO5 0x01000000 276 277 /* CLOCK_CNTL register constants */ 278 #define CLOCK_SEL 0x0f 279 #define CLOCK_DIV 0x30 280 #define CLOCK_DIV1 0x00 281 #define CLOCK_DIV2 0x10 282 #define CLOCK_DIV4 0x20 283 #define CLOCK_STROBE 0x40 284 #define PLL_WR_EN 0x02 285 286 /* PLL registers */ 287 #define PLL_MACRO_CNTL 0x01 288 #define PLL_REF_DIV 0x02 289 #define PLL_GEN_CNTL 0x03 290 #define MCLK_FB_DIV 0x04 291 #define PLL_VCLK_CNTL 0x05 292 #define VCLK_POST_DIV 0x06 293 #define VCLK0_FB_DIV 0x07 294 #define VCLK1_FB_DIV 0x08 295 #define VCLK2_FB_DIV 0x09 296 #define VCLK3_FB_DIV 0x0A 297 #define PLL_XCLK_CNTL 0x0B 298 #define PLL_TEST_CTRL 0x0E 299 #define PLL_TEST_COUNT 0x0F 300 301 /* Memory types for CT, ET, VT, GT */ 302 #define DRAM 1 303 #define EDO_DRAM 2 304 #define PSEUDO_EDO 3 305 #define SDRAM 4 306 #define SGRAM 5 307 #define SGRAM32 6 308 309 #define DAC_INTERNAL 0x00 310 #define DAC_IBMRGB514 0x01 311 #define DAC_ATI68875 0x02 312 #define DAC_TVP3026_A 0x72 313 #define DAC_BT476 0x03 314 #define DAC_BT481 0x04 315 #define DAC_ATT20C491 0x14 316 #define DAC_SC15026 0x24 317 #define DAC_MU9C1880 0x34 318 #define DAC_IMSG174 0x44 319 #define DAC_ATI68860_B 0x05 320 #define DAC_ATI68860_C 0x15 321 #define DAC_TVP3026_B 0x75 322 #define DAC_STG1700 0x06 323 #define DAC_ATT498 0x16 324 #define DAC_STG1702 0x07 325 #define DAC_SC15021 0x17 326 #define DAC_ATT21C498 0x27 327 #define DAC_STG1703 0x37 328 #define DAC_CH8398 0x47 329 #define DAC_ATT20C408 0x57 330 331 #define CLK_ATI18818_0 0 332 #define CLK_ATI18818_1 1 333 #define CLK_STG1703 2 334 #define CLK_CH8398 3 335 #define CLK_INTERNAL 4 336 #define CLK_ATT20C408 5 337 #define CLK_IBMRGB514 6 338 339 /* DST_CNTL register constants */ 340 #define DST_X_RIGHT_TO_LEFT 0 341 #define DST_X_LEFT_TO_RIGHT 1 342 #define DST_Y_BOTTOM_TO_TOP 0 343 #define DST_Y_TOP_TO_BOTTOM 2 344 #define DST_X_MAJOR 0 345 #define DST_Y_MAJOR 4 346 #define DST_X_TILE 8 347 #define DST_Y_TILE 0x10 348 #define DST_LAST_PEL 0x20 349 #define DST_POLYGON_ENABLE 0x40 350 #define DST_24_ROTATION_ENABLE 0x80 351 352 /* SRC_CNTL register constants */ 353 #define SRC_PATTERN_ENABLE 1 354 #define SRC_ROTATION_ENABLE 2 355 #define SRC_LINEAR_ENABLE 4 356 #define SRC_BYTE_ALIGN 8 357 #define SRC_LINE_X_RIGHT_TO_LEFT 0 358 #define SRC_LINE_X_LEFT_TO_RIGHT 0x10 359 360 /* HOST_CNTL register constants */ 361 #define HOST_BYTE_ALIGN 1 362 363 /* DP_CHAIN_MASK register constants */ 364 #define DP_CHAIN_4BPP 0x8888 365 #define DP_CHAIN_7BPP 0xD2D2 366 #define DP_CHAIN_8BPP 0x8080 367 #define DP_CHAIN_8BPP_RGB 0x9292 368 #define DP_CHAIN_15BPP 0x4210 369 #define DP_CHAIN_16BPP 0x8410 370 #define DP_CHAIN_24BPP 0x8080 371 #define DP_CHAIN_32BPP 0x8080 372 373 /* DP_PIX_WIDTH register constants */ 374 #define DST_1BPP 0 375 #define DST_4BPP 1 376 #define DST_8BPP 2 377 #define DST_15BPP 3 378 #define DST_16BPP 4 379 #define DST_32BPP 6 380 #define SRC_1BPP 0 381 #define SRC_4BPP 0x100 382 #define SRC_8BPP 0x200 383 #define SRC_15BPP 0x300 384 #define SRC_16BPP 0x400 385 #define SRC_32BPP 0x600 386 #define HOST_1BPP 0 387 #define HOST_4BPP 0x10000 388 #define HOST_8BPP 0x20000 389 #define HOST_15BPP 0x30000 390 #define HOST_16BPP 0x40000 391 #define HOST_32BPP 0x60000 392 #define BYTE_ORDER_MSB_TO_LSB 0 393 #define BYTE_ORDER_LSB_TO_MSB 0x1000000 394 395 /* DP_SRC register constants */ 396 #define BKGD_SRC_BKGD_CLR 0 397 #define BKGD_SRC_FRGD_CLR 1 398 #define BKGD_SRC_HOST 2 399 #define BKGD_SRC_BLIT 3 400 #define BKGD_SRC_PATTERN 4 401 #define FRGD_SRC_BKGD_CLR 0 402 #define FRGD_SRC_FRGD_CLR 0x100 403 #define FRGD_SRC_HOST 0x200 404 #define FRGD_SRC_BLIT 0x300 405 #define FRGD_SRC_PATTERN 0x400 406 #define MONO_SRC_ONE 0 407 #define MONO_SRC_PATTERN 0x10000 408 #define MONO_SRC_HOST 0x20000 409 #define MONO_SRC_BLIT 0x30000 410
Indexes created Thu Sep 25 08:09:54 GMT 2025