mgafb.c revision 1.2
1 /* $NetBSD: mgafb.c,v 1.2 2026/03/17 12:51:37 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2024 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Driver for the Matrox Millennium (MGA-2064W). 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: mgafb.c,v 1.2 2026/03/17 12:51:37 macallan Exp $"); 37 38 #include "opt_mgafb.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/kauth.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcidevs.h> 49 #include <dev/pci/pciio.h> 50 51 #include <dev/pci/mgafbreg.h> 52 #include <dev/pci/mgafbvar.h> 53 54 #include <dev/pci/wsdisplay_pci.h> 55 56 #include <dev/videomode/videomode.h> 57 #include <dev/videomode/edidvar.h> 58 59 #include <dev/i2c/i2cvar.h> 60 #include <dev/i2c/i2c_bitbang.h> 61 #include <dev/i2c/ddcvar.h> 62 63 #include "opt_wsemul.h" 64 65 /* #define MGAFB_ACCEL can be the default - it works */ 66 67 static inline void 68 MGA_WRITE4(struct mgafb_softc *sc, bus_size_t reg, uint32_t v) 69 { 70 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, v); 71 bus_space_barrier(sc->sc_regt, sc->sc_regh, reg, 4, 72 BUS_SPACE_BARRIER_WRITE); 73 } 74 75 static inline void 76 MGA_WRITE1(struct mgafb_softc *sc, bus_size_t reg, uint8_t v) 77 { 78 bus_space_write_1(sc->sc_regt, sc->sc_regh, reg, v); 79 bus_space_barrier(sc->sc_regt, sc->sc_regh, reg, 1, 80 BUS_SPACE_BARRIER_WRITE); 81 } 82 83 static inline uint32_t 84 MGA_READ4(struct mgafb_softc *sc, bus_size_t reg) 85 { 86 bus_space_barrier(sc->sc_regt, sc->sc_regh, reg, 4, 87 BUS_SPACE_BARRIER_READ); 88 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 89 } 90 91 static inline uint8_t 92 MGA_READ1(struct mgafb_softc *sc, bus_size_t reg) 93 { 94 bus_space_barrier(sc->sc_regt, sc->sc_regh, reg, 1, 95 BUS_SPACE_BARRIER_READ); 96 return bus_space_read_1(sc->sc_regt, sc->sc_regh, reg); 97 } 98 99 100 static int mgafb_match(device_t, cfdata_t, void *); 101 static void mgafb_attach(device_t, device_t, void *); 102 103 #ifdef MGAFB_PINS 104 static void mgafb_read_pins(struct mgafb_softc *, const struct pci_attach_args *); 105 static void mgafb_dump_pins(struct mgafb_softc *); 106 #endif /* MGAFB_PINS */ 107 108 #ifndef MGAFB_NO_HW_INIT 109 static void mgafb_preinit_wram(struct mgafb_softc *); 110 static void mgafb_set_mclk(struct mgafb_softc *, int); 111 static void mgafb_preinit_1064sg(struct mgafb_softc *); 112 #endif 113 114 static void mgafb_detect_vram(struct mgafb_softc *); 115 116 static void mgafb_calc_pll(int, uint8_t *, uint8_t *, uint8_t *); 117 static void mgafb_calc_pll_1064sg(int, uint8_t *, uint8_t *, uint8_t *); 118 static void mgafb_calc_crtc(const struct videomode *, int, bool, 119 uint8_t [25], uint8_t [6], uint8_t *, uint8_t *); 120 121 static bool mgafb_mode_fits(struct mgafb_softc *, const struct videomode *); 122 static const struct videomode *mgafb_pick_mode(struct mgafb_softc *); 123 124 static void mgafb_resolve_bars(struct mgafb_softc *, 125 const struct pci_attach_args *, int *, int *); 126 static uint8_t mgafb_crtcext3_scale(struct mgafb_softc *); 127 128 static void mgafb_set_mode(struct mgafb_softc *); 129 static void mgafb_tvp3026_setup_dac(struct mgafb_softc *, bool); 130 static void mgafb_tvp3026_set_pclk(struct mgafb_softc *, int, bool); 131 static void mgafb_idac_setup_dac(struct mgafb_softc *); 132 static void mgafb_idac_set_pclk(struct mgafb_softc *, int); 133 134 static void mgafb_dac_write(struct mgafb_softc *, uint8_t, uint8_t); 135 static uint8_t mgafb_dac_read(struct mgafb_softc *, uint8_t); 136 static void mgafb_dac_write_ind(struct mgafb_softc *, uint8_t, uint8_t); 137 static uint8_t mgafb_dac_read_ind(struct mgafb_softc *, uint8_t); 138 139 static void mgafb_ddc_read(struct mgafb_softc *); 140 static void mgafb_i2cbb_set_bits(void *, uint32_t); 141 static void mgafb_i2cbb_set_dir(void *, uint32_t); 142 static uint32_t mgafb_i2cbb_read_bits(void *); 143 static int mgafb_i2c_send_start(void *, int); 144 static int mgafb_i2c_send_stop(void *, int); 145 static int mgafb_i2c_initiate_xfer(void *, i2c_addr_t, int); 146 static int mgafb_i2c_read_byte(void *, uint8_t *, int); 147 static int mgafb_i2c_write_byte(void *, uint8_t, int); 148 149 static const struct i2c_bitbang_ops mgafb_i2cbb_ops = { 150 mgafb_i2cbb_set_bits, 151 mgafb_i2cbb_set_dir, 152 mgafb_i2cbb_read_bits, 153 { 154 MGA_DDC_SDA, /* [I2C_BIT_SDA] = bit 2 */ 155 MGA_DDC_SCL, /* [I2C_BIT_SCL] = bit 4 */ 156 0, 157 0 158 } 159 }; 160 161 static void mgafb_load_cmap(struct mgafb_softc *, u_int, u_int); 162 static void mgafb_init_default_cmap(struct mgafb_softc *); 163 static int mgafb_putcmap(struct mgafb_softc *, struct wsdisplay_cmap *); 164 static int mgafb_getcmap(struct mgafb_softc *, struct wsdisplay_cmap *); 165 166 static void mgafb_cursor_init(struct mgafb_softc *); 167 static void mgafb_cursor_enable(struct mgafb_softc *, bool); 168 static void mgafb_cursor_setpos(struct mgafb_softc *, int, int); 169 static void mgafb_cursor_setcmap(struct mgafb_softc *); 170 static void mgafb_cursor_setshape(struct mgafb_softc *, int, int); 171 172 static void mgafb_init_screen(void *, struct vcons_screen *, int, long *); 173 static int mgafb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 174 static paddr_t mgafb_mmap(void *, void *, off_t, int); 175 176 #ifdef MGAFB_ACCEL 177 static void mgafb_wait_fifo(struct mgafb_softc *, int); 178 static void mgafb_wait_idle(struct mgafb_softc *); 179 static uint32_t mgafb_color_replicate(struct mgafb_softc *, uint32_t); 180 static void mgafb_fill_rect(struct mgafb_softc *, int, int, int, int, 181 uint32_t); 182 static void mgafb_blit_rect(struct mgafb_softc *, int, int, int, int, 183 int, int); 184 static void mgafb_gc_bitblt(void *, int, int, int, int, int, int, int); 185 static void mgafb_putchar(void *, int, int, u_int, long); 186 static void mgafb_putchar_aa(void *, int, int, u_int, long); 187 static void mgafb_copyrows(void *, int, int, int); 188 static void mgafb_eraserows(void *, int, int, long); 189 static void mgafb_copycols(void *, int, int, int, int); 190 static void mgafb_erasecols(void *, int, int, int, long); 191 #endif /* MGAFB_ACCEL */ 192 193 CFATTACH_DECL_NEW(mgafb, sizeof(struct mgafb_softc), 194 mgafb_match, mgafb_attach, NULL, NULL); 195 196 static const struct mgafb_chip_info mgafb_chips[] = { 197 [MGAFB_CHIP_2064W] = { 198 .ci_name = "2064W", 199 .ci_max_pclk = 175000, 200 .ci_vram_default = 0, 201 .ci_has_tvp3026 = true, 202 .ci_has_wram = true, 203 .ci_probe_vram = true, 204 }, 205 [MGAFB_CHIP_2164W] = { 206 .ci_name = "2164W", 207 .ci_max_pclk = 220000, 208 .ci_vram_default = 4*1024*1024, 209 .ci_has_tvp3026 = true, 210 .ci_has_wram = true, 211 .ci_probe_vram = false, 212 }, 213 [MGAFB_CHIP_1064SG] = { 214 .ci_name = "1064SG", 215 .ci_max_pclk = 135000, 216 .ci_vram_default = 0, 217 .ci_has_tvp3026 = false, 218 .ci_has_wram = false, 219 .ci_probe_vram = true, 220 }, 221 }; 222 223 static struct wsdisplay_accessops mgafb_accessops = { 224 mgafb_ioctl, 225 mgafb_mmap, 226 NULL, /* alloc_screen */ 227 NULL, /* free_screen */ 228 NULL, /* show_screen */ 229 NULL, /* load_font */ 230 NULL, /* pollc */ 231 NULL, /* scroll */ 232 }; 233 234 static int 235 mgafb_match(device_t parent, cfdata_t match, void *aux) 236 { 237 const struct pci_attach_args *pa = aux; 238 239 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_MATROX) 240 return 0; 241 242 switch (PCI_PRODUCT(pa->pa_id)) { 243 case PCI_PRODUCT_MATROX_MILLENNIUM: 244 /* 245 case PCI_PRODUCT_MATROX_MILLENNIUM2: 246 case PCI_PRODUCT_MATROX_MILLENNIUM2_AGP: 247 case PCI_PRODUCT_MATROX_MYSTIQUE: 248 */ 249 return 100; 250 } 251 252 return 0; 253 } 254 255 static void 256 mgafb_attach(device_t parent, device_t self, void *aux) 257 { 258 struct mgafb_softc *sc = device_private(self); 259 struct wsemuldisplaydev_attach_args ws_aa; 260 struct rasops_info *ri; 261 const struct pci_attach_args *pa = aux; 262 pcireg_t screg; 263 bool console; 264 long defattr; 265 int regbar; 266 int fbbar; 267 268 #ifdef MGAFB_CONSOLE 269 console = true; 270 #else 271 prop_dictionary_get_bool(device_properties(self), "is_console", 272 &console); 273 #endif 274 275 sc->sc_dev = self; 276 sc->sc_pc = pa->pa_pc; 277 sc->sc_pcitag = pa->pa_tag; 278 279 switch (PCI_PRODUCT(pa->pa_id)) { 280 case PCI_PRODUCT_MATROX_MILLENNIUM2: 281 case PCI_PRODUCT_MATROX_MILLENNIUM2_AGP: 282 sc->sc_chip = MGAFB_CHIP_2164W; 283 break; 284 case PCI_PRODUCT_MATROX_MYSTIQUE: 285 sc->sc_chip = MGAFB_CHIP_1064SG; 286 break; 287 default: 288 sc->sc_chip = MGAFB_CHIP_2064W; 289 break; 290 } 291 sc->sc_ci = &mgafb_chips[sc->sc_chip]; 292 293 /* Enable PCI memory decoding. */ 294 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 295 PCI_COMMAND_STATUS_REG); 296 screg |= PCI_COMMAND_MEM_ENABLE; 297 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 298 screg); 299 300 pci_aprint_devinfo(pa, NULL); 301 302 mgafb_resolve_bars(sc, pa, ®bar, &fbbar); 303 304 if (pci_mapreg_map(pa, regbar, 305 PCI_MAPREG_TYPE_MEM, BUS_SPACE_MAP_LINEAR, 306 &sc->sc_regt, &sc->sc_regh, 307 &sc->sc_reg_pa, &sc->sc_reg_size) != 0) { 308 aprint_error_dev(self, 309 "unable to map control aperture\n"); 310 return; 311 } 312 if (pci_mapreg_map(pa, fbbar, 313 PCI_MAPREG_TYPE_MEM, BUS_SPACE_MAP_LINEAR, 314 &sc->sc_fbt, &sc->sc_fbh, 315 &sc->sc_fb_pa, &sc->sc_fb_size) != 0) { 316 aprint_error_dev(self, 317 "unable to map framebuffer\n"); 318 return; 319 } 320 321 aprint_normal_dev(self, 322 "control at 0x%08" PRIxPADDR ", fb at 0x%08" PRIxPADDR "\n", 323 (paddr_t)sc->sc_reg_pa, (paddr_t)sc->sc_fb_pa); 324 325 #ifdef MGAFB_PINS 326 mgafb_read_pins(sc, pa); 327 mgafb_dump_pins(sc); 328 #endif /* MGAFB_PINS */ 329 330 #ifdef MGAFB_8BPP 331 sc->sc_depth = 8; 332 #else 333 sc->sc_depth = 16; 334 #endif 335 336 #ifndef MGAFB_NO_HW_INIT 337 if (sc->sc_ci->ci_has_wram) { 338 mgafb_preinit_wram(sc); 339 mgafb_set_mclk(sc, MGA_MCLK_KHZ); 340 } else { 341 mgafb_preinit_1064sg(sc); 342 } 343 #else 344 aprint_normal_dev(self, 345 "hardware init skipped\n"); 346 #endif 347 348 mgafb_detect_vram(sc); 349 350 mgafb_ddc_read(sc); 351 352 sc->sc_videomode = mgafb_pick_mode(sc); 353 sc->sc_width = sc->sc_videomode->hdisplay; 354 sc->sc_height = sc->sc_videomode->vdisplay; 355 sc->sc_stride = sc->sc_width * (sc->sc_depth / 8); 356 aprint_normal_dev(self, "videomode: %dx%d, %d kHz dot clock\n", 357 sc->sc_width, sc->sc_height, sc->sc_videomode->dot_clock); 358 359 mgafb_set_mode(sc); 360 361 if (sc->sc_ci->ci_has_tvp3026) 362 mgafb_cursor_init(sc); 363 364 aprint_normal_dev(self, "setting %dx%d %dbpp\n", 365 sc->sc_width, sc->sc_height, sc->sc_depth); 366 367 sc->sc_defaultscreen_descr = (struct wsscreen_descr){ 368 "default", 369 0, 0, 370 NULL, 371 8, 16, 372 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 373 NULL 374 }; 375 sc->sc_screens[0] = &sc->sc_defaultscreen_descr; 376 sc->sc_screenlist = (struct wsscreen_list){1, sc->sc_screens}; 377 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 378 sc->sc_video = WSDISPLAYIO_VIDEO_ON; 379 380 vcons_init(&sc->vd, sc, &sc->sc_defaultscreen_descr, 381 &mgafb_accessops); 382 sc->vd.init_screen = mgafb_init_screen; 383 384 #ifdef MGAFB_ACCEL 385 sc->sc_gc.gc_bitblt = mgafb_gc_bitblt; 386 sc->sc_gc.gc_rectfill = NULL; 387 sc->sc_gc.gc_blitcookie = sc; 388 sc->sc_gc.gc_rop = 0; /* copy; mgafb_gc_bitblt ignores rop */ 389 sc->vd.show_screen_cookie = &sc->sc_gc; 390 sc->vd.show_screen_cb = glyphcache_adapt; 391 #endif 392 393 ri = &sc->sc_console_screen.scr_ri; 394 395 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, &defattr); 396 sc->sc_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 397 398 sc->sc_defaultscreen_descr.textops = &ri->ri_ops; 399 sc->sc_defaultscreen_descr.capabilities = ri->ri_caps; 400 sc->sc_defaultscreen_descr.nrows = ri->ri_rows; 401 sc->sc_defaultscreen_descr.ncols = ri->ri_cols; 402 403 #ifdef MGAFB_ACCEL 404 /* Initialize the glyph cache BEFORE vcons_redraw_screen.*/ 405 glyphcache_init(&sc->sc_gc, 406 sc->sc_height, 407 (int)(sc->sc_vram_size / (bus_size_t)sc->sc_stride) - sc->sc_height, 408 sc->sc_width, 409 ri->ri_font->fontwidth, 410 ri->ri_font->fontheight, 411 defattr); 412 #endif 413 414 if (sc->sc_depth == 8) 415 mgafb_init_default_cmap(sc); 416 vcons_redraw_screen(&sc->sc_console_screen); 417 418 if (console) { 419 wsdisplay_cnattach(&sc->sc_defaultscreen_descr, ri, 0, 0, 420 defattr); 421 422 vcons_replay_msgbuf(&sc->sc_console_screen); 423 } 424 425 #ifdef MGAFB_ACCEL 426 aprint_normal_dev(sc->sc_dev, 427 "glyph cache at VRAM offset 0x%x (%d lines, %d cells)\n", 428 sc->sc_height * sc->sc_stride, 429 sc->sc_gc.gc_lines, 430 sc->sc_gc.gc_numcells); 431 #endif 432 433 if (!console && sc->sc_depth == 8) 434 mgafb_init_default_cmap(sc); 435 436 ws_aa.console = console; 437 ws_aa.scrdata = &sc->sc_screenlist; 438 ws_aa.accessops = &mgafb_accessops; 439 ws_aa.accesscookie = &sc->vd; 440 441 config_found(sc->sc_dev, &ws_aa, wsemuldisplaydevprint, CFARGS_NONE); 442 } 443 444 static void 445 mgafb_dac_write(struct mgafb_softc *sc, uint8_t reg, uint8_t val) 446 { 447 MGA_WRITE1(sc, MGA_DAC_BASE + reg, val); 448 } 449 450 static uint8_t 451 mgafb_dac_read(struct mgafb_softc *sc, uint8_t reg) 452 { 453 return MGA_READ1(sc, MGA_DAC_BASE + reg); 454 } 455 456 static void 457 mgafb_dac_write_ind(struct mgafb_softc *sc, uint8_t idx, uint8_t val) 458 { 459 mgafb_dac_write(sc, MGA_DAC_IND_INDEX, idx); 460 mgafb_dac_write(sc, MGA_DAC_IND_DATA, val); 461 } 462 463 static uint8_t 464 mgafb_dac_read_ind(struct mgafb_softc *sc, uint8_t idx) 465 { 466 mgafb_dac_write(sc, MGA_DAC_IND_INDEX, idx); 467 return mgafb_dac_read(sc, MGA_DAC_IND_DATA); 468 } 469 470 static void 471 mgafb_i2cbb_set_bits(void *cookie, uint32_t bits) 472 { 473 struct mgafb_softc *sc = cookie; 474 475 /* CTL: 1 = drive LOW (assert), 0 = release HIGH. */ 476 sc->sc_ddc_ctl &= ~(MGA_DDC_SDA | MGA_DDC_SCL); 477 sc->sc_ddc_ctl |= (~bits) & (MGA_DDC_SDA | MGA_DDC_SCL); 478 mgafb_dac_write_ind(sc, MGA_TVP_GEN_IO_CTL, sc->sc_ddc_ctl); 479 480 /* DATA: mirror desired state (1 = HIGH, 0 = LOW). */ 481 mgafb_dac_write_ind(sc, MGA_TVP_GEN_IO_DATA, 482 (uint8_t)bits & (MGA_DDC_SDA | MGA_DDC_SCL)); 483 } 484 485 static void 486 mgafb_i2cbb_set_dir(void *cookie, uint32_t dir) 487 { 488 /* Nothing to do. */ 489 } 490 491 static uint32_t 492 mgafb_i2cbb_read_bits(void *cookie) 493 { 494 struct mgafb_softc *sc = cookie; 495 496 return mgafb_dac_read_ind(sc, MGA_TVP_GEN_IO_DATA); 497 } 498 499 static int 500 mgafb_i2c_send_start(void *cookie, int flags) 501 { 502 return i2c_bitbang_send_start(cookie, flags, &mgafb_i2cbb_ops); 503 } 504 505 static int 506 mgafb_i2c_send_stop(void *cookie, int flags) 507 { 508 return i2c_bitbang_send_stop(cookie, flags, &mgafb_i2cbb_ops); 509 } 510 511 static int 512 mgafb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 513 { 514 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &mgafb_i2cbb_ops); 515 } 516 517 static int 518 mgafb_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 519 { 520 return i2c_bitbang_read_byte(cookie, valp, flags, &mgafb_i2cbb_ops); 521 } 522 523 static int 524 mgafb_i2c_write_byte(void *cookie, uint8_t val, int flags) 525 { 526 return i2c_bitbang_write_byte(cookie, val, flags, &mgafb_i2cbb_ops); 527 } 528 529 static void 530 mgafb_ddc_read(struct mgafb_softc *sc) 531 { 532 int i; 533 534 /* Release both lines to idle-HIGH before starting the controller. */ 535 sc->sc_ddc_ctl = mgafb_dac_read_ind(sc, MGA_TVP_GEN_IO_CTL); 536 sc->sc_ddc_ctl &= ~(MGA_DDC_SDA | MGA_DDC_SCL); 537 mgafb_dac_write_ind(sc, MGA_TVP_GEN_IO_CTL, sc->sc_ddc_ctl); 538 539 iic_tag_init(&sc->sc_i2c); 540 sc->sc_i2c.ic_cookie = sc; 541 sc->sc_i2c.ic_send_start = mgafb_i2c_send_start; 542 sc->sc_i2c.ic_send_stop = mgafb_i2c_send_stop; 543 sc->sc_i2c.ic_initiate_xfer = mgafb_i2c_initiate_xfer; 544 sc->sc_i2c.ic_read_byte = mgafb_i2c_read_byte; 545 sc->sc_i2c.ic_write_byte = mgafb_i2c_write_byte; 546 547 /* Some monitors don't respond on the first attempt. */ 548 sc->sc_edid_valid = false; 549 memset(sc->sc_edid, 0, sizeof(sc->sc_edid)); 550 for (i = 0; i < 3; i++) { 551 if (ddc_read_edid(&sc->sc_i2c, sc->sc_edid, 128) == 0 && 552 sc->sc_edid[1] != 0) 553 break; 554 memset(sc->sc_edid, 0, sizeof(sc->sc_edid)); 555 } 556 557 if (sc->sc_edid[1] == 0) { 558 aprint_normal_dev(sc->sc_dev, "DDC: no EDID response\n"); 559 return; 560 } 561 562 if (edid_parse(sc->sc_edid, &sc->sc_edid_info) == -1) { 563 aprint_error_dev(sc->sc_dev, 564 "DDC: EDID parse failed (bad header or checksum)\n"); 565 return; 566 } 567 568 sc->sc_edid_valid = true; 569 edid_print(&sc->sc_edid_info); 570 } 571 572 #ifdef MGAFB_PINS 573 /* 574 * This now sort of works for PInS v1, but needs a rewrite and support 575 * for later PInS versions. 576 */ 577 static void 578 mgafb_read_pins(struct mgafb_softc *sc, const struct pci_attach_args *pa) 579 { 580 bus_space_tag_t romt; 581 bus_space_handle_t romh; 582 bus_size_t rom_size; 583 bool rom_mapped = false; /* true if we called pci_mapreg_map */ 584 pcireg_t saved_rombar; 585 bool rom_bar_programmed = false; 586 uint32_t opt; 587 pcireg_t rombar; 588 uint16_t pins_off; 589 uint16_t rom_magic; 590 uint8_t pins_ver, pins_vcosel; 591 uint16_t pins_maxdac_raw, pins_syspll; 592 593 sc->sc_pins_valid = false; 594 sc->sc_pins_mclk_khz = 0; 595 sc->sc_pins_maxdac_khz = 0; 596 597 opt = pci_conf_read(sc->sc_pc, sc->sc_pcitag, MGA_PCI_OPTION); 598 if ((opt & MGA_OPTION_BIOSEN) == 0) { 599 aprint_error_dev(sc->sc_dev, 600 "PInS: BIOS ROM disabled (biosen=0 in OPTION 0x%08x)\n", 601 opt); 602 return; 603 } 604 605 rombar = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM); 606 saved_rombar = rombar; 607 aprint_verbose_dev(sc->sc_dev, 608 "PInS: ROM BAR = 0x%08x (enable=%d)\n", 609 rombar, (rombar & PCI_MAPREG_ROM_ENABLE) ? 1 : 0); 610 611 if ((rombar & PCI_MAPREG_ROM_ADDR_MASK) == 0) { 612 /* 613 * ROM BAR was not configured. Temporarily point 614 * the ROM BAR at the framebuffer aperture the 2064W spec 615 * says BIOS EPROM has highest decode precedence when 616 * apertures overlap. 617 */ 618 aprint_verbose_dev(sc->sc_dev, 619 "PInS: ROM BAR unassigned, borrowing FB " 620 "address 0x%08lx\n", 621 (unsigned long)sc->sc_fb_pa); 622 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 623 PCI_MAPREG_ROM, 624 (sc->sc_fb_pa & PCI_MAPREG_ROM_ADDR_MASK) | 625 PCI_MAPREG_ROM_ENABLE); 626 rom_bar_programmed = true; 627 628 /* Read through the existing FB mapping. */ 629 romt = sc->sc_fbt; 630 romh = sc->sc_fbh; 631 rom_size = sc->sc_fb_size; 632 } else { 633 /* 634 * ROM BAR has an address assigned by firmware. 635 * Map it normally. 636 */ 637 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, 638 PCI_MAPREG_TYPE_ROM, BUS_SPACE_MAP_PREFETCHABLE, 639 &romt, &romh, NULL, &rom_size) != 0) { 640 aprint_error_dev(sc->sc_dev, 641 "PInS: cannot map expansion ROM\n"); 642 return; 643 } 644 rom_mapped = true; 645 } 646 647 /* 648 * Old Matrox ROM may (or may not) have PCIR headers that don't 649 * match the PCI device ID or class code... 650 */ 651 rom_magic = bus_space_read_1(romt, romh, 0) | 652 ((uint16_t)bus_space_read_1(romt, romh, 1) << 8); 653 if (rom_magic != 0xAA55) { 654 aprint_error_dev(sc->sc_dev, 655 "PInS: ROM header magic 0x%04x (expected 0xAA55)\n", 656 rom_magic); 657 goto out_cleanup; 658 } 659 660 if (rom_size < 0x8000) { 661 aprint_normal_dev(sc->sc_dev, 662 "PInS: ROM too small for PInS (%zu bytes)\n", 663 (size_t)rom_size); 664 goto out_cleanup; 665 } 666 667 pins_off = bus_space_read_1(romt, romh, 0x7FFC); 668 pins_off |= (uint16_t)bus_space_read_1(romt, romh, 0x7FFD) << 8; 669 670 if (pins_off < 2 || pins_off >= 0x8000) { 671 aprint_normal_dev(sc->sc_dev, 672 "PInS: pointer out of range (0x%04x)\n", pins_off); 673 goto out_cleanup; 674 } 675 676 aprint_verbose_dev(sc->sc_dev, 677 "PInS: pointer at 0x7FFC = 0x%04x, first 4 bytes at offset:" 678 " %02x %02x %02x %02x\n", pins_off, 679 bus_space_read_1(romt, romh, pins_off + 0), 680 bus_space_read_1(romt, romh, pins_off + 1), 681 bus_space_read_1(romt, romh, pins_off + 2), 682 bus_space_read_1(romt, romh, pins_off + 3)); 683 684 if (bus_space_read_1(romt, romh, pins_off + 0) == 0x2E && 685 bus_space_read_1(romt, romh, pins_off + 1) == 0x41) { 686 pins_ver = bus_space_read_1(romt, romh, pins_off + 5); 687 aprint_verbose_dev(sc->sc_dev, 688 "PInS: version %u format at offset 0x%04x\n", 689 pins_ver, pins_off); 690 691 pins_vcosel = bus_space_read_1(romt, romh, pins_off + 41); 692 sc->sc_pins_maxdac_khz = ((uint32_t)pins_vcosel + 100) * 1000; 693 694 pins_vcosel = bus_space_read_1(romt, romh, pins_off + 43); 695 if (pins_vcosel != 0 && 696 ((uint32_t)pins_vcosel + 100) * 1000 >= 100000) { 697 sc->sc_pins_mclk_khz = 698 ((uint32_t)pins_vcosel + 100) * 1000; 699 } 700 701 sc->sc_pins_valid = true; 702 703 } else if (bus_space_read_1(romt, romh, pins_off + 0) == 64 && 704 bus_space_read_1(romt, romh, pins_off + 1) == 0x00) { 705 aprint_normal_dev(sc->sc_dev, 706 "PInS: version 1 format at offset 0x%04x\n", pins_off); 707 708 pins_vcosel = bus_space_read_1(romt, romh, pins_off + 22); 709 pins_maxdac_raw = bus_space_read_1(romt, romh, pins_off + 24); 710 pins_maxdac_raw |= 711 (uint16_t)bus_space_read_1(romt, romh, pins_off + 25) << 8; 712 pins_syspll = bus_space_read_1(romt, romh, pins_off + 28); 713 pins_syspll |= 714 (uint16_t)bus_space_read_1(romt, romh, pins_off + 29) << 8; 715 716 switch (pins_vcosel) { 717 case 0: 718 sc->sc_pins_maxdac_khz = 175000; 719 break; 720 case 1: 721 sc->sc_pins_maxdac_khz = 220000; 722 break; 723 default: 724 /* Undefined value use conservative maximum. */ 725 sc->sc_pins_maxdac_khz = pins_maxdac_raw ? 726 (uint32_t)pins_maxdac_raw * 10 : 240000; 727 break; 728 } 729 730 sc->sc_pins_mclk_khz = pins_syspll ? 731 (uint32_t)pins_syspll * 10 : 50000; 732 733 sc->sc_pins_valid = true; 734 735 } else { 736 aprint_normal_dev(sc->sc_dev, 737 "PInS: unrecognised header at offset 0x%04x " 738 "(bytes 0x%02x 0x%02x)\n", pins_off, 739 bus_space_read_1(romt, romh, pins_off + 0), 740 bus_space_read_1(romt, romh, pins_off + 1)); 741 } 742 743 out_cleanup: 744 if (rom_mapped) 745 bus_space_unmap(romt, romh, rom_size); 746 747 /* 748 * Restore the ROM BAR. If we borrowed the FB address, write 749 * back the original (unassigned) value. Otherwise just clear 750 * ROM enable so the ROM stops decoding. 751 */ 752 if (rom_bar_programmed) 753 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 754 PCI_MAPREG_ROM, saved_rombar); 755 else 756 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 757 pci_conf_read(sc->sc_pc, sc->sc_pcitag, 758 PCI_MAPREG_ROM) & ~PCI_MAPREG_ROM_ENABLE); 759 } 760 761 static void 762 mgafb_dump_pins(struct mgafb_softc *sc) 763 { 764 if (!sc->sc_pins_valid) { 765 aprint_normal_dev 766 (sc->sc_dev, 767 "PInS: not available (ROM absent, unreadable, or format 2+)\n"); 768 return; 769 } 770 aprint_normal_dev(sc->sc_dev, 771 "PInS: MCLK %u kHz, max pixel clock %u kHz\n", 772 sc->sc_pins_mclk_khz, sc->sc_pins_maxdac_khz); 773 } 774 #endif /* MGAFB_PINS */ 775 776 #ifndef MGAFB_NO_HW_INIT 777 static void 778 mgafb_preinit_wram(struct mgafb_softc *sc) 779 { 780 uint32_t opt; 781 782 aprint_verbose_dev(sc->sc_dev, "WRAM init: stabilising MEMPLLCTRL\n"); 783 784 /* Stabilise MEMPLLCTRL before toggling reset. */ 785 mgafb_dac_write_ind(sc, MGA_TVP_MEMPLLCTRL, 786 MGA_TVP_MEMPLLCTRL_STROBEMKC4 | MGA_TVP_MEMPLLCTRL_MCLK_MCLKPLL); 787 delay(200); 788 789 /* WRAM controller reset */ 790 if (sc->sc_chip == MGAFB_CHIP_2164W) { 791 /* Use RST.softreset */ 792 aprint_verbose_dev(sc->sc_dev, 793 "2164W WRAM init: asserting softreset\n"); 794 MGA_WRITE4(sc, MGA_RST, 1); 795 delay(200); 796 MGA_WRITE4(sc, MGA_RST, 0); 797 aprint_verbose_dev(sc->sc_dev, 798 "2164W WRAM init: softreset deasserted\n"); 799 delay(200); 800 801 /* Program rfhcnt to a safe initial value. */ 802 opt = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 803 MGA_PCI_OPTION); 804 opt &= ~MGA_OPTION_RFHCNT_MASK; 805 opt |= (8U << MGA_OPTION_RFHCNT_SHIFT) & 806 MGA_OPTION_RFHCNT_MASK; 807 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 808 MGA_PCI_OPTION, opt); 809 delay(250); 810 } else { 811 /* Use M_RESET to reset the WRAM controller. */ 812 aprint_verbose_dev(sc->sc_dev, 813 "2064W WRAM init: asserting M_RESET\n"); 814 opt = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 815 MGA_PCI_OPTION); 816 pci_conf_write(sc->sc_pc, sc->sc_pcitag, MGA_PCI_OPTION, 817 opt | MGA_OPTION_M_RESET); 818 delay(250); 819 820 /* Deassert M_RESET. */ 821 pci_conf_write(sc->sc_pc, sc->sc_pcitag, MGA_PCI_OPTION, 822 opt & ~MGA_OPTION_M_RESET); 823 aprint_verbose_dev(sc->sc_dev, 824 "2064W WRAM init: M_RESET deasserted\n"); 825 delay(250); 826 } 827 828 /* Trigger WRAM initialisation cycle */ 829 aprint_verbose_dev(sc->sc_dev, "WRAM init: triggering init cycle\n"); 830 MGA_WRITE4(sc, MGA_MACCESS, MGA_MACCESS_WRAM_INIT); 831 delay(10); 832 833 aprint_verbose_dev(sc->sc_dev, "WRAM init: complete\n"); 834 } 835 836 static void 837 mgafb_set_mclk(struct mgafb_softc *sc, int freq_khz) 838 { 839 uint8_t pclk_n, pclk_m, pclk_p; 840 uint8_t n, m, p; 841 uint8_t mclk_ctl; 842 int fvco_khz, rfhcnt, i; 843 uint32_t opt; 844 845 aprint_verbose_dev(sc->sc_dev, "MCLK: programming to %d kHz\n", 846 freq_khz); 847 848 (void)freq_khz; /* only 50000 kHz supported for now */ 849 850 n = 52; 851 m = 42; 852 p = 2; 853 fvco_khz = 8 * MGA_TVP_REFCLK * (65 - m) / (65 - n); 854 855 /* Save current PCLK N/M/P from TVP3026 regs. */ 856 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, MGA_TVP_PLLADDR_PCLK_N); 857 pclk_n = mgafb_dac_read_ind(sc, MGA_TVP_PLLDATA); 858 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, MGA_TVP_PLLADDR_PCLK_M); 859 pclk_m = mgafb_dac_read_ind(sc, MGA_TVP_PLLDATA); 860 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, MGA_TVP_PLLADDR_PCLK_STOP); 861 pclk_p = mgafb_dac_read_ind(sc, MGA_TVP_PLLDATA); 862 863 /* Stop PCLK. */ 864 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, MGA_TVP_PLLADDR_PCLK_STOP); 865 mgafb_dac_write_ind(sc, MGA_TVP_PLLDATA, 0x00); 866 867 /* Temporarily set PCLK to target MCLK frequency. */ 868 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, MGA_TVP_PLLADDR_PCLK_START); 869 mgafb_dac_write_ind(sc, MGA_TVP_PLLDATA, 0xC0 | n); /* N at 0x00 */ 870 mgafb_dac_write_ind(sc, MGA_TVP_PLLDATA, m); /* M at 0x01 */ 871 mgafb_dac_write_ind(sc, MGA_TVP_PLLDATA, 0xB0 | p); /* P at 0x02; PLL restarts */ 872 873 /* Wait for temporary PCLK to lock. */ 874 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, MGA_TVP_PLLADDR_ALL_STATUS); 875 for (i = 0; i < 10000; i++) { 876 if (mgafb_dac_read_ind(sc, MGA_TVP_PLLDATA) & 877 MGA_TVP_PLL_LOCKED) 878 break; 879 delay(10); 880 } 881 if (i == 10000) 882 aprint_error_dev(sc->sc_dev, 883 "MCLK: timeout waiting for temporary PCLK lock\n"); 884 else 885 aprint_verbose_dev 886 (sc->sc_dev, 887 "MCLK: temporary PCLK locked after %d polls\n", i); 888 889 /* Route temp PCLK to MCLK */ 890 mclk_ctl = mgafb_dac_read_ind(sc, MGA_TVP_MEMPLLCTRL); 891 aprint_normal_dev(sc->sc_dev, 892 "MCLK: MEMPLLCTRL was 0x%02x, routing PCLK to MCLK\n", mclk_ctl); 893 mgafb_dac_write_ind(sc, MGA_TVP_MEMPLLCTRL, 894 mclk_ctl & 0xe7); /* clear bits[4:3]: source=PIXPLL, strobe=0 */ 895 mgafb_dac_write_ind(sc, MGA_TVP_MEMPLLCTRL, 896 (mclk_ctl & 0xe7) | 0x08); /* set strobe to latch PIXPLL routing */ 897 delay(1000); 898 aprint_verbose_dev(sc->sc_dev, "MCLK: PIXPLL routing latched\n"); 899 900 /* Stop MCLK PLL. */ 901 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, MGA_TVP_PLLADDR_MCLK_STOP); 902 mgafb_dac_write_ind(sc, MGA_TVP_MEMPLLDATA, 0x00); 903 aprint_verbose_dev(sc->sc_dev, "MCLK: PLL stopped\n"); 904 905 /* Program MCLK PLL with target N/M/P. */ 906 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, MGA_TVP_PLLADDR_MCLK_START); 907 mgafb_dac_write_ind(sc, MGA_TVP_MEMPLLDATA, 0xC0 | n); 908 mgafb_dac_write_ind(sc, MGA_TVP_MEMPLLDATA, m); 909 mgafb_dac_write_ind(sc, MGA_TVP_MEMPLLDATA, 0xB0 | p); 910 aprint_verbose_dev(sc->sc_dev, "MCLK: PLL programmed N=%u M=%u P=%u\n", 911 n, m, p); 912 913 /* Wait for MCLK PLL to lock. */ 914 for (i = 0; i < 10000; i++) { 915 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, 916 MGA_TVP_PLLADDR_ALL_STATUS); 917 if (mgafb_dac_read_ind(sc, MGA_TVP_MEMPLLDATA) & 918 MGA_TVP_PLL_LOCKED) 919 break; 920 delay(10); 921 } 922 if (i == 10000) 923 aprint_error_dev(sc->sc_dev, 924 "MCLK: timeout waiting for MCLK PLL lock\n"); 925 else 926 aprint_verbose_dev(sc->sc_dev, 927 "MCLK: PLL locked after %d polls\n", i); 928 929 /* Update WRAM refresh counter. */ 930 rfhcnt = (fvco_khz * 333 / (10000 * (1 << p)) - 64) / 128; 931 if (rfhcnt < 0) 932 rfhcnt = 0; 933 if (rfhcnt > 15) 934 rfhcnt = 15; 935 936 opt = pci_conf_read(sc->sc_pc, sc->sc_pcitag, MGA_PCI_OPTION); 937 opt &= ~MGA_OPTION_RFHCNT_MASK; 938 opt |= ((uint32_t)rfhcnt << MGA_OPTION_RFHCNT_SHIFT) & 939 MGA_OPTION_RFHCNT_MASK; 940 pci_conf_write(sc->sc_pc, sc->sc_pcitag, MGA_PCI_OPTION, opt); 941 aprint_normal_dev(sc->sc_dev, 942 "MCLK: Fvco=%d kHz Fpll=%d kHz rfhcnt=%d\n", 943 fvco_khz, fvco_khz / (1 << p), rfhcnt); 944 945 /* Switch MCLK source to MCLK PLL. */ 946 mgafb_dac_write_ind(sc, MGA_TVP_MEMPLLCTRL, 947 (mclk_ctl & 0xe7) | 0x10); /* source=MCLKPLL (bit4), strobe=0 */ 948 mgafb_dac_write_ind(sc, MGA_TVP_MEMPLLCTRL, 949 (mclk_ctl & 0xe7) | 0x18); /* set strobe to latch MCLKPLL routing */ 950 delay(1000); 951 952 /* Stop PCLK and restore its original N/M/P. */ 953 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, MGA_TVP_PLLADDR_PCLK_STOP); 954 mgafb_dac_write_ind(sc, MGA_TVP_PLLDATA, 0x00); 955 956 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, MGA_TVP_PLLADDR_PCLK_START); 957 mgafb_dac_write_ind(sc, MGA_TVP_PLLDATA, pclk_n); /* N at 0x00 */ 958 mgafb_dac_write_ind(sc, MGA_TVP_PLLDATA, pclk_m); /* M at 0x01 */ 959 mgafb_dac_write_ind(sc, MGA_TVP_PLLDATA, pclk_p); /* P at 0x02; PLL restarts */ 960 961 /* Lock check. */ 962 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, MGA_TVP_PLLADDR_ALL_STATUS); 963 for (i = 0; i < 10000; i++) { 964 if (mgafb_dac_read_ind(sc, MGA_TVP_PLLDATA) & 965 MGA_TVP_PLL_LOCKED) 966 break; 967 delay(10); 968 } 969 if (i == 10000) 970 aprint_error_dev(sc->sc_dev, 971 "MCLK: timeout waiting for PCLK relock\n"); 972 else 973 aprint_verbose_dev 974 (sc->sc_dev, 975 "MCLK: programming complete\n"); 976 } 977 978 static void 979 mgafb_preinit_1064sg(struct mgafb_softc *sc) 980 { 981 int i; 982 983 aprint_verbose_dev(sc->sc_dev, 984 "1064SG: writing OPTION register %lx\n", 985 MGA1064_OPTION_DEFAULT); 986 pci_conf_write(sc->sc_pc, sc->sc_pcitag, MGA_PCI_OPTION, 987 MGA1064_OPTION_DEFAULT); 988 delay(250); 989 990 /* System PLL with hardcoded values from xf86-video-mga... */ 991 aprint_verbose_dev(sc->sc_dev, "1064SG: programming system PLL\n"); 992 mgafb_dac_write_ind(sc, MGA_IDAC_SYS_PLL_M, 0x04); 993 mgafb_dac_write_ind(sc, MGA_IDAC_SYS_PLL_N, 0x44); 994 mgafb_dac_write_ind(sc, MGA_IDAC_SYS_PLL_P, 0x18); 995 996 for (i = 0; i < 10000; i++) { 997 if (mgafb_dac_read_ind(sc, MGA_IDAC_SYS_PLL_STAT) & 0x40) 998 break; 999 delay(10); 1000 } 1001 if (i == 10000) 1002 aprint_error_dev(sc->sc_dev, 1003 "1064SG: timeout waiting for system PLL lock\n"); 1004 else 1005 aprint_verbose_dev(sc->sc_dev, 1006 "1064SG: system PLL locked after %d polls\n", i); 1007 } 1008 #endif /* MGA_NO_HW_INIT */ 1009 1010 static void 1011 mgafb_detect_vram(struct mgafb_softc *sc) 1012 { 1013 volatile uint8_t *fb; 1014 bus_size_t probe_max; 1015 bus_size_t vram_bytes; 1016 bus_size_t off; 1017 uint8_t saved_crtcext3; 1018 uint32_t opt; 1019 1020 if (!sc->sc_ci->ci_probe_vram) { 1021 sc->sc_vram_size = sc->sc_ci->ci_vram_default; 1022 aprint_normal_dev(sc->sc_dev, 1023 "%zu MB VRAM assumed (%s)\n", 1024 (size_t)(sc->sc_vram_size / (1024*1024)), 1025 sc->sc_ci->ci_name); 1026 return; 1027 } 1028 1029 probe_max = (bus_size_t)8*1024*1024; 1030 if (probe_max > sc->sc_fb_size) 1031 probe_max = sc->sc_fb_size; 1032 1033 fb = bus_space_vaddr(sc->sc_fbt, sc->sc_fbh); 1034 if (fb == NULL) { 1035 aprint_error_dev(sc->sc_dev, 1036 "VRAM probe: bus_space_vaddr failed; assuming 2 MB\n"); 1037 sc->sc_vram_size = 2*1024*1024; 1038 return; 1039 } 1040 1041 MGA_WRITE1(sc, MGA_CRTCEXT_INDEX, 3); 1042 saved_crtcext3 = MGA_READ1(sc, MGA_CRTCEXT_DATA); 1043 MGA_WRITE1(sc, MGA_CRTCEXT_INDEX, 3); 1044 MGA_WRITE1(sc, MGA_CRTCEXT_DATA, saved_crtcext3 | MGA_CRTCEXT3_MGAMODE); 1045 1046 for (off = probe_max; off > (bus_size_t)2*1024*1024; 1047 off -= (bus_size_t)2*1024*1024) 1048 fb[off - 1] = 0xAA; 1049 1050 /* Ensure probe writes have reached VRAM before read-back. */ 1051 bus_space_barrier(sc->sc_fbt, sc->sc_fbh, 0, probe_max, 1052 BUS_SPACE_BARRIER_WRITE); 1053 1054 /* Cache flush. */ 1055 MGA_WRITE1(sc, MGA_VGA_CRTC_INDEX, 0); 1056 delay(10); 1057 1058 /* Ensure we read actual VRAM, not stale CPU cache lines. */ 1059 bus_space_barrier(sc->sc_fbt, sc->sc_fbh, 0, probe_max, 1060 BUS_SPACE_BARRIER_READ); 1061 1062 vram_bytes = (bus_size_t)2*1024*1024; 1063 for (off = probe_max; off > (bus_size_t)2*1024*1024; 1064 off -= (bus_size_t)2*1024*1024) { 1065 if (fb[off - 1] == 0xAA) { 1066 vram_bytes = off; 1067 break; 1068 } 1069 } 1070 1071 sc->sc_vram_size = vram_bytes; 1072 1073 if (sc->sc_ci->ci_has_wram) 1074 aprint_normal_dev(sc->sc_dev, 1075 "%zu MB VRAM detected (%s WRAM bus)\n", 1076 (size_t)(vram_bytes / (1024*1024)), 1077 vram_bytes > (bus_size_t)2*1024*1024 ? 1078 "64-bit" : "32-bit"); 1079 else 1080 aprint_normal_dev(sc->sc_dev, 1081 "%zu MB VRAM detected (SGRAM)\n", 1082 (size_t)(vram_bytes / (1024*1024))); 1083 1084 MGA_WRITE1(sc, MGA_CRTCEXT_INDEX, 3); 1085 MGA_WRITE1(sc, MGA_CRTCEXT_DATA, saved_crtcext3); 1086 1087 /* 1088 * Set interleave bit (2064W only OPTION bit 12). 1089 * Other chips either lack this bit or use SGRAM. 1090 */ 1091 if (sc->sc_chip == MGAFB_CHIP_2064W) { 1092 opt = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 1093 MGA_PCI_OPTION); 1094 opt &= ~MGA_OPTION_INTERLEAVE; 1095 if (vram_bytes > (bus_size_t)2*1024*1024) 1096 opt |= MGA_OPTION_INTERLEAVE; 1097 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 1098 MGA_PCI_OPTION, opt); 1099 } 1100 } 1101 1102 static void 1103 mgafb_calc_pll(int target_khz, uint8_t *n_out, uint8_t *m_out, uint8_t *p_out) 1104 { 1105 int p, m, n, fvco, fpll, err; 1106 int best_err, best_n, best_m, best_p; 1107 1108 /* 1109 * Millenium I comes with two variants of DACs - we should detect it. 1110 * 175MHz DAC can do 220MHz VCO, 250MHz DAC can do 250MHz VCO. 1111 */ 1112 const int fvco_min = 110000; 1113 const int fvco_max = 220000; 1114 1115 /* 1116 * Init 65 MHz pixel clock. 1117 */ 1118 best_err = target_khz + 1; 1119 best_n = 43; 1120 best_m = 40; 1121 best_p = 1; 1122 1123 for (p = 3; p >= 0; p--) { 1124 for (m = 1; m <= 62; m++) { 1125 for (n = 1; n <= 62; n++) { 1126 fvco = 8 * MGA_TVP_REFCLK * (65 - m) / (65 - n); 1127 if (fvco < fvco_min || fvco > fvco_max) 1128 continue; 1129 fpll = fvco >> p; 1130 err = fpll - target_khz; 1131 if (err < 0) 1132 err = -err; 1133 if (err < best_err) { 1134 best_err = err; 1135 best_n = n; 1136 best_m = m; 1137 best_p = p; 1138 } 1139 } 1140 } 1141 } 1142 1143 *n_out = (uint8_t)best_n; 1144 *m_out = (uint8_t)best_m; 1145 *p_out = (uint8_t)best_p; 1146 } 1147 1148 static void 1149 mgafb_calc_pll_1064sg(int target_khz, uint8_t *m_out, uint8_t *n_out, 1150 uint8_t *p_out) 1151 { 1152 int m, n, p, s; 1153 int best_m, best_n, best_p; 1154 int best_err; 1155 int fvco, fpll, err; 1156 int f_vco_target; 1157 static const int pvals[] = { 0, 1, 3, 7 }; 1158 1159 best_m = 1; 1160 best_n = 100; 1161 best_p = 0; 1162 best_err = target_khz + 1; 1163 1164 /* 1165 * Find P such that Fvco = target * (P+1) >= 50 MHz. 1166 */ 1167 f_vco_target = target_khz; 1168 for (p = 0; p <= 3; p++) { 1169 if (f_vco_target >= 50000) 1170 break; 1171 f_vco_target *= 2; 1172 } 1173 p = pvals[p > 3 ? 3 : p]; 1174 1175 for (m = 1; m <= 31; m++) { 1176 for (n = 100; n <= 127; n++) { 1177 fvco = MGA_IDAC_REFCLK * (n + 1) / (m + 1); 1178 if (fvco < 50000 || fvco > 220000) 1179 continue; 1180 fpll = fvco / (p + 1); 1181 err = fpll - target_khz; 1182 if (err < 0) 1183 err = -err; 1184 if (err < best_err) { 1185 best_err = err; 1186 best_m = m; 1187 best_n = n; 1188 best_p = p; 1189 } 1190 } 1191 } 1192 1193 /* S value for loop filter bandwidth. */ 1194 fvco = MGA_IDAC_REFCLK * (best_n + 1) / (best_m + 1); 1195 if (fvco < 100000) 1196 s = 0; 1197 else if (fvco < 140000) 1198 s = 1; 1199 else if (fvco < 180000) 1200 s = 2; 1201 else 1202 s = 3; 1203 1204 *m_out = (uint8_t)(best_m & 0x1F); 1205 *n_out = (uint8_t)(best_n & 0x7F); 1206 *p_out = (uint8_t)((best_p & 0x07) | ((s & 0x03) << 3)); 1207 } 1208 1209 /* 1210 * Resolve PCI BAR assignments for control and framebuffer apertures. 1211 * Layout varies by chip and sometimes by PCI revision. 1212 */ 1213 static void 1214 mgafb_resolve_bars(struct mgafb_softc *sc, const struct pci_attach_args *pa, 1215 int *regbar, int *fbbar) 1216 { 1217 1218 if (sc->sc_chip == MGAFB_CHIP_2164W || 1219 (sc->sc_chip == MGAFB_CHIP_1064SG && 1220 PCI_REVISION(pa->pa_class) >= 3)) { 1221 *fbbar = MILL2_BAR_FB; 1222 *regbar = MILL2_BAR_REG; 1223 } else { 1224 *fbbar = MILL_BAR_FB; 1225 *regbar = MILL_BAR_REG; 1226 } 1227 } 1228 1229 /* 1230 * Compute CRTCEXT3 scale bits based on memory bus width and pixel depth. 1231 * 1064SG always has a 32-bit SGRAM bus (narrow). 1232 * 2064W with <= 2MB WRAM has a 32-bit bus (narrow). 1233 * 2064W with > 2MB / 2164W has a 64-bit bus (wide). 1234 */ 1235 static uint8_t 1236 mgafb_crtcext3_scale(struct mgafb_softc *sc) 1237 { 1238 bool is_narrow; 1239 1240 is_narrow = !sc->sc_ci->ci_has_wram || 1241 sc->sc_vram_size <= (bus_size_t)2*1024*1024; 1242 1243 if (sc->sc_depth == 8) 1244 return is_narrow ? 0x01 : 0x00; 1245 else 1246 return is_narrow ? 0x03 : 0x01; 1247 } 1248 1249 static void 1250 mgafb_calc_crtc(const struct videomode *vm, int depth, bool interleave, 1251 uint8_t crtc_out[25], uint8_t crtcext_out[6], 1252 uint8_t *misc_out, uint8_t *vsyncpol_out) 1253 { 1254 int hd, hs, he, ht; 1255 int vd, vs, ve, vt; 1256 int wd; /* logical scanline width */ 1257 1258 hd = (vm->hdisplay >> 3) - 1; 1259 hs = (vm->hsync_start >> 3) - 1; 1260 he = (vm->hsync_end >> 3) - 1; 1261 ht = (vm->htotal >> 3) - 1; 1262 1263 vd = vm->vdisplay - 1; 1264 vs = vm->vsync_start; 1265 ve = vm->vsync_end; 1266 vt = vm->vtotal - 2; 1267 1268 /* 1269 * HTOTAL workaround, round up as a precaution. 1270 */ 1271 if ((ht & 0x07) == 0x06 || (ht & 0x07) == 0x04) 1272 ht++; 1273 1274 wd = vm->hdisplay * (depth / 8) / (interleave ? 16 : 8); 1275 1276 *misc_out = 0xEF; 1277 1278 if ((vm->flags & (VID_PHSYNC | VID_NHSYNC)) && 1279 (vm->flags & (VID_PVSYNC | VID_NVSYNC))) { 1280 *vsyncpol_out = 0; 1281 if (vm->flags & VID_PHSYNC) 1282 *vsyncpol_out |= 0x01; 1283 if (vm->flags & VID_PVSYNC) 1284 *vsyncpol_out |= 0x02; 1285 } else { 1286 if (vm->vdisplay < 400) *vsyncpol_out = 0x01; /* +H -V */ 1287 else if (vm->vdisplay < 480) *vsyncpol_out = 0x02; /* -H +V */ 1288 else if (vm->vdisplay < 768) *vsyncpol_out = 0x00; /* -H -V */ 1289 else *vsyncpol_out = 0x03; /* +H +V */ 1290 } 1291 1292 memset(crtc_out, 0, 25); 1293 1294 crtc_out[0] = (uint8_t)(ht - 4); /* CR00: HTotal */ 1295 crtc_out[1] = (uint8_t)hd; /* CR01: HDispEnd */ 1296 crtc_out[2] = (uint8_t)hd; /* CR02: HBlankStart = HDE */ 1297 crtc_out[3] = (uint8_t)((ht & 0x1F) | 0x80); /* CR03: HBlankEnd[4:0] */ 1298 crtc_out[4] = (uint8_t)hs; /* CR04: HSyncStart */ 1299 crtc_out[5] = (uint8_t)(((ht & 0x20) << 2) | /* CR05: HBlankEnd[5] */ 1300 (he & 0x1F)); /* + HSyncEnd[4:0] */ 1301 crtc_out[6] = (uint8_t)(vt & 0xFF); /* CR06: VTotal[7:0] */ 1302 crtc_out[7] = (uint8_t)( /* CR07: Overflow */ 1303 ((vt & 0x100) >> 8) | /* bit0: VT[8] */ 1304 ((vd & 0x100) >> 7) | /* bit1: VDE[8] */ 1305 ((vs & 0x100) >> 6) | /* bit2: VRS[8] */ 1306 ((vd & 0x100) >> 5) | /* bit3: VBS[8] = VDE[8] */ 1307 0x10 | /* bit4: always 1 */ 1308 ((vt & 0x200) >> 4) | /* bit5: VT[9] */ 1309 ((vd & 0x200) >> 3) | /* bit6: VDE[9] */ 1310 ((vs & 0x200) >> 2)); /* bit7: VRS[9] */ 1311 /* crtc_out[8] = 0: CR08 PresetRowScan */ 1312 crtc_out[9] = (uint8_t)(((vd & 0x200) >> 4) | /* CR09: MaxScanLine */ 1313 0x40); /* bit6: LineCompare[9] */ 1314 /* crtc_out[10..15] = 0: cursor / start address */ 1315 crtc_out[16] = (uint8_t)(vs & 0xFF); /* CR10: VSyncStart[7:0] */ 1316 crtc_out[17] = (uint8_t)((ve & 0x0F) | 0x20); /* CR11: VSyncEnd[3:0] */ 1317 crtc_out[18] = (uint8_t)(vd & 0xFF); /* CR12: VDispEnd[7:0] */ 1318 crtc_out[19] = (uint8_t)(wd & 0xFF); /* CR13: Offset */ 1319 /* crtc_out[20] = 0: CR14 Underline */ 1320 crtc_out[21] = (uint8_t)(vd & 0xFF); /* CR15: VBlankStart[7:0] */ 1321 crtc_out[22] = (uint8_t)((vt + 1) & 0xFF); /* CR16: VBlankEnd */ 1322 crtc_out[23] = 0xC3; /* CR17: byte mode */ 1323 crtc_out[24] = 0xFF; /* CR18: LineCompare */ 1324 1325 memset(crtcext_out, 0, 6); 1326 1327 crtcext_out[0] = (uint8_t)((wd & 0x300) >> 4); 1328 crtcext_out[1] = (uint8_t)( 1329 (((ht - 4) & 0x100) >> 8) | 1330 ((hd & 0x100) >> 7) | 1331 ((hs & 0x100) >> 6) | 1332 (ht & 0x40)); 1333 crtcext_out[2] = (uint8_t)( 1334 ((vt & 0xC00) >> 10) | 1335 ((vd & 0x400) >> 8) | 1336 ((vd & 0xC00) >> 7) | 1337 ((vs & 0xC00) >> 5)); 1338 /* crtcext_out[3] left at 0; caller sets mgamode | scale */ 1339 } 1340 1341 static bool 1342 mgafb_mode_fits(struct mgafb_softc *sc, const struct videomode *vm) 1343 { 1344 uint32_t max_pclk_khz; 1345 1346 #ifdef MGAFB_PINS 1347 if (sc->sc_pins_valid) 1348 max_pclk_khz = sc->sc_pins_maxdac_khz; 1349 else 1350 #endif 1351 max_pclk_khz = sc->sc_ci->ci_max_pclk; 1352 1353 if ((uint32_t)vm->dot_clock > max_pclk_khz) 1354 return false; 1355 1356 if ((bus_size_t)vm->hdisplay * (bus_size_t)vm->vdisplay * 1357 (bus_size_t)(sc->sc_depth / 8) > sc->sc_vram_size) 1358 return false; 1359 1360 return true; 1361 } 1362 1363 static const struct videomode * 1364 mgafb_pick_mode(struct mgafb_softc *sc) 1365 { 1366 const struct videomode *mode, *m; 1367 prop_dictionary_t dict; 1368 uint32_t prop_w, prop_h; 1369 1370 /* Start with safe default. */ 1371 mode = pick_mode_by_ref(640, 480, 60); 1372 KASSERT(mode != NULL); 1373 1374 /* Read firmware params. */ 1375 dict = device_properties(sc->sc_dev); 1376 if (prop_dictionary_get_uint32(dict, "width", &prop_w) && 1377 prop_dictionary_get_uint32(dict, "height", &prop_h)) { 1378 m = pick_mode_by_ref((int)prop_w, (int)prop_h, 60); 1379 if (m != NULL && mgafb_mode_fits(sc, m)) { 1380 aprint_verbose_dev(sc->sc_dev, 1381 "mode: firmware resolution %ux%u\n", 1382 prop_w, prop_h); 1383 mode = m; 1384 } 1385 } 1386 1387 /* EDID preferred mode highest priority. */ 1388 if (sc->sc_edid_valid && 1389 sc->sc_edid_info.edid_preferred_mode != NULL) { 1390 m = sc->sc_edid_info.edid_preferred_mode; 1391 if (mgafb_mode_fits(sc, m)) { 1392 aprint_verbose_dev(sc->sc_dev, 1393 "mode: EDID preferred %dx%d (%d kHz)\n", 1394 m->hdisplay, m->vdisplay, m->dot_clock); 1395 mode = m; 1396 } else { 1397 aprint_verbose_dev(sc->sc_dev, 1398 "mode: EDID preferred %dx%d (%d kHz) exceeds " 1399 "hardware limits, ignoring\n", 1400 m->hdisplay, m->vdisplay, m->dot_clock); 1401 } 1402 } 1403 1404 return mode; 1405 } 1406 1407 /* 1408 * TVP3026 DAC register setup for the selected pixel depth. 1409 */ 1410 static void 1411 mgafb_tvp3026_setup_dac(struct mgafb_softc *sc, bool interleave) 1412 { 1413 1414 if (sc->sc_depth == 8) { 1415 mgafb_dac_write_ind(sc, MGA_TVP_COLORMODE, 0x06); 1416 mgafb_dac_write_ind(sc, MGA_TVP_PIXFMT, 0x80); 1417 mgafb_dac_write_ind(sc, MGA_TVP_CURCTL, 1418 interleave ? 0x4C : 0x4B); 1419 mgafb_dac_write_ind(sc, MGA_TVP_MUXCTL, 0x25); 1420 mgafb_dac_write_ind(sc, MGA_TVP_LUTBYPASS, 0x0C); 1421 mgafb_dac_write_ind(sc, MGA_TVP_KEY_CTL, 0x00); 1422 } else { 1423 mgafb_dac_write_ind(sc, MGA_TVP_COLORMODE, 0x07); 1424 mgafb_dac_write_ind(sc, MGA_TVP_PIXFMT, 0x05); 1425 mgafb_dac_write_ind(sc, MGA_TVP_CURCTL, 1426 interleave ? 0x54 : 0x53); 1427 mgafb_dac_write_ind(sc, MGA_TVP_MUXCTL, 0x15); 1428 mgafb_dac_write_ind(sc, MGA_TVP_LUTBYPASS, 0x24); 1429 } 1430 } 1431 1432 /* 1433 * Program the TVP3026 PCLK PLL and loop PLL (VCLK). 1434 */ 1435 static void 1436 mgafb_tvp3026_set_pclk(struct mgafb_softc *sc, int dot_clock, bool interleave) 1437 { 1438 uint8_t pll_n, pll_m, pll_p; 1439 uint8_t lclk_n, lclk_p, lclk_q; 1440 uint32_t lclk_z100, bus_bytes, lclk_65mn; 1441 int i; 1442 1443 mgafb_calc_pll(dot_clock, &pll_n, &pll_m, &pll_p); 1444 aprint_verbose_dev(sc->sc_dev, 1445 "mode: PLL N=%u M=%u P=%u (target %d kHz)\n", 1446 pll_n, pll_m, pll_p, dot_clock); 1447 1448 /* Disable both PLLs before reprogramming. */ 1449 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, 0x2A); 1450 mgafb_dac_write_ind(sc, MGA_TVP_LOOPPLLDATA, 0x00); 1451 mgafb_dac_write_ind(sc, MGA_TVP_PLLDATA, 0x00); 1452 1453 /* Program PCLK shadow registers. */ 1454 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, 1455 MGA_TVP_PLLADDR_PCLK_START); 1456 mgafb_dac_write_ind(sc, MGA_TVP_PLLDATA, 0xC0 | pll_n); 1457 mgafb_dac_write_ind(sc, MGA_TVP_PLLDATA, pll_m); 1458 mgafb_dac_write_ind(sc, MGA_TVP_PLLDATA, 0xB0 | pll_p); 1459 1460 /* Wait for PCLK lock. */ 1461 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, 1462 MGA_TVP_PLLADDR_ALL_STATUS); 1463 for (i = 0; i < 10000; i++) { 1464 if (mgafb_dac_read_ind(sc, MGA_TVP_PLLDATA) & 1465 MGA_TVP_PLL_LOCKED) 1466 break; 1467 delay(1); 1468 } 1469 if (i == 10000) 1470 aprint_error_dev(sc->sc_dev, 1471 "mode: timeout waiting for PCLK lock (%d kHz)\n", 1472 dot_clock); 1473 else 1474 aprint_verbose_dev(sc->sc_dev, 1475 "mode: PCLK locked after %d polls\n", i); 1476 1477 /* Loop PLL (VCLK). */ 1478 bus_bytes = interleave ? 8U : 4U; 1479 lclk_65mn = 32U * bus_bytes / (uint32_t)sc->sc_depth; 1480 lclk_n = (uint8_t)(65U - lclk_65mn); 1481 lclk_z100 = 2750U * lclk_65mn * 1000U / (uint32_t)dot_clock; 1482 1483 if (lclk_z100 <= 200) { 1484 lclk_p = 0; lclk_q = 0; 1485 } else if (lclk_z100 <= 400) { 1486 lclk_p = 1; lclk_q = 0; 1487 } else if (lclk_z100 <= 800) { 1488 lclk_p = 2; lclk_q = 0; 1489 } else if (lclk_z100 <= 1600) { 1490 lclk_p = 3; lclk_q = 0; 1491 } else { 1492 lclk_p = 3; 1493 lclk_q = (uint8_t)((lclk_z100 / 1600U) - 1U); 1494 } 1495 1496 aprint_verbose_dev(sc->sc_dev, 1497 "mode: LCLK N=%u M=61 P=%u Q=%u (z*100=%u)\n", 1498 lclk_n, lclk_p, lclk_q, lclk_z100); 1499 1500 /* MEMPLLCTRL Q-divider / strobe. */ 1501 mgafb_dac_write_ind(sc, MGA_TVP_MEMPLLCTRL, 0x30U | lclk_q); 1502 mgafb_dac_write_ind(sc, MGA_TVP_MEMPLLCTRL, 0x38U | lclk_q); 1503 1504 /* Program loop PLL. */ 1505 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, 1506 MGA_TVP_PLLADDR_PCLK_START); 1507 mgafb_dac_write_ind(sc, MGA_TVP_LOOPPLLDATA, 0xC0 | lclk_n); 1508 mgafb_dac_write_ind(sc, MGA_TVP_LOOPPLLDATA, 61); 1509 mgafb_dac_write_ind(sc, MGA_TVP_LOOPPLLDATA, 0xF0 | lclk_p); 1510 1511 /* Wait for LCLK lock. */ 1512 mgafb_dac_write_ind(sc, MGA_TVP_PLLADDR, 1513 MGA_TVP_PLLADDR_ALL_STATUS); 1514 for (i = 0; i < 10000; i++) { 1515 if (mgafb_dac_read_ind(sc, MGA_TVP_LOOPPLLDATA) & 1516 MGA_TVP_PLL_LOCKED) 1517 break; 1518 delay(1); 1519 } 1520 if (i == 10000) 1521 aprint_error_dev(sc->sc_dev, 1522 "mode: timeout waiting for LCLK lock\n"); 1523 else 1524 aprint_normal_dev(sc->sc_dev, 1525 "mode: LCLK locked after %d polls\n", i); 1526 } 1527 1528 /* 1529 * 1064SG integrated DAC register setup for the selected pixel depth. 1530 */ 1531 static void 1532 mgafb_idac_setup_dac(struct mgafb_softc *sc) 1533 { 1534 1535 if (sc->sc_depth == 8) 1536 mgafb_dac_write_ind(sc, MGA_IDAC_MUL_CTL, MGA_MULCTL_8BPP); 1537 else 1538 mgafb_dac_write_ind(sc, MGA_IDAC_MUL_CTL, MGA_MULCTL_16BPP); 1539 1540 mgafb_dac_write_ind(sc, MGA_IDAC_MISC_CTL, 0x00); 1541 mgafb_dac_write_ind(sc, MGA_IDAC_VREF_CTL, 0x03); 1542 } 1543 1544 /* 1545 * Program the 1064SG integrated pixel PLL (set C). 1546 */ 1547 static void 1548 mgafb_idac_set_pclk(struct mgafb_softc *sc, int dot_clock) 1549 { 1550 uint8_t pll_m, pll_n, pll_p; 1551 int i; 1552 1553 mgafb_calc_pll_1064sg(dot_clock, &pll_m, &pll_n, &pll_p); 1554 aprint_verbose_dev(sc->sc_dev, 1555 "mode: 1064SG PLL M=%u N=%u P=0x%02x (target %d kHz)\n", 1556 pll_m, pll_n, pll_p, dot_clock); 1557 1558 /* Disable pixel clock during reprogramming. */ 1559 mgafb_dac_write_ind(sc, MGA_IDAC_PIX_CLK_CTL, 1560 MGA_PIXCLK_DISABLE | MGA_PIXCLK_SRC_PLL); 1561 1562 /* Write pixel PLL set C. */ 1563 mgafb_dac_write_ind(sc, MGA_IDAC_PIX_PLLC_M, pll_m); 1564 mgafb_dac_write_ind(sc, MGA_IDAC_PIX_PLLC_N, pll_n); 1565 mgafb_dac_write_ind(sc, MGA_IDAC_PIX_PLLC_P, pll_p); 1566 1567 /* Wait for pixel PLL lock. */ 1568 for (i = 0; i < 10000; i++) { 1569 if (mgafb_dac_read_ind(sc, MGA_IDAC_PIX_PLL_STAT) & 0x40) 1570 break; 1571 delay(1); 1572 } 1573 if (i == 10000) 1574 aprint_error_dev(sc->sc_dev, 1575 "mode: timeout waiting for pixel PLL lock (%d kHz)\n", 1576 dot_clock); 1577 else 1578 aprint_verbose_dev(sc->sc_dev, 1579 "mode: pixel PLL locked after %d polls\n", i); 1580 1581 /* Enable pixel clock from PLL. */ 1582 mgafb_dac_write_ind(sc, MGA_IDAC_PIX_CLK_CTL, MGA_PIXCLK_SRC_PLL); 1583 } 1584 1585 static void 1586 mgafb_set_mode(struct mgafb_softc *sc) 1587 { 1588 int i; 1589 uint8_t locked; 1590 uint8_t crtc[25], crtcext[6], misc, vsyncpol; 1591 bool interleave; 1592 1593 /* 1594 * WRAM chips interleave when VRAM > 2 MB (64-bit bus). 1595 * SGRAM chips always use a 32-bit bus no interleave. 1596 */ 1597 interleave = sc->sc_ci->ci_has_wram && 1598 sc->sc_vram_size > (bus_size_t)2*1024*1024; 1599 1600 /* Step 1: Sequencer async reset. */ 1601 MGA_WRITE1(sc, MGA_VGA_SEQ_INDEX, 0x00); 1602 MGA_WRITE1(sc, MGA_VGA_SEQ_DATA, 0x01); 1603 MGA_WRITE1(sc, MGA_VGA_MISC_W, 0xEF); 1604 1605 /* Step 2: CRTC timing (shared across all chips). */ 1606 mgafb_calc_crtc(sc->sc_videomode, sc->sc_depth, interleave, 1607 crtc, crtcext, &misc, &vsyncpol); 1608 1609 /* Step 3: DAC setup chip-specific. */ 1610 if (sc->sc_ci->ci_has_tvp3026) { 1611 mgafb_tvp3026_setup_dac(sc, interleave); 1612 mgafb_dac_write_ind(sc, MGA_TVP_VSYNCPOL, vsyncpol); 1613 } else { 1614 mgafb_idac_setup_dac(sc); 1615 } 1616 1617 /* Step 4: Pixel PLL chip-specific. */ 1618 if (sc->sc_ci->ci_has_tvp3026) 1619 mgafb_tvp3026_set_pclk(sc, sc->sc_videomode->dot_clock, 1620 interleave); 1621 else 1622 mgafb_idac_set_pclk(sc, sc->sc_videomode->dot_clock); 1623 1624 /* Step 5: VGA CRTC timing (shared). */ 1625 MGA_WRITE1(sc, MGA_VGA_CRTC_INDEX, 0x11); 1626 locked = MGA_READ1(sc, MGA_VGA_CRTC_DATA); 1627 MGA_WRITE1(sc, MGA_VGA_CRTC_DATA, locked & ~0x80); /* unlock */ 1628 1629 for (i = 0; i < 25; i++) { 1630 MGA_WRITE1(sc, MGA_VGA_CRTC_INDEX, i); 1631 MGA_WRITE1(sc, MGA_VGA_CRTC_DATA, crtc[i]); 1632 } 1633 1634 MGA_WRITE1(sc, MGA_VGA_CRTC_INDEX, 0x11); 1635 MGA_WRITE1(sc, MGA_VGA_CRTC_DATA, crtc[0x11] | 0x80); /* re-lock */ 1636 1637 /* Step 6: CRTCEXT registers. */ 1638 crtcext[3] = MGA_CRTCEXT3_MGAMODE | mgafb_crtcext3_scale(sc); 1639 1640 for (i = 0; i < 6; i++) { 1641 MGA_WRITE1(sc, MGA_CRTCEXT_INDEX, i); 1642 MGA_WRITE1(sc, MGA_CRTCEXT_DATA, crtcext[i]); 1643 } 1644 1645 MGA_WRITE1(sc, MGA_VGA_SEQ_INDEX, 0x00); 1646 MGA_WRITE1(sc, MGA_VGA_SEQ_DATA, 0x03); 1647 1648 /* Step 7: Drawing engine init (shared across all chips). */ 1649 aprint_verbose_dev(sc->sc_dev, "mode: initialising drawing engine\n"); 1650 MGA_WRITE4(sc, MGA_MACCESS, 1651 (sc->sc_depth == 8) ? MGA_PW8 : MGA_PW16); 1652 MGA_WRITE4(sc, MGA_PITCH, (uint32_t)sc->sc_width); 1653 MGA_WRITE4(sc, MGA_PLNWT, 0xFFFFFFFF); 1654 MGA_WRITE4(sc, MGA_YDSTORG, 0); 1655 MGA_WRITE4(sc, MGA_CXBNDRY, 1656 ((uint32_t)(sc->sc_width - 1) << 16) | 0); 1657 MGA_WRITE4(sc, MGA_YTOP, 0); 1658 /* 1659 * YBOT must cover the full VRAM, not just the visible area. 1660 * The glyph cache lives in off-screen rows (y >= sc_height); 1661 * blits to/from those rows would be clipped if YBOT were set 1662 * to (sc_height-1)*sc_width. 1663 */ 1664 MGA_WRITE4(sc, MGA_YBOT, 1665 ((uint32_t)(sc->sc_vram_size / (bus_size_t)sc->sc_stride) - 1U) * 1666 (uint32_t)sc->sc_width); 1667 1668 aprint_verbose_dev(sc->sc_dev, "mode: programming complete\n"); 1669 } 1670 1671 static void 1672 mgafb_load_cmap(struct mgafb_softc *sc, u_int start, u_int count) 1673 { 1674 u_int i; 1675 1676 mgafb_dac_write(sc, MGA_DAC_PALADDR_W, (uint8_t)start); 1677 for (i = start; i < start + count; i++) { 1678 mgafb_dac_write(sc, MGA_DAC_PALDATA, sc->sc_cmap_red[i]); 1679 mgafb_dac_write(sc, MGA_DAC_PALDATA, sc->sc_cmap_green[i]); 1680 mgafb_dac_write(sc, MGA_DAC_PALDATA, sc->sc_cmap_blue[i]); 1681 } 1682 } 1683 1684 static void 1685 mgafb_init_default_cmap(struct mgafb_softc *sc) 1686 { 1687 struct rasops_info *ri = &sc->sc_console_screen.scr_ri; 1688 uint8_t cmap[256 * 3]; 1689 int i, idx; 1690 1691 rasops_get_cmap(ri, cmap, sizeof(cmap)); 1692 1693 idx = 0; 1694 for (i = 0; i < 256; i++) { 1695 sc->sc_cmap_red[i] = cmap[idx++]; 1696 sc->sc_cmap_green[i] = cmap[idx++]; 1697 sc->sc_cmap_blue[i] = cmap[idx++]; 1698 } 1699 1700 mgafb_load_cmap(sc, 0, 256); 1701 } 1702 1703 static int 1704 mgafb_putcmap(struct mgafb_softc *sc, struct wsdisplay_cmap *cm) 1705 { 1706 u_int index = cm->index; 1707 u_int count = cm->count; 1708 const uint8_t *r = cm->red, *g = cm->green, *b = cm->blue; 1709 uint8_t rv, gv, bv; 1710 u_int i; 1711 int error; 1712 1713 if (index >= 256 || count > 256 - index) 1714 return EINVAL; 1715 1716 for (i = 0; i < count; i++) { 1717 if ((error = copyin(r++, &rv, 1)) != 0 || 1718 (error = copyin(g++, &gv, 1)) != 0 || 1719 (error = copyin(b++, &bv, 1)) != 0) 1720 return error; 1721 sc->sc_cmap_red[index + i] = rv; 1722 sc->sc_cmap_green[index + i] = gv; 1723 sc->sc_cmap_blue[index + i] = bv; 1724 } 1725 1726 mgafb_load_cmap(sc, index, count); 1727 return 0; 1728 } 1729 1730 static int 1731 mgafb_getcmap(struct mgafb_softc *sc, struct wsdisplay_cmap *cm) 1732 { 1733 u_int index = cm->index; 1734 u_int count = cm->count; 1735 uint8_t *r = cm->red, *g = cm->green, *b = cm->blue; 1736 u_int i; 1737 int error; 1738 1739 if (index >= 256 || count > 256 - index) 1740 return EINVAL; 1741 1742 for (i = 0; i < count; i++) { 1743 if ((error = copyout(&sc->sc_cmap_red[index + i], 1744 r++, 1)) != 0 || 1745 (error = copyout(&sc->sc_cmap_green[index + i], 1746 g++, 1)) != 0 || 1747 (error = copyout(&sc->sc_cmap_blue[index + i], 1748 b++, 1)) != 0) 1749 return error; 1750 } 1751 return 0; 1752 } 1753 1754 #ifdef MGAFB_ACCEL 1755 1756 static void 1757 mgafb_wait_fifo(struct mgafb_softc *sc, int n) 1758 { 1759 while ((int)(uint8_t)MGA_READ1(sc, MGA_FIFOSTATUS) < n) 1760 ; 1761 } 1762 1763 static void 1764 mgafb_wait_idle(struct mgafb_softc *sc) 1765 { 1766 while (MGA_READ4(sc, MGA_STATUS) & MGA_DWGENGSTS) 1767 ; 1768 } 1769 1770 /* Replicate a pixel colour value to fill FCOL, BCOL */ 1771 static uint32_t 1772 mgafb_color_replicate(struct mgafb_softc *sc, uint32_t color) 1773 { 1774 if (sc->sc_depth == 8) { 1775 color &= 0xFF; 1776 return color | (color << 8) | (color << 16) | (color << 24); 1777 } else { 1778 color &= 0xFFFF; 1779 return color | (color << 16); 1780 } 1781 } 1782 1783 static void 1784 mgafb_fill_rect(struct mgafb_softc *sc, int x, int y, int w, int h, 1785 uint32_t color) 1786 { 1787 uint32_t fcol; 1788 1789 fcol = mgafb_color_replicate(sc, color); 1790 1791 mgafb_wait_fifo(sc, 4); 1792 MGA_WRITE4(sc, MGA_DWGCTL, MGA_DWGCTL_FILL); 1793 MGA_WRITE4(sc, MGA_FCOL, fcol); 1794 MGA_WRITE4(sc, MGA_FXBNDRY, 1795 ((uint32_t)(x + w - 1) << 16) | (uint32_t)(x & 0xFFFF)); 1796 MGA_WRITE4(sc, MGA_YDSTLEN | MGA_EXEC, 1797 ((uint32_t)y << 16) | (uint32_t)h); 1798 1799 mgafb_wait_idle(sc); 1800 } 1801 1802 static void 1803 mgafb_blit_rect(struct mgafb_softc *sc, 1804 int srcx, int srcy, int dstx, int dsty, int w, int h) 1805 { 1806 int pitch = sc->sc_width; 1807 uint32_t sgn = 0; 1808 int32_t ar5; 1809 int src_left, src_right, adj_srcy, adj_dsty; 1810 1811 adj_srcy = srcy; 1812 adj_dsty = dsty; 1813 1814 if (dsty > srcy) { 1815 sgn |= MGA_SGN_BLIT_UP; 1816 ar5 = -(int32_t)pitch; 1817 adj_srcy = srcy + h - 1; 1818 adj_dsty = dsty + h - 1; 1819 } else { 1820 ar5 = (int32_t)pitch; 1821 } 1822 1823 if (dsty == srcy && dstx > srcx) 1824 sgn |= MGA_SGN_BLIT_LEFT; 1825 1826 src_left = adj_srcy * pitch + srcx; 1827 src_right = adj_srcy * pitch + srcx + w - 1; 1828 1829 mgafb_wait_fifo(sc, 7); 1830 if ((srcx & 127) == (dstx & 127) && (sgn == 0)) { 1831 /* fast copy */ 1832 MGA_WRITE4(sc, MGA_DWGCTL, MGA_DWGCTL_FASTCOPY); 1833 } else { 1834 MGA_WRITE4(sc, MGA_DWGCTL, MGA_DWGCTL_COPY); 1835 MGA_WRITE4(sc, MGA_SGN, sgn); 1836 } 1837 MGA_WRITE4(sc, MGA_AR5, (uint32_t)ar5); 1838 /* AR3 = scan start, AR0 = scan end */ 1839 if (sgn & MGA_SGN_BLIT_LEFT) { 1840 MGA_WRITE4(sc, MGA_AR3, (uint32_t)src_right); 1841 MGA_WRITE4(sc, MGA_AR0, (uint32_t)src_left); 1842 } else { 1843 MGA_WRITE4(sc, MGA_AR3, (uint32_t)src_left); 1844 MGA_WRITE4(sc, MGA_AR0, (uint32_t)src_right); 1845 } 1846 MGA_WRITE4(sc, MGA_FXBNDRY, 1847 ((uint32_t)(dstx + w - 1) << 16) | (uint32_t)(dstx & 0xFFFF)); 1848 MGA_WRITE4(sc, MGA_YDSTLEN | MGA_EXEC, 1849 ((uint32_t)adj_dsty << 16) | (uint32_t)h); 1850 1851 mgafb_wait_idle(sc); 1852 } 1853 1854 /* 1855 * The rop parameter is not used; glyphcache always passes gc->gc_rop 1856 * which we set to 0 (copy). 1857 */ 1858 static void 1859 mgafb_gc_bitblt(void *cookie, int srcx, int srcy, int dstx, int dsty, 1860 int w, int h, int rop) 1861 { 1862 mgafb_blit_rect((struct mgafb_softc *)cookie, 1863 srcx, srcy, dstx, dsty, w, h); 1864 } 1865 1866 /* 1867 * Uses ILOAD-with-Expansion to stream the raw 1bpp glyph bitmap from 1868 * the CPU to the drawing engine, which hardware-expands bits to FCOL 1869 * or BCOL as it writes to WRAM. 1870 */ 1871 static void 1872 mgafb_putchar(void *cookie, int row, int col, u_int uc, long attr) 1873 { 1874 struct rasops_info *ri = cookie; 1875 struct vcons_screen *scr = ri->ri_hw; 1876 struct mgafb_softc *sc = scr->scr_vd->cookie; 1877 struct wsdisplay_font *font = ri->ri_font; 1878 const uint8_t *data; 1879 int x, y, i, j; 1880 int32_t fg, bg, ul; 1881 uint32_t fcol, bcol, dword; 1882 int glyphidx, stride, dwords_per_row; 1883 int rv; 1884 1885 rasops_unpack_attr(attr, &fg, &bg, &ul); 1886 1887 x = ri->ri_xorigin + col * font->fontwidth; 1888 y = ri->ri_yorigin + row * font->fontheight; 1889 1890 /* Unknown character: fill with background. */ 1891 glyphidx = (int)uc - font->firstchar; 1892 if ((unsigned int)glyphidx >= (unsigned int)font->numchars) { 1893 mgafb_fill_rect(sc, x, y, font->fontwidth, font->fontheight, 1894 (uint32_t)ri->ri_devcmap[bg]); 1895 return; 1896 } 1897 1898 /* 1899 * Try the glyph cache first. Skip for underlined glyphs: the ILOAD 1900 * renders the underline as part of the last scanline (all-foreground), 1901 * so the cached pixel data would be underlined regardless of attr, 1902 * corrupting non-underlined renders of the same character. 1903 */ 1904 if (!ul) { 1905 rv = glyphcache_try(&sc->sc_gc, (int)uc, x, y, attr); 1906 if (rv == GC_OK) 1907 return; 1908 } else { 1909 rv = GC_NOPE; 1910 } 1911 1912 data = (const uint8_t *)font->data + glyphidx * ri->ri_fontscale; 1913 stride = font->stride; 1914 dwords_per_row = (font->fontwidth + 31) / 32; 1915 1916 fcol = mgafb_color_replicate(sc, (uint32_t)ri->ri_devcmap[fg]); 1917 bcol = mgafb_color_replicate(sc, (uint32_t)ri->ri_devcmap[bg]); 1918 1919 /* Enable pseudo-DMA BLIT WRITE */ 1920 MGA_WRITE4(sc, MGA_OPMODE, MGA_OPMODE_DMA_BLIT_WR); 1921 1922 /* Write ILOAD setup registers into the drawing FIFO. */ 1923 mgafb_wait_fifo(sc, 8); 1924 MGA_WRITE4(sc, MGA_DWGCTL, MGA_DWGCTL_ILOAD_OPAQUE); 1925 MGA_WRITE4(sc, MGA_FCOL, fcol); 1926 MGA_WRITE4(sc, MGA_BCOL, bcol); 1927 MGA_WRITE4(sc, MGA_FXBNDRY, 1928 ((uint32_t)(x + font->fontwidth - 1) << 16) | (uint32_t)x); 1929 MGA_WRITE4(sc, MGA_AR5, 0); 1930 MGA_WRITE4(sc, MGA_AR3, 0); 1931 MGA_WRITE4(sc, MGA_AR0, (uint32_t)(font->fontwidth - 1)); 1932 MGA_WRITE4(sc, MGA_YDSTLEN | MGA_EXEC, 1933 ((uint32_t)y << 16) | (uint32_t)font->fontheight); 1934 1935 /* Stream glyph scanlines into DMAWIN. */ 1936 for (i = 0; i < font->fontheight; i++, data += stride) { 1937 for (j = 0; j < dwords_per_row; j++) { 1938 int b = j * 4; /* byte offset into this row */ 1939 if (ul && i == font->fontheight - 1) { 1940 dword = 0xFFFFFFFF; 1941 } else { 1942 dword = (b + 0 < stride) ? 1943 (uint32_t)data[b + 0] : 0; 1944 dword |= (b + 1 < stride) ? 1945 (uint32_t)data[b + 1] << 8 : 0; 1946 dword |= (b + 2 < stride) ? 1947 (uint32_t)data[b + 2] << 16 : 0; 1948 dword |= (b + 3 < stride) ? 1949 (uint32_t)data[b + 3] << 24 : 0; 1950 } 1951 MGA_WRITE4(sc, MGA_DMAWIN, dword); 1952 } 1953 } 1954 1955 /* Restore OPMODE and wait for the ILOAD to finish writing to WRAM. */ 1956 MGA_WRITE4(sc, MGA_OPMODE, MGA_OPMODE_DMA_OFF); 1957 mgafb_wait_idle(sc); 1958 1959 if (rv == GC_ADD) 1960 glyphcache_add(&sc->sc_gc, (int)uc, x, y); 1961 } 1962 1963 /* 1964 * Alpha-blends glyph data into 16bpp RBG pixels, 1965 * then stream via ILOAD BFCOL. 1966 * 1967 * wsfontload PragmataPro_12x24.wsf 1968 * wsconsctl -f /dev/ttyE0 -dw font=PragmataPro 1969 */ 1970 static void 1971 mgafb_putchar_aa(void *cookie, int row, int col, u_int uc, long attr) 1972 { 1973 struct rasops_info *ri = cookie; 1974 struct vcons_screen *scr = ri->ri_hw; 1975 struct mgafb_softc *sc = scr->scr_vd->cookie; 1976 struct wsdisplay_font *font = PICK_FONT(ri, uc); 1977 const uint8_t *data; 1978 int x, y, wi, he; 1979 int32_t fg, bg, ul; 1980 int glyphidx, rv; 1981 int fgo, bgo; 1982 int r0, g0, b0, r1, g1, b1; 1983 uint16_t bg16, fg16; 1984 uint32_t latch; 1985 int stride, pi, glyph_row, glyph_col; 1986 1987 rasops_unpack_attr(attr, &fg, &bg, &ul); 1988 1989 x = ri->ri_xorigin + col * font->fontwidth; 1990 y = ri->ri_yorigin + row * font->fontheight; 1991 wi = font->fontwidth; 1992 he = font->fontheight; 1993 1994 /* seemingly weird blitting artifacts 1995 if (uc == 0x20) { 1996 mgafb_fill_rect(sc, x, y, wi, he, 1997 (uint32_t)ri->ri_devcmap[bg]); 1998 if (ul) 1999 mgafb_fill_rect(sc, x, y + he - 2, wi, 1, 2000 (uint32_t)ri->ri_devcmap[fg]); 2001 return; 2002 }*/ 2003 2004 /* Unknown character: fill with background. */ 2005 glyphidx = (int)uc - font->firstchar; 2006 if ((unsigned int)glyphidx >= (unsigned int)font->numchars) { 2007 mgafb_fill_rect(sc, x, y, wi, he, 2008 (uint32_t)ri->ri_devcmap[bg]); 2009 return; 2010 } 2011 2012 /* Glyph cache skip for underlined characters. */ 2013 if (!ul) { 2014 rv = glyphcache_try(&sc->sc_gc, (int)uc, x, y, attr); 2015 if (rv == GC_OK) 2016 return; 2017 } else { 2018 rv = GC_NOPE; 2019 } 2020 2021 data = (const uint8_t *)font->data + glyphidx * ri->ri_fontscale; 2022 2023 /* 2024 * Extract 8-bit RGB components from rasops_cmap for blending. 2025 * Attr encodes fg index in bits 27:24, bg index in bits 23:16. 2026 */ 2027 fgo = ((attr >> 24) & 0xf) * 3; 2028 bgo = ((attr >> 16) & 0xf) * 3; 2029 r0 = rasops_cmap[bgo]; 2030 r1 = rasops_cmap[fgo]; 2031 g0 = rasops_cmap[bgo + 1]; 2032 g1 = rasops_cmap[fgo + 1]; 2033 b0 = rasops_cmap[bgo + 2]; 2034 b1 = rasops_cmap[fgo + 2]; 2035 2036 bg16 = (uint16_t)ri->ri_devcmap[bg]; 2037 fg16 = (uint16_t)ri->ri_devcmap[fg]; 2038 2039 /* Set up ILOAD in full-color (BFCOL) mode. */ 2040 MGA_WRITE4(sc, MGA_OPMODE, MGA_OPMODE_DMA_BLIT_WR); 2041 2042 mgafb_wait_fifo(sc, 6); 2043 MGA_WRITE4(sc, MGA_DWGCTL, MGA_DWGCTL_ILOAD_COLOR); 2044 MGA_WRITE4(sc, MGA_FXBNDRY, 2045 ((uint32_t)(x + wi - 1) << 16) | (uint32_t)x); 2046 MGA_WRITE4(sc, MGA_AR5, 0); 2047 MGA_WRITE4(sc, MGA_AR3, 0); 2048 MGA_WRITE4(sc, MGA_AR0, (uint32_t)(wi - 1)); 2049 MGA_WRITE4(sc, MGA_YDSTLEN | MGA_EXEC, 2050 ((uint32_t)y << 16) | (uint32_t)he); 2051 2052 /* 2053 * Alpha-blend and stream pixels row by row. 2054 */ 2055 stride = font->stride; 2056 latch = 0; 2057 pi = 0; 2058 2059 for (glyph_row = 0; glyph_row < he; glyph_row++, data += stride) { 2060 for (glyph_col = 0; glyph_col < wi; glyph_col++) { 2061 int aval = data[glyph_col]; 2062 uint16_t pixel; 2063 2064 if (ul && glyph_row == he - 1) { 2065 pixel = fg16; 2066 } else if (aval == 0) { 2067 pixel = bg16; 2068 } else if (aval == 255) { 2069 pixel = fg16; 2070 } else { 2071 int r = (aval * r1 + (255 - aval) * r0) >> 8; 2072 int g = (aval * g1 + (255 - aval) * g0) >> 8; 2073 int b = (aval * b1 + (255 - aval) * b0) >> 8; 2074 pixel = ((r >> 3) << 11) | 2075 ((g >> 2) << 5) | (b >> 3); 2076 } 2077 2078 latch |= (uint32_t)pixel << (16 * pi); 2079 pi++; 2080 if (pi == 2) { 2081 MGA_WRITE4(sc, MGA_DMAWIN, latch); 2082 latch = 0; 2083 pi = 0; 2084 } 2085 } 2086 } 2087 if (pi != 0) 2088 MGA_WRITE4(sc, MGA_DMAWIN, latch); 2089 2090 MGA_WRITE4(sc, MGA_OPMODE, MGA_OPMODE_DMA_OFF); 2091 mgafb_wait_idle(sc); 2092 2093 if (rv == GC_ADD) 2094 glyphcache_add(&sc->sc_gc, (int)uc, x, y); 2095 } 2096 2097 static void 2098 mgafb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2099 { 2100 struct rasops_info *ri = cookie; 2101 struct vcons_screen *scr = ri->ri_hw; 2102 struct mgafb_softc *sc = scr->scr_vd->cookie; 2103 int srcY, dstY, w, h; 2104 2105 srcY = ri->ri_yorigin + srcrow * ri->ri_font->fontheight; 2106 dstY = ri->ri_yorigin + dstrow * ri->ri_font->fontheight; 2107 w = ri->ri_emuwidth; 2108 h = nrows * ri->ri_font->fontheight; 2109 2110 mgafb_blit_rect(sc, ri->ri_xorigin, srcY, ri->ri_xorigin, dstY, w, h); 2111 } 2112 2113 static void 2114 mgafb_eraserows(void *cookie, int row, int nrows, long attr) 2115 { 2116 struct rasops_info *ri = cookie; 2117 struct vcons_screen *scr = ri->ri_hw; 2118 struct mgafb_softc *sc = scr->scr_vd->cookie; 2119 int y, w, h; 2120 int32_t fg, bg, ul; 2121 2122 rasops_unpack_attr(attr, &fg, &bg, &ul); 2123 2124 y = ri->ri_yorigin + row * ri->ri_font->fontheight; 2125 w = ri->ri_emuwidth; 2126 h = nrows * ri->ri_font->fontheight; 2127 2128 mgafb_fill_rect(sc, ri->ri_xorigin, y, w, h, ri->ri_devcmap[bg]); 2129 } 2130 2131 static void 2132 mgafb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2133 { 2134 struct rasops_info *ri = cookie; 2135 struct vcons_screen *scr = ri->ri_hw; 2136 struct mgafb_softc *sc = scr->scr_vd->cookie; 2137 int srcX, dstX, y, w, h; 2138 2139 srcX = ri->ri_xorigin + srccol * ri->ri_font->fontwidth; 2140 dstX = ri->ri_xorigin + dstcol * ri->ri_font->fontwidth; 2141 y = ri->ri_yorigin + row * ri->ri_font->fontheight; 2142 w = ncols * ri->ri_font->fontwidth; 2143 h = ri->ri_font->fontheight; 2144 2145 mgafb_blit_rect(sc, srcX, y, dstX, y, w, h); 2146 } 2147 2148 static void 2149 mgafb_erasecols(void *cookie, int row, int col, int ncols, long attr) 2150 { 2151 struct rasops_info *ri = cookie; 2152 struct vcons_screen *scr = ri->ri_hw; 2153 struct mgafb_softc *sc = scr->scr_vd->cookie; 2154 int x, y, w, h; 2155 int32_t fg, bg, ul; 2156 2157 rasops_unpack_attr(attr, &fg, &bg, &ul); 2158 2159 x = ri->ri_xorigin + col * ri->ri_font->fontwidth; 2160 y = ri->ri_yorigin + row * ri->ri_font->fontheight; 2161 w = ncols * ri->ri_font->fontwidth; 2162 h = ri->ri_font->fontheight; 2163 2164 mgafb_fill_rect(sc, x, y, w, h, ri->ri_devcmap[bg]); 2165 } 2166 2167 #endif /* MGAFB_ACCEL */ 2168 2169 /* 2170 * The TVP3026 has a 64x64x2-plane hardware cursor with its own RAM, 2171 * color registers, and position registers, independent of the drawing 2172 * engine and framebuffer depth. 2173 */ 2174 static void 2175 mgafb_cursor_enable(struct mgafb_softc *sc, bool on) 2176 { 2177 uint8_t v; 2178 2179 v = mgafb_dac_read_ind(sc, MGA_TVP_CURCTL_IND); 2180 v &= ~MGA_TVP_CURCTL_CMASK; 2181 if (on) 2182 v |= MGA_TVP_CURCTL_XGA; 2183 mgafb_dac_write_ind(sc, MGA_TVP_CURCTL_IND, v); 2184 sc->sc_cursor.mc_enabled = on; 2185 } 2186 2187 static void 2188 mgafb_cursor_setpos(struct mgafb_softc *sc, int x, int y) 2189 { 2190 int px, py; 2191 2192 px = x + MGA_CURSOR_ORIGIN; 2193 py = y + MGA_CURSOR_ORIGIN; 2194 if (px < 0) 2195 px = 0; 2196 if (py < 0) 2197 py = 0; 2198 2199 mgafb_dac_write(sc, MGA_DAC_CUR_X_LSB, px & 0xFF); 2200 mgafb_dac_write(sc, MGA_DAC_CUR_X_MSB, (px >> 8) & 0x0F); 2201 mgafb_dac_write(sc, MGA_DAC_CUR_Y_LSB, py & 0xFF); 2202 mgafb_dac_write(sc, MGA_DAC_CUR_Y_MSB, (py >> 8) & 0x0F); 2203 } 2204 2205 static void 2206 mgafb_cursor_setcmap(struct mgafb_softc *sc) 2207 { 2208 2209 /* Cursor color 0 (background) at address 1, 2210 * cursor color 1 (foreground) at address 2. 2211 * Address auto-increments after each blue byte. */ 2212 mgafb_dac_write(sc, MGA_DAC_CUR_COL_ADDR_W, 1); 2213 mgafb_dac_write(sc, MGA_DAC_CUR_COL_DATA, sc->sc_cursor.mc_r[0]); 2214 mgafb_dac_write(sc, MGA_DAC_CUR_COL_DATA, sc->sc_cursor.mc_g[0]); 2215 mgafb_dac_write(sc, MGA_DAC_CUR_COL_DATA, sc->sc_cursor.mc_b[0]); 2216 mgafb_dac_write(sc, MGA_DAC_CUR_COL_DATA, sc->sc_cursor.mc_r[1]); 2217 mgafb_dac_write(sc, MGA_DAC_CUR_COL_DATA, sc->sc_cursor.mc_g[1]); 2218 mgafb_dac_write(sc, MGA_DAC_CUR_COL_DATA, sc->sc_cursor.mc_b[1]); 2219 } 2220 2221 static void 2222 mgafb_cursor_setshape(struct mgafb_softc *sc, int width, int height) 2223 { 2224 uint8_t v, rowbyte; 2225 int row, col; 2226 2227 /* Disable cursor during RAM load to prevent glitches. */ 2228 mgafb_cursor_enable(sc, false); 2229 2230 /* 2231 * Clear CCR7 (use indirect control) and CCR3:CCR2 (bank 00). 2232 * Then reset cursor RAM address to 0. Auto-increment wraps 2233 * through all 1024 bytes (plane 0 then plane 1). 2234 */ 2235 v = mgafb_dac_read_ind(sc, MGA_TVP_CURCTL_IND); 2236 v &= ~(MGA_TVP_CURCTL_BMASK | MGA_TVP_CURCTL_CMASK | 2237 MGA_TVP_CURCTL_CCR7); 2238 mgafb_dac_write_ind(sc, MGA_TVP_CURCTL_IND, v); 2239 2240 mgafb_dac_write(sc, MGA_DAC_PALADDR_W, 0x00); 2241 2242 /* Build a complement (XOR) block cursor using XGA mode.*/ 2243 2244 /* Plane 0 (image): set bits for cursor block area. */ 2245 for (row = 0; row < MGA_CURSOR_MAX; row++) { 2246 for (col = 0; col < 8; col++) { 2247 if (row < height && col < (width + 7) / 8) { 2248 int bits_in_byte = width - col * 8; 2249 if (bits_in_byte >= 8) 2250 rowbyte = 0xFF; 2251 else 2252 rowbyte = (uint8_t)(0xFF << 2253 (8 - bits_in_byte)); 2254 } else { 2255 rowbyte = 0x00; 2256 } 2257 mgafb_dac_write(sc, MGA_DAC_CUR_DATA, rowbyte); 2258 } 2259 } 2260 2261 /* Plane 1 (mask): all 1s makes non-cursor pixels transparent, 2262 * cursor pixels complemented (XOR with screen). */ 2263 for (row = 0; row < MGA_CURSOR_MAX; row++) { 2264 for (col = 0; col < 8; col++) 2265 mgafb_dac_write(sc, MGA_DAC_CUR_DATA, 0xFF); 2266 } 2267 } 2268 2269 static void 2270 mgafb_cursor_init(struct mgafb_softc *sc) 2271 { 2272 uint8_t v; 2273 2274 memset(&sc->sc_cursor, 0, sizeof(sc->sc_cursor)); 2275 2276 sc->sc_cursor.mc_r[0] = sc->sc_cursor.mc_r[1] = 0xFF; 2277 sc->sc_cursor.mc_g[0] = sc->sc_cursor.mc_g[1] = 0xFF; 2278 sc->sc_cursor.mc_b[0] = sc->sc_cursor.mc_b[1] = 0xFF; 2279 2280 /* Ensure CCR7=0 so indirect CCR (reg 0x06) is in control. */ 2281 v = mgafb_dac_read_ind(sc, MGA_TVP_CURCTL_IND); 2282 v &= ~(MGA_TVP_CURCTL_CCR7 | MGA_TVP_CURCTL_CMASK); 2283 mgafb_dac_write_ind(sc, MGA_TVP_CURCTL_IND, v); 2284 2285 mgafb_cursor_setcmap(sc); 2286 /* Reload when font is known */ 2287 mgafb_cursor_setshape(sc, 8, 16); 2288 mgafb_cursor_setpos(sc, 0, 0); 2289 } 2290 2291 static void 2292 mgafb_hw_cursor(void *cookie, int on, int row, int col) 2293 { 2294 struct rasops_info *ri = cookie; 2295 struct vcons_screen *scr = ri->ri_hw; 2296 struct mgafb_softc *sc = scr->scr_cookie; 2297 2298 if (on) { 2299 int x = col * ri->ri_font->fontwidth + ri->ri_xorigin; 2300 int y = row * ri->ri_font->fontheight + ri->ri_yorigin; 2301 2302 ri->ri_crow = row; 2303 ri->ri_ccol = col; 2304 ri->ri_flg |= RI_CURSOR; 2305 2306 mgafb_cursor_setpos(sc, x, y); 2307 mgafb_cursor_enable(sc, true); 2308 } else { 2309 ri->ri_flg &= ~RI_CURSOR; 2310 mgafb_cursor_enable(sc, false); 2311 } 2312 } 2313 2314 static void 2315 mgafb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2316 long *defattr) 2317 { 2318 struct mgafb_softc *sc = cookie; 2319 struct rasops_info *ri = &scr->scr_ri; 2320 2321 wsfont_init(); 2322 2323 ri->ri_depth = sc->sc_depth; 2324 ri->ri_width = sc->sc_width; 2325 ri->ri_height = sc->sc_height; 2326 ri->ri_stride = sc->sc_stride; 2327 ri->ri_flg = RI_CENTER | RI_CLEAR; 2328 if (sc->sc_depth == 16) 2329 ri->ri_flg |= RI_ENABLE_ALPHA | RI_PREFER_ALPHA; 2330 2331 /* Uhh... */ 2332 #if BYTE_ORDER == BIG_ENDIAN 2333 if (sc->sc_depth > 8) 2334 ri->ri_flg |= RI_BSWAP; 2335 #endif 2336 /* tested only for aa path */ 2337 scr->scr_flags |= VCONS_LOADFONT; 2338 2339 if (sc->sc_depth == 16) { 2340 /* 16bpp 5:6:5 */ 2341 ri->ri_rnum = 5; ri->ri_rpos = 11; 2342 ri->ri_gnum = 6; ri->ri_gpos = 5; 2343 ri->ri_bnum = 5; ri->ri_bpos = 0; 2344 } 2345 ri->ri_bits = bus_space_vaddr(sc->sc_fbt, sc->sc_fbh); 2346 2347 rasops_init(ri, 0, 0); 2348 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_RESIZE 2349 | WSSCREEN_UNDERLINE ; 2350 rasops_reconfig(ri, 2351 sc->sc_height / ri->ri_font->fontheight, 2352 sc->sc_width / ri->ri_font->fontwidth); 2353 2354 ri->ri_hw = scr; 2355 2356 #ifdef MGAFB_ACCEL 2357 aprint_verbose_dev(sc->sc_dev, 2358 "font: %dx%d stride=%d %s\n", 2359 ri->ri_font->fontwidth, ri->ri_font->fontheight, 2360 ri->ri_font->stride, 2361 FONT_IS_ALPHA(ri->ri_font) ? "alpha" : "bitmap"); 2362 2363 if (sc->sc_depth == 16 && FONT_IS_ALPHA(ri->ri_font)) { 2364 ri->ri_ops.putchar = mgafb_putchar_aa; 2365 aprint_normal_dev(sc->sc_dev, 2366 "using antialiasing\n"); 2367 } else { 2368 ri->ri_ops.putchar = mgafb_putchar; 2369 } 2370 ri->ri_ops.copyrows = mgafb_copyrows; 2371 ri->ri_ops.eraserows = mgafb_eraserows; 2372 ri->ri_ops.copycols = mgafb_copycols; 2373 ri->ri_ops.erasecols = mgafb_erasecols; 2374 2375 #endif /* MGAFB_ACCEL */ 2376 2377 if (sc->sc_ci->ci_has_tvp3026) { 2378 ri->ri_ops.cursor = mgafb_hw_cursor; 2379 mgafb_cursor_setshape(sc, ri->ri_font->fontwidth, 2380 ri->ri_font->fontheight); 2381 } 2382 } 2383 2384 /* screenblank -b / -u confirmed working */ 2385 static void 2386 mgafb_set_dpms(struct mgafb_softc *sc, int state) 2387 { 2388 uint8_t seq1, crtcext1; 2389 2390 sc->sc_video = state; 2391 2392 MGA_WRITE1(sc, MGA_VGA_SEQ_INDEX, 0x01); 2393 seq1 = MGA_READ1(sc, MGA_VGA_SEQ_DATA) & ~0x20; 2394 2395 MGA_WRITE1(sc, MGA_CRTCEXT_INDEX, 0x01); 2396 crtcext1 = MGA_READ1(sc, MGA_CRTCEXT_DATA) & ~0x30; 2397 2398 if (state == WSDISPLAYIO_VIDEO_OFF) { 2399 seq1 |= 0x20; /* screen blank */ 2400 crtcext1 |= 0x30; /* hsync + vsync off */ 2401 } 2402 2403 MGA_WRITE1(sc, MGA_VGA_SEQ_INDEX, 0x01); 2404 MGA_WRITE1(sc, MGA_VGA_SEQ_DATA, seq1); 2405 2406 MGA_WRITE1(sc, MGA_CRTCEXT_INDEX, 0x01); 2407 MGA_WRITE1(sc, MGA_CRTCEXT_DATA, crtcext1); 2408 } 2409 2410 static int 2411 mgafb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 2412 struct lwp *l) 2413 { 2414 struct vcons_data *vd = v; 2415 struct mgafb_softc *sc = vd->cookie; 2416 struct vcons_screen *ms = vd->active; 2417 2418 switch (cmd) { 2419 case WSDISPLAYIO_GTYPE: 2420 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 2421 return 0; 2422 2423 case WSDISPLAYIO_GINFO: 2424 if (ms == NULL) 2425 return ENODEV; 2426 { 2427 struct wsdisplay_fbinfo *wsfbi = data; 2428 wsfbi->height = ms->scr_ri.ri_height; 2429 wsfbi->width = ms->scr_ri.ri_width; 2430 wsfbi->depth = ms->scr_ri.ri_depth; 2431 wsfbi->cmsize = (sc->sc_depth == 8) ? 256 : 0; 2432 } 2433 return 0; 2434 2435 case WSDISPLAYIO_PUTCMAP: 2436 if (sc->sc_depth != 8) 2437 return EINVAL; 2438 return mgafb_putcmap(sc, (struct wsdisplay_cmap *)data); 2439 2440 case WSDISPLAYIO_GETCMAP: 2441 if (sc->sc_depth != 8) 2442 return EINVAL; 2443 return mgafb_getcmap(sc, (struct wsdisplay_cmap *)data); 2444 2445 case WSDISPLAYIO_LINEBYTES: 2446 *(u_int *)data = sc->sc_stride; 2447 return 0; 2448 2449 case WSDISPLAYIO_GVIDEO: 2450 *(int *)data = sc->sc_video; 2451 return 0; 2452 2453 case WSDISPLAYIO_SVIDEO: 2454 mgafb_set_dpms(sc, *(int *)data); 2455 return 0; 2456 2457 case WSDISPLAYIO_SMODE: 2458 { 2459 int new_mode = *(int *)data; 2460 if (new_mode != sc->sc_mode) { 2461 sc->sc_mode = new_mode; 2462 if (new_mode == WSDISPLAYIO_MODE_EMUL) { 2463 if (sc->sc_ci->ci_has_tvp3026) 2464 mgafb_cursor_init(sc); 2465 vcons_redraw_screen(ms); 2466 } else { 2467 #ifdef MGAFB_ACCEL 2468 mgafb_wait_idle(sc); 2469 #endif 2470 if (sc->sc_ci->ci_has_tvp3026) 2471 mgafb_cursor_enable(sc, 2472 false); 2473 } 2474 } 2475 } 2476 return 0; 2477 2478 case WSDISPLAYIO_GET_FBINFO: 2479 { 2480 struct wsdisplayio_fbinfo *fbi = data; 2481 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 2482 } 2483 2484 case PCI_IOC_CFGREAD: 2485 case PCI_IOC_CFGWRITE: 2486 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 2487 cmd, data, flag, l); 2488 2489 case WSDISPLAYIO_GET_BUSID: 2490 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 2491 sc->sc_pcitag, data); 2492 } 2493 2494 return EPASSTHROUGH; 2495 } 2496 2497 static paddr_t 2498 mgafb_mmap(void *v, void *vs, off_t offset, int prot) 2499 { 2500 struct vcons_data *vd = v; 2501 struct mgafb_softc *sc = vd->cookie; 2502 2503 if (sc->sc_mode == WSDISPLAYIO_MODE_DUMBFB) { 2504 if (offset >= 0 && offset < (off_t)sc->sc_vram_size) 2505 return bus_space_mmap(sc->sc_fbt, sc->sc_fb_pa, 2506 offset, prot, 2507 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE); 2508 } else if (sc->sc_mode == WSDISPLAYIO_MODE_MAPPED) { 2509 if (kauth_authorize_machdep(kauth_cred_get(), 2510 KAUTH_MACHDEP_UNMANAGEDMEM, NULL, NULL, NULL, NULL) != 0) { 2511 aprint_error_dev(sc->sc_dev, "mmap() rejected\n"); 2512 return -1; 2513 } 2514 2515 /* MGABASE2: framebuffer aperture. */ 2516 if (offset >= (off_t)sc->sc_fb_pa && 2517 offset < (off_t)(sc->sc_fb_pa + sc->sc_fb_size)) 2518 return bus_space_mmap(sc->sc_fbt, offset, 0, prot, 2519 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE); 2520 2521 /* MGABASE1: control aperture / registers. */ 2522 if (offset >= (off_t)sc->sc_reg_pa && 2523 offset < (off_t)(sc->sc_reg_pa + sc->sc_reg_size)) 2524 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 2525 BUS_SPACE_MAP_LINEAR); 2526 } 2527 2528 return -1; 2529 } 2530
Indexes created Wed Mar 25 00:23:37 UTC 2026