mlx_pci.c revision 1.26 1 1.26 pgoyette /* $NetBSD: mlx_pci.c,v 1.26 2016/09/27 03:33:32 pgoyette Exp $ */
2 1.1 ad
3 1.1 ad /*-
4 1.1 ad * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 1.1 ad * All rights reserved.
6 1.1 ad *
7 1.1 ad * This code is derived from software contributed to The NetBSD Foundation
8 1.1 ad * by Andrew Doran.
9 1.1 ad *
10 1.1 ad * Redistribution and use in source and binary forms, with or without
11 1.1 ad * modification, are permitted provided that the following conditions
12 1.1 ad * are met:
13 1.1 ad * 1. Redistributions of source code must retain the above copyright
14 1.1 ad * notice, this list of conditions and the following disclaimer.
15 1.1 ad * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 ad * notice, this list of conditions and the following disclaimer in the
17 1.1 ad * documentation and/or other materials provided with the distribution.
18 1.1 ad *
19 1.1 ad * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 ad * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 ad * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 ad * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 ad * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 ad * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 ad * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 ad * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 ad * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 ad * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 ad * POSSIBILITY OF SUCH DAMAGE.
30 1.1 ad */
31 1.1 ad
32 1.1 ad /*-
33 1.1 ad * Copyright (c) 1999 Michael Smith
34 1.1 ad * All rights reserved.
35 1.1 ad *
36 1.1 ad * Redistribution and use in source and binary forms, with or without
37 1.1 ad * modification, are permitted provided that the following conditions
38 1.1 ad * are met:
39 1.1 ad * 1. Redistributions of source code must retain the above copyright
40 1.1 ad * notice, this list of conditions and the following disclaimer.
41 1.1 ad * 2. Redistributions in binary form must reproduce the above copyright
42 1.1 ad * notice, this list of conditions and the following disclaimer in the
43 1.1 ad * documentation and/or other materials provided with the distribution.
44 1.1 ad *
45 1.1 ad * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
46 1.1 ad * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47 1.1 ad * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48 1.1 ad * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
49 1.1 ad * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50 1.1 ad * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51 1.1 ad * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 1.1 ad * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53 1.1 ad * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54 1.1 ad * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 1.1 ad * SUCH DAMAGE.
56 1.1 ad *
57 1.1 ad * from FreeBSD: mlx_pci.c,v 1.4.2.4 2000/10/28 10:48:09 msmith Exp
58 1.1 ad */
59 1.1 ad
60 1.1 ad /*
61 1.1 ad * PCI front-end for the mlx(4) driver.
62 1.1 ad */
63 1.6 lukem
64 1.6 lukem #include <sys/cdefs.h>
65 1.26 pgoyette __KERNEL_RCSID(0, "$NetBSD: mlx_pci.c,v 1.26 2016/09/27 03:33:32 pgoyette Exp $");
66 1.1 ad
67 1.1 ad #include <sys/param.h>
68 1.1 ad #include <sys/systm.h>
69 1.1 ad #include <sys/kernel.h>
70 1.1 ad #include <sys/device.h>
71 1.1 ad #include <sys/queue.h>
72 1.1 ad #include <sys/callout.h>
73 1.26 pgoyette #include <sys/module.h>
74 1.1 ad
75 1.1 ad #include <machine/endian.h>
76 1.17 ad #include <sys/bus.h>
77 1.1 ad
78 1.1 ad #include <dev/ic/mlxreg.h>
79 1.1 ad #include <dev/ic/mlxio.h>
80 1.1 ad #include <dev/ic/mlxvar.h>
81 1.1 ad
82 1.1 ad #include <dev/pci/pcireg.h>
83 1.1 ad #include <dev/pci/pcivar.h>
84 1.1 ad #include <dev/pci/pcidevs.h>
85 1.1 ad
86 1.26 pgoyette #include "ioconf.h"
87 1.26 pgoyette
88 1.21 cegger static void mlx_pci_attach(device_t, device_t, void *);
89 1.21 cegger static int mlx_pci_match(device_t, cfdata_t, void *);
90 1.1 ad static const struct mlx_pci_ident *mlx_pci_findmpi(struct pci_attach_args *);
91 1.1 ad
92 1.1 ad static int mlx_v3_submit(struct mlx_softc *, struct mlx_ccb *);
93 1.1 ad static int mlx_v3_findcomplete(struct mlx_softc *, u_int *, u_int *);
94 1.1 ad static void mlx_v3_intaction(struct mlx_softc *, int);
95 1.1 ad static int mlx_v3_fw_handshake(struct mlx_softc *, int *, int *, int *);
96 1.3 ad #ifdef MLX_RESET
97 1.3 ad static int mlx_v3_reset(struct mlx_softc *);
98 1.3 ad #endif
99 1.1 ad
100 1.1 ad static int mlx_v4_submit(struct mlx_softc *, struct mlx_ccb *);
101 1.1 ad static int mlx_v4_findcomplete(struct mlx_softc *, u_int *, u_int *);
102 1.1 ad static void mlx_v4_intaction(struct mlx_softc *, int);
103 1.1 ad static int mlx_v4_fw_handshake(struct mlx_softc *, int *, int *, int *);
104 1.1 ad
105 1.1 ad static int mlx_v5_submit(struct mlx_softc *, struct mlx_ccb *);
106 1.1 ad static int mlx_v5_findcomplete(struct mlx_softc *, u_int *, u_int *);
107 1.1 ad static void mlx_v5_intaction(struct mlx_softc *, int);
108 1.1 ad static int mlx_v5_fw_handshake(struct mlx_softc *, int *, int *, int *);
109 1.1 ad
110 1.14 christos static struct mlx_pci_ident {
111 1.1 ad u_short mpi_vendor;
112 1.1 ad u_short mpi_product;
113 1.1 ad u_short mpi_subvendor;
114 1.1 ad u_short mpi_subproduct;
115 1.1 ad int mpi_iftype;
116 1.14 christos } const mlx_pci_ident[] = {
117 1.1 ad {
118 1.1 ad PCI_VENDOR_MYLEX,
119 1.1 ad PCI_PRODUCT_MYLEX_RAID_V2,
120 1.1 ad 0x0000,
121 1.1 ad 0x0000,
122 1.1 ad 2,
123 1.1 ad },
124 1.1 ad {
125 1.1 ad PCI_VENDOR_MYLEX,
126 1.1 ad PCI_PRODUCT_MYLEX_RAID_V3,
127 1.1 ad 0x0000,
128 1.1 ad 0x0000,
129 1.1 ad 3,
130 1.1 ad },
131 1.1 ad {
132 1.1 ad PCI_VENDOR_MYLEX,
133 1.1 ad PCI_PRODUCT_MYLEX_RAID_V4,
134 1.1 ad 0x0000,
135 1.1 ad 0x0000,
136 1.1 ad 4,
137 1.1 ad },
138 1.1 ad {
139 1.1 ad PCI_VENDOR_DEC,
140 1.1 ad PCI_PRODUCT_DEC_SWXCR,
141 1.1 ad PCI_VENDOR_MYLEX,
142 1.1 ad PCI_PRODUCT_MYLEX_RAID_V5,
143 1.1 ad 5,
144 1.1 ad },
145 1.1 ad };
146 1.1 ad
147 1.26 pgoyette static int
148 1.26 pgoyette mlx_pci_rescan(device_t self, const char *attr, const int *flag)
149 1.26 pgoyette {
150 1.26 pgoyette
151 1.26 pgoyette return mlx_configure(device_private(self), 1);
152 1.26 pgoyette }
153 1.26 pgoyette
154 1.26 pgoyette CFATTACH_DECL3_NEW(mlx_pci, sizeof(struct mlx_softc),
155 1.26 pgoyette mlx_pci_match, mlx_pci_attach, NULL, NULL, mlx_pci_rescan, NULL, 0);
156 1.1 ad
157 1.1 ad /*
158 1.1 ad * Try to find a `mlx_pci_ident' entry corresponding to this board.
159 1.1 ad */
160 1.1 ad static const struct mlx_pci_ident *
161 1.1 ad mlx_pci_findmpi(struct pci_attach_args *pa)
162 1.1 ad {
163 1.1 ad const struct mlx_pci_ident *mpi, *maxmpi;
164 1.1 ad pcireg_t reg;
165 1.1 ad
166 1.1 ad mpi = mlx_pci_ident;
167 1.1 ad maxmpi = mpi + sizeof(mlx_pci_ident) / sizeof(mlx_pci_ident[0]);
168 1.1 ad
169 1.1 ad for (; mpi < maxmpi; mpi++) {
170 1.1 ad if (PCI_VENDOR(pa->pa_id) != mpi->mpi_vendor ||
171 1.1 ad PCI_PRODUCT(pa->pa_id) != mpi->mpi_product)
172 1.1 ad continue;
173 1.1 ad
174 1.1 ad if (mpi->mpi_subvendor == 0x0000)
175 1.1 ad return (mpi);
176 1.1 ad
177 1.1 ad reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
178 1.1 ad
179 1.1 ad if (PCI_VENDOR(reg) == mpi->mpi_subvendor &&
180 1.1 ad PCI_PRODUCT(reg) == mpi->mpi_subproduct)
181 1.1 ad return (mpi);
182 1.1 ad }
183 1.1 ad
184 1.1 ad return (NULL);
185 1.1 ad }
186 1.1 ad
187 1.1 ad /*
188 1.1 ad * Match a supported board.
189 1.1 ad */
190 1.1 ad static int
191 1.21 cegger mlx_pci_match(device_t parent, cfdata_t cfdata, void *aux)
192 1.1 ad {
193 1.1 ad
194 1.1 ad return (mlx_pci_findmpi(aux) != NULL);
195 1.1 ad }
196 1.1 ad
197 1.1 ad /*
198 1.1 ad * Attach a supported board.
199 1.1 ad */
200 1.1 ad static void
201 1.21 cegger mlx_pci_attach(device_t parent, device_t self, void *aux)
202 1.1 ad {
203 1.1 ad struct pci_attach_args *pa;
204 1.1 ad struct mlx_softc *mlx;
205 1.1 ad pci_chipset_tag_t pc;
206 1.1 ad pci_intr_handle_t ih;
207 1.5 ad bus_space_handle_t memh, ioh;
208 1.5 ad bus_space_tag_t memt, iot;
209 1.1 ad pcireg_t reg;
210 1.1 ad const char *intrstr;
211 1.1 ad int ior, memr, i;
212 1.1 ad const struct mlx_pci_ident *mpi;
213 1.25 christos char intrbuf[PCI_INTRSTR_LEN];
214 1.1 ad
215 1.22 cegger mlx = device_private(self);
216 1.1 ad pa = aux;
217 1.1 ad pc = pa->pa_pc;
218 1.1 ad mpi = mlx_pci_findmpi(aux);
219 1.1 ad
220 1.24 chs mlx->mlx_dv = self;
221 1.1 ad mlx->mlx_dmat = pa->pa_dmat;
222 1.7 ad mlx->mlx_ci.ci_iftype = mpi->mpi_iftype;
223 1.1 ad
224 1.1 ad printf(": Mylex RAID (v%d interface)\n", mpi->mpi_iftype);
225 1.1 ad
226 1.1 ad /*
227 1.1 ad * Map the PCI register window.
228 1.1 ad */
229 1.1 ad memr = -1;
230 1.1 ad ior = -1;
231 1.1 ad
232 1.1 ad for (i = 0x10; i <= 0x14; i += 4) {
233 1.1 ad reg = pci_conf_read(pa->pa_pc, pa->pa_tag, i);
234 1.1 ad
235 1.1 ad if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) {
236 1.1 ad if (ior == -1 && PCI_MAPREG_IO_SIZE(reg) != 0)
237 1.1 ad ior = i;
238 1.1 ad } else {
239 1.1 ad if (memr == -1 && PCI_MAPREG_MEM_SIZE(reg) != 0)
240 1.1 ad memr = i;
241 1.1 ad }
242 1.1 ad }
243 1.1 ad
244 1.1 ad if (memr != -1)
245 1.1 ad if (pci_mapreg_map(pa, memr, PCI_MAPREG_TYPE_MEM, 0,
246 1.5 ad &memt, &memh, NULL, NULL))
247 1.1 ad memr = -1;
248 1.5 ad if (ior != -1)
249 1.1 ad if (pci_mapreg_map(pa, ior, PCI_MAPREG_TYPE_IO, 0,
250 1.5 ad &iot, &ioh, NULL, NULL))
251 1.1 ad ior = -1;
252 1.5 ad
253 1.5 ad if (memr != -1) {
254 1.5 ad mlx->mlx_iot = memt;
255 1.5 ad mlx->mlx_ioh = memh;
256 1.5 ad } else if (ior != -1) {
257 1.5 ad mlx->mlx_iot = iot;
258 1.5 ad mlx->mlx_ioh = ioh;
259 1.5 ad } else {
260 1.18 cegger aprint_error_dev(self, "can't map i/o or memory space\n");
261 1.1 ad return;
262 1.1 ad }
263 1.1 ad
264 1.1 ad /* Enable the device. */
265 1.1 ad reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
266 1.1 ad pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
267 1.1 ad reg | PCI_COMMAND_MASTER_ENABLE);
268 1.1 ad
269 1.1 ad /* Map and establish the interrupt. */
270 1.1 ad if (pci_intr_map(pa, &ih)) {
271 1.18 cegger aprint_error_dev(self, "can't map interrupt\n");
272 1.1 ad return;
273 1.1 ad }
274 1.25 christos intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
275 1.1 ad mlx->mlx_ih = pci_intr_establish(pc, ih, IPL_BIO, mlx_intr, mlx);
276 1.1 ad if (mlx->mlx_ih == NULL) {
277 1.18 cegger aprint_error_dev(self, "can't establish interrupt");
278 1.1 ad if (intrstr != NULL)
279 1.23 njoly aprint_error(" at %s", intrstr);
280 1.23 njoly aprint_error("\n");
281 1.1 ad return;
282 1.1 ad }
283 1.1 ad
284 1.1 ad /* Select linkage based on controller interface type. */
285 1.7 ad switch (mlx->mlx_ci.ci_iftype) {
286 1.1 ad case 2:
287 1.1 ad case 3:
288 1.1 ad mlx->mlx_submit = mlx_v3_submit;
289 1.1 ad mlx->mlx_findcomplete = mlx_v3_findcomplete;
290 1.1 ad mlx->mlx_intaction = mlx_v3_intaction;
291 1.1 ad mlx->mlx_fw_handshake = mlx_v3_fw_handshake;
292 1.3 ad #ifdef MLX_RESET
293 1.3 ad mlx->mlx_reset = mlx_v3_reset;
294 1.3 ad #endif
295 1.1 ad break;
296 1.1 ad
297 1.1 ad case 4:
298 1.1 ad mlx->mlx_submit = mlx_v4_submit;
299 1.1 ad mlx->mlx_findcomplete = mlx_v4_findcomplete;
300 1.1 ad mlx->mlx_intaction = mlx_v4_intaction;
301 1.1 ad mlx->mlx_fw_handshake = mlx_v4_fw_handshake;
302 1.1 ad break;
303 1.1 ad
304 1.1 ad case 5:
305 1.1 ad mlx->mlx_submit = mlx_v5_submit;
306 1.1 ad mlx->mlx_findcomplete = mlx_v5_findcomplete;
307 1.1 ad mlx->mlx_intaction = mlx_v5_intaction;
308 1.1 ad mlx->mlx_fw_handshake = mlx_v5_fw_handshake;
309 1.1 ad break;
310 1.1 ad }
311 1.1 ad
312 1.1 ad mlx_init(mlx, intrstr);
313 1.1 ad }
314 1.1 ad
315 1.1 ad /*
316 1.1 ad * ================= V3 interface linkage =================
317 1.1 ad */
318 1.1 ad
319 1.1 ad /*
320 1.1 ad * Try to give (mc) to the controller. Returns 1 if successful, 0 on
321 1.1 ad * failure (the controller is not ready to take a command).
322 1.1 ad *
323 1.1 ad * Must be called at splbio or in a fashion that prevents reentry.
324 1.1 ad */
325 1.1 ad static int
326 1.1 ad mlx_v3_submit(struct mlx_softc *mlx, struct mlx_ccb *mc)
327 1.1 ad {
328 1.1 ad
329 1.1 ad /* Ready for our command? */
330 1.1 ad if ((mlx_inb(mlx, MLX_V3REG_IDB) & MLX_V3_IDB_FULL) == 0) {
331 1.1 ad /* Copy mailbox data to window. */
332 1.1 ad bus_space_write_region_1(mlx->mlx_iot, mlx->mlx_ioh,
333 1.8 ad MLX_V3REG_MAILBOX, mc->mc_mbox, 13);
334 1.1 ad bus_space_barrier(mlx->mlx_iot, mlx->mlx_ioh,
335 1.8 ad MLX_V3REG_MAILBOX, 13,
336 1.1 ad BUS_SPACE_BARRIER_WRITE);
337 1.1 ad
338 1.1 ad /* Post command. */
339 1.1 ad mlx_outb(mlx, MLX_V3REG_IDB, MLX_V3_IDB_FULL);
340 1.1 ad return (1);
341 1.1 ad }
342 1.1 ad
343 1.1 ad return (0);
344 1.1 ad }
345 1.1 ad
346 1.1 ad /*
347 1.1 ad * See if a command has been completed, if so acknowledge its completion and
348 1.1 ad * recover the slot number and status code.
349 1.1 ad *
350 1.1 ad * Must be called at splbio or in a fashion that prevents reentry.
351 1.1 ad */
352 1.1 ad static int
353 1.1 ad mlx_v3_findcomplete(struct mlx_softc *mlx, u_int *slot, u_int *status)
354 1.1 ad {
355 1.1 ad
356 1.1 ad /* Status available? */
357 1.1 ad if ((mlx_inb(mlx, MLX_V3REG_ODB) & MLX_V3_ODB_SAVAIL) != 0) {
358 1.1 ad *slot = mlx_inb(mlx, MLX_V3REG_STATUS_IDENT);
359 1.1 ad *status = mlx_inw(mlx, MLX_V3REG_STATUS);
360 1.1 ad
361 1.1 ad /* Acknowledge completion. */
362 1.1 ad mlx_outb(mlx, MLX_V3REG_ODB, MLX_V3_ODB_SAVAIL);
363 1.1 ad mlx_outb(mlx, MLX_V3REG_IDB, MLX_V3_IDB_SACK);
364 1.1 ad return (1);
365 1.1 ad }
366 1.1 ad
367 1.1 ad return (0);
368 1.1 ad }
369 1.1 ad
370 1.1 ad /*
371 1.1 ad * Enable/disable interrupts as requested. (No acknowledge required)
372 1.1 ad *
373 1.1 ad * Must be called at splbio or in a fashion that prevents reentry.
374 1.1 ad */
375 1.1 ad static void
376 1.1 ad mlx_v3_intaction(struct mlx_softc *mlx, int action)
377 1.1 ad {
378 1.1 ad
379 1.1 ad mlx_outb(mlx, MLX_V3REG_IE, action != 0);
380 1.1 ad }
381 1.1 ad
382 1.1 ad /*
383 1.1 ad * Poll for firmware error codes during controller initialisation.
384 1.1 ad *
385 1.1 ad * Returns 0 if initialisation is complete, 1 if still in progress but no
386 1.1 ad * error has been fetched, 2 if an error has been retrieved.
387 1.1 ad */
388 1.12 perry static int
389 1.1 ad mlx_v3_fw_handshake(struct mlx_softc *mlx, int *error, int *param1, int *param2)
390 1.1 ad {
391 1.1 ad u_int8_t fwerror;
392 1.1 ad
393 1.1 ad /* First time around, clear any hardware completion status. */
394 1.1 ad if ((mlx->mlx_flags & MLXF_FW_INITTED) == 0) {
395 1.1 ad mlx_outb(mlx, MLX_V3REG_IDB, MLX_V3_IDB_SACK);
396 1.1 ad DELAY(1000);
397 1.1 ad mlx->mlx_flags |= MLXF_FW_INITTED;
398 1.1 ad }
399 1.1 ad
400 1.1 ad /* Init in progress? */
401 1.1 ad if ((mlx_inb(mlx, MLX_V3REG_IDB) & MLX_V3_IDB_INIT_BUSY) == 0)
402 1.1 ad return (0);
403 1.1 ad
404 1.1 ad /* Test error value. */
405 1.1 ad fwerror = mlx_inb(mlx, MLX_V3REG_FWERROR);
406 1.1 ad
407 1.1 ad if ((fwerror & MLX_V3_FWERROR_PEND) == 0)
408 1.1 ad return (1);
409 1.1 ad
410 1.1 ad /* Mask status pending bit, fetch status. */
411 1.1 ad *error = fwerror & ~MLX_V3_FWERROR_PEND;
412 1.1 ad *param1 = mlx_inb(mlx, MLX_V3REG_FWERROR_PARAM1);
413 1.1 ad *param2 = mlx_inb(mlx, MLX_V3REG_FWERROR_PARAM2);
414 1.1 ad
415 1.1 ad /* Acknowledge. */
416 1.1 ad mlx_outb(mlx, MLX_V3REG_FWERROR, 0);
417 1.1 ad
418 1.1 ad return (2);
419 1.1 ad }
420 1.1 ad
421 1.3 ad #ifdef MLX_RESET
422 1.3 ad /*
423 1.3 ad * Reset the controller. Return non-zero on failure.
424 1.3 ad */
425 1.12 perry static int
426 1.3 ad mlx_v3_reset(struct mlx_softc *mlx)
427 1.3 ad {
428 1.3 ad int i;
429 1.3 ad
430 1.3 ad mlx_outb(mlx, MLX_V3REG_IDB, MLX_V3_IDB_SACK);
431 1.3 ad delay(1000000);
432 1.3 ad
433 1.3 ad /* Wait up to 2 minutes for the bit to clear. */
434 1.3 ad for (i = 120; i != 0; i--) {
435 1.3 ad delay(1000000);
436 1.3 ad if ((mlx_inb(mlx, MLX_V3REG_IDB) & MLX_V3_IDB_SACK) == 0)
437 1.3 ad break;
438 1.3 ad }
439 1.3 ad if (i == 0) {
440 1.3 ad /* ZZZ */
441 1.3 ad printf("mlx0: SACK didn't clear\n");
442 1.3 ad return (-1);
443 1.3 ad }
444 1.3 ad
445 1.3 ad mlx_outb(mlx, MLX_V3REG_IDB, MLX_V3_IDB_RESET);
446 1.3 ad
447 1.3 ad /* Wait up to 5 seconds for the bit to clear. */
448 1.3 ad for (i = 5; i != 0; i--) {
449 1.3 ad delay(1000000);
450 1.3 ad if ((mlx_inb(mlx, MLX_V3REG_IDB) & MLX_V3_IDB_RESET) == 0)
451 1.3 ad break;
452 1.3 ad }
453 1.3 ad if (i == 0) {
454 1.3 ad /* ZZZ */
455 1.3 ad printf("mlx0: RESET didn't clear\n");
456 1.3 ad return (-1);
457 1.3 ad }
458 1.3 ad
459 1.3 ad return (0);
460 1.3 ad }
461 1.3 ad #endif /* MLX_RESET */
462 1.3 ad
463 1.1 ad /*
464 1.1 ad * ================= V4 interface linkage =================
465 1.1 ad */
466 1.1 ad
467 1.1 ad /*
468 1.1 ad * Try to give (mc) to the controller. Returns 1 if successful, 0 on
469 1.1 ad * failure (the controller is not ready to take a command).
470 1.1 ad *
471 1.1 ad * Must be called at splbio or in a fashion that prevents reentry.
472 1.1 ad */
473 1.1 ad static int
474 1.1 ad mlx_v4_submit(struct mlx_softc *mlx, struct mlx_ccb *mc)
475 1.1 ad {
476 1.1 ad
477 1.1 ad /* Ready for our command? */
478 1.1 ad if ((mlx_inl(mlx, MLX_V4REG_IDB) & MLX_V4_IDB_FULL) == 0) {
479 1.1 ad /* Copy mailbox data to window. */
480 1.3 ad bus_space_write_region_1(mlx->mlx_iot, mlx->mlx_ioh,
481 1.8 ad MLX_V4REG_MAILBOX, mc->mc_mbox, 13);
482 1.1 ad bus_space_barrier(mlx->mlx_iot, mlx->mlx_ioh,
483 1.8 ad MLX_V4REG_MAILBOX, 13,
484 1.1 ad BUS_SPACE_BARRIER_WRITE);
485 1.1 ad
486 1.1 ad /* Post command. */
487 1.1 ad mlx_outl(mlx, MLX_V4REG_IDB, MLX_V4_IDB_HWMBOX_CMD);
488 1.1 ad return (1);
489 1.1 ad }
490 1.1 ad
491 1.1 ad return (0);
492 1.1 ad }
493 1.1 ad
494 1.1 ad /*
495 1.1 ad * See if a command has been completed, if so acknowledge its completion and
496 1.1 ad * recover the slot number and status code.
497 1.1 ad *
498 1.1 ad * Must be called at splbio or in a fashion that prevents reentry.
499 1.1 ad */
500 1.1 ad static int
501 1.1 ad mlx_v4_findcomplete(struct mlx_softc *mlx, u_int *slot, u_int *status)
502 1.1 ad {
503 1.1 ad
504 1.1 ad /* Status available? */
505 1.1 ad if ((mlx_inl(mlx, MLX_V4REG_ODB) & MLX_V4_ODB_HWSAVAIL) != 0) {
506 1.1 ad *slot = mlx_inb(mlx, MLX_V4REG_STATUS_IDENT);
507 1.1 ad *status = mlx_inw(mlx, MLX_V4REG_STATUS);
508 1.1 ad
509 1.1 ad /* Acknowledge completion. */
510 1.1 ad mlx_outl(mlx, MLX_V4REG_ODB, MLX_V4_ODB_HWMBOX_ACK);
511 1.1 ad mlx_outl(mlx, MLX_V4REG_IDB, MLX_V4_IDB_SACK);
512 1.1 ad return (1);
513 1.1 ad }
514 1.1 ad
515 1.1 ad return (0);
516 1.1 ad }
517 1.1 ad
518 1.1 ad /*
519 1.1 ad * Enable/disable interrupts as requested.
520 1.1 ad *
521 1.1 ad * Must be called at splbio or in a fashion that prevents reentry.
522 1.1 ad */
523 1.1 ad static void
524 1.1 ad mlx_v4_intaction(struct mlx_softc *mlx, int action)
525 1.1 ad {
526 1.1 ad u_int32_t ier;
527 1.1 ad
528 1.1 ad if (!action)
529 1.1 ad ier = MLX_V4_IE_MASK | MLX_V4_IE_DISINT;
530 1.1 ad else
531 1.1 ad ier = MLX_V4_IE_MASK & ~MLX_V4_IE_DISINT;
532 1.1 ad
533 1.1 ad mlx_outl(mlx, MLX_V4REG_IE, ier);
534 1.1 ad }
535 1.1 ad
536 1.1 ad /*
537 1.1 ad * Poll for firmware error codes during controller initialisation.
538 1.1 ad *
539 1.1 ad * Returns 0 if initialisation is complete, 1 if still in progress but no
540 1.1 ad * error has been fetched, 2 if an error has been retrieved.
541 1.1 ad */
542 1.12 perry static int
543 1.1 ad mlx_v4_fw_handshake(struct mlx_softc *mlx, int *error, int *param1, int *param2)
544 1.1 ad {
545 1.1 ad u_int8_t fwerror;
546 1.1 ad
547 1.1 ad /* First time around, clear any hardware completion status. */
548 1.1 ad if ((mlx->mlx_flags & MLXF_FW_INITTED) == 0) {
549 1.1 ad mlx_outl(mlx, MLX_V4REG_IDB, MLX_V4_IDB_SACK);
550 1.1 ad DELAY(1000);
551 1.1 ad mlx->mlx_flags |= MLXF_FW_INITTED;
552 1.1 ad }
553 1.1 ad
554 1.1 ad /* Init in progress? */
555 1.1 ad if ((mlx_inl(mlx, MLX_V4REG_IDB) & MLX_V4_IDB_INIT_BUSY) == 0)
556 1.1 ad return (0);
557 1.1 ad
558 1.1 ad /* Test error value */
559 1.1 ad fwerror = mlx_inb(mlx, MLX_V4REG_FWERROR);
560 1.1 ad if ((fwerror & MLX_V4_FWERROR_PEND) == 0)
561 1.1 ad return (1);
562 1.1 ad
563 1.1 ad /* Mask status pending bit, fetch status. */
564 1.1 ad *error = fwerror & ~MLX_V4_FWERROR_PEND;
565 1.1 ad *param1 = mlx_inb(mlx, MLX_V4REG_FWERROR_PARAM1);
566 1.1 ad *param2 = mlx_inb(mlx, MLX_V4REG_FWERROR_PARAM2);
567 1.1 ad
568 1.1 ad /* Acknowledge. */
569 1.1 ad mlx_outb(mlx, MLX_V4REG_FWERROR, 0);
570 1.1 ad
571 1.1 ad return (2);
572 1.1 ad }
573 1.1 ad
574 1.1 ad /*
575 1.1 ad * ================= V5 interface linkage =================
576 1.1 ad */
577 1.1 ad
578 1.1 ad /*
579 1.1 ad * Try to give (mc) to the controller. Returns 1 if successful, 0 on failure
580 1.1 ad * (the controller is not ready to take a command).
581 1.1 ad *
582 1.1 ad * Must be called at splbio or in a fashion that prevents reentry.
583 1.1 ad */
584 1.1 ad static int
585 1.1 ad mlx_v5_submit(struct mlx_softc *mlx, struct mlx_ccb *mc)
586 1.1 ad {
587 1.1 ad
588 1.1 ad /* Ready for our command? */
589 1.1 ad if ((mlx_inb(mlx, MLX_V5REG_IDB) & MLX_V5_IDB_EMPTY) != 0) {
590 1.1 ad /* Copy mailbox data to window. */
591 1.3 ad bus_space_write_region_1(mlx->mlx_iot, mlx->mlx_ioh,
592 1.8 ad MLX_V5REG_MAILBOX, mc->mc_mbox, 13);
593 1.1 ad bus_space_barrier(mlx->mlx_iot, mlx->mlx_ioh,
594 1.8 ad MLX_V5REG_MAILBOX, 13,
595 1.1 ad BUS_SPACE_BARRIER_WRITE);
596 1.1 ad
597 1.1 ad /* Post command */
598 1.1 ad mlx_outb(mlx, MLX_V5REG_IDB, MLX_V5_IDB_HWMBOX_CMD);
599 1.1 ad return (1);
600 1.1 ad }
601 1.1 ad
602 1.1 ad return (0);
603 1.1 ad }
604 1.1 ad
605 1.1 ad /*
606 1.1 ad * See if a command has been completed, if so acknowledge its completion and
607 1.1 ad * recover the slot number and status code.
608 1.1 ad *
609 1.1 ad * Must be called at splbio or in a fashion that prevents reentry.
610 1.1 ad */
611 1.1 ad static int
612 1.1 ad mlx_v5_findcomplete(struct mlx_softc *mlx, u_int *slot, u_int *status)
613 1.1 ad {
614 1.1 ad
615 1.1 ad /* Status available? */
616 1.1 ad if ((mlx_inb(mlx, MLX_V5REG_ODB) & MLX_V5_ODB_HWSAVAIL) != 0) {
617 1.1 ad *slot = mlx_inb(mlx, MLX_V5REG_STATUS_IDENT);
618 1.1 ad *status = mlx_inw(mlx, MLX_V5REG_STATUS);
619 1.1 ad
620 1.1 ad /* Acknowledge completion. */
621 1.1 ad mlx_outb(mlx, MLX_V5REG_ODB, MLX_V5_ODB_HWMBOX_ACK);
622 1.1 ad mlx_outb(mlx, MLX_V5REG_IDB, MLX_V5_IDB_SACK);
623 1.1 ad return (1);
624 1.1 ad }
625 1.1 ad
626 1.1 ad return (0);
627 1.1 ad }
628 1.1 ad
629 1.1 ad /*
630 1.1 ad * Enable/disable interrupts as requested.
631 1.1 ad *
632 1.1 ad * Must be called at splbio or in a fashion that prevents reentry.
633 1.1 ad */
634 1.1 ad static void
635 1.1 ad mlx_v5_intaction(struct mlx_softc *mlx, int action)
636 1.1 ad {
637 1.1 ad u_int8_t ier;
638 1.1 ad
639 1.1 ad if (!action)
640 1.1 ad ier = 0xff & MLX_V5_IE_DISINT;
641 1.1 ad else
642 1.1 ad ier = 0xff & ~MLX_V5_IE_DISINT;
643 1.1 ad
644 1.1 ad mlx_outb(mlx, MLX_V5REG_IE, ier);
645 1.1 ad }
646 1.1 ad
647 1.1 ad /*
648 1.1 ad * Poll for firmware error codes during controller initialisation.
649 1.1 ad *
650 1.1 ad * Returns 0 if initialisation is complete, 1 if still in progress but no
651 1.1 ad * error has been fetched, 2 if an error has been retrieved.
652 1.1 ad */
653 1.12 perry static int
654 1.1 ad mlx_v5_fw_handshake(struct mlx_softc *mlx, int *error, int *param1, int *param2)
655 1.1 ad {
656 1.1 ad u_int8_t fwerror;
657 1.1 ad
658 1.1 ad /* First time around, clear any hardware completion status. */
659 1.1 ad if ((mlx->mlx_flags & MLXF_FW_INITTED) == 0) {
660 1.1 ad mlx_outb(mlx, MLX_V5REG_IDB, MLX_V5_IDB_SACK);
661 1.1 ad DELAY(1000);
662 1.1 ad mlx->mlx_flags |= MLXF_FW_INITTED;
663 1.1 ad }
664 1.1 ad
665 1.1 ad /* Init in progress? */
666 1.1 ad if ((mlx_inb(mlx, MLX_V5REG_IDB) & MLX_V5_IDB_INIT_DONE) != 0)
667 1.1 ad return (0);
668 1.1 ad
669 1.1 ad /* Test for error value. */
670 1.1 ad fwerror = mlx_inb(mlx, MLX_V5REG_FWERROR);
671 1.1 ad if ((fwerror & MLX_V5_FWERROR_PEND) == 0)
672 1.1 ad return (1);
673 1.1 ad
674 1.1 ad /* Mask status pending bit, fetch status. */
675 1.1 ad *error = fwerror & ~MLX_V5_FWERROR_PEND;
676 1.1 ad *param1 = mlx_inb(mlx, MLX_V5REG_FWERROR_PARAM1);
677 1.1 ad *param2 = mlx_inb(mlx, MLX_V5REG_FWERROR_PARAM2);
678 1.1 ad
679 1.1 ad /* Acknowledge. */
680 1.1 ad mlx_outb(mlx, MLX_V5REG_FWERROR, 0xff);
681 1.1 ad
682 1.1 ad return (2);
683 1.1 ad }
684 1.26 pgoyette
685 1.26 pgoyette MODULE(MODULE_CLASS_DRIVER, mlx_pci, "mlx,pci");
686 1.26 pgoyette
687 1.26 pgoyette #ifdef _MODULE
688 1.26 pgoyette /*
689 1.26 pgoyette * XXX Don't allow ioconf.c to redefine the "struct cfdriver ld_cd"
690 1.26 pgoyette * XXX it will be defined in the common-code module
691 1.26 pgoyette */
692 1.26 pgoyette #undef CFDRIVER_DECL
693 1.26 pgoyette #define CFDRIVER_DECL(name, class, attr)
694 1.26 pgoyette #include "ioconf.c"
695 1.26 pgoyette #endif
696 1.26 pgoyette
697 1.26 pgoyette static int
698 1.26 pgoyette mlx_pci_modcmd(modcmd_t cmd, void *opaque)
699 1.26 pgoyette {
700 1.26 pgoyette int error = 0;
701 1.26 pgoyette
702 1.26 pgoyette #ifdef _MODULE
703 1.26 pgoyette switch (cmd) {
704 1.26 pgoyette case MODULE_CMD_INIT:
705 1.26 pgoyette /*
706 1.26 pgoyette * We skip over the first entry in cfdriver[] array
707 1.26 pgoyette * since the cfdriver is attached by the common
708 1.26 pgoyette * (non-attachment-specific) code.
709 1.26 pgoyette */
710 1.26 pgoyette error = config_init_component(&cfdriver_ioconf_mlx_pci[1],
711 1.26 pgoyette cfattach_ioconf_mlx_pci, cfdata_ioconf_mlx_pci);
712 1.26 pgoyette break;
713 1.26 pgoyette case MODULE_CMD_FINI:
714 1.26 pgoyette error = config_fini_component(&cfdriver_ioconf_mlx_pci[1],
715 1.26 pgoyette cfattach_ioconf_mlx_pci, cfdata_ioconf_mlx_pci);
716 1.26 pgoyette break;
717 1.26 pgoyette default:
718 1.26 pgoyette error = ENOTTY;
719 1.26 pgoyette break;
720 1.26 pgoyette }
721 1.26 pgoyette #endif
722 1.26 pgoyette
723 1.26 pgoyette return error;
724 1.26 pgoyette }
725