mly.c revision 1.7.2.6
1 1.7.2.6 nathanw /* $NetBSD: mly.c,v 1.7.2.6 2002/09/17 21:20:18 nathanw Exp $ */ 2 1.7.2.2 nathanw 3 1.7.2.2 nathanw /*- 4 1.7.2.2 nathanw * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 1.7.2.2 nathanw * All rights reserved. 6 1.7.2.2 nathanw * 7 1.7.2.2 nathanw * This code is derived from software contributed to The NetBSD Foundation 8 1.7.2.2 nathanw * by Andrew Doran, Thor Lancelot Simon, and Eric Haszlakiewicz. 9 1.7.2.2 nathanw * 10 1.7.2.2 nathanw * Redistribution and use in source and binary forms, with or without 11 1.7.2.2 nathanw * modification, are permitted provided that the following conditions 12 1.7.2.2 nathanw * are met: 13 1.7.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 14 1.7.2.2 nathanw * notice, this list of conditions and the following disclaimer. 15 1.7.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 16 1.7.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 17 1.7.2.2 nathanw * documentation and/or other materials provided with the distribution. 18 1.7.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 19 1.7.2.2 nathanw * must display the following acknowledgement: 20 1.7.2.2 nathanw * This product includes software developed by the NetBSD 21 1.7.2.2 nathanw * Foundation, Inc. and its contributors. 22 1.7.2.2 nathanw * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.7.2.2 nathanw * contributors may be used to endorse or promote products derived 24 1.7.2.2 nathanw * from this software without specific prior written permission. 25 1.7.2.2 nathanw * 26 1.7.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.7.2.2 nathanw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.7.2.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.7.2.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.7.2.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.7.2.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.7.2.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.7.2.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.7.2.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.7.2.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.7.2.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 37 1.7.2.2 nathanw */ 38 1.7.2.2 nathanw 39 1.7.2.2 nathanw /*- 40 1.7.2.2 nathanw * Copyright (c) 2000, 2001 Michael Smith 41 1.7.2.2 nathanw * Copyright (c) 2000 BSDi 42 1.7.2.2 nathanw * All rights reserved. 43 1.7.2.2 nathanw * 44 1.7.2.2 nathanw * Redistribution and use in source and binary forms, with or without 45 1.7.2.2 nathanw * modification, are permitted provided that the following conditions 46 1.7.2.2 nathanw * are met: 47 1.7.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 48 1.7.2.2 nathanw * notice, this list of conditions and the following disclaimer. 49 1.7.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 50 1.7.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 51 1.7.2.2 nathanw * documentation and/or other materials provided with the distribution. 52 1.7.2.2 nathanw * 53 1.7.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 1.7.2.2 nathanw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 1.7.2.2 nathanw * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 1.7.2.2 nathanw * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 1.7.2.2 nathanw * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 1.7.2.2 nathanw * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 1.7.2.2 nathanw * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 1.7.2.2 nathanw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 1.7.2.2 nathanw * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 1.7.2.2 nathanw * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 1.7.2.2 nathanw * SUCH DAMAGE. 64 1.7.2.2 nathanw * 65 1.7.2.2 nathanw * from FreeBSD: mly.c,v 1.8 2001/07/14 00:12:22 msmith Exp 66 1.7.2.2 nathanw */ 67 1.7.2.2 nathanw 68 1.7.2.2 nathanw /* 69 1.7.2.2 nathanw * Driver for the Mylex AcceleRAID and eXtremeRAID family with v6 firmware. 70 1.7.2.2 nathanw * 71 1.7.2.2 nathanw * TODO: 72 1.7.2.2 nathanw * 73 1.7.2.2 nathanw * o Make mly->mly_btl a hash, then MLY_BTL_RESCAN becomes a SIMPLEQ. 74 1.7.2.2 nathanw * o Handle FC and multiple LUNs. 75 1.7.2.2 nathanw * o Fix mmbox usage. 76 1.7.2.2 nathanw * o Fix transfer speed fudge. 77 1.7.2.2 nathanw */ 78 1.7.2.2 nathanw 79 1.7.2.3 nathanw #include <sys/cdefs.h> 80 1.7.2.6 nathanw __KERNEL_RCSID(0, "$NetBSD: mly.c,v 1.7.2.6 2002/09/17 21:20:18 nathanw Exp $"); 81 1.7.2.3 nathanw 82 1.7.2.2 nathanw #include <sys/param.h> 83 1.7.2.2 nathanw #include <sys/systm.h> 84 1.7.2.2 nathanw #include <sys/device.h> 85 1.7.2.2 nathanw #include <sys/kernel.h> 86 1.7.2.2 nathanw #include <sys/queue.h> 87 1.7.2.2 nathanw #include <sys/buf.h> 88 1.7.2.2 nathanw #include <sys/endian.h> 89 1.7.2.2 nathanw #include <sys/conf.h> 90 1.7.2.2 nathanw #include <sys/malloc.h> 91 1.7.2.2 nathanw #include <sys/ioctl.h> 92 1.7.2.2 nathanw #include <sys/scsiio.h> 93 1.7.2.2 nathanw #include <sys/kthread.h> 94 1.7.2.2 nathanw 95 1.7.2.2 nathanw #include <uvm/uvm_extern.h> 96 1.7.2.2 nathanw 97 1.7.2.2 nathanw #include <machine/bus.h> 98 1.7.2.2 nathanw 99 1.7.2.2 nathanw #include <dev/scsipi/scsi_all.h> 100 1.7.2.2 nathanw #include <dev/scsipi/scsipi_all.h> 101 1.7.2.2 nathanw #include <dev/scsipi/scsiconf.h> 102 1.7.2.2 nathanw 103 1.7.2.2 nathanw #include <dev/pci/pcireg.h> 104 1.7.2.2 nathanw #include <dev/pci/pcivar.h> 105 1.7.2.2 nathanw #include <dev/pci/pcidevs.h> 106 1.7.2.2 nathanw 107 1.7.2.2 nathanw #include <dev/pci/mlyreg.h> 108 1.7.2.2 nathanw #include <dev/pci/mlyio.h> 109 1.7.2.2 nathanw #include <dev/pci/mlyvar.h> 110 1.7.2.2 nathanw #include <dev/pci/mly_tables.h> 111 1.7.2.2 nathanw 112 1.7.2.2 nathanw static void mly_attach(struct device *, struct device *, void *); 113 1.7.2.2 nathanw static int mly_match(struct device *, struct cfdata *, void *); 114 1.7.2.2 nathanw static const struct mly_ident *mly_find_ident(struct pci_attach_args *); 115 1.7.2.2 nathanw static int mly_fwhandshake(struct mly_softc *); 116 1.7.2.2 nathanw static int mly_flush(struct mly_softc *); 117 1.7.2.2 nathanw static int mly_intr(void *); 118 1.7.2.2 nathanw static void mly_shutdown(void *); 119 1.7.2.2 nathanw 120 1.7.2.2 nathanw static int mly_alloc_ccbs(struct mly_softc *); 121 1.7.2.2 nathanw static void mly_check_event(struct mly_softc *); 122 1.7.2.2 nathanw static void mly_complete_event(struct mly_softc *, struct mly_ccb *); 123 1.7.2.2 nathanw static void mly_complete_rescan(struct mly_softc *, struct mly_ccb *); 124 1.7.2.2 nathanw static int mly_dmamem_alloc(struct mly_softc *, int, bus_dmamap_t *, 125 1.7.2.2 nathanw caddr_t *, bus_addr_t *, bus_dma_segment_t *); 126 1.7.2.2 nathanw static void mly_dmamem_free(struct mly_softc *, int, bus_dmamap_t, 127 1.7.2.2 nathanw caddr_t, bus_dma_segment_t *); 128 1.7.2.2 nathanw static int mly_enable_mmbox(struct mly_softc *); 129 1.7.2.2 nathanw static void mly_fetch_event(struct mly_softc *); 130 1.7.2.2 nathanw static int mly_get_controllerinfo(struct mly_softc *); 131 1.7.2.2 nathanw static int mly_get_eventstatus(struct mly_softc *); 132 1.7.2.2 nathanw static int mly_ioctl(struct mly_softc *, struct mly_cmd_ioctl *, 133 1.7.2.2 nathanw void **, size_t, void *, size_t *); 134 1.7.2.2 nathanw static void mly_padstr(char *, const char *, int); 135 1.7.2.2 nathanw static void mly_process_event(struct mly_softc *, struct mly_event *); 136 1.7.2.2 nathanw static void mly_release_ccbs(struct mly_softc *); 137 1.7.2.2 nathanw static int mly_scan_btl(struct mly_softc *, int, int); 138 1.7.2.2 nathanw static void mly_scan_channel(struct mly_softc *, int); 139 1.7.2.2 nathanw static void mly_thread(void *); 140 1.7.2.2 nathanw static void mly_thread_create(void *); 141 1.7.2.2 nathanw 142 1.7.2.2 nathanw static int mly_ccb_alloc(struct mly_softc *, struct mly_ccb **); 143 1.7.2.2 nathanw static void mly_ccb_complete(struct mly_softc *, struct mly_ccb *); 144 1.7.2.2 nathanw static void mly_ccb_enqueue(struct mly_softc *, struct mly_ccb *); 145 1.7.2.2 nathanw static void mly_ccb_free(struct mly_softc *, struct mly_ccb *); 146 1.7.2.2 nathanw static int mly_ccb_map(struct mly_softc *, struct mly_ccb *); 147 1.7.2.2 nathanw static int mly_ccb_poll(struct mly_softc *, struct mly_ccb *, int); 148 1.7.2.2 nathanw static int mly_ccb_submit(struct mly_softc *, struct mly_ccb *); 149 1.7.2.2 nathanw static void mly_ccb_unmap(struct mly_softc *, struct mly_ccb *); 150 1.7.2.2 nathanw static int mly_ccb_wait(struct mly_softc *, struct mly_ccb *, int); 151 1.7.2.2 nathanw 152 1.7.2.2 nathanw static void mly_get_xfer_mode(struct mly_softc *, int, 153 1.7.2.2 nathanw struct scsipi_xfer_mode *); 154 1.7.2.2 nathanw static void mly_scsipi_complete(struct mly_softc *, struct mly_ccb *); 155 1.7.2.2 nathanw static int mly_scsipi_ioctl(struct scsipi_channel *, u_long, caddr_t, 156 1.7.2.2 nathanw int, struct proc *); 157 1.7.2.2 nathanw static void mly_scsipi_minphys(struct buf *); 158 1.7.2.2 nathanw static void mly_scsipi_request(struct scsipi_channel *, 159 1.7.2.2 nathanw scsipi_adapter_req_t, void *); 160 1.7.2.2 nathanw 161 1.7.2.2 nathanw static int mly_user_command(struct mly_softc *, struct mly_user_command *); 162 1.7.2.2 nathanw static int mly_user_health(struct mly_softc *, struct mly_user_health *); 163 1.7.2.2 nathanw 164 1.7.2.2 nathanw extern struct cfdriver mly_cd; 165 1.7.2.2 nathanw 166 1.7.2.2 nathanw struct cfattach mly_ca = { 167 1.7.2.2 nathanw sizeof(struct mly_softc), mly_match, mly_attach 168 1.7.2.2 nathanw }; 169 1.7.2.2 nathanw 170 1.7.2.6 nathanw dev_type_open(mlyopen); 171 1.7.2.6 nathanw dev_type_close(mlyclose); 172 1.7.2.6 nathanw dev_type_ioctl(mlyioctl); 173 1.7.2.6 nathanw 174 1.7.2.6 nathanw const struct cdevsw mly_cdevsw = { 175 1.7.2.6 nathanw mlyopen, mlyclose, noread, nowrite, mlyioctl, 176 1.7.2.6 nathanw nostop, notty, nopoll, nommap, 177 1.7.2.6 nathanw }; 178 1.7.2.6 nathanw 179 1.7.2.2 nathanw struct mly_ident { 180 1.7.2.2 nathanw u_short vendor; 181 1.7.2.2 nathanw u_short product; 182 1.7.2.2 nathanw u_short subvendor; 183 1.7.2.2 nathanw u_short subproduct; 184 1.7.2.2 nathanw int hwif; 185 1.7.2.2 nathanw const char *desc; 186 1.7.2.2 nathanw } static const mly_ident[] = { 187 1.7.2.2 nathanw { 188 1.7.2.2 nathanw PCI_VENDOR_MYLEX, 189 1.7.2.2 nathanw PCI_PRODUCT_MYLEX_EXTREMERAID, 190 1.7.2.2 nathanw PCI_VENDOR_MYLEX, 191 1.7.2.2 nathanw 0x0040, 192 1.7.2.2 nathanw MLY_HWIF_STRONGARM, 193 1.7.2.2 nathanw "eXtremeRAID 2000" 194 1.7.2.2 nathanw }, 195 1.7.2.2 nathanw { 196 1.7.2.2 nathanw PCI_VENDOR_MYLEX, 197 1.7.2.2 nathanw PCI_PRODUCT_MYLEX_EXTREMERAID, 198 1.7.2.2 nathanw PCI_VENDOR_MYLEX, 199 1.7.2.2 nathanw 0x0030, 200 1.7.2.2 nathanw MLY_HWIF_STRONGARM, 201 1.7.2.2 nathanw "eXtremeRAID 3000" 202 1.7.2.2 nathanw }, 203 1.7.2.2 nathanw { 204 1.7.2.2 nathanw PCI_VENDOR_MYLEX, 205 1.7.2.2 nathanw PCI_PRODUCT_MYLEX_ACCELERAID, 206 1.7.2.2 nathanw PCI_VENDOR_MYLEX, 207 1.7.2.2 nathanw 0x0050, 208 1.7.2.2 nathanw MLY_HWIF_I960RX, 209 1.7.2.2 nathanw "AcceleRAID 352" 210 1.7.2.2 nathanw }, 211 1.7.2.2 nathanw { 212 1.7.2.2 nathanw PCI_VENDOR_MYLEX, 213 1.7.2.2 nathanw PCI_PRODUCT_MYLEX_ACCELERAID, 214 1.7.2.2 nathanw PCI_VENDOR_MYLEX, 215 1.7.2.2 nathanw 0x0052, 216 1.7.2.2 nathanw MLY_HWIF_I960RX, 217 1.7.2.2 nathanw "AcceleRAID 170" 218 1.7.2.2 nathanw }, 219 1.7.2.2 nathanw { 220 1.7.2.2 nathanw PCI_VENDOR_MYLEX, 221 1.7.2.2 nathanw PCI_PRODUCT_MYLEX_ACCELERAID, 222 1.7.2.2 nathanw PCI_VENDOR_MYLEX, 223 1.7.2.2 nathanw 0x0054, 224 1.7.2.2 nathanw MLY_HWIF_I960RX, 225 1.7.2.2 nathanw "AcceleRAID 160" 226 1.7.2.2 nathanw }, 227 1.7.2.2 nathanw }; 228 1.7.2.2 nathanw 229 1.7.2.2 nathanw static void *mly_sdh; 230 1.7.2.2 nathanw 231 1.7.2.2 nathanw /* 232 1.7.2.2 nathanw * Try to find a `mly_ident' entry corresponding to this board. 233 1.7.2.2 nathanw */ 234 1.7.2.2 nathanw static const struct mly_ident * 235 1.7.2.2 nathanw mly_find_ident(struct pci_attach_args *pa) 236 1.7.2.2 nathanw { 237 1.7.2.2 nathanw const struct mly_ident *mpi, *maxmpi; 238 1.7.2.2 nathanw pcireg_t reg; 239 1.7.2.2 nathanw 240 1.7.2.2 nathanw mpi = mly_ident; 241 1.7.2.2 nathanw maxmpi = mpi + sizeof(mly_ident) / sizeof(mly_ident[0]); 242 1.7.2.2 nathanw 243 1.7.2.2 nathanw if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 244 1.7.2.2 nathanw return (NULL); 245 1.7.2.2 nathanw 246 1.7.2.2 nathanw for (; mpi < maxmpi; mpi++) { 247 1.7.2.2 nathanw if (PCI_VENDOR(pa->pa_id) != mpi->vendor || 248 1.7.2.2 nathanw PCI_PRODUCT(pa->pa_id) != mpi->product) 249 1.7.2.2 nathanw continue; 250 1.7.2.2 nathanw 251 1.7.2.2 nathanw if (mpi->subvendor == 0x0000) 252 1.7.2.2 nathanw return (mpi); 253 1.7.2.2 nathanw 254 1.7.2.2 nathanw reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 255 1.7.2.2 nathanw 256 1.7.2.2 nathanw if (PCI_VENDOR(reg) == mpi->subvendor && 257 1.7.2.2 nathanw PCI_PRODUCT(reg) == mpi->subproduct) 258 1.7.2.2 nathanw return (mpi); 259 1.7.2.2 nathanw } 260 1.7.2.2 nathanw 261 1.7.2.2 nathanw return (NULL); 262 1.7.2.2 nathanw } 263 1.7.2.2 nathanw 264 1.7.2.2 nathanw /* 265 1.7.2.2 nathanw * Match a supported board. 266 1.7.2.2 nathanw */ 267 1.7.2.2 nathanw static int 268 1.7.2.2 nathanw mly_match(struct device *parent, struct cfdata *cfdata, void *aux) 269 1.7.2.2 nathanw { 270 1.7.2.2 nathanw 271 1.7.2.2 nathanw return (mly_find_ident(aux) != NULL); 272 1.7.2.2 nathanw } 273 1.7.2.2 nathanw 274 1.7.2.2 nathanw /* 275 1.7.2.2 nathanw * Attach a supported board. 276 1.7.2.2 nathanw */ 277 1.7.2.2 nathanw static void 278 1.7.2.2 nathanw mly_attach(struct device *parent, struct device *self, void *aux) 279 1.7.2.2 nathanw { 280 1.7.2.2 nathanw struct pci_attach_args *pa; 281 1.7.2.2 nathanw struct mly_softc *mly; 282 1.7.2.2 nathanw struct mly_ioctl_getcontrollerinfo *mi; 283 1.7.2.2 nathanw const struct mly_ident *ident; 284 1.7.2.2 nathanw pci_chipset_tag_t pc; 285 1.7.2.2 nathanw pci_intr_handle_t ih; 286 1.7.2.2 nathanw bus_space_handle_t memh, ioh; 287 1.7.2.2 nathanw bus_space_tag_t memt, iot; 288 1.7.2.2 nathanw pcireg_t reg; 289 1.7.2.2 nathanw const char *intrstr; 290 1.7.2.2 nathanw int ior, memr, i, rv, state; 291 1.7.2.2 nathanw struct scsipi_adapter *adapt; 292 1.7.2.2 nathanw struct scsipi_channel *chan; 293 1.7.2.2 nathanw 294 1.7.2.2 nathanw mly = (struct mly_softc *)self; 295 1.7.2.2 nathanw pa = aux; 296 1.7.2.2 nathanw pc = pa->pa_pc; 297 1.7.2.2 nathanw ident = mly_find_ident(pa); 298 1.7.2.2 nathanw state = 0; 299 1.7.2.2 nathanw 300 1.7.2.2 nathanw mly->mly_dmat = pa->pa_dmat; 301 1.7.2.2 nathanw mly->mly_hwif = ident->hwif; 302 1.7.2.2 nathanw 303 1.7.2.2 nathanw printf(": Mylex %s\n", ident->desc); 304 1.7.2.2 nathanw 305 1.7.2.2 nathanw /* 306 1.7.2.2 nathanw * Map the PCI register window. 307 1.7.2.2 nathanw */ 308 1.7.2.2 nathanw memr = -1; 309 1.7.2.2 nathanw ior = -1; 310 1.7.2.2 nathanw 311 1.7.2.2 nathanw for (i = 0x10; i <= 0x14; i += 4) { 312 1.7.2.2 nathanw reg = pci_conf_read(pa->pa_pc, pa->pa_tag, i); 313 1.7.2.2 nathanw 314 1.7.2.2 nathanw if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) { 315 1.7.2.2 nathanw if (ior == -1 && PCI_MAPREG_IO_SIZE(reg) != 0) 316 1.7.2.2 nathanw ior = i; 317 1.7.2.2 nathanw } else { 318 1.7.2.2 nathanw if (memr == -1 && PCI_MAPREG_MEM_SIZE(reg) != 0) 319 1.7.2.2 nathanw memr = i; 320 1.7.2.2 nathanw } 321 1.7.2.2 nathanw } 322 1.7.2.2 nathanw 323 1.7.2.2 nathanw if (memr != -1) 324 1.7.2.2 nathanw if (pci_mapreg_map(pa, memr, PCI_MAPREG_TYPE_MEM, 0, 325 1.7.2.2 nathanw &memt, &memh, NULL, NULL)) 326 1.7.2.2 nathanw memr = -1; 327 1.7.2.2 nathanw if (ior != -1) 328 1.7.2.2 nathanw if (pci_mapreg_map(pa, ior, PCI_MAPREG_TYPE_IO, 0, 329 1.7.2.2 nathanw &iot, &ioh, NULL, NULL)) 330 1.7.2.2 nathanw ior = -1; 331 1.7.2.2 nathanw 332 1.7.2.2 nathanw if (memr != -1) { 333 1.7.2.2 nathanw mly->mly_iot = memt; 334 1.7.2.2 nathanw mly->mly_ioh = memh; 335 1.7.2.2 nathanw } else if (ior != -1) { 336 1.7.2.2 nathanw mly->mly_iot = iot; 337 1.7.2.2 nathanw mly->mly_ioh = ioh; 338 1.7.2.2 nathanw } else { 339 1.7.2.2 nathanw printf("%s: can't map i/o or memory space\n", self->dv_xname); 340 1.7.2.2 nathanw return; 341 1.7.2.2 nathanw } 342 1.7.2.2 nathanw 343 1.7.2.2 nathanw /* 344 1.7.2.2 nathanw * Enable the device. 345 1.7.2.2 nathanw */ 346 1.7.2.2 nathanw reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 347 1.7.2.2 nathanw pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 348 1.7.2.2 nathanw reg | PCI_COMMAND_MASTER_ENABLE); 349 1.7.2.2 nathanw 350 1.7.2.2 nathanw /* 351 1.7.2.2 nathanw * Map and establish the interrupt. 352 1.7.2.2 nathanw */ 353 1.7.2.2 nathanw if (pci_intr_map(pa, &ih)) { 354 1.7.2.2 nathanw printf("%s: can't map interrupt\n", self->dv_xname); 355 1.7.2.2 nathanw return; 356 1.7.2.2 nathanw } 357 1.7.2.2 nathanw intrstr = pci_intr_string(pc, ih); 358 1.7.2.2 nathanw mly->mly_ih = pci_intr_establish(pc, ih, IPL_BIO, mly_intr, mly); 359 1.7.2.2 nathanw if (mly->mly_ih == NULL) { 360 1.7.2.2 nathanw printf("%s: can't establish interrupt", self->dv_xname); 361 1.7.2.2 nathanw if (intrstr != NULL) 362 1.7.2.2 nathanw printf(" at %s", intrstr); 363 1.7.2.2 nathanw printf("\n"); 364 1.7.2.2 nathanw return; 365 1.7.2.2 nathanw } 366 1.7.2.2 nathanw 367 1.7.2.2 nathanw if (intrstr != NULL) 368 1.7.2.2 nathanw printf("%s: interrupting at %s\n", mly->mly_dv.dv_xname, 369 1.7.2.2 nathanw intrstr); 370 1.7.2.2 nathanw 371 1.7.2.2 nathanw /* 372 1.7.2.2 nathanw * Take care of interface-specific tasks. 373 1.7.2.2 nathanw */ 374 1.7.2.2 nathanw switch (mly->mly_hwif) { 375 1.7.2.2 nathanw case MLY_HWIF_I960RX: 376 1.7.2.2 nathanw mly->mly_doorbell_true = 0x00; 377 1.7.2.2 nathanw mly->mly_cmd_mailbox = MLY_I960RX_COMMAND_MAILBOX; 378 1.7.2.2 nathanw mly->mly_status_mailbox = MLY_I960RX_STATUS_MAILBOX; 379 1.7.2.2 nathanw mly->mly_idbr = MLY_I960RX_IDBR; 380 1.7.2.2 nathanw mly->mly_odbr = MLY_I960RX_ODBR; 381 1.7.2.2 nathanw mly->mly_error_status = MLY_I960RX_ERROR_STATUS; 382 1.7.2.2 nathanw mly->mly_interrupt_status = MLY_I960RX_INTERRUPT_STATUS; 383 1.7.2.2 nathanw mly->mly_interrupt_mask = MLY_I960RX_INTERRUPT_MASK; 384 1.7.2.2 nathanw break; 385 1.7.2.2 nathanw 386 1.7.2.2 nathanw case MLY_HWIF_STRONGARM: 387 1.7.2.2 nathanw mly->mly_doorbell_true = 0xff; 388 1.7.2.2 nathanw mly->mly_cmd_mailbox = MLY_STRONGARM_COMMAND_MAILBOX; 389 1.7.2.2 nathanw mly->mly_status_mailbox = MLY_STRONGARM_STATUS_MAILBOX; 390 1.7.2.2 nathanw mly->mly_idbr = MLY_STRONGARM_IDBR; 391 1.7.2.2 nathanw mly->mly_odbr = MLY_STRONGARM_ODBR; 392 1.7.2.2 nathanw mly->mly_error_status = MLY_STRONGARM_ERROR_STATUS; 393 1.7.2.2 nathanw mly->mly_interrupt_status = MLY_STRONGARM_INTERRUPT_STATUS; 394 1.7.2.2 nathanw mly->mly_interrupt_mask = MLY_STRONGARM_INTERRUPT_MASK; 395 1.7.2.2 nathanw break; 396 1.7.2.2 nathanw } 397 1.7.2.2 nathanw 398 1.7.2.2 nathanw /* 399 1.7.2.2 nathanw * Allocate and map the scatter/gather lists. 400 1.7.2.2 nathanw */ 401 1.7.2.2 nathanw rv = mly_dmamem_alloc(mly, MLY_SGL_SIZE * MLY_MAX_CCBS, 402 1.7.2.2 nathanw &mly->mly_sg_dmamap, (caddr_t *)&mly->mly_sg, 403 1.7.2.2 nathanw &mly->mly_sg_busaddr, &mly->mly_sg_seg); 404 1.7.2.2 nathanw if (rv) { 405 1.7.2.2 nathanw printf("%s: unable to allocate S/G maps\n", 406 1.7.2.2 nathanw mly->mly_dv.dv_xname); 407 1.7.2.2 nathanw goto bad; 408 1.7.2.2 nathanw } 409 1.7.2.2 nathanw state++; 410 1.7.2.2 nathanw 411 1.7.2.2 nathanw /* 412 1.7.2.2 nathanw * Allocate and map the memory mailbox. 413 1.7.2.2 nathanw */ 414 1.7.2.2 nathanw rv = mly_dmamem_alloc(mly, sizeof(struct mly_mmbox), 415 1.7.2.2 nathanw &mly->mly_mmbox_dmamap, (caddr_t *)&mly->mly_mmbox, 416 1.7.2.2 nathanw &mly->mly_mmbox_busaddr, &mly->mly_mmbox_seg); 417 1.7.2.2 nathanw if (rv) { 418 1.7.2.2 nathanw printf("%s: unable to allocate mailboxes\n", 419 1.7.2.2 nathanw mly->mly_dv.dv_xname); 420 1.7.2.2 nathanw goto bad; 421 1.7.2.2 nathanw } 422 1.7.2.2 nathanw state++; 423 1.7.2.2 nathanw 424 1.7.2.2 nathanw /* 425 1.7.2.2 nathanw * Initialise per-controller queues. 426 1.7.2.2 nathanw */ 427 1.7.2.2 nathanw SLIST_INIT(&mly->mly_ccb_free); 428 1.7.2.2 nathanw SIMPLEQ_INIT(&mly->mly_ccb_queue); 429 1.7.2.2 nathanw 430 1.7.2.2 nathanw /* 431 1.7.2.2 nathanw * Disable interrupts before we start talking to the controller. 432 1.7.2.2 nathanw */ 433 1.7.2.2 nathanw mly_outb(mly, mly->mly_interrupt_mask, MLY_INTERRUPT_MASK_DISABLE); 434 1.7.2.2 nathanw 435 1.7.2.2 nathanw /* 436 1.7.2.2 nathanw * Wait for the controller to come ready, handshaking with the 437 1.7.2.2 nathanw * firmware if required. This is typically only necessary on 438 1.7.2.2 nathanw * platforms where the controller BIOS does not run. 439 1.7.2.2 nathanw */ 440 1.7.2.2 nathanw if (mly_fwhandshake(mly)) { 441 1.7.2.2 nathanw printf("%s: unable to bring controller online\n", 442 1.7.2.2 nathanw mly->mly_dv.dv_xname); 443 1.7.2.2 nathanw goto bad; 444 1.7.2.2 nathanw } 445 1.7.2.2 nathanw 446 1.7.2.2 nathanw /* 447 1.7.2.2 nathanw * Allocate initial command buffers, obtain controller feature 448 1.7.2.2 nathanw * information, and then reallocate command buffers, since we'll 449 1.7.2.2 nathanw * know how many we want. 450 1.7.2.2 nathanw */ 451 1.7.2.2 nathanw if (mly_alloc_ccbs(mly)) { 452 1.7.2.2 nathanw printf("%s: unable to allocate CCBs\n", 453 1.7.2.2 nathanw mly->mly_dv.dv_xname); 454 1.7.2.2 nathanw goto bad; 455 1.7.2.2 nathanw } 456 1.7.2.2 nathanw state++; 457 1.7.2.2 nathanw if (mly_get_controllerinfo(mly)) { 458 1.7.2.2 nathanw printf("%s: unable to retrieve controller info\n", 459 1.7.2.2 nathanw mly->mly_dv.dv_xname); 460 1.7.2.2 nathanw goto bad; 461 1.7.2.2 nathanw } 462 1.7.2.2 nathanw mly_release_ccbs(mly); 463 1.7.2.2 nathanw if (mly_alloc_ccbs(mly)) { 464 1.7.2.2 nathanw printf("%s: unable to allocate CCBs\n", 465 1.7.2.2 nathanw mly->mly_dv.dv_xname); 466 1.7.2.2 nathanw state--; 467 1.7.2.2 nathanw goto bad; 468 1.7.2.2 nathanw } 469 1.7.2.2 nathanw 470 1.7.2.2 nathanw /* 471 1.7.2.2 nathanw * Get the current event counter for health purposes, populate the 472 1.7.2.2 nathanw * initial health status buffer. 473 1.7.2.2 nathanw */ 474 1.7.2.2 nathanw if (mly_get_eventstatus(mly)) { 475 1.7.2.2 nathanw printf("%s: unable to retrieve event status\n", 476 1.7.2.2 nathanw mly->mly_dv.dv_xname); 477 1.7.2.2 nathanw goto bad; 478 1.7.2.2 nathanw } 479 1.7.2.2 nathanw 480 1.7.2.2 nathanw /* 481 1.7.2.2 nathanw * Enable memory-mailbox mode. 482 1.7.2.2 nathanw */ 483 1.7.2.2 nathanw if (mly_enable_mmbox(mly)) { 484 1.7.2.2 nathanw printf("%s: unable to enable memory mailbox\n", 485 1.7.2.2 nathanw mly->mly_dv.dv_xname); 486 1.7.2.2 nathanw goto bad; 487 1.7.2.2 nathanw } 488 1.7.2.2 nathanw 489 1.7.2.2 nathanw /* 490 1.7.2.2 nathanw * Print a little information about the controller. 491 1.7.2.2 nathanw */ 492 1.7.2.2 nathanw mi = mly->mly_controllerinfo; 493 1.7.2.2 nathanw 494 1.7.2.2 nathanw printf("%s: %d physical channel%s, firmware %d.%02d-%d-%02d " 495 1.7.2.2 nathanw "(%02d%02d%02d%02d), %dMB RAM\n", mly->mly_dv.dv_xname, 496 1.7.2.2 nathanw mi->physical_channels_present, 497 1.7.2.2 nathanw (mi->physical_channels_present) > 1 ? "s" : "", 498 1.7.2.2 nathanw mi->fw_major, mi->fw_minor, mi->fw_turn, mi->fw_build, 499 1.7.2.2 nathanw mi->fw_century, mi->fw_year, mi->fw_month, mi->fw_day, 500 1.7.2.2 nathanw le16toh(mi->memory_size)); 501 1.7.2.2 nathanw 502 1.7.2.2 nathanw /* 503 1.7.2.2 nathanw * Register our `shutdownhook'. 504 1.7.2.2 nathanw */ 505 1.7.2.2 nathanw if (mly_sdh == NULL) 506 1.7.2.2 nathanw shutdownhook_establish(mly_shutdown, NULL); 507 1.7.2.2 nathanw 508 1.7.2.2 nathanw /* 509 1.7.2.2 nathanw * Clear any previous BTL information. For each bus that scsipi 510 1.7.2.2 nathanw * wants to scan, we'll receive the SCBUSIOLLSCAN ioctl and retrieve 511 1.7.2.2 nathanw * all BTL info at that point. 512 1.7.2.2 nathanw */ 513 1.7.2.2 nathanw memset(&mly->mly_btl, 0, sizeof(mly->mly_btl)); 514 1.7.2.2 nathanw 515 1.7.2.2 nathanw mly->mly_nchans = mly->mly_controllerinfo->physical_channels_present + 516 1.7.2.2 nathanw mly->mly_controllerinfo->virtual_channels_present; 517 1.7.2.2 nathanw 518 1.7.2.2 nathanw /* 519 1.7.2.2 nathanw * Attach to scsipi. 520 1.7.2.2 nathanw */ 521 1.7.2.2 nathanw adapt = &mly->mly_adapt; 522 1.7.2.2 nathanw memset(adapt, 0, sizeof(*adapt)); 523 1.7.2.2 nathanw adapt->adapt_dev = &mly->mly_dv; 524 1.7.2.2 nathanw adapt->adapt_nchannels = mly->mly_nchans; 525 1.7.2.2 nathanw adapt->adapt_openings = mly->mly_ncmds - MLY_CCBS_RESV; 526 1.7.2.2 nathanw adapt->adapt_max_periph = mly->mly_ncmds - MLY_CCBS_RESV; 527 1.7.2.2 nathanw adapt->adapt_request = mly_scsipi_request; 528 1.7.2.2 nathanw adapt->adapt_minphys = mly_scsipi_minphys; 529 1.7.2.2 nathanw adapt->adapt_ioctl = mly_scsipi_ioctl; 530 1.7.2.2 nathanw 531 1.7.2.2 nathanw for (i = 0; i < mly->mly_nchans; i++) { 532 1.7.2.2 nathanw chan = &mly->mly_chans[i]; 533 1.7.2.2 nathanw memset(chan, 0, sizeof(*chan)); 534 1.7.2.2 nathanw chan->chan_adapter = adapt; 535 1.7.2.2 nathanw chan->chan_bustype = &scsi_bustype; 536 1.7.2.2 nathanw chan->chan_channel = i; 537 1.7.2.2 nathanw chan->chan_ntargets = MLY_MAX_TARGETS; 538 1.7.2.2 nathanw chan->chan_nluns = MLY_MAX_LUNS; 539 1.7.2.2 nathanw chan->chan_id = mly->mly_controllerparam->initiator_id; 540 1.7.2.2 nathanw chan->chan_flags = SCSIPI_CHAN_NOSETTLE; 541 1.7.2.2 nathanw config_found(&mly->mly_dv, chan, scsiprint); 542 1.7.2.2 nathanw } 543 1.7.2.2 nathanw 544 1.7.2.2 nathanw /* 545 1.7.2.2 nathanw * Now enable interrupts... 546 1.7.2.2 nathanw */ 547 1.7.2.2 nathanw mly_outb(mly, mly->mly_interrupt_mask, MLY_INTERRUPT_MASK_ENABLE); 548 1.7.2.2 nathanw 549 1.7.2.2 nathanw /* 550 1.7.2.2 nathanw * Finally, create our monitoring thread. 551 1.7.2.2 nathanw */ 552 1.7.2.2 nathanw kthread_create(mly_thread_create, mly); 553 1.7.2.2 nathanw 554 1.7.2.2 nathanw mly->mly_state |= MLY_STATE_INITOK; 555 1.7.2.2 nathanw return; 556 1.7.2.2 nathanw 557 1.7.2.2 nathanw bad: 558 1.7.2.2 nathanw if (state > 2) 559 1.7.2.2 nathanw mly_release_ccbs(mly); 560 1.7.2.2 nathanw if (state > 1) 561 1.7.2.2 nathanw mly_dmamem_free(mly, sizeof(struct mly_mmbox), 562 1.7.2.2 nathanw mly->mly_mmbox_dmamap, (caddr_t)mly->mly_mmbox, 563 1.7.2.2 nathanw &mly->mly_mmbox_seg); 564 1.7.2.2 nathanw if (state > 0) 565 1.7.2.2 nathanw mly_dmamem_free(mly, MLY_SGL_SIZE * MLY_MAX_CCBS, 566 1.7.2.2 nathanw mly->mly_sg_dmamap, (caddr_t)mly->mly_sg, 567 1.7.2.2 nathanw &mly->mly_sg_seg); 568 1.7.2.2 nathanw } 569 1.7.2.2 nathanw 570 1.7.2.2 nathanw /* 571 1.7.2.2 nathanw * Scan all possible devices on the specified channel. 572 1.7.2.2 nathanw */ 573 1.7.2.2 nathanw static void 574 1.7.2.2 nathanw mly_scan_channel(struct mly_softc *mly, int bus) 575 1.7.2.2 nathanw { 576 1.7.2.2 nathanw int s, target; 577 1.7.2.2 nathanw 578 1.7.2.2 nathanw for (target = 0; target < MLY_MAX_TARGETS; target++) { 579 1.7.2.2 nathanw s = splbio(); 580 1.7.2.2 nathanw if (!mly_scan_btl(mly, bus, target)) { 581 1.7.2.2 nathanw tsleep(&mly->mly_btl[bus][target], PRIBIO, "mlyscan", 582 1.7.2.2 nathanw 0); 583 1.7.2.2 nathanw } 584 1.7.2.2 nathanw splx(s); 585 1.7.2.2 nathanw } 586 1.7.2.2 nathanw } 587 1.7.2.2 nathanw 588 1.7.2.2 nathanw /* 589 1.7.2.2 nathanw * Shut down all configured `mly' devices. 590 1.7.2.2 nathanw */ 591 1.7.2.2 nathanw static void 592 1.7.2.2 nathanw mly_shutdown(void *cookie) 593 1.7.2.2 nathanw { 594 1.7.2.2 nathanw struct mly_softc *mly; 595 1.7.2.2 nathanw int i; 596 1.7.2.2 nathanw 597 1.7.2.2 nathanw for (i = 0; i < mly_cd.cd_ndevs; i++) { 598 1.7.2.2 nathanw if ((mly = device_lookup(&mly_cd, i)) == NULL) 599 1.7.2.2 nathanw continue; 600 1.7.2.2 nathanw 601 1.7.2.2 nathanw if (mly_flush(mly)) 602 1.7.2.2 nathanw printf("%s: unable to flush cache\n", 603 1.7.2.2 nathanw mly->mly_dv.dv_xname); 604 1.7.2.2 nathanw } 605 1.7.2.2 nathanw } 606 1.7.2.2 nathanw 607 1.7.2.2 nathanw /* 608 1.7.2.2 nathanw * Fill in the mly_controllerinfo and mly_controllerparam fields in the 609 1.7.2.2 nathanw * softc. 610 1.7.2.2 nathanw */ 611 1.7.2.2 nathanw static int 612 1.7.2.2 nathanw mly_get_controllerinfo(struct mly_softc *mly) 613 1.7.2.2 nathanw { 614 1.7.2.2 nathanw struct mly_cmd_ioctl mci; 615 1.7.2.2 nathanw int rv; 616 1.7.2.2 nathanw 617 1.7.2.2 nathanw /* 618 1.7.2.2 nathanw * Build the getcontrollerinfo ioctl and send it. 619 1.7.2.2 nathanw */ 620 1.7.2.2 nathanw memset(&mci, 0, sizeof(mci)); 621 1.7.2.2 nathanw mci.sub_ioctl = MDACIOCTL_GETCONTROLLERINFO; 622 1.7.2.2 nathanw rv = mly_ioctl(mly, &mci, (void **)&mly->mly_controllerinfo, 623 1.7.2.2 nathanw sizeof(*mly->mly_controllerinfo), NULL, NULL); 624 1.7.2.2 nathanw if (rv != 0) 625 1.7.2.2 nathanw return (rv); 626 1.7.2.2 nathanw 627 1.7.2.2 nathanw /* 628 1.7.2.2 nathanw * Build the getcontrollerparameter ioctl and send it. 629 1.7.2.2 nathanw */ 630 1.7.2.2 nathanw memset(&mci, 0, sizeof(mci)); 631 1.7.2.2 nathanw mci.sub_ioctl = MDACIOCTL_GETCONTROLLERPARAMETER; 632 1.7.2.2 nathanw rv = mly_ioctl(mly, &mci, (void **)&mly->mly_controllerparam, 633 1.7.2.2 nathanw sizeof(*mly->mly_controllerparam), NULL, NULL); 634 1.7.2.2 nathanw 635 1.7.2.2 nathanw return (rv); 636 1.7.2.2 nathanw } 637 1.7.2.2 nathanw 638 1.7.2.2 nathanw /* 639 1.7.2.2 nathanw * Rescan a device, possibly as a consequence of getting an event which 640 1.7.2.2 nathanw * suggests that it may have changed. Must be called with interrupts 641 1.7.2.2 nathanw * blocked. 642 1.7.2.2 nathanw */ 643 1.7.2.2 nathanw static int 644 1.7.2.2 nathanw mly_scan_btl(struct mly_softc *mly, int bus, int target) 645 1.7.2.2 nathanw { 646 1.7.2.2 nathanw struct mly_ccb *mc; 647 1.7.2.2 nathanw struct mly_cmd_ioctl *mci; 648 1.7.2.2 nathanw int rv; 649 1.7.2.2 nathanw 650 1.7.2.2 nathanw if (target == mly->mly_controllerparam->initiator_id) { 651 1.7.2.2 nathanw mly->mly_btl[bus][target].mb_flags = MLY_BTL_PROTECTED; 652 1.7.2.2 nathanw return (EIO); 653 1.7.2.2 nathanw } 654 1.7.2.2 nathanw 655 1.7.2.2 nathanw /* Don't re-scan if a scan is already in progress. */ 656 1.7.2.2 nathanw if ((mly->mly_btl[bus][target].mb_flags & MLY_BTL_SCANNING) != 0) 657 1.7.2.2 nathanw return (EBUSY); 658 1.7.2.2 nathanw 659 1.7.2.2 nathanw /* Get a command. */ 660 1.7.2.2 nathanw if ((rv = mly_ccb_alloc(mly, &mc)) != 0) 661 1.7.2.2 nathanw return (rv); 662 1.7.2.2 nathanw 663 1.7.2.2 nathanw /* Set up the data buffer. */ 664 1.7.2.2 nathanw mc->mc_data = malloc(sizeof(union mly_devinfo), 665 1.7.2.4 nathanw M_DEVBUF, M_NOWAIT|M_ZERO); 666 1.7.2.2 nathanw 667 1.7.2.2 nathanw mc->mc_flags |= MLY_CCB_DATAIN; 668 1.7.2.2 nathanw mc->mc_complete = mly_complete_rescan; 669 1.7.2.2 nathanw 670 1.7.2.2 nathanw /* 671 1.7.2.2 nathanw * Build the ioctl. 672 1.7.2.2 nathanw */ 673 1.7.2.2 nathanw mci = (struct mly_cmd_ioctl *)&mc->mc_packet->ioctl; 674 1.7.2.2 nathanw mci->opcode = MDACMD_IOCTL; 675 1.7.2.2 nathanw mci->timeout = 30 | MLY_TIMEOUT_SECONDS; 676 1.7.2.2 nathanw memset(&mci->param, 0, sizeof(mci->param)); 677 1.7.2.2 nathanw 678 1.7.2.2 nathanw if (MLY_BUS_IS_VIRTUAL(mly, bus)) { 679 1.7.2.2 nathanw mc->mc_length = sizeof(struct mly_ioctl_getlogdevinfovalid); 680 1.7.2.2 nathanw mci->data_size = htole32(mc->mc_length); 681 1.7.2.2 nathanw mci->sub_ioctl = MDACIOCTL_GETLOGDEVINFOVALID; 682 1.7.2.2 nathanw _lto3l(MLY_LOGADDR(0, MLY_LOGDEV_ID(mly, bus, target)), 683 1.7.2.2 nathanw mci->addr); 684 1.7.2.2 nathanw } else { 685 1.7.2.2 nathanw mc->mc_length = sizeof(struct mly_ioctl_getphysdevinfovalid); 686 1.7.2.2 nathanw mci->data_size = htole32(mc->mc_length); 687 1.7.2.2 nathanw mci->sub_ioctl = MDACIOCTL_GETPHYSDEVINFOVALID; 688 1.7.2.2 nathanw _lto3l(MLY_PHYADDR(0, bus, target, 0), mci->addr); 689 1.7.2.2 nathanw } 690 1.7.2.2 nathanw 691 1.7.2.2 nathanw /* 692 1.7.2.2 nathanw * Dispatch the command. 693 1.7.2.2 nathanw */ 694 1.7.2.2 nathanw if ((rv = mly_ccb_map(mly, mc)) != 0) { 695 1.7.2.2 nathanw free(mc->mc_data, M_DEVBUF); 696 1.7.2.2 nathanw mly_ccb_free(mly, mc); 697 1.7.2.2 nathanw return(rv); 698 1.7.2.2 nathanw } 699 1.7.2.2 nathanw 700 1.7.2.2 nathanw mly->mly_btl[bus][target].mb_flags |= MLY_BTL_SCANNING; 701 1.7.2.2 nathanw mly_ccb_enqueue(mly, mc); 702 1.7.2.2 nathanw return (0); 703 1.7.2.2 nathanw } 704 1.7.2.2 nathanw 705 1.7.2.2 nathanw /* 706 1.7.2.2 nathanw * Handle the completion of a rescan operation. 707 1.7.2.2 nathanw */ 708 1.7.2.2 nathanw static void 709 1.7.2.2 nathanw mly_complete_rescan(struct mly_softc *mly, struct mly_ccb *mc) 710 1.7.2.2 nathanw { 711 1.7.2.2 nathanw struct mly_ioctl_getlogdevinfovalid *ldi; 712 1.7.2.2 nathanw struct mly_ioctl_getphysdevinfovalid *pdi; 713 1.7.2.2 nathanw struct mly_cmd_ioctl *mci; 714 1.7.2.2 nathanw struct mly_btl btl, *btlp; 715 1.7.2.2 nathanw struct scsipi_xfer_mode xm; 716 1.7.2.2 nathanw int bus, target, rescan; 717 1.7.2.2 nathanw u_int tmp; 718 1.7.2.2 nathanw 719 1.7.2.2 nathanw mly_ccb_unmap(mly, mc); 720 1.7.2.2 nathanw 721 1.7.2.2 nathanw /* 722 1.7.2.2 nathanw * Recover the bus and target from the command. We need these even 723 1.7.2.2 nathanw * in the case where we don't have a useful response. 724 1.7.2.2 nathanw */ 725 1.7.2.2 nathanw mci = (struct mly_cmd_ioctl *)&mc->mc_packet->ioctl; 726 1.7.2.2 nathanw tmp = _3ltol(mci->addr); 727 1.7.2.2 nathanw rescan = 0; 728 1.7.2.2 nathanw 729 1.7.2.2 nathanw if (mci->sub_ioctl == MDACIOCTL_GETLOGDEVINFOVALID) { 730 1.7.2.2 nathanw bus = MLY_LOGDEV_BUS(mly, MLY_LOGADDR_DEV(tmp)); 731 1.7.2.2 nathanw target = MLY_LOGDEV_TARGET(mly, MLY_LOGADDR_DEV(tmp)); 732 1.7.2.2 nathanw } else { 733 1.7.2.2 nathanw bus = MLY_PHYADDR_CHANNEL(tmp); 734 1.7.2.2 nathanw target = MLY_PHYADDR_TARGET(tmp); 735 1.7.2.2 nathanw } 736 1.7.2.2 nathanw 737 1.7.2.2 nathanw btlp = &mly->mly_btl[bus][target]; 738 1.7.2.2 nathanw 739 1.7.2.2 nathanw /* The default result is 'no device'. */ 740 1.7.2.2 nathanw memset(&btl, 0, sizeof(btl)); 741 1.7.2.2 nathanw btl.mb_flags = MLY_BTL_PROTECTED; 742 1.7.2.2 nathanw 743 1.7.2.2 nathanw /* If the rescan completed OK, we have possibly-new BTL data. */ 744 1.7.2.2 nathanw if (mc->mc_status != 0) 745 1.7.2.2 nathanw goto out; 746 1.7.2.2 nathanw 747 1.7.2.2 nathanw if (mc->mc_length == sizeof(*ldi)) { 748 1.7.2.2 nathanw ldi = (struct mly_ioctl_getlogdevinfovalid *)mc->mc_data; 749 1.7.2.2 nathanw tmp = le32toh(ldi->logical_device_number); 750 1.7.2.2 nathanw 751 1.7.2.2 nathanw if (MLY_LOGDEV_BUS(mly, tmp) != bus || 752 1.7.2.2 nathanw MLY_LOGDEV_TARGET(mly, tmp) != target) { 753 1.7.2.2 nathanw #ifdef MLYDEBUG 754 1.7.2.2 nathanw printf("%s: WARNING: BTL rescan (logical) for %d:%d " 755 1.7.2.2 nathanw "returned data for %d:%d instead\n", 756 1.7.2.2 nathanw mly->mly_dv.dv_xname, bus, target, 757 1.7.2.2 nathanw MLY_LOGDEV_BUS(mly, tmp), 758 1.7.2.2 nathanw MLY_LOGDEV_TARGET(mly, tmp)); 759 1.7.2.2 nathanw #endif 760 1.7.2.2 nathanw goto out; 761 1.7.2.2 nathanw } 762 1.7.2.2 nathanw 763 1.7.2.2 nathanw btl.mb_flags = MLY_BTL_LOGICAL | MLY_BTL_TQING; 764 1.7.2.2 nathanw btl.mb_type = ldi->raid_level; 765 1.7.2.2 nathanw btl.mb_state = ldi->state; 766 1.7.2.2 nathanw } else if (mc->mc_length == sizeof(*pdi)) { 767 1.7.2.2 nathanw pdi = (struct mly_ioctl_getphysdevinfovalid *)mc->mc_data; 768 1.7.2.2 nathanw 769 1.7.2.2 nathanw if (pdi->channel != bus || pdi->target != target) { 770 1.7.2.2 nathanw #ifdef MLYDEBUG 771 1.7.2.2 nathanw printf("%s: WARNING: BTL rescan (physical) for %d:%d " 772 1.7.2.2 nathanw " returned data for %d:%d instead\n", 773 1.7.2.2 nathanw mly->mly_dv.dv_xname, 774 1.7.2.2 nathanw bus, target, pdi->channel, pdi->target); 775 1.7.2.2 nathanw #endif 776 1.7.2.2 nathanw goto out; 777 1.7.2.2 nathanw } 778 1.7.2.2 nathanw 779 1.7.2.2 nathanw btl.mb_flags = MLY_BTL_PHYSICAL; 780 1.7.2.2 nathanw btl.mb_type = MLY_DEVICE_TYPE_PHYSICAL; 781 1.7.2.2 nathanw btl.mb_state = pdi->state; 782 1.7.2.2 nathanw btl.mb_speed = pdi->speed; 783 1.7.2.2 nathanw btl.mb_width = pdi->width; 784 1.7.2.2 nathanw 785 1.7.2.2 nathanw if (pdi->state != MLY_DEVICE_STATE_UNCONFIGURED) 786 1.7.2.2 nathanw btl.mb_flags |= MLY_BTL_PROTECTED; 787 1.7.2.2 nathanw if (pdi->command_tags != 0) 788 1.7.2.2 nathanw btl.mb_flags |= MLY_BTL_TQING; 789 1.7.2.2 nathanw } else { 790 1.7.2.2 nathanw printf("%s: BTL rescan result invalid\n", mly->mly_dv.dv_xname); 791 1.7.2.2 nathanw goto out; 792 1.7.2.2 nathanw } 793 1.7.2.2 nathanw 794 1.7.2.2 nathanw /* Decide whether we need to rescan the device. */ 795 1.7.2.2 nathanw if (btl.mb_flags != btlp->mb_flags || 796 1.7.2.2 nathanw btl.mb_speed != btlp->mb_speed || 797 1.7.2.2 nathanw btl.mb_width != btlp->mb_width) 798 1.7.2.2 nathanw rescan = 1; 799 1.7.2.2 nathanw 800 1.7.2.2 nathanw out: 801 1.7.2.2 nathanw *btlp = btl; 802 1.7.2.2 nathanw 803 1.7.2.2 nathanw if (rescan && (btl.mb_flags & MLY_BTL_PROTECTED) == 0) { 804 1.7.2.2 nathanw xm.xm_target = target; 805 1.7.2.2 nathanw mly_get_xfer_mode(mly, bus, &xm); 806 1.7.2.2 nathanw /* XXX SCSI mid-layer rescan goes here. */ 807 1.7.2.2 nathanw } 808 1.7.2.2 nathanw 809 1.7.2.2 nathanw /* Wake anybody waiting on the device to be rescanned. */ 810 1.7.2.2 nathanw wakeup(btlp); 811 1.7.2.2 nathanw 812 1.7.2.2 nathanw free(mc->mc_data, M_DEVBUF); 813 1.7.2.2 nathanw mly_ccb_free(mly, mc); 814 1.7.2.2 nathanw } 815 1.7.2.2 nathanw 816 1.7.2.2 nathanw /* 817 1.7.2.2 nathanw * Get the current health status and set the 'next event' counter to suit. 818 1.7.2.2 nathanw */ 819 1.7.2.2 nathanw static int 820 1.7.2.2 nathanw mly_get_eventstatus(struct mly_softc *mly) 821 1.7.2.2 nathanw { 822 1.7.2.2 nathanw struct mly_cmd_ioctl mci; 823 1.7.2.2 nathanw struct mly_health_status *mh; 824 1.7.2.2 nathanw int rv; 825 1.7.2.2 nathanw 826 1.7.2.2 nathanw /* Build the gethealthstatus ioctl and send it. */ 827 1.7.2.2 nathanw memset(&mci, 0, sizeof(mci)); 828 1.7.2.2 nathanw mh = NULL; 829 1.7.2.2 nathanw mci.sub_ioctl = MDACIOCTL_GETHEALTHSTATUS; 830 1.7.2.2 nathanw 831 1.7.2.2 nathanw rv = mly_ioctl(mly, &mci, (void **)&mh, sizeof(*mh), NULL, NULL); 832 1.7.2.2 nathanw if (rv) 833 1.7.2.2 nathanw return (rv); 834 1.7.2.2 nathanw 835 1.7.2.2 nathanw /* Get the event counter. */ 836 1.7.2.2 nathanw mly->mly_event_change = le32toh(mh->change_counter); 837 1.7.2.2 nathanw mly->mly_event_waiting = le32toh(mh->next_event); 838 1.7.2.2 nathanw mly->mly_event_counter = le32toh(mh->next_event); 839 1.7.2.2 nathanw 840 1.7.2.2 nathanw /* Save the health status into the memory mailbox */ 841 1.7.2.2 nathanw memcpy(&mly->mly_mmbox->mmm_health.status, mh, sizeof(*mh)); 842 1.7.2.2 nathanw 843 1.7.2.2 nathanw bus_dmamap_sync(mly->mly_dmat, mly->mly_mmbox_dmamap, 844 1.7.2.2 nathanw offsetof(struct mly_mmbox, mmm_health), 845 1.7.2.2 nathanw sizeof(mly->mly_mmbox->mmm_health), 846 1.7.2.2 nathanw BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 847 1.7.2.2 nathanw 848 1.7.2.2 nathanw free(mh, M_DEVBUF); 849 1.7.2.2 nathanw return (0); 850 1.7.2.2 nathanw } 851 1.7.2.2 nathanw 852 1.7.2.2 nathanw /* 853 1.7.2.2 nathanw * Enable memory mailbox mode. 854 1.7.2.2 nathanw */ 855 1.7.2.2 nathanw static int 856 1.7.2.2 nathanw mly_enable_mmbox(struct mly_softc *mly) 857 1.7.2.2 nathanw { 858 1.7.2.2 nathanw struct mly_cmd_ioctl mci; 859 1.7.2.2 nathanw u_int8_t *sp; 860 1.7.2.2 nathanw u_int64_t tmp; 861 1.7.2.2 nathanw int rv; 862 1.7.2.2 nathanw 863 1.7.2.2 nathanw /* Build the ioctl and send it. */ 864 1.7.2.2 nathanw memset(&mci, 0, sizeof(mci)); 865 1.7.2.2 nathanw mci.sub_ioctl = MDACIOCTL_SETMEMORYMAILBOX; 866 1.7.2.2 nathanw 867 1.7.2.2 nathanw /* Set buffer addresses. */ 868 1.7.2.2 nathanw tmp = mly->mly_mmbox_busaddr + offsetof(struct mly_mmbox, mmm_command); 869 1.7.2.2 nathanw mci.param.setmemorymailbox.command_mailbox_physaddr = htole64(tmp); 870 1.7.2.2 nathanw 871 1.7.2.2 nathanw tmp = mly->mly_mmbox_busaddr + offsetof(struct mly_mmbox, mmm_status); 872 1.7.2.2 nathanw mci.param.setmemorymailbox.status_mailbox_physaddr = htole64(tmp); 873 1.7.2.2 nathanw 874 1.7.2.2 nathanw tmp = mly->mly_mmbox_busaddr + offsetof(struct mly_mmbox, mmm_health); 875 1.7.2.2 nathanw mci.param.setmemorymailbox.health_buffer_physaddr = htole64(tmp); 876 1.7.2.2 nathanw 877 1.7.2.2 nathanw /* Set buffer sizes - abuse of data_size field is revolting. */ 878 1.7.2.2 nathanw sp = (u_int8_t *)&mci.data_size; 879 1.7.2.2 nathanw sp[0] = (sizeof(union mly_cmd_packet) * MLY_MMBOX_COMMANDS) >> 10; 880 1.7.2.2 nathanw sp[1] = (sizeof(union mly_status_packet) * MLY_MMBOX_STATUS) >> 10; 881 1.7.2.2 nathanw mci.param.setmemorymailbox.health_buffer_size = 882 1.7.2.2 nathanw sizeof(union mly_health_region) >> 10; 883 1.7.2.2 nathanw 884 1.7.2.2 nathanw rv = mly_ioctl(mly, &mci, NULL, 0, NULL, NULL); 885 1.7.2.2 nathanw if (rv) 886 1.7.2.2 nathanw return (rv); 887 1.7.2.2 nathanw 888 1.7.2.2 nathanw mly->mly_state |= MLY_STATE_MMBOX_ACTIVE; 889 1.7.2.2 nathanw return (0); 890 1.7.2.2 nathanw } 891 1.7.2.2 nathanw 892 1.7.2.2 nathanw /* 893 1.7.2.2 nathanw * Flush all pending I/O from the controller. 894 1.7.2.2 nathanw */ 895 1.7.2.2 nathanw static int 896 1.7.2.2 nathanw mly_flush(struct mly_softc *mly) 897 1.7.2.2 nathanw { 898 1.7.2.2 nathanw struct mly_cmd_ioctl mci; 899 1.7.2.2 nathanw 900 1.7.2.2 nathanw /* Build the ioctl */ 901 1.7.2.2 nathanw memset(&mci, 0, sizeof(mci)); 902 1.7.2.2 nathanw mci.sub_ioctl = MDACIOCTL_FLUSHDEVICEDATA; 903 1.7.2.2 nathanw mci.param.deviceoperation.operation_device = 904 1.7.2.2 nathanw MLY_OPDEVICE_PHYSICAL_CONTROLLER; 905 1.7.2.2 nathanw 906 1.7.2.2 nathanw /* Pass it off to the controller */ 907 1.7.2.2 nathanw return (mly_ioctl(mly, &mci, NULL, 0, NULL, NULL)); 908 1.7.2.2 nathanw } 909 1.7.2.2 nathanw 910 1.7.2.2 nathanw /* 911 1.7.2.2 nathanw * Perform an ioctl command. 912 1.7.2.2 nathanw * 913 1.7.2.2 nathanw * If (data) is not NULL, the command requires data transfer to the 914 1.7.2.2 nathanw * controller. If (*data) is NULL the command requires data transfer from 915 1.7.2.2 nathanw * the controller, and we will allocate a buffer for it. 916 1.7.2.2 nathanw */ 917 1.7.2.2 nathanw static int 918 1.7.2.2 nathanw mly_ioctl(struct mly_softc *mly, struct mly_cmd_ioctl *ioctl, void **data, 919 1.7.2.2 nathanw size_t datasize, void *sense_buffer, 920 1.7.2.2 nathanw size_t *sense_length) 921 1.7.2.2 nathanw { 922 1.7.2.2 nathanw struct mly_ccb *mc; 923 1.7.2.2 nathanw struct mly_cmd_ioctl *mci; 924 1.7.2.2 nathanw u_int8_t status; 925 1.7.2.2 nathanw int rv; 926 1.7.2.2 nathanw 927 1.7.2.2 nathanw mc = NULL; 928 1.7.2.2 nathanw if ((rv = mly_ccb_alloc(mly, &mc)) != 0) 929 1.7.2.2 nathanw goto bad; 930 1.7.2.2 nathanw 931 1.7.2.2 nathanw /* 932 1.7.2.2 nathanw * Copy the ioctl structure, but save some important fields and then 933 1.7.2.2 nathanw * fixup. 934 1.7.2.2 nathanw */ 935 1.7.2.2 nathanw mci = &mc->mc_packet->ioctl; 936 1.7.2.2 nathanw ioctl->sense_buffer_address = htole64(mci->sense_buffer_address); 937 1.7.2.2 nathanw ioctl->maximum_sense_size = mci->maximum_sense_size; 938 1.7.2.2 nathanw *mci = *ioctl; 939 1.7.2.2 nathanw mci->opcode = MDACMD_IOCTL; 940 1.7.2.2 nathanw mci->timeout = 30 | MLY_TIMEOUT_SECONDS; 941 1.7.2.2 nathanw 942 1.7.2.2 nathanw /* Handle the data buffer. */ 943 1.7.2.2 nathanw if (data != NULL) { 944 1.7.2.2 nathanw if (*data == NULL) { 945 1.7.2.2 nathanw /* Allocate data buffer */ 946 1.7.2.2 nathanw mc->mc_data = malloc(datasize, M_DEVBUF, M_NOWAIT); 947 1.7.2.2 nathanw mc->mc_flags |= MLY_CCB_DATAIN; 948 1.7.2.2 nathanw } else { 949 1.7.2.2 nathanw mc->mc_data = *data; 950 1.7.2.2 nathanw mc->mc_flags |= MLY_CCB_DATAOUT; 951 1.7.2.2 nathanw } 952 1.7.2.2 nathanw mc->mc_length = datasize; 953 1.7.2.2 nathanw mc->mc_packet->generic.data_size = htole32(datasize); 954 1.7.2.2 nathanw } 955 1.7.2.2 nathanw 956 1.7.2.2 nathanw /* Run the command. */ 957 1.7.2.2 nathanw if (datasize > 0) 958 1.7.2.2 nathanw if ((rv = mly_ccb_map(mly, mc)) != 0) 959 1.7.2.2 nathanw goto bad; 960 1.7.2.2 nathanw rv = mly_ccb_poll(mly, mc, 30000); 961 1.7.2.2 nathanw if (datasize > 0) 962 1.7.2.2 nathanw mly_ccb_unmap(mly, mc); 963 1.7.2.2 nathanw if (rv != 0) 964 1.7.2.2 nathanw goto bad; 965 1.7.2.2 nathanw 966 1.7.2.2 nathanw /* Clean up and return any data. */ 967 1.7.2.2 nathanw status = mc->mc_status; 968 1.7.2.2 nathanw 969 1.7.2.2 nathanw if (status != 0) 970 1.7.2.2 nathanw printf("mly_ioctl: command status %d\n", status); 971 1.7.2.2 nathanw 972 1.7.2.2 nathanw if (mc->mc_sense > 0 && sense_buffer != NULL) { 973 1.7.2.2 nathanw memcpy(sense_buffer, mc->mc_packet, mc->mc_sense); 974 1.7.2.2 nathanw *sense_length = mc->mc_sense; 975 1.7.2.2 nathanw goto bad; 976 1.7.2.2 nathanw } 977 1.7.2.2 nathanw 978 1.7.2.2 nathanw /* Should we return a data pointer? */ 979 1.7.2.2 nathanw if (data != NULL && *data == NULL) 980 1.7.2.2 nathanw *data = mc->mc_data; 981 1.7.2.2 nathanw 982 1.7.2.2 nathanw /* Command completed OK. */ 983 1.7.2.2 nathanw rv = (status != 0 ? EIO : 0); 984 1.7.2.2 nathanw 985 1.7.2.2 nathanw bad: 986 1.7.2.2 nathanw if (mc != NULL) { 987 1.7.2.2 nathanw /* Do we need to free a data buffer we allocated? */ 988 1.7.2.2 nathanw if (rv != 0 && mc->mc_data != NULL && *data == NULL) 989 1.7.2.2 nathanw free(mc->mc_data, M_DEVBUF); 990 1.7.2.2 nathanw mly_ccb_free(mly, mc); 991 1.7.2.2 nathanw } 992 1.7.2.2 nathanw 993 1.7.2.2 nathanw return (rv); 994 1.7.2.2 nathanw } 995 1.7.2.2 nathanw 996 1.7.2.2 nathanw /* 997 1.7.2.2 nathanw * Check for event(s) outstanding in the controller. 998 1.7.2.2 nathanw */ 999 1.7.2.2 nathanw static void 1000 1.7.2.2 nathanw mly_check_event(struct mly_softc *mly) 1001 1.7.2.2 nathanw { 1002 1.7.2.2 nathanw 1003 1.7.2.2 nathanw bus_dmamap_sync(mly->mly_dmat, mly->mly_mmbox_dmamap, 1004 1.7.2.2 nathanw offsetof(struct mly_mmbox, mmm_health), 1005 1.7.2.2 nathanw sizeof(mly->mly_mmbox->mmm_health), 1006 1.7.2.2 nathanw BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1007 1.7.2.2 nathanw 1008 1.7.2.2 nathanw /* 1009 1.7.2.2 nathanw * The controller may have updated the health status information, so 1010 1.7.2.2 nathanw * check for it here. Note that the counters are all in host 1011 1.7.2.2 nathanw * memory, so this check is very cheap. Also note that we depend on 1012 1.7.2.2 nathanw * checking on completion 1013 1.7.2.2 nathanw */ 1014 1.7.2.2 nathanw if (le32toh(mly->mly_mmbox->mmm_health.status.change_counter) != 1015 1.7.2.2 nathanw mly->mly_event_change) { 1016 1.7.2.2 nathanw mly->mly_event_change = 1017 1.7.2.2 nathanw le32toh(mly->mly_mmbox->mmm_health.status.change_counter); 1018 1.7.2.2 nathanw mly->mly_event_waiting = 1019 1.7.2.2 nathanw le32toh(mly->mly_mmbox->mmm_health.status.next_event); 1020 1.7.2.2 nathanw 1021 1.7.2.2 nathanw /* Wake up anyone that might be interested in this. */ 1022 1.7.2.2 nathanw wakeup(&mly->mly_event_change); 1023 1.7.2.2 nathanw } 1024 1.7.2.2 nathanw 1025 1.7.2.2 nathanw bus_dmamap_sync(mly->mly_dmat, mly->mly_mmbox_dmamap, 1026 1.7.2.2 nathanw offsetof(struct mly_mmbox, mmm_health), 1027 1.7.2.2 nathanw sizeof(mly->mly_mmbox->mmm_health), 1028 1.7.2.2 nathanw BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1029 1.7.2.2 nathanw 1030 1.7.2.2 nathanw if (mly->mly_event_counter != mly->mly_event_waiting) 1031 1.7.2.2 nathanw mly_fetch_event(mly); 1032 1.7.2.2 nathanw } 1033 1.7.2.2 nathanw 1034 1.7.2.2 nathanw /* 1035 1.7.2.2 nathanw * Fetch one event from the controller. If we fail due to resource 1036 1.7.2.2 nathanw * starvation, we'll be retried the next time a command completes. 1037 1.7.2.2 nathanw */ 1038 1.7.2.2 nathanw static void 1039 1.7.2.2 nathanw mly_fetch_event(struct mly_softc *mly) 1040 1.7.2.2 nathanw { 1041 1.7.2.2 nathanw struct mly_ccb *mc; 1042 1.7.2.2 nathanw struct mly_cmd_ioctl *mci; 1043 1.7.2.2 nathanw int s; 1044 1.7.2.2 nathanw u_int32_t event; 1045 1.7.2.2 nathanw 1046 1.7.2.2 nathanw /* Get a command. */ 1047 1.7.2.2 nathanw if (mly_ccb_alloc(mly, &mc)) 1048 1.7.2.2 nathanw return; 1049 1.7.2.2 nathanw 1050 1.7.2.2 nathanw /* Set up the data buffer. */ 1051 1.7.2.4 nathanw mc->mc_data = malloc(sizeof(struct mly_event), M_DEVBUF, 1052 1.7.2.4 nathanw M_NOWAIT|M_ZERO); 1053 1.7.2.2 nathanw 1054 1.7.2.2 nathanw mc->mc_length = sizeof(struct mly_event); 1055 1.7.2.2 nathanw mc->mc_flags |= MLY_CCB_DATAIN; 1056 1.7.2.2 nathanw mc->mc_complete = mly_complete_event; 1057 1.7.2.2 nathanw 1058 1.7.2.2 nathanw /* 1059 1.7.2.2 nathanw * Get an event number to fetch. It's possible that we've raced 1060 1.7.2.2 nathanw * with another context for the last event, in which case there will 1061 1.7.2.2 nathanw * be no more events. 1062 1.7.2.2 nathanw */ 1063 1.7.2.2 nathanw s = splbio(); 1064 1.7.2.2 nathanw if (mly->mly_event_counter == mly->mly_event_waiting) { 1065 1.7.2.2 nathanw splx(s); 1066 1.7.2.2 nathanw free(mc->mc_data, M_DEVBUF); 1067 1.7.2.2 nathanw mly_ccb_free(mly, mc); 1068 1.7.2.2 nathanw return; 1069 1.7.2.2 nathanw } 1070 1.7.2.2 nathanw event = mly->mly_event_counter++; 1071 1.7.2.2 nathanw splx(s); 1072 1.7.2.2 nathanw 1073 1.7.2.2 nathanw /* 1074 1.7.2.2 nathanw * Build the ioctl. 1075 1.7.2.2 nathanw * 1076 1.7.2.2 nathanw * At this point we are committed to sending this request, as it 1077 1.7.2.2 nathanw * will be the only one constructed for this particular event 1078 1.7.2.2 nathanw * number. 1079 1.7.2.2 nathanw */ 1080 1.7.2.2 nathanw mci = (struct mly_cmd_ioctl *)&mc->mc_packet->ioctl; 1081 1.7.2.2 nathanw mci->opcode = MDACMD_IOCTL; 1082 1.7.2.2 nathanw mci->data_size = htole32(sizeof(struct mly_event)); 1083 1.7.2.2 nathanw _lto3l(MLY_PHYADDR(0, 0, (event >> 16) & 0xff, (event >> 24) & 0xff), 1084 1.7.2.2 nathanw mci->addr); 1085 1.7.2.2 nathanw mci->timeout = 30 | MLY_TIMEOUT_SECONDS; 1086 1.7.2.2 nathanw mci->sub_ioctl = MDACIOCTL_GETEVENT; 1087 1.7.2.2 nathanw mci->param.getevent.sequence_number_low = htole16(event & 0xffff); 1088 1.7.2.2 nathanw 1089 1.7.2.2 nathanw /* 1090 1.7.2.2 nathanw * Submit the command. 1091 1.7.2.2 nathanw */ 1092 1.7.2.2 nathanw if (mly_ccb_map(mly, mc) != 0) 1093 1.7.2.2 nathanw goto bad; 1094 1.7.2.2 nathanw mly_ccb_enqueue(mly, mc); 1095 1.7.2.2 nathanw return; 1096 1.7.2.2 nathanw 1097 1.7.2.2 nathanw bad: 1098 1.7.2.2 nathanw printf("%s: couldn't fetch event %u\n", mly->mly_dv.dv_xname, event); 1099 1.7.2.2 nathanw free(mc->mc_data, M_DEVBUF); 1100 1.7.2.2 nathanw mly_ccb_free(mly, mc); 1101 1.7.2.2 nathanw } 1102 1.7.2.2 nathanw 1103 1.7.2.2 nathanw /* 1104 1.7.2.2 nathanw * Handle the completion of an event poll. 1105 1.7.2.2 nathanw */ 1106 1.7.2.2 nathanw static void 1107 1.7.2.2 nathanw mly_complete_event(struct mly_softc *mly, struct mly_ccb *mc) 1108 1.7.2.2 nathanw { 1109 1.7.2.2 nathanw struct mly_event *me; 1110 1.7.2.2 nathanw 1111 1.7.2.2 nathanw me = (struct mly_event *)mc->mc_data; 1112 1.7.2.2 nathanw mly_ccb_unmap(mly, mc); 1113 1.7.2.2 nathanw mly_ccb_free(mly, mc); 1114 1.7.2.2 nathanw 1115 1.7.2.2 nathanw /* If the event was successfully fetched, process it. */ 1116 1.7.2.2 nathanw if (mc->mc_status == SCSI_OK) 1117 1.7.2.2 nathanw mly_process_event(mly, me); 1118 1.7.2.2 nathanw else 1119 1.7.2.2 nathanw printf("%s: unable to fetch event; status = 0x%x\n", 1120 1.7.2.2 nathanw mly->mly_dv.dv_xname, mc->mc_status); 1121 1.7.2.2 nathanw 1122 1.7.2.2 nathanw free(me, M_DEVBUF); 1123 1.7.2.2 nathanw 1124 1.7.2.2 nathanw /* Check for another event. */ 1125 1.7.2.2 nathanw mly_check_event(mly); 1126 1.7.2.2 nathanw } 1127 1.7.2.2 nathanw 1128 1.7.2.2 nathanw /* 1129 1.7.2.2 nathanw * Process a controller event. Called with interupts blocked (i.e., at 1130 1.7.2.2 nathanw * interrupt time). 1131 1.7.2.2 nathanw */ 1132 1.7.2.2 nathanw static void 1133 1.7.2.2 nathanw mly_process_event(struct mly_softc *mly, struct mly_event *me) 1134 1.7.2.2 nathanw { 1135 1.7.2.2 nathanw struct scsipi_sense_data *ssd; 1136 1.7.2.2 nathanw int bus, target, event, class, action; 1137 1.7.2.2 nathanw const char *fp, *tp; 1138 1.7.2.2 nathanw 1139 1.7.2.2 nathanw ssd = (struct scsipi_sense_data *)&me->sense[0]; 1140 1.7.2.2 nathanw 1141 1.7.2.2 nathanw /* 1142 1.7.2.2 nathanw * Errors can be reported using vendor-unique sense data. In this 1143 1.7.2.2 nathanw * case, the event code will be 0x1c (Request sense data present), 1144 1.7.2.2 nathanw * the sense key will be 0x09 (vendor specific), the MSB of the ASC 1145 1.7.2.2 nathanw * will be set, and the actual event code will be a 16-bit value 1146 1.7.2.2 nathanw * comprised of the ASCQ (low byte) and low seven bits of the ASC 1147 1.7.2.2 nathanw * (low seven bits of the high byte). 1148 1.7.2.2 nathanw */ 1149 1.7.2.2 nathanw if (le32toh(me->code) == 0x1c && 1150 1.7.2.2 nathanw (ssd->flags & SSD_KEY) == SKEY_VENDOR_UNIQUE && 1151 1.7.2.2 nathanw (ssd->add_sense_code & 0x80) != 0) { 1152 1.7.2.2 nathanw event = ((int)(ssd->add_sense_code & ~0x80) << 8) + 1153 1.7.2.2 nathanw ssd->add_sense_code_qual; 1154 1.7.2.2 nathanw } else 1155 1.7.2.2 nathanw event = le32toh(me->code); 1156 1.7.2.2 nathanw 1157 1.7.2.2 nathanw /* Look up event, get codes. */ 1158 1.7.2.2 nathanw fp = mly_describe_code(mly_table_event, event); 1159 1.7.2.2 nathanw 1160 1.7.2.2 nathanw /* Quiet event? */ 1161 1.7.2.2 nathanw class = fp[0]; 1162 1.7.2.2 nathanw #ifdef notyet 1163 1.7.2.2 nathanw if (isupper(class) && bootverbose) 1164 1.7.2.2 nathanw class = tolower(class); 1165 1.7.2.2 nathanw #endif 1166 1.7.2.2 nathanw 1167 1.7.2.2 nathanw /* Get action code, text string. */ 1168 1.7.2.2 nathanw action = fp[1]; 1169 1.7.2.2 nathanw tp = fp + 3; 1170 1.7.2.2 nathanw 1171 1.7.2.2 nathanw /* 1172 1.7.2.2 nathanw * Print some information about the event. 1173 1.7.2.2 nathanw * 1174 1.7.2.2 nathanw * This code uses a table derived from the corresponding portion of 1175 1.7.2.2 nathanw * the Linux driver, and thus the parser is very similar. 1176 1.7.2.2 nathanw */ 1177 1.7.2.2 nathanw switch (class) { 1178 1.7.2.2 nathanw case 'p': 1179 1.7.2.2 nathanw /* 1180 1.7.2.2 nathanw * Error on physical drive. 1181 1.7.2.2 nathanw */ 1182 1.7.2.2 nathanw printf("%s: physical device %d:%d %s\n", mly->mly_dv.dv_xname, 1183 1.7.2.2 nathanw me->channel, me->target, tp); 1184 1.7.2.2 nathanw if (action == 'r') 1185 1.7.2.2 nathanw mly->mly_btl[me->channel][me->target].mb_flags |= 1186 1.7.2.2 nathanw MLY_BTL_RESCAN; 1187 1.7.2.2 nathanw break; 1188 1.7.2.2 nathanw 1189 1.7.2.2 nathanw case 'l': 1190 1.7.2.2 nathanw case 'm': 1191 1.7.2.2 nathanw /* 1192 1.7.2.2 nathanw * Error on logical unit, or message about logical unit. 1193 1.7.2.2 nathanw */ 1194 1.7.2.2 nathanw bus = MLY_LOGDEV_BUS(mly, me->lun); 1195 1.7.2.2 nathanw target = MLY_LOGDEV_TARGET(mly, me->lun); 1196 1.7.2.2 nathanw printf("%s: logical device %d:%d %s\n", mly->mly_dv.dv_xname, 1197 1.7.2.2 nathanw bus, target, tp); 1198 1.7.2.2 nathanw if (action == 'r') 1199 1.7.2.2 nathanw mly->mly_btl[bus][target].mb_flags |= MLY_BTL_RESCAN; 1200 1.7.2.2 nathanw break; 1201 1.7.2.2 nathanw 1202 1.7.2.2 nathanw case 's': 1203 1.7.2.2 nathanw /* 1204 1.7.2.2 nathanw * Report of sense data. 1205 1.7.2.2 nathanw */ 1206 1.7.2.2 nathanw if (((ssd->flags & SSD_KEY) == SKEY_NO_SENSE || 1207 1.7.2.2 nathanw (ssd->flags & SSD_KEY) == SKEY_NOT_READY) && 1208 1.7.2.2 nathanw ssd->add_sense_code == 0x04 && 1209 1.7.2.2 nathanw (ssd->add_sense_code_qual == 0x01 || 1210 1.7.2.2 nathanw ssd->add_sense_code_qual == 0x02)) { 1211 1.7.2.2 nathanw /* Ignore NO_SENSE or NOT_READY in one case */ 1212 1.7.2.2 nathanw break; 1213 1.7.2.2 nathanw } 1214 1.7.2.2 nathanw 1215 1.7.2.2 nathanw /* 1216 1.7.2.2 nathanw * XXX Should translate this if SCSIVERBOSE. 1217 1.7.2.2 nathanw */ 1218 1.7.2.2 nathanw printf("%s: physical device %d:%d %s\n", mly->mly_dv.dv_xname, 1219 1.7.2.2 nathanw me->channel, me->target, tp); 1220 1.7.2.2 nathanw printf("%s: sense key %d asc %02x ascq %02x\n", 1221 1.7.2.2 nathanw mly->mly_dv.dv_xname, ssd->flags & SSD_KEY, 1222 1.7.2.2 nathanw ssd->add_sense_code, ssd->add_sense_code_qual); 1223 1.7.2.2 nathanw printf("%s: info %x%x%x%x csi %x%x%x%x\n", 1224 1.7.2.2 nathanw mly->mly_dv.dv_xname, ssd->info[0], ssd->info[1], 1225 1.7.2.2 nathanw ssd->info[2], ssd->info[3], ssd->cmd_spec_info[0], 1226 1.7.2.2 nathanw ssd->cmd_spec_info[1], ssd->cmd_spec_info[2], 1227 1.7.2.2 nathanw ssd->cmd_spec_info[3]); 1228 1.7.2.2 nathanw if (action == 'r') 1229 1.7.2.2 nathanw mly->mly_btl[me->channel][me->target].mb_flags |= 1230 1.7.2.2 nathanw MLY_BTL_RESCAN; 1231 1.7.2.2 nathanw break; 1232 1.7.2.2 nathanw 1233 1.7.2.2 nathanw case 'e': 1234 1.7.2.2 nathanw printf("%s: ", mly->mly_dv.dv_xname); 1235 1.7.2.2 nathanw printf(tp, me->target, me->lun); 1236 1.7.2.2 nathanw break; 1237 1.7.2.2 nathanw 1238 1.7.2.2 nathanw case 'c': 1239 1.7.2.2 nathanw printf("%s: controller %s\n", mly->mly_dv.dv_xname, tp); 1240 1.7.2.2 nathanw break; 1241 1.7.2.2 nathanw 1242 1.7.2.2 nathanw case '?': 1243 1.7.2.2 nathanw printf("%s: %s - %d\n", mly->mly_dv.dv_xname, tp, event); 1244 1.7.2.2 nathanw break; 1245 1.7.2.2 nathanw 1246 1.7.2.2 nathanw default: 1247 1.7.2.2 nathanw /* Probably a 'noisy' event being ignored. */ 1248 1.7.2.2 nathanw break; 1249 1.7.2.2 nathanw } 1250 1.7.2.2 nathanw } 1251 1.7.2.2 nathanw 1252 1.7.2.2 nathanw /* 1253 1.7.2.2 nathanw * Create the monitoring thread. Called after the standard kernel threads 1254 1.7.2.2 nathanw * have been created. 1255 1.7.2.2 nathanw */ 1256 1.7.2.2 nathanw static void 1257 1.7.2.2 nathanw mly_thread_create(void *cookie) 1258 1.7.2.2 nathanw { 1259 1.7.2.2 nathanw struct mly_softc *mly; 1260 1.7.2.2 nathanw int rv; 1261 1.7.2.2 nathanw 1262 1.7.2.2 nathanw mly = cookie; 1263 1.7.2.2 nathanw 1264 1.7.2.2 nathanw rv = kthread_create1(mly_thread, mly, &mly->mly_thread, "%s", 1265 1.7.2.2 nathanw mly->mly_dv.dv_xname); 1266 1.7.2.2 nathanw if (rv != 0) 1267 1.7.2.2 nathanw printf("%s: unable to create thread (%d)\n", 1268 1.7.2.2 nathanw mly->mly_dv.dv_xname, rv); 1269 1.7.2.2 nathanw } 1270 1.7.2.2 nathanw 1271 1.7.2.2 nathanw /* 1272 1.7.2.2 nathanw * Perform periodic activities. 1273 1.7.2.2 nathanw */ 1274 1.7.2.2 nathanw static void 1275 1.7.2.2 nathanw mly_thread(void *cookie) 1276 1.7.2.2 nathanw { 1277 1.7.2.2 nathanw struct mly_softc *mly; 1278 1.7.2.2 nathanw struct mly_btl *btl; 1279 1.7.2.2 nathanw int s, bus, target, done; 1280 1.7.2.2 nathanw 1281 1.7.2.2 nathanw mly = (struct mly_softc *)cookie; 1282 1.7.2.2 nathanw 1283 1.7.2.2 nathanw for (;;) { 1284 1.7.2.2 nathanw /* Check for new events. */ 1285 1.7.2.2 nathanw mly_check_event(mly); 1286 1.7.2.2 nathanw 1287 1.7.2.2 nathanw /* Re-scan up to 1 device. */ 1288 1.7.2.2 nathanw s = splbio(); 1289 1.7.2.2 nathanw done = 0; 1290 1.7.2.2 nathanw for (bus = 0; bus < mly->mly_nchans && !done; bus++) { 1291 1.7.2.2 nathanw for (target = 0; target < MLY_MAX_TARGETS; target++) { 1292 1.7.2.2 nathanw /* Perform device rescan? */ 1293 1.7.2.2 nathanw btl = &mly->mly_btl[bus][target]; 1294 1.7.2.2 nathanw if ((btl->mb_flags & MLY_BTL_RESCAN) != 0) { 1295 1.7.2.2 nathanw btl->mb_flags ^= MLY_BTL_RESCAN; 1296 1.7.2.2 nathanw mly_scan_btl(mly, bus, target); 1297 1.7.2.2 nathanw done = 1; 1298 1.7.2.2 nathanw break; 1299 1.7.2.2 nathanw } 1300 1.7.2.2 nathanw } 1301 1.7.2.2 nathanw } 1302 1.7.2.2 nathanw splx(s); 1303 1.7.2.2 nathanw 1304 1.7.2.2 nathanw /* Sleep for N seconds. */ 1305 1.7.2.2 nathanw tsleep(mly_thread, PWAIT, "mlyzzz", 1306 1.7.2.2 nathanw hz * MLY_PERIODIC_INTERVAL); 1307 1.7.2.2 nathanw } 1308 1.7.2.2 nathanw } 1309 1.7.2.2 nathanw 1310 1.7.2.2 nathanw /* 1311 1.7.2.2 nathanw * Submit a command to the controller and poll on completion. Return 1312 1.7.2.2 nathanw * non-zero on timeout. 1313 1.7.2.2 nathanw */ 1314 1.7.2.2 nathanw static int 1315 1.7.2.2 nathanw mly_ccb_poll(struct mly_softc *mly, struct mly_ccb *mc, int timo) 1316 1.7.2.2 nathanw { 1317 1.7.2.2 nathanw int rv; 1318 1.7.2.2 nathanw 1319 1.7.2.2 nathanw if ((rv = mly_ccb_submit(mly, mc)) != 0) 1320 1.7.2.2 nathanw return (rv); 1321 1.7.2.2 nathanw 1322 1.7.2.2 nathanw for (timo *= 10; timo != 0; timo--) { 1323 1.7.2.2 nathanw if ((mc->mc_flags & MLY_CCB_COMPLETE) != 0) 1324 1.7.2.2 nathanw break; 1325 1.7.2.2 nathanw mly_intr(mly); 1326 1.7.2.2 nathanw DELAY(100); 1327 1.7.2.2 nathanw } 1328 1.7.2.2 nathanw 1329 1.7.2.2 nathanw return (timo == 0); 1330 1.7.2.2 nathanw } 1331 1.7.2.2 nathanw 1332 1.7.2.2 nathanw /* 1333 1.7.2.2 nathanw * Submit a command to the controller and sleep on completion. Return 1334 1.7.2.2 nathanw * non-zero on timeout. 1335 1.7.2.2 nathanw */ 1336 1.7.2.2 nathanw static int 1337 1.7.2.2 nathanw mly_ccb_wait(struct mly_softc *mly, struct mly_ccb *mc, int timo) 1338 1.7.2.2 nathanw { 1339 1.7.2.2 nathanw int rv, s; 1340 1.7.2.2 nathanw 1341 1.7.2.2 nathanw mly_ccb_enqueue(mly, mc); 1342 1.7.2.2 nathanw 1343 1.7.2.2 nathanw s = splbio(); 1344 1.7.2.2 nathanw if ((mc->mc_flags & MLY_CCB_COMPLETE) != 0) { 1345 1.7.2.2 nathanw splx(s); 1346 1.7.2.2 nathanw return (0); 1347 1.7.2.2 nathanw } 1348 1.7.2.2 nathanw rv = tsleep(mc, PRIBIO, "mlywccb", timo * hz / 1000); 1349 1.7.2.2 nathanw splx(s); 1350 1.7.2.2 nathanw 1351 1.7.2.2 nathanw return (rv); 1352 1.7.2.2 nathanw } 1353 1.7.2.2 nathanw 1354 1.7.2.2 nathanw /* 1355 1.7.2.2 nathanw * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1356 1.7.2.2 nathanw * the order that they were enqueued and try to submit their command blocks 1357 1.7.2.2 nathanw * to the controller for execution. 1358 1.7.2.2 nathanw */ 1359 1.7.2.2 nathanw void 1360 1.7.2.2 nathanw mly_ccb_enqueue(struct mly_softc *mly, struct mly_ccb *mc) 1361 1.7.2.2 nathanw { 1362 1.7.2.2 nathanw int s; 1363 1.7.2.2 nathanw 1364 1.7.2.2 nathanw s = splbio(); 1365 1.7.2.2 nathanw 1366 1.7.2.2 nathanw if (mc != NULL) 1367 1.7.2.2 nathanw SIMPLEQ_INSERT_TAIL(&mly->mly_ccb_queue, mc, mc_link.simpleq); 1368 1.7.2.2 nathanw 1369 1.7.2.2 nathanw while ((mc = SIMPLEQ_FIRST(&mly->mly_ccb_queue)) != NULL) { 1370 1.7.2.2 nathanw if (mly_ccb_submit(mly, mc)) 1371 1.7.2.2 nathanw break; 1372 1.7.2.5 nathanw SIMPLEQ_REMOVE_HEAD(&mly->mly_ccb_queue, mc_link.simpleq); 1373 1.7.2.2 nathanw } 1374 1.7.2.2 nathanw 1375 1.7.2.2 nathanw splx(s); 1376 1.7.2.2 nathanw } 1377 1.7.2.2 nathanw 1378 1.7.2.2 nathanw /* 1379 1.7.2.2 nathanw * Deliver a command to the controller. 1380 1.7.2.2 nathanw */ 1381 1.7.2.2 nathanw static int 1382 1.7.2.2 nathanw mly_ccb_submit(struct mly_softc *mly, struct mly_ccb *mc) 1383 1.7.2.2 nathanw { 1384 1.7.2.2 nathanw union mly_cmd_packet *pkt; 1385 1.7.2.2 nathanw int s, off; 1386 1.7.2.2 nathanw 1387 1.7.2.2 nathanw mc->mc_packet->generic.command_id = htole16(mc->mc_slot); 1388 1.7.2.2 nathanw 1389 1.7.2.2 nathanw bus_dmamap_sync(mly->mly_dmat, mly->mly_pkt_dmamap, 1390 1.7.2.2 nathanw mc->mc_packetphys - mly->mly_pkt_busaddr, 1391 1.7.2.2 nathanw sizeof(union mly_cmd_packet), 1392 1.7.2.2 nathanw BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1393 1.7.2.2 nathanw 1394 1.7.2.2 nathanw s = splbio(); 1395 1.7.2.2 nathanw 1396 1.7.2.2 nathanw /* 1397 1.7.2.2 nathanw * Do we have to use the hardware mailbox? 1398 1.7.2.2 nathanw */ 1399 1.7.2.2 nathanw if ((mly->mly_state & MLY_STATE_MMBOX_ACTIVE) == 0) { 1400 1.7.2.2 nathanw /* 1401 1.7.2.2 nathanw * Check to see if the controller is ready for us. 1402 1.7.2.2 nathanw */ 1403 1.7.2.2 nathanw if (mly_idbr_true(mly, MLY_HM_CMDSENT)) { 1404 1.7.2.2 nathanw splx(s); 1405 1.7.2.2 nathanw return (EBUSY); 1406 1.7.2.2 nathanw } 1407 1.7.2.2 nathanw 1408 1.7.2.2 nathanw /* 1409 1.7.2.2 nathanw * It's ready, send the command. 1410 1.7.2.2 nathanw */ 1411 1.7.2.2 nathanw mly_outl(mly, mly->mly_cmd_mailbox, 1412 1.7.2.2 nathanw (u_int64_t)mc->mc_packetphys & 0xffffffff); 1413 1.7.2.2 nathanw mly_outl(mly, mly->mly_cmd_mailbox + 4, 1414 1.7.2.2 nathanw (u_int64_t)mc->mc_packetphys >> 32); 1415 1.7.2.2 nathanw mly_outb(mly, mly->mly_idbr, MLY_HM_CMDSENT); 1416 1.7.2.2 nathanw } else { 1417 1.7.2.2 nathanw pkt = &mly->mly_mmbox->mmm_command[mly->mly_mmbox_cmd_idx]; 1418 1.7.2.2 nathanw off = (caddr_t)pkt - (caddr_t)mly->mly_mmbox; 1419 1.7.2.2 nathanw 1420 1.7.2.2 nathanw bus_dmamap_sync(mly->mly_dmat, mly->mly_mmbox_dmamap, 1421 1.7.2.2 nathanw off, sizeof(mly->mly_mmbox->mmm_command[0]), 1422 1.7.2.2 nathanw BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1423 1.7.2.2 nathanw 1424 1.7.2.2 nathanw /* Check to see if the next index is free yet. */ 1425 1.7.2.2 nathanw if (pkt->mmbox.flag != 0) { 1426 1.7.2.2 nathanw splx(s); 1427 1.7.2.2 nathanw return (EBUSY); 1428 1.7.2.2 nathanw } 1429 1.7.2.2 nathanw 1430 1.7.2.2 nathanw /* Copy in new command */ 1431 1.7.2.2 nathanw memcpy(pkt->mmbox.data, mc->mc_packet->mmbox.data, 1432 1.7.2.2 nathanw sizeof(pkt->mmbox.data)); 1433 1.7.2.2 nathanw 1434 1.7.2.2 nathanw /* Copy flag last. */ 1435 1.7.2.2 nathanw pkt->mmbox.flag = mc->mc_packet->mmbox.flag; 1436 1.7.2.2 nathanw 1437 1.7.2.2 nathanw bus_dmamap_sync(mly->mly_dmat, mly->mly_mmbox_dmamap, 1438 1.7.2.2 nathanw off, sizeof(mly->mly_mmbox->mmm_command[0]), 1439 1.7.2.2 nathanw BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1440 1.7.2.2 nathanw 1441 1.7.2.2 nathanw /* Signal controller and update index. */ 1442 1.7.2.2 nathanw mly_outb(mly, mly->mly_idbr, MLY_AM_CMDSENT); 1443 1.7.2.2 nathanw mly->mly_mmbox_cmd_idx = 1444 1.7.2.2 nathanw (mly->mly_mmbox_cmd_idx + 1) % MLY_MMBOX_COMMANDS; 1445 1.7.2.2 nathanw } 1446 1.7.2.2 nathanw 1447 1.7.2.2 nathanw splx(s); 1448 1.7.2.2 nathanw return (0); 1449 1.7.2.2 nathanw } 1450 1.7.2.2 nathanw 1451 1.7.2.2 nathanw /* 1452 1.7.2.2 nathanw * Pick up completed commands from the controller and handle accordingly. 1453 1.7.2.2 nathanw */ 1454 1.7.2.2 nathanw int 1455 1.7.2.2 nathanw mly_intr(void *cookie) 1456 1.7.2.2 nathanw { 1457 1.7.2.2 nathanw struct mly_ccb *mc; 1458 1.7.2.2 nathanw union mly_status_packet *sp; 1459 1.7.2.2 nathanw u_int16_t slot; 1460 1.7.2.2 nathanw int forus, off; 1461 1.7.2.2 nathanw struct mly_softc *mly; 1462 1.7.2.2 nathanw 1463 1.7.2.2 nathanw mly = cookie; 1464 1.7.2.2 nathanw forus = 0; 1465 1.7.2.2 nathanw 1466 1.7.2.2 nathanw /* 1467 1.7.2.2 nathanw * Pick up hardware-mailbox commands. 1468 1.7.2.2 nathanw */ 1469 1.7.2.2 nathanw if (mly_odbr_true(mly, MLY_HM_STSREADY)) { 1470 1.7.2.2 nathanw slot = mly_inw(mly, mly->mly_status_mailbox); 1471 1.7.2.2 nathanw 1472 1.7.2.2 nathanw if (slot < MLY_SLOT_MAX) { 1473 1.7.2.2 nathanw mc = mly->mly_ccbs + (slot - MLY_SLOT_START); 1474 1.7.2.2 nathanw mc->mc_status = 1475 1.7.2.2 nathanw mly_inb(mly, mly->mly_status_mailbox + 2); 1476 1.7.2.2 nathanw mc->mc_sense = 1477 1.7.2.2 nathanw mly_inb(mly, mly->mly_status_mailbox + 3); 1478 1.7.2.2 nathanw mc->mc_resid = 1479 1.7.2.2 nathanw mly_inl(mly, mly->mly_status_mailbox + 4); 1480 1.7.2.2 nathanw 1481 1.7.2.2 nathanw mly_ccb_complete(mly, mc); 1482 1.7.2.2 nathanw } else { 1483 1.7.2.2 nathanw /* Slot 0xffff may mean "extremely bogus command". */ 1484 1.7.2.2 nathanw printf("%s: got HM completion for illegal slot %u\n", 1485 1.7.2.2 nathanw mly->mly_dv.dv_xname, slot); 1486 1.7.2.2 nathanw } 1487 1.7.2.2 nathanw 1488 1.7.2.2 nathanw /* Unconditionally acknowledge status. */ 1489 1.7.2.2 nathanw mly_outb(mly, mly->mly_odbr, MLY_HM_STSREADY); 1490 1.7.2.2 nathanw mly_outb(mly, mly->mly_idbr, MLY_HM_STSACK); 1491 1.7.2.2 nathanw forus = 1; 1492 1.7.2.2 nathanw } 1493 1.7.2.2 nathanw 1494 1.7.2.2 nathanw /* 1495 1.7.2.2 nathanw * Pick up memory-mailbox commands. 1496 1.7.2.2 nathanw */ 1497 1.7.2.2 nathanw if (mly_odbr_true(mly, MLY_AM_STSREADY)) { 1498 1.7.2.2 nathanw for (;;) { 1499 1.7.2.2 nathanw sp = &mly->mly_mmbox->mmm_status[mly->mly_mmbox_sts_idx]; 1500 1.7.2.2 nathanw off = (caddr_t)sp - (caddr_t)mly->mly_mmbox; 1501 1.7.2.2 nathanw 1502 1.7.2.2 nathanw bus_dmamap_sync(mly->mly_dmat, mly->mly_mmbox_dmamap, 1503 1.7.2.2 nathanw off, sizeof(mly->mly_mmbox->mmm_command[0]), 1504 1.7.2.2 nathanw BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1505 1.7.2.2 nathanw 1506 1.7.2.2 nathanw /* Check for more status. */ 1507 1.7.2.2 nathanw if (sp->mmbox.flag == 0) 1508 1.7.2.2 nathanw break; 1509 1.7.2.2 nathanw 1510 1.7.2.2 nathanw /* Get slot number. */ 1511 1.7.2.2 nathanw slot = le16toh(sp->status.command_id); 1512 1.7.2.2 nathanw if (slot < MLY_SLOT_MAX) { 1513 1.7.2.2 nathanw mc = mly->mly_ccbs + (slot - MLY_SLOT_START); 1514 1.7.2.2 nathanw mc->mc_status = sp->status.status; 1515 1.7.2.2 nathanw mc->mc_sense = sp->status.sense_length; 1516 1.7.2.2 nathanw mc->mc_resid = le32toh(sp->status.residue); 1517 1.7.2.2 nathanw mly_ccb_complete(mly, mc); 1518 1.7.2.2 nathanw } else { 1519 1.7.2.2 nathanw /* 1520 1.7.2.2 nathanw * Slot 0xffff may mean "extremely bogus 1521 1.7.2.2 nathanw * command". 1522 1.7.2.2 nathanw */ 1523 1.7.2.2 nathanw printf("%s: got AM completion for illegal " 1524 1.7.2.2 nathanw "slot %u at %d\n", mly->mly_dv.dv_xname, 1525 1.7.2.2 nathanw slot, mly->mly_mmbox_sts_idx); 1526 1.7.2.2 nathanw } 1527 1.7.2.2 nathanw 1528 1.7.2.2 nathanw /* Clear and move to next index. */ 1529 1.7.2.2 nathanw sp->mmbox.flag = 0; 1530 1.7.2.2 nathanw mly->mly_mmbox_sts_idx = 1531 1.7.2.2 nathanw (mly->mly_mmbox_sts_idx + 1) % MLY_MMBOX_STATUS; 1532 1.7.2.2 nathanw } 1533 1.7.2.2 nathanw 1534 1.7.2.2 nathanw /* Acknowledge that we have collected status value(s). */ 1535 1.7.2.2 nathanw mly_outb(mly, mly->mly_odbr, MLY_AM_STSREADY); 1536 1.7.2.2 nathanw forus = 1; 1537 1.7.2.2 nathanw } 1538 1.7.2.2 nathanw 1539 1.7.2.2 nathanw /* 1540 1.7.2.2 nathanw * Run the queue. 1541 1.7.2.2 nathanw */ 1542 1.7.2.5 nathanw if (forus && ! SIMPLEQ_EMPTY(&mly->mly_ccb_queue)) 1543 1.7.2.2 nathanw mly_ccb_enqueue(mly, NULL); 1544 1.7.2.2 nathanw 1545 1.7.2.2 nathanw return (forus); 1546 1.7.2.2 nathanw } 1547 1.7.2.2 nathanw 1548 1.7.2.2 nathanw /* 1549 1.7.2.2 nathanw * Process completed commands 1550 1.7.2.2 nathanw */ 1551 1.7.2.2 nathanw static void 1552 1.7.2.2 nathanw mly_ccb_complete(struct mly_softc *mly, struct mly_ccb *mc) 1553 1.7.2.2 nathanw { 1554 1.7.2.2 nathanw void (*complete)(struct mly_softc *, struct mly_ccb *); 1555 1.7.2.2 nathanw 1556 1.7.2.2 nathanw bus_dmamap_sync(mly->mly_dmat, mly->mly_pkt_dmamap, 1557 1.7.2.2 nathanw mc->mc_packetphys - mly->mly_pkt_busaddr, 1558 1.7.2.2 nathanw sizeof(union mly_cmd_packet), 1559 1.7.2.2 nathanw BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1560 1.7.2.2 nathanw 1561 1.7.2.2 nathanw complete = mc->mc_complete; 1562 1.7.2.2 nathanw mc->mc_flags |= MLY_CCB_COMPLETE; 1563 1.7.2.2 nathanw 1564 1.7.2.2 nathanw /* 1565 1.7.2.2 nathanw * Call completion handler or wake up sleeping consumer. 1566 1.7.2.2 nathanw */ 1567 1.7.2.2 nathanw if (complete != NULL) 1568 1.7.2.2 nathanw (*complete)(mly, mc); 1569 1.7.2.2 nathanw else 1570 1.7.2.2 nathanw wakeup(mc); 1571 1.7.2.2 nathanw } 1572 1.7.2.2 nathanw 1573 1.7.2.2 nathanw /* 1574 1.7.2.2 nathanw * Allocate a command. 1575 1.7.2.2 nathanw */ 1576 1.7.2.2 nathanw int 1577 1.7.2.2 nathanw mly_ccb_alloc(struct mly_softc *mly, struct mly_ccb **mcp) 1578 1.7.2.2 nathanw { 1579 1.7.2.2 nathanw struct mly_ccb *mc; 1580 1.7.2.2 nathanw int s; 1581 1.7.2.2 nathanw 1582 1.7.2.2 nathanw s = splbio(); 1583 1.7.2.2 nathanw mc = SLIST_FIRST(&mly->mly_ccb_free); 1584 1.7.2.2 nathanw if (mc != NULL) 1585 1.7.2.2 nathanw SLIST_REMOVE_HEAD(&mly->mly_ccb_free, mc_link.slist); 1586 1.7.2.2 nathanw splx(s); 1587 1.7.2.2 nathanw 1588 1.7.2.2 nathanw *mcp = mc; 1589 1.7.2.2 nathanw return (mc == NULL ? EAGAIN : 0); 1590 1.7.2.2 nathanw } 1591 1.7.2.2 nathanw 1592 1.7.2.2 nathanw /* 1593 1.7.2.2 nathanw * Release a command back to the freelist. 1594 1.7.2.2 nathanw */ 1595 1.7.2.2 nathanw void 1596 1.7.2.2 nathanw mly_ccb_free(struct mly_softc *mly, struct mly_ccb *mc) 1597 1.7.2.2 nathanw { 1598 1.7.2.2 nathanw int s; 1599 1.7.2.2 nathanw 1600 1.7.2.2 nathanw /* 1601 1.7.2.2 nathanw * Fill in parts of the command that may cause confusion if a 1602 1.7.2.2 nathanw * consumer doesn't when we are later allocated. 1603 1.7.2.2 nathanw */ 1604 1.7.2.2 nathanw mc->mc_data = NULL; 1605 1.7.2.2 nathanw mc->mc_flags = 0; 1606 1.7.2.2 nathanw mc->mc_complete = NULL; 1607 1.7.2.2 nathanw mc->mc_private = NULL; 1608 1.7.2.2 nathanw mc->mc_packet->generic.command_control = 0; 1609 1.7.2.2 nathanw 1610 1.7.2.2 nathanw /* 1611 1.7.2.2 nathanw * By default, we set up to overwrite the command packet with sense 1612 1.7.2.2 nathanw * information. 1613 1.7.2.2 nathanw */ 1614 1.7.2.2 nathanw mc->mc_packet->generic.sense_buffer_address = 1615 1.7.2.2 nathanw htole64(mc->mc_packetphys); 1616 1.7.2.2 nathanw mc->mc_packet->generic.maximum_sense_size = 1617 1.7.2.2 nathanw sizeof(union mly_cmd_packet); 1618 1.7.2.2 nathanw 1619 1.7.2.2 nathanw s = splbio(); 1620 1.7.2.2 nathanw SLIST_INSERT_HEAD(&mly->mly_ccb_free, mc, mc_link.slist); 1621 1.7.2.2 nathanw splx(s); 1622 1.7.2.2 nathanw } 1623 1.7.2.2 nathanw 1624 1.7.2.2 nathanw /* 1625 1.7.2.2 nathanw * Allocate and initialise command and packet structures. 1626 1.7.2.2 nathanw * 1627 1.7.2.2 nathanw * If the controller supports fewer than MLY_MAX_CCBS commands, limit our 1628 1.7.2.2 nathanw * allocation to that number. If we don't yet know how many commands the 1629 1.7.2.2 nathanw * controller supports, allocate a very small set (suitable for initialisation 1630 1.7.2.2 nathanw * purposes only). 1631 1.7.2.2 nathanw */ 1632 1.7.2.2 nathanw static int 1633 1.7.2.2 nathanw mly_alloc_ccbs(struct mly_softc *mly) 1634 1.7.2.2 nathanw { 1635 1.7.2.2 nathanw struct mly_ccb *mc; 1636 1.7.2.2 nathanw int i, rv; 1637 1.7.2.2 nathanw 1638 1.7.2.2 nathanw if (mly->mly_controllerinfo == NULL) 1639 1.7.2.2 nathanw mly->mly_ncmds = MLY_CCBS_RESV; 1640 1.7.2.2 nathanw else { 1641 1.7.2.2 nathanw i = le16toh(mly->mly_controllerinfo->maximum_parallel_commands); 1642 1.7.2.2 nathanw mly->mly_ncmds = min(MLY_MAX_CCBS, i); 1643 1.7.2.2 nathanw } 1644 1.7.2.2 nathanw 1645 1.7.2.2 nathanw /* 1646 1.7.2.2 nathanw * Allocate enough space for all the command packets in one chunk 1647 1.7.2.2 nathanw * and map them permanently into controller-visible space. 1648 1.7.2.2 nathanw */ 1649 1.7.2.2 nathanw rv = mly_dmamem_alloc(mly, 1650 1.7.2.2 nathanw mly->mly_ncmds * sizeof(union mly_cmd_packet), 1651 1.7.2.2 nathanw &mly->mly_pkt_dmamap, (caddr_t *)&mly->mly_pkt, 1652 1.7.2.2 nathanw &mly->mly_pkt_busaddr, &mly->mly_pkt_seg); 1653 1.7.2.2 nathanw if (rv) 1654 1.7.2.2 nathanw return (rv); 1655 1.7.2.2 nathanw 1656 1.7.2.2 nathanw mly->mly_ccbs = malloc(sizeof(struct mly_ccb) * mly->mly_ncmds, 1657 1.7.2.4 nathanw M_DEVBUF, M_NOWAIT|M_ZERO); 1658 1.7.2.2 nathanw 1659 1.7.2.2 nathanw for (i = 0; i < mly->mly_ncmds; i++) { 1660 1.7.2.2 nathanw mc = mly->mly_ccbs + i; 1661 1.7.2.2 nathanw mc->mc_slot = MLY_SLOT_START + i; 1662 1.7.2.2 nathanw mc->mc_packet = mly->mly_pkt + i; 1663 1.7.2.2 nathanw mc->mc_packetphys = mly->mly_pkt_busaddr + 1664 1.7.2.2 nathanw (i * sizeof(union mly_cmd_packet)); 1665 1.7.2.2 nathanw 1666 1.7.2.2 nathanw rv = bus_dmamap_create(mly->mly_dmat, MLY_MAX_XFER, 1667 1.7.2.2 nathanw MLY_MAX_SEGS, MLY_MAX_XFER, 0, 1668 1.7.2.2 nathanw BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1669 1.7.2.2 nathanw &mc->mc_datamap); 1670 1.7.2.2 nathanw if (rv) { 1671 1.7.2.2 nathanw mly_release_ccbs(mly); 1672 1.7.2.2 nathanw return (rv); 1673 1.7.2.2 nathanw } 1674 1.7.2.2 nathanw 1675 1.7.2.2 nathanw mly_ccb_free(mly, mc); 1676 1.7.2.2 nathanw } 1677 1.7.2.2 nathanw 1678 1.7.2.2 nathanw return (0); 1679 1.7.2.2 nathanw } 1680 1.7.2.2 nathanw 1681 1.7.2.2 nathanw /* 1682 1.7.2.2 nathanw * Free all the storage held by commands. 1683 1.7.2.2 nathanw * 1684 1.7.2.2 nathanw * Must be called with all commands on the free list. 1685 1.7.2.2 nathanw */ 1686 1.7.2.2 nathanw static void 1687 1.7.2.2 nathanw mly_release_ccbs(struct mly_softc *mly) 1688 1.7.2.2 nathanw { 1689 1.7.2.2 nathanw struct mly_ccb *mc; 1690 1.7.2.2 nathanw 1691 1.7.2.2 nathanw /* Throw away command buffer DMA maps. */ 1692 1.7.2.2 nathanw while (mly_ccb_alloc(mly, &mc) == 0) 1693 1.7.2.2 nathanw bus_dmamap_destroy(mly->mly_dmat, mc->mc_datamap); 1694 1.7.2.2 nathanw 1695 1.7.2.2 nathanw /* Release CCB storage. */ 1696 1.7.2.2 nathanw free(mly->mly_ccbs, M_DEVBUF); 1697 1.7.2.2 nathanw 1698 1.7.2.2 nathanw /* Release the packet storage. */ 1699 1.7.2.2 nathanw mly_dmamem_free(mly, mly->mly_ncmds * sizeof(union mly_cmd_packet), 1700 1.7.2.2 nathanw mly->mly_pkt_dmamap, (caddr_t)mly->mly_pkt, &mly->mly_pkt_seg); 1701 1.7.2.2 nathanw } 1702 1.7.2.2 nathanw 1703 1.7.2.2 nathanw /* 1704 1.7.2.2 nathanw * Map a command into controller-visible space. 1705 1.7.2.2 nathanw */ 1706 1.7.2.2 nathanw static int 1707 1.7.2.2 nathanw mly_ccb_map(struct mly_softc *mly, struct mly_ccb *mc) 1708 1.7.2.2 nathanw { 1709 1.7.2.2 nathanw struct mly_cmd_generic *gen; 1710 1.7.2.2 nathanw struct mly_sg_entry *sg; 1711 1.7.2.2 nathanw bus_dma_segment_t *ds; 1712 1.7.2.2 nathanw int flg, nseg, rv; 1713 1.7.2.2 nathanw 1714 1.7.2.2 nathanw #ifdef DIAGNOSTIC 1715 1.7.2.2 nathanw /* Don't map more than once. */ 1716 1.7.2.2 nathanw if ((mc->mc_flags & MLY_CCB_MAPPED) != 0) 1717 1.7.2.2 nathanw panic("mly_ccb_map: already mapped"); 1718 1.7.2.2 nathanw mc->mc_flags |= MLY_CCB_MAPPED; 1719 1.7.2.2 nathanw 1720 1.7.2.2 nathanw /* Does the command have a data buffer? */ 1721 1.7.2.2 nathanw if (mc->mc_data == NULL) 1722 1.7.2.2 nathanw panic("mly_ccb_map: no data buffer"); 1723 1.7.2.2 nathanw #endif 1724 1.7.2.2 nathanw 1725 1.7.2.2 nathanw rv = bus_dmamap_load(mly->mly_dmat, mc->mc_datamap, mc->mc_data, 1726 1.7.2.2 nathanw mc->mc_length, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1727 1.7.2.2 nathanw ((mc->mc_flags & MLY_CCB_DATAIN) != 0 ? 1728 1.7.2.2 nathanw BUS_DMA_READ : BUS_DMA_WRITE)); 1729 1.7.2.2 nathanw if (rv != 0) 1730 1.7.2.2 nathanw return (rv); 1731 1.7.2.2 nathanw 1732 1.7.2.2 nathanw gen = &mc->mc_packet->generic; 1733 1.7.2.2 nathanw 1734 1.7.2.2 nathanw /* 1735 1.7.2.2 nathanw * Can we use the transfer structure directly? 1736 1.7.2.2 nathanw */ 1737 1.7.2.2 nathanw if ((nseg = mc->mc_datamap->dm_nsegs) <= 2) { 1738 1.7.2.2 nathanw mc->mc_sgoff = -1; 1739 1.7.2.2 nathanw sg = &gen->transfer.direct.sg[0]; 1740 1.7.2.2 nathanw } else { 1741 1.7.2.2 nathanw mc->mc_sgoff = (mc->mc_slot - MLY_SLOT_START) * 1742 1.7.2.2 nathanw MLY_MAX_SEGS; 1743 1.7.2.2 nathanw sg = mly->mly_sg + mc->mc_sgoff; 1744 1.7.2.2 nathanw gen->command_control |= MLY_CMDCTL_EXTENDED_SG_TABLE; 1745 1.7.2.2 nathanw gen->transfer.indirect.entries[0] = htole16(nseg); 1746 1.7.2.2 nathanw gen->transfer.indirect.table_physaddr[0] = 1747 1.7.2.2 nathanw htole64(mly->mly_sg_busaddr + 1748 1.7.2.2 nathanw (mc->mc_sgoff * sizeof(struct mly_sg_entry))); 1749 1.7.2.2 nathanw } 1750 1.7.2.2 nathanw 1751 1.7.2.2 nathanw /* 1752 1.7.2.2 nathanw * Fill the S/G table. 1753 1.7.2.2 nathanw */ 1754 1.7.2.2 nathanw for (ds = mc->mc_datamap->dm_segs; nseg != 0; nseg--, sg++, ds++) { 1755 1.7.2.2 nathanw sg->physaddr = htole64(ds->ds_addr); 1756 1.7.2.2 nathanw sg->length = htole64(ds->ds_len); 1757 1.7.2.2 nathanw } 1758 1.7.2.2 nathanw 1759 1.7.2.2 nathanw /* 1760 1.7.2.2 nathanw * Sync up the data map. 1761 1.7.2.2 nathanw */ 1762 1.7.2.2 nathanw if ((mc->mc_flags & MLY_CCB_DATAIN) != 0) 1763 1.7.2.2 nathanw flg = BUS_DMASYNC_PREREAD; 1764 1.7.2.2 nathanw else /* if ((mc->mc_flags & MLY_CCB_DATAOUT) != 0) */ { 1765 1.7.2.2 nathanw gen->command_control |= MLY_CMDCTL_DATA_DIRECTION; 1766 1.7.2.2 nathanw flg = BUS_DMASYNC_PREWRITE; 1767 1.7.2.2 nathanw } 1768 1.7.2.2 nathanw 1769 1.7.2.2 nathanw bus_dmamap_sync(mly->mly_dmat, mc->mc_datamap, 0, mc->mc_length, flg); 1770 1.7.2.2 nathanw 1771 1.7.2.2 nathanw /* 1772 1.7.2.2 nathanw * Sync up the chained S/G table, if we're using one. 1773 1.7.2.2 nathanw */ 1774 1.7.2.2 nathanw if (mc->mc_sgoff == -1) 1775 1.7.2.2 nathanw return (0); 1776 1.7.2.2 nathanw 1777 1.7.2.2 nathanw bus_dmamap_sync(mly->mly_dmat, mly->mly_sg_dmamap, mc->mc_sgoff, 1778 1.7.2.2 nathanw MLY_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1779 1.7.2.2 nathanw 1780 1.7.2.2 nathanw return (0); 1781 1.7.2.2 nathanw } 1782 1.7.2.2 nathanw 1783 1.7.2.2 nathanw /* 1784 1.7.2.2 nathanw * Unmap a command from controller-visible space. 1785 1.7.2.2 nathanw */ 1786 1.7.2.2 nathanw static void 1787 1.7.2.2 nathanw mly_ccb_unmap(struct mly_softc *mly, struct mly_ccb *mc) 1788 1.7.2.2 nathanw { 1789 1.7.2.2 nathanw int flg; 1790 1.7.2.2 nathanw 1791 1.7.2.2 nathanw #ifdef DIAGNOSTIC 1792 1.7.2.2 nathanw if ((mc->mc_flags & MLY_CCB_MAPPED) == 0) 1793 1.7.2.2 nathanw panic("mly_ccb_unmap: not mapped"); 1794 1.7.2.2 nathanw mc->mc_flags &= ~MLY_CCB_MAPPED; 1795 1.7.2.2 nathanw #endif 1796 1.7.2.2 nathanw 1797 1.7.2.2 nathanw if ((mc->mc_flags & MLY_CCB_DATAIN) != 0) 1798 1.7.2.2 nathanw flg = BUS_DMASYNC_POSTREAD; 1799 1.7.2.2 nathanw else /* if ((mc->mc_flags & MLY_CCB_DATAOUT) != 0) */ 1800 1.7.2.2 nathanw flg = BUS_DMASYNC_POSTWRITE; 1801 1.7.2.2 nathanw 1802 1.7.2.2 nathanw bus_dmamap_sync(mly->mly_dmat, mc->mc_datamap, 0, mc->mc_length, flg); 1803 1.7.2.2 nathanw bus_dmamap_unload(mly->mly_dmat, mc->mc_datamap); 1804 1.7.2.2 nathanw 1805 1.7.2.2 nathanw if (mc->mc_sgoff == -1) 1806 1.7.2.2 nathanw return; 1807 1.7.2.2 nathanw 1808 1.7.2.2 nathanw bus_dmamap_sync(mly->mly_dmat, mly->mly_sg_dmamap, mc->mc_sgoff, 1809 1.7.2.2 nathanw MLY_SGL_SIZE, BUS_DMASYNC_POSTWRITE); 1810 1.7.2.2 nathanw } 1811 1.7.2.2 nathanw 1812 1.7.2.2 nathanw /* 1813 1.7.2.2 nathanw * Adjust the size of each I/O before it passes to the SCSI layer. 1814 1.7.2.2 nathanw */ 1815 1.7.2.2 nathanw static void 1816 1.7.2.2 nathanw mly_scsipi_minphys(struct buf *bp) 1817 1.7.2.2 nathanw { 1818 1.7.2.2 nathanw 1819 1.7.2.2 nathanw if (bp->b_bcount > MLY_MAX_XFER) 1820 1.7.2.2 nathanw bp->b_bcount = MLY_MAX_XFER; 1821 1.7.2.2 nathanw minphys(bp); 1822 1.7.2.2 nathanw } 1823 1.7.2.2 nathanw 1824 1.7.2.2 nathanw /* 1825 1.7.2.2 nathanw * Start a SCSI command. 1826 1.7.2.2 nathanw */ 1827 1.7.2.2 nathanw static void 1828 1.7.2.2 nathanw mly_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 1829 1.7.2.2 nathanw void *arg) 1830 1.7.2.2 nathanw { 1831 1.7.2.2 nathanw struct mly_ccb *mc; 1832 1.7.2.2 nathanw struct mly_cmd_scsi_small *ss; 1833 1.7.2.2 nathanw struct scsipi_xfer *xs; 1834 1.7.2.2 nathanw struct scsipi_periph *periph; 1835 1.7.2.2 nathanw struct mly_softc *mly; 1836 1.7.2.2 nathanw struct mly_btl *btl; 1837 1.7.2.2 nathanw int s, tmp; 1838 1.7.2.2 nathanw 1839 1.7.2.2 nathanw mly = (void *)chan->chan_adapter->adapt_dev; 1840 1.7.2.2 nathanw 1841 1.7.2.2 nathanw switch (req) { 1842 1.7.2.2 nathanw case ADAPTER_REQ_RUN_XFER: 1843 1.7.2.2 nathanw xs = arg; 1844 1.7.2.2 nathanw periph = xs->xs_periph; 1845 1.7.2.2 nathanw btl = &mly->mly_btl[chan->chan_channel][periph->periph_target]; 1846 1.7.2.2 nathanw s = splbio(); 1847 1.7.2.2 nathanw tmp = btl->mb_flags; 1848 1.7.2.2 nathanw splx(s); 1849 1.7.2.2 nathanw 1850 1.7.2.2 nathanw /* 1851 1.7.2.2 nathanw * Check for I/O attempt to a protected or non-existant 1852 1.7.2.2 nathanw * device. 1853 1.7.2.2 nathanw */ 1854 1.7.2.2 nathanw if ((tmp & MLY_BTL_PROTECTED) != 0) { 1855 1.7.2.2 nathanw xs->error = XS_SELTIMEOUT; 1856 1.7.2.2 nathanw scsipi_done(xs); 1857 1.7.2.2 nathanw break; 1858 1.7.2.2 nathanw } 1859 1.7.2.2 nathanw 1860 1.7.2.2 nathanw #ifdef DIAGNOSTIC 1861 1.7.2.2 nathanw /* XXX Increase if/when we support large SCSI commands. */ 1862 1.7.2.2 nathanw if (xs->cmdlen > MLY_CMD_SCSI_SMALL_CDB) { 1863 1.7.2.2 nathanw printf("%s: cmd too large\n", mly->mly_dv.dv_xname); 1864 1.7.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 1865 1.7.2.2 nathanw scsipi_done(xs); 1866 1.7.2.2 nathanw break; 1867 1.7.2.2 nathanw } 1868 1.7.2.2 nathanw #endif 1869 1.7.2.2 nathanw 1870 1.7.2.2 nathanw if (mly_ccb_alloc(mly, &mc)) { 1871 1.7.2.2 nathanw xs->error = XS_RESOURCE_SHORTAGE; 1872 1.7.2.2 nathanw scsipi_done(xs); 1873 1.7.2.2 nathanw break; 1874 1.7.2.2 nathanw } 1875 1.7.2.2 nathanw 1876 1.7.2.2 nathanw /* Build the command. */ 1877 1.7.2.2 nathanw mc->mc_data = xs->data; 1878 1.7.2.2 nathanw mc->mc_length = xs->datalen; 1879 1.7.2.2 nathanw mc->mc_complete = mly_scsipi_complete; 1880 1.7.2.2 nathanw mc->mc_private = xs; 1881 1.7.2.2 nathanw 1882 1.7.2.2 nathanw /* Build the packet for the controller. */ 1883 1.7.2.2 nathanw ss = &mc->mc_packet->scsi_small; 1884 1.7.2.2 nathanw ss->opcode = MDACMD_SCSI; 1885 1.7.2.2 nathanw #ifdef notdef 1886 1.7.2.2 nathanw /* 1887 1.7.2.2 nathanw * XXX FreeBSD does this, but it doesn't fix anything, 1888 1.7.2.2 nathanw * XXX and appears potentially harmful. 1889 1.7.2.2 nathanw */ 1890 1.7.2.2 nathanw ss->command_control |= MLY_CMDCTL_DISABLE_DISCONNECT; 1891 1.7.2.2 nathanw #endif 1892 1.7.2.2 nathanw 1893 1.7.2.2 nathanw ss->data_size = htole32(xs->datalen); 1894 1.7.2.2 nathanw _lto3l(MLY_PHYADDR(0, chan->chan_channel, 1895 1.7.2.2 nathanw periph->periph_target, periph->periph_lun), ss->addr); 1896 1.7.2.2 nathanw 1897 1.7.2.2 nathanw if (xs->timeout < 60 * 1000) 1898 1.7.2.2 nathanw ss->timeout = xs->timeout / 1000 | 1899 1.7.2.2 nathanw MLY_TIMEOUT_SECONDS; 1900 1.7.2.2 nathanw else if (xs->timeout < 60 * 60 * 1000) 1901 1.7.2.2 nathanw ss->timeout = xs->timeout / (60 * 1000) | 1902 1.7.2.2 nathanw MLY_TIMEOUT_MINUTES; 1903 1.7.2.2 nathanw else 1904 1.7.2.2 nathanw ss->timeout = xs->timeout / (60 * 60 * 1000) | 1905 1.7.2.2 nathanw MLY_TIMEOUT_HOURS; 1906 1.7.2.2 nathanw 1907 1.7.2.2 nathanw ss->maximum_sense_size = sizeof(xs->sense); 1908 1.7.2.2 nathanw ss->cdb_length = xs->cmdlen; 1909 1.7.2.2 nathanw memcpy(ss->cdb, xs->cmd, xs->cmdlen); 1910 1.7.2.2 nathanw 1911 1.7.2.2 nathanw if (mc->mc_length != 0) { 1912 1.7.2.2 nathanw if ((xs->xs_control & XS_CTL_DATA_OUT) != 0) 1913 1.7.2.2 nathanw mc->mc_flags |= MLY_CCB_DATAOUT; 1914 1.7.2.2 nathanw else /* if ((xs->xs_control & XS_CTL_DATA_IN) != 0) */ 1915 1.7.2.2 nathanw mc->mc_flags |= MLY_CCB_DATAIN; 1916 1.7.2.2 nathanw 1917 1.7.2.2 nathanw if (mly_ccb_map(mly, mc) != 0) { 1918 1.7.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 1919 1.7.2.2 nathanw mly_ccb_free(mly, mc); 1920 1.7.2.2 nathanw scsipi_done(xs); 1921 1.7.2.2 nathanw break; 1922 1.7.2.2 nathanw } 1923 1.7.2.2 nathanw } 1924 1.7.2.2 nathanw 1925 1.7.2.2 nathanw /* 1926 1.7.2.2 nathanw * Give the command to the controller. 1927 1.7.2.2 nathanw */ 1928 1.7.2.2 nathanw if ((xs->xs_control & XS_CTL_POLL) != 0) { 1929 1.7.2.2 nathanw if (mly_ccb_poll(mly, mc, xs->timeout + 5000)) { 1930 1.7.2.2 nathanw xs->error = XS_REQUEUE; 1931 1.7.2.2 nathanw if (mc->mc_length != 0) 1932 1.7.2.2 nathanw mly_ccb_unmap(mly, mc); 1933 1.7.2.2 nathanw mly_ccb_free(mly, mc); 1934 1.7.2.2 nathanw scsipi_done(xs); 1935 1.7.2.2 nathanw } 1936 1.7.2.2 nathanw } else 1937 1.7.2.2 nathanw mly_ccb_enqueue(mly, mc); 1938 1.7.2.2 nathanw 1939 1.7.2.2 nathanw break; 1940 1.7.2.2 nathanw 1941 1.7.2.2 nathanw case ADAPTER_REQ_GROW_RESOURCES: 1942 1.7.2.2 nathanw /* 1943 1.7.2.2 nathanw * Not supported. 1944 1.7.2.2 nathanw */ 1945 1.7.2.2 nathanw break; 1946 1.7.2.2 nathanw 1947 1.7.2.2 nathanw case ADAPTER_REQ_SET_XFER_MODE: 1948 1.7.2.2 nathanw /* 1949 1.7.2.2 nathanw * We can't change the transfer mode, but at least let 1950 1.7.2.2 nathanw * scsipi know what the adapter has negotiated. 1951 1.7.2.2 nathanw */ 1952 1.7.2.2 nathanw mly_get_xfer_mode(mly, chan->chan_channel, arg); 1953 1.7.2.2 nathanw break; 1954 1.7.2.2 nathanw } 1955 1.7.2.2 nathanw } 1956 1.7.2.2 nathanw 1957 1.7.2.2 nathanw /* 1958 1.7.2.2 nathanw * Handle completion of a SCSI command. 1959 1.7.2.2 nathanw */ 1960 1.7.2.2 nathanw static void 1961 1.7.2.2 nathanw mly_scsipi_complete(struct mly_softc *mly, struct mly_ccb *mc) 1962 1.7.2.2 nathanw { 1963 1.7.2.2 nathanw struct scsipi_xfer *xs; 1964 1.7.2.2 nathanw struct scsipi_channel *chan; 1965 1.7.2.2 nathanw struct scsipi_inquiry_data *inq; 1966 1.7.2.2 nathanw struct mly_btl *btl; 1967 1.7.2.2 nathanw int target, sl, s; 1968 1.7.2.2 nathanw const char *p; 1969 1.7.2.2 nathanw 1970 1.7.2.2 nathanw xs = mc->mc_private; 1971 1.7.2.2 nathanw xs->status = mc->mc_status; 1972 1.7.2.2 nathanw 1973 1.7.2.2 nathanw /* 1974 1.7.2.2 nathanw * XXX The `resid' value as returned by the controller appears to be 1975 1.7.2.2 nathanw * bogus, so we always set it to zero. Is it perhaps the transfer 1976 1.7.2.2 nathanw * count? 1977 1.7.2.2 nathanw */ 1978 1.7.2.2 nathanw xs->resid = 0; /* mc->mc_resid; */ 1979 1.7.2.2 nathanw 1980 1.7.2.2 nathanw if (mc->mc_length != 0) 1981 1.7.2.2 nathanw mly_ccb_unmap(mly, mc); 1982 1.7.2.2 nathanw 1983 1.7.2.2 nathanw switch (mc->mc_status) { 1984 1.7.2.2 nathanw case SCSI_OK: 1985 1.7.2.2 nathanw /* 1986 1.7.2.2 nathanw * In order to report logical device type and status, we 1987 1.7.2.2 nathanw * overwrite the result of the INQUIRY command to logical 1988 1.7.2.2 nathanw * devices. 1989 1.7.2.2 nathanw */ 1990 1.7.2.2 nathanw if (xs->cmd->opcode == INQUIRY) { 1991 1.7.2.2 nathanw chan = xs->xs_periph->periph_channel; 1992 1.7.2.2 nathanw target = xs->xs_periph->periph_target; 1993 1.7.2.2 nathanw btl = &mly->mly_btl[chan->chan_channel][target]; 1994 1.7.2.2 nathanw 1995 1.7.2.2 nathanw s = splbio(); 1996 1.7.2.2 nathanw if ((btl->mb_flags & MLY_BTL_LOGICAL) != 0) { 1997 1.7.2.2 nathanw inq = (struct scsipi_inquiry_data *)xs->data; 1998 1.7.2.2 nathanw mly_padstr(inq->vendor, "MYLEX", 8); 1999 1.7.2.2 nathanw p = mly_describe_code(mly_table_device_type, 2000 1.7.2.2 nathanw btl->mb_type); 2001 1.7.2.2 nathanw mly_padstr(inq->product, p, 16); 2002 1.7.2.2 nathanw p = mly_describe_code(mly_table_device_state, 2003 1.7.2.2 nathanw btl->mb_state); 2004 1.7.2.2 nathanw mly_padstr(inq->revision, p, 4); 2005 1.7.2.2 nathanw } 2006 1.7.2.2 nathanw splx(s); 2007 1.7.2.2 nathanw } 2008 1.7.2.2 nathanw 2009 1.7.2.2 nathanw xs->error = XS_NOERROR; 2010 1.7.2.2 nathanw break; 2011 1.7.2.2 nathanw 2012 1.7.2.2 nathanw case SCSI_CHECK: 2013 1.7.2.2 nathanw sl = mc->mc_sense; 2014 1.7.2.2 nathanw if (sl > sizeof(xs->sense.scsi_sense)) 2015 1.7.2.2 nathanw sl = sizeof(xs->sense.scsi_sense); 2016 1.7.2.2 nathanw memcpy(&xs->sense.scsi_sense, mc->mc_packet, sl); 2017 1.7.2.2 nathanw xs->error = XS_SENSE; 2018 1.7.2.2 nathanw break; 2019 1.7.2.2 nathanw 2020 1.7.2.2 nathanw case SCSI_BUSY: 2021 1.7.2.2 nathanw case SCSI_QUEUE_FULL: 2022 1.7.2.2 nathanw xs->error = XS_BUSY; 2023 1.7.2.2 nathanw break; 2024 1.7.2.2 nathanw 2025 1.7.2.2 nathanw default: 2026 1.7.2.2 nathanw printf("%s: unknown SCSI status 0x%x\n", 2027 1.7.2.2 nathanw mly->mly_dv.dv_xname, xs->status); 2028 1.7.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 2029 1.7.2.2 nathanw break; 2030 1.7.2.2 nathanw } 2031 1.7.2.2 nathanw 2032 1.7.2.2 nathanw mly_ccb_free(mly, mc); 2033 1.7.2.2 nathanw scsipi_done(xs); 2034 1.7.2.2 nathanw } 2035 1.7.2.2 nathanw 2036 1.7.2.2 nathanw /* 2037 1.7.2.2 nathanw * Notify scsipi about a target's transfer mode. 2038 1.7.2.2 nathanw */ 2039 1.7.2.2 nathanw static void 2040 1.7.2.2 nathanw mly_get_xfer_mode(struct mly_softc *mly, int bus, struct scsipi_xfer_mode *xm) 2041 1.7.2.2 nathanw { 2042 1.7.2.2 nathanw struct mly_btl *btl; 2043 1.7.2.2 nathanw int s; 2044 1.7.2.2 nathanw 2045 1.7.2.2 nathanw btl = &mly->mly_btl[bus][xm->xm_target]; 2046 1.7.2.2 nathanw xm->xm_mode = 0; 2047 1.7.2.2 nathanw 2048 1.7.2.2 nathanw s = splbio(); 2049 1.7.2.2 nathanw 2050 1.7.2.2 nathanw if ((btl->mb_flags & MLY_BTL_PHYSICAL) != 0) { 2051 1.7.2.2 nathanw if (btl->mb_speed == 0) { 2052 1.7.2.2 nathanw xm->xm_period = 0; 2053 1.7.2.2 nathanw xm->xm_offset = 0; 2054 1.7.2.2 nathanw } else { 2055 1.7.2.2 nathanw xm->xm_period = 12; /* XXX */ 2056 1.7.2.2 nathanw xm->xm_offset = 8; /* XXX */ 2057 1.7.2.2 nathanw xm->xm_mode |= PERIPH_CAP_SYNC; /* XXX */ 2058 1.7.2.2 nathanw } 2059 1.7.2.2 nathanw 2060 1.7.2.2 nathanw switch (btl->mb_width) { 2061 1.7.2.2 nathanw case 32: 2062 1.7.2.2 nathanw xm->xm_mode = PERIPH_CAP_WIDE32; 2063 1.7.2.2 nathanw break; 2064 1.7.2.2 nathanw case 16: 2065 1.7.2.2 nathanw xm->xm_mode = PERIPH_CAP_WIDE16; 2066 1.7.2.2 nathanw break; 2067 1.7.2.2 nathanw default: 2068 1.7.2.2 nathanw xm->xm_mode = 0; 2069 1.7.2.2 nathanw break; 2070 1.7.2.2 nathanw } 2071 1.7.2.2 nathanw } else /* ((btl->mb_flags & MLY_BTL_LOGICAL) != 0) */ { 2072 1.7.2.2 nathanw xm->xm_mode = PERIPH_CAP_WIDE16 | PERIPH_CAP_SYNC; 2073 1.7.2.2 nathanw xm->xm_period = 12; 2074 1.7.2.2 nathanw xm->xm_offset = 8; 2075 1.7.2.2 nathanw } 2076 1.7.2.2 nathanw 2077 1.7.2.2 nathanw if ((btl->mb_flags & MLY_BTL_TQING) != 0) 2078 1.7.2.2 nathanw xm->xm_mode |= PERIPH_CAP_TQING; 2079 1.7.2.2 nathanw 2080 1.7.2.2 nathanw splx(s); 2081 1.7.2.2 nathanw 2082 1.7.2.2 nathanw scsipi_async_event(&mly->mly_chans[bus], ASYNC_EVENT_XFER_MODE, xm); 2083 1.7.2.2 nathanw } 2084 1.7.2.2 nathanw 2085 1.7.2.2 nathanw /* 2086 1.7.2.2 nathanw * ioctl hook; used here only to initiate low-level rescans. 2087 1.7.2.2 nathanw */ 2088 1.7.2.2 nathanw static int 2089 1.7.2.2 nathanw mly_scsipi_ioctl(struct scsipi_channel *chan, u_long cmd, caddr_t data, 2090 1.7.2.2 nathanw int flag, struct proc *p) 2091 1.7.2.2 nathanw { 2092 1.7.2.2 nathanw struct mly_softc *mly; 2093 1.7.2.2 nathanw int rv; 2094 1.7.2.2 nathanw 2095 1.7.2.2 nathanw mly = (struct mly_softc *)chan->chan_adapter->adapt_dev; 2096 1.7.2.2 nathanw 2097 1.7.2.2 nathanw switch (cmd) { 2098 1.7.2.2 nathanw case SCBUSIOLLSCAN: 2099 1.7.2.2 nathanw mly_scan_channel(mly, chan->chan_channel); 2100 1.7.2.2 nathanw rv = 0; 2101 1.7.2.2 nathanw break; 2102 1.7.2.2 nathanw default: 2103 1.7.2.2 nathanw rv = ENOTTY; 2104 1.7.2.2 nathanw break; 2105 1.7.2.2 nathanw } 2106 1.7.2.2 nathanw 2107 1.7.2.2 nathanw return (rv); 2108 1.7.2.2 nathanw } 2109 1.7.2.2 nathanw 2110 1.7.2.2 nathanw /* 2111 1.7.2.2 nathanw * Handshake with the firmware while the card is being initialised. 2112 1.7.2.2 nathanw */ 2113 1.7.2.2 nathanw static int 2114 1.7.2.2 nathanw mly_fwhandshake(struct mly_softc *mly) 2115 1.7.2.2 nathanw { 2116 1.7.2.2 nathanw u_int8_t error, param0, param1; 2117 1.7.2.2 nathanw int spinup; 2118 1.7.2.2 nathanw 2119 1.7.2.2 nathanw spinup = 0; 2120 1.7.2.2 nathanw 2121 1.7.2.2 nathanw /* Set HM_STSACK and let the firmware initialise. */ 2122 1.7.2.2 nathanw mly_outb(mly, mly->mly_idbr, MLY_HM_STSACK); 2123 1.7.2.2 nathanw DELAY(1000); /* too short? */ 2124 1.7.2.2 nathanw 2125 1.7.2.2 nathanw /* If HM_STSACK is still true, the controller is initialising. */ 2126 1.7.2.2 nathanw if (!mly_idbr_true(mly, MLY_HM_STSACK)) 2127 1.7.2.2 nathanw return (0); 2128 1.7.2.2 nathanw 2129 1.7.2.2 nathanw printf("%s: controller initialisation started\n", 2130 1.7.2.2 nathanw mly->mly_dv.dv_xname); 2131 1.7.2.2 nathanw 2132 1.7.2.2 nathanw /* 2133 1.7.2.2 nathanw * Spin waiting for initialisation to finish, or for a message to be 2134 1.7.2.2 nathanw * delivered. 2135 1.7.2.2 nathanw */ 2136 1.7.2.2 nathanw while (mly_idbr_true(mly, MLY_HM_STSACK)) { 2137 1.7.2.2 nathanw /* Check for a message */ 2138 1.7.2.2 nathanw if (!mly_error_valid(mly)) 2139 1.7.2.2 nathanw continue; 2140 1.7.2.2 nathanw 2141 1.7.2.2 nathanw error = mly_inb(mly, mly->mly_error_status) & ~MLY_MSG_EMPTY; 2142 1.7.2.2 nathanw param0 = mly_inb(mly, mly->mly_cmd_mailbox); 2143 1.7.2.2 nathanw param1 = mly_inb(mly, mly->mly_cmd_mailbox + 1); 2144 1.7.2.2 nathanw 2145 1.7.2.2 nathanw switch (error) { 2146 1.7.2.2 nathanw case MLY_MSG_SPINUP: 2147 1.7.2.2 nathanw if (!spinup) { 2148 1.7.2.2 nathanw printf("%s: drive spinup in progress\n", 2149 1.7.2.2 nathanw mly->mly_dv.dv_xname); 2150 1.7.2.2 nathanw spinup = 1; 2151 1.7.2.2 nathanw } 2152 1.7.2.2 nathanw break; 2153 1.7.2.2 nathanw 2154 1.7.2.2 nathanw case MLY_MSG_RACE_RECOVERY_FAIL: 2155 1.7.2.2 nathanw printf("%s: mirror race recovery failed - \n", 2156 1.7.2.2 nathanw mly->mly_dv.dv_xname); 2157 1.7.2.2 nathanw printf("%s: one or more drives offline\n", 2158 1.7.2.2 nathanw mly->mly_dv.dv_xname); 2159 1.7.2.2 nathanw break; 2160 1.7.2.2 nathanw 2161 1.7.2.2 nathanw case MLY_MSG_RACE_IN_PROGRESS: 2162 1.7.2.2 nathanw printf("%s: mirror race recovery in progress\n", 2163 1.7.2.2 nathanw mly->mly_dv.dv_xname); 2164 1.7.2.2 nathanw break; 2165 1.7.2.2 nathanw 2166 1.7.2.2 nathanw case MLY_MSG_RACE_ON_CRITICAL: 2167 1.7.2.2 nathanw printf("%s: mirror race recovery on critical drive\n", 2168 1.7.2.2 nathanw mly->mly_dv.dv_xname); 2169 1.7.2.2 nathanw break; 2170 1.7.2.2 nathanw 2171 1.7.2.2 nathanw case MLY_MSG_PARITY_ERROR: 2172 1.7.2.2 nathanw printf("%s: FATAL MEMORY PARITY ERROR\n", 2173 1.7.2.2 nathanw mly->mly_dv.dv_xname); 2174 1.7.2.2 nathanw return (ENXIO); 2175 1.7.2.2 nathanw 2176 1.7.2.2 nathanw default: 2177 1.7.2.2 nathanw printf("%s: unknown initialisation code 0x%x\n", 2178 1.7.2.2 nathanw mly->mly_dv.dv_xname, error); 2179 1.7.2.2 nathanw break; 2180 1.7.2.2 nathanw } 2181 1.7.2.2 nathanw } 2182 1.7.2.2 nathanw 2183 1.7.2.2 nathanw return (0); 2184 1.7.2.2 nathanw } 2185 1.7.2.2 nathanw 2186 1.7.2.2 nathanw /* 2187 1.7.2.2 nathanw * Space-fill a character string 2188 1.7.2.2 nathanw */ 2189 1.7.2.2 nathanw static void 2190 1.7.2.2 nathanw mly_padstr(char *dst, const char *src, int len) 2191 1.7.2.2 nathanw { 2192 1.7.2.2 nathanw 2193 1.7.2.2 nathanw while (len-- > 0) { 2194 1.7.2.2 nathanw if (*src != '\0') 2195 1.7.2.2 nathanw *dst++ = *src++; 2196 1.7.2.2 nathanw else 2197 1.7.2.2 nathanw *dst++ = ' '; 2198 1.7.2.2 nathanw } 2199 1.7.2.2 nathanw } 2200 1.7.2.2 nathanw 2201 1.7.2.2 nathanw /* 2202 1.7.2.2 nathanw * Allocate DMA safe memory. 2203 1.7.2.2 nathanw */ 2204 1.7.2.2 nathanw static int 2205 1.7.2.2 nathanw mly_dmamem_alloc(struct mly_softc *mly, int size, bus_dmamap_t *dmamap, 2206 1.7.2.2 nathanw caddr_t *kva, bus_addr_t *paddr, bus_dma_segment_t *seg) 2207 1.7.2.2 nathanw { 2208 1.7.2.2 nathanw int rseg, rv, state; 2209 1.7.2.2 nathanw 2210 1.7.2.2 nathanw state = 0; 2211 1.7.2.2 nathanw 2212 1.7.2.2 nathanw if ((rv = bus_dmamem_alloc(mly->mly_dmat, size, NBPG, 0, 2213 1.7.2.2 nathanw seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 2214 1.7.2.2 nathanw printf("%s: dmamem_alloc = %d\n", mly->mly_dv.dv_xname, rv); 2215 1.7.2.2 nathanw goto bad; 2216 1.7.2.2 nathanw } 2217 1.7.2.2 nathanw 2218 1.7.2.2 nathanw state++; 2219 1.7.2.2 nathanw 2220 1.7.2.2 nathanw if ((rv = bus_dmamem_map(mly->mly_dmat, seg, 1, size, kva, 2221 1.7.2.2 nathanw BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 2222 1.7.2.2 nathanw printf("%s: dmamem_map = %d\n", mly->mly_dv.dv_xname, rv); 2223 1.7.2.2 nathanw goto bad; 2224 1.7.2.2 nathanw } 2225 1.7.2.2 nathanw 2226 1.7.2.2 nathanw state++; 2227 1.7.2.2 nathanw 2228 1.7.2.2 nathanw if ((rv = bus_dmamap_create(mly->mly_dmat, size, size, 1, 0, 2229 1.7.2.2 nathanw BUS_DMA_NOWAIT, dmamap)) != 0) { 2230 1.7.2.2 nathanw printf("%s: dmamap_create = %d\n", mly->mly_dv.dv_xname, rv); 2231 1.7.2.2 nathanw goto bad; 2232 1.7.2.2 nathanw } 2233 1.7.2.2 nathanw 2234 1.7.2.2 nathanw state++; 2235 1.7.2.2 nathanw 2236 1.7.2.2 nathanw if ((rv = bus_dmamap_load(mly->mly_dmat, *dmamap, *kva, size, 2237 1.7.2.2 nathanw NULL, BUS_DMA_NOWAIT)) != 0) { 2238 1.7.2.2 nathanw printf("%s: dmamap_load = %d\n", mly->mly_dv.dv_xname, rv); 2239 1.7.2.2 nathanw goto bad; 2240 1.7.2.2 nathanw } 2241 1.7.2.2 nathanw 2242 1.7.2.2 nathanw *paddr = (*dmamap)->dm_segs[0].ds_addr; 2243 1.7.2.2 nathanw memset(*kva, 0, size); 2244 1.7.2.2 nathanw return (0); 2245 1.7.2.2 nathanw 2246 1.7.2.2 nathanw bad: 2247 1.7.2.2 nathanw if (state > 2) 2248 1.7.2.2 nathanw bus_dmamap_destroy(mly->mly_dmat, *dmamap); 2249 1.7.2.2 nathanw if (state > 1) 2250 1.7.2.2 nathanw bus_dmamem_unmap(mly->mly_dmat, *kva, size); 2251 1.7.2.2 nathanw if (state > 0) 2252 1.7.2.2 nathanw bus_dmamem_free(mly->mly_dmat, seg, 1); 2253 1.7.2.2 nathanw 2254 1.7.2.2 nathanw return (rv); 2255 1.7.2.2 nathanw } 2256 1.7.2.2 nathanw 2257 1.7.2.2 nathanw /* 2258 1.7.2.2 nathanw * Free DMA safe memory. 2259 1.7.2.2 nathanw */ 2260 1.7.2.2 nathanw static void 2261 1.7.2.2 nathanw mly_dmamem_free(struct mly_softc *mly, int size, bus_dmamap_t dmamap, 2262 1.7.2.2 nathanw caddr_t kva, bus_dma_segment_t *seg) 2263 1.7.2.2 nathanw { 2264 1.7.2.2 nathanw 2265 1.7.2.2 nathanw bus_dmamap_unload(mly->mly_dmat, dmamap); 2266 1.7.2.2 nathanw bus_dmamap_destroy(mly->mly_dmat, dmamap); 2267 1.7.2.2 nathanw bus_dmamem_unmap(mly->mly_dmat, kva, size); 2268 1.7.2.2 nathanw bus_dmamem_free(mly->mly_dmat, seg, 1); 2269 1.7.2.2 nathanw } 2270 1.7.2.2 nathanw 2271 1.7.2.2 nathanw 2272 1.7.2.2 nathanw /* 2273 1.7.2.2 nathanw * Accept an open operation on the control device. 2274 1.7.2.2 nathanw */ 2275 1.7.2.2 nathanw int 2276 1.7.2.2 nathanw mlyopen(dev_t dev, int flag, int mode, struct proc *p) 2277 1.7.2.2 nathanw { 2278 1.7.2.2 nathanw struct mly_softc *mly; 2279 1.7.2.2 nathanw 2280 1.7.2.2 nathanw if ((mly = device_lookup(&mly_cd, minor(dev))) == NULL) 2281 1.7.2.2 nathanw return (ENXIO); 2282 1.7.2.2 nathanw if ((mly->mly_state & MLY_STATE_INITOK) == 0) 2283 1.7.2.2 nathanw return (ENXIO); 2284 1.7.2.2 nathanw if ((mly->mly_state & MLY_STATE_OPEN) != 0) 2285 1.7.2.2 nathanw return (EBUSY); 2286 1.7.2.2 nathanw 2287 1.7.2.2 nathanw mly->mly_state |= MLY_STATE_OPEN; 2288 1.7.2.2 nathanw return (0); 2289 1.7.2.2 nathanw } 2290 1.7.2.2 nathanw 2291 1.7.2.2 nathanw /* 2292 1.7.2.2 nathanw * Accept the last close on the control device. 2293 1.7.2.2 nathanw */ 2294 1.7.2.2 nathanw int 2295 1.7.2.2 nathanw mlyclose(dev_t dev, int flag, int mode, struct proc *p) 2296 1.7.2.2 nathanw { 2297 1.7.2.2 nathanw struct mly_softc *mly; 2298 1.7.2.2 nathanw 2299 1.7.2.2 nathanw mly = device_lookup(&mly_cd, minor(dev)); 2300 1.7.2.2 nathanw mly->mly_state &= ~MLY_STATE_OPEN; 2301 1.7.2.2 nathanw return (0); 2302 1.7.2.2 nathanw } 2303 1.7.2.2 nathanw 2304 1.7.2.2 nathanw /* 2305 1.7.2.2 nathanw * Handle control operations. 2306 1.7.2.2 nathanw */ 2307 1.7.2.2 nathanw int 2308 1.7.2.2 nathanw mlyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 2309 1.7.2.2 nathanw { 2310 1.7.2.2 nathanw struct mly_softc *mly; 2311 1.7.2.2 nathanw int rv; 2312 1.7.2.2 nathanw 2313 1.7.2.2 nathanw if (securelevel >= 2) 2314 1.7.2.2 nathanw return (EPERM); 2315 1.7.2.2 nathanw 2316 1.7.2.2 nathanw mly = device_lookup(&mly_cd, minor(dev)); 2317 1.7.2.2 nathanw 2318 1.7.2.2 nathanw switch (cmd) { 2319 1.7.2.2 nathanw case MLYIO_COMMAND: 2320 1.7.2.2 nathanw rv = mly_user_command(mly, (void *)data); 2321 1.7.2.2 nathanw break; 2322 1.7.2.2 nathanw case MLYIO_HEALTH: 2323 1.7.2.2 nathanw rv = mly_user_health(mly, (void *)data); 2324 1.7.2.2 nathanw break; 2325 1.7.2.2 nathanw default: 2326 1.7.2.2 nathanw rv = ENOTTY; 2327 1.7.2.2 nathanw break; 2328 1.7.2.2 nathanw } 2329 1.7.2.2 nathanw 2330 1.7.2.2 nathanw return (rv); 2331 1.7.2.2 nathanw } 2332 1.7.2.2 nathanw 2333 1.7.2.2 nathanw /* 2334 1.7.2.2 nathanw * Execute a command passed in from userspace. 2335 1.7.2.2 nathanw * 2336 1.7.2.2 nathanw * The control structure contains the actual command for the controller, as 2337 1.7.2.2 nathanw * well as the user-space data pointer and data size, and an optional sense 2338 1.7.2.2 nathanw * buffer size/pointer. On completion, the data size is adjusted to the 2339 1.7.2.2 nathanw * command residual, and the sense buffer size to the size of the returned 2340 1.7.2.2 nathanw * sense data. 2341 1.7.2.2 nathanw */ 2342 1.7.2.2 nathanw static int 2343 1.7.2.2 nathanw mly_user_command(struct mly_softc *mly, struct mly_user_command *uc) 2344 1.7.2.2 nathanw { 2345 1.7.2.2 nathanw struct mly_ccb *mc; 2346 1.7.2.2 nathanw int rv, mapped; 2347 1.7.2.2 nathanw 2348 1.7.2.2 nathanw if ((rv = mly_ccb_alloc(mly, &mc)) != 0) 2349 1.7.2.2 nathanw return (rv); 2350 1.7.2.2 nathanw 2351 1.7.2.2 nathanw mapped = 0; 2352 1.7.2.2 nathanw mc->mc_data = NULL; 2353 1.7.2.2 nathanw 2354 1.7.2.2 nathanw /* 2355 1.7.2.2 nathanw * Handle data size/direction. 2356 1.7.2.2 nathanw */ 2357 1.7.2.2 nathanw if ((mc->mc_length = abs(uc->DataTransferLength)) != 0) { 2358 1.7.2.2 nathanw if (mc->mc_length > MAXPHYS) { 2359 1.7.2.2 nathanw rv = EINVAL; 2360 1.7.2.2 nathanw goto out; 2361 1.7.2.2 nathanw } 2362 1.7.2.2 nathanw 2363 1.7.2.2 nathanw mc->mc_data = malloc(mc->mc_length, M_DEVBUF, M_WAITOK); 2364 1.7.2.2 nathanw if (mc->mc_data == NULL) { 2365 1.7.2.2 nathanw rv = ENOMEM; 2366 1.7.2.2 nathanw goto out; 2367 1.7.2.2 nathanw } 2368 1.7.2.2 nathanw 2369 1.7.2.2 nathanw if (uc->DataTransferLength > 0) { 2370 1.7.2.2 nathanw mc->mc_flags |= MLY_CCB_DATAIN; 2371 1.7.2.2 nathanw memset(mc->mc_data, 0, mc->mc_length); 2372 1.7.2.2 nathanw } 2373 1.7.2.2 nathanw 2374 1.7.2.2 nathanw if (uc->DataTransferLength < 0) { 2375 1.7.2.2 nathanw mc->mc_flags |= MLY_CCB_DATAOUT; 2376 1.7.2.2 nathanw rv = copyin(uc->DataTransferBuffer, mc->mc_data, 2377 1.7.2.2 nathanw mc->mc_length); 2378 1.7.2.2 nathanw if (rv != 0) 2379 1.7.2.2 nathanw goto out; 2380 1.7.2.2 nathanw } 2381 1.7.2.2 nathanw 2382 1.7.2.2 nathanw if ((rv = mly_ccb_map(mly, mc)) != 0) 2383 1.7.2.2 nathanw goto out; 2384 1.7.2.2 nathanw mapped = 1; 2385 1.7.2.2 nathanw } 2386 1.7.2.2 nathanw 2387 1.7.2.2 nathanw /* Copy in the command and execute it. */ 2388 1.7.2.2 nathanw memcpy(mc->mc_packet, &uc->CommandMailbox, sizeof(uc->CommandMailbox)); 2389 1.7.2.2 nathanw 2390 1.7.2.2 nathanw if ((rv = mly_ccb_wait(mly, mc, 60000)) != 0) 2391 1.7.2.2 nathanw goto out; 2392 1.7.2.2 nathanw 2393 1.7.2.2 nathanw /* Return the data to userspace. */ 2394 1.7.2.2 nathanw if (uc->DataTransferLength > 0) { 2395 1.7.2.2 nathanw rv = copyout(mc->mc_data, uc->DataTransferBuffer, 2396 1.7.2.2 nathanw mc->mc_length); 2397 1.7.2.2 nathanw if (rv != 0) 2398 1.7.2.2 nathanw goto out; 2399 1.7.2.2 nathanw } 2400 1.7.2.2 nathanw 2401 1.7.2.2 nathanw /* Return the sense buffer to userspace. */ 2402 1.7.2.2 nathanw if (uc->RequestSenseLength > 0 && mc->mc_sense > 0) { 2403 1.7.2.2 nathanw rv = copyout(mc->mc_packet, uc->RequestSenseBuffer, 2404 1.7.2.2 nathanw min(uc->RequestSenseLength, mc->mc_sense)); 2405 1.7.2.2 nathanw if (rv != 0) 2406 1.7.2.2 nathanw goto out; 2407 1.7.2.2 nathanw } 2408 1.7.2.2 nathanw 2409 1.7.2.2 nathanw /* Return command results to userspace (caller will copy out). */ 2410 1.7.2.2 nathanw uc->DataTransferLength = mc->mc_resid; 2411 1.7.2.2 nathanw uc->RequestSenseLength = min(uc->RequestSenseLength, mc->mc_sense); 2412 1.7.2.2 nathanw uc->CommandStatus = mc->mc_status; 2413 1.7.2.2 nathanw rv = 0; 2414 1.7.2.2 nathanw 2415 1.7.2.2 nathanw out: 2416 1.7.2.2 nathanw if (mapped) 2417 1.7.2.2 nathanw mly_ccb_unmap(mly, mc); 2418 1.7.2.2 nathanw if (mc->mc_data != NULL) 2419 1.7.2.2 nathanw free(mc->mc_data, M_DEVBUF); 2420 1.7.2.2 nathanw if (mc != NULL) 2421 1.7.2.2 nathanw mly_ccb_free(mly, mc); 2422 1.7.2.2 nathanw 2423 1.7.2.2 nathanw return (rv); 2424 1.7.2.2 nathanw } 2425 1.7.2.2 nathanw 2426 1.7.2.2 nathanw /* 2427 1.7.2.2 nathanw * Return health status to userspace. If the health change index in the 2428 1.7.2.2 nathanw * user structure does not match that currently exported by the controller, 2429 1.7.2.2 nathanw * we return the current status immediately. Otherwise, we block until 2430 1.7.2.2 nathanw * either interrupted or new status is delivered. 2431 1.7.2.2 nathanw */ 2432 1.7.2.2 nathanw static int 2433 1.7.2.2 nathanw mly_user_health(struct mly_softc *mly, struct mly_user_health *uh) 2434 1.7.2.2 nathanw { 2435 1.7.2.2 nathanw struct mly_health_status mh; 2436 1.7.2.2 nathanw int rv, s; 2437 1.7.2.2 nathanw 2438 1.7.2.2 nathanw /* Fetch the current health status from userspace. */ 2439 1.7.2.2 nathanw rv = copyin(uh->HealthStatusBuffer, &mh, sizeof(mh)); 2440 1.7.2.2 nathanw if (rv != 0) 2441 1.7.2.2 nathanw return (rv); 2442 1.7.2.2 nathanw 2443 1.7.2.2 nathanw /* spin waiting for a status update */ 2444 1.7.2.2 nathanw s = splbio(); 2445 1.7.2.2 nathanw if (mly->mly_event_change == mh.change_counter) 2446 1.7.2.2 nathanw rv = tsleep(&mly->mly_event_change, PRIBIO | PCATCH, 2447 1.7.2.2 nathanw "mlyhealth", 0); 2448 1.7.2.2 nathanw splx(s); 2449 1.7.2.2 nathanw 2450 1.7.2.2 nathanw if (rv == 0) { 2451 1.7.2.2 nathanw /* 2452 1.7.2.2 nathanw * Copy the controller's health status buffer out (there is 2453 1.7.2.2 nathanw * a race here if it changes again). 2454 1.7.2.2 nathanw */ 2455 1.7.2.2 nathanw rv = copyout(&mly->mly_mmbox->mmm_health.status, 2456 1.7.2.2 nathanw uh->HealthStatusBuffer, sizeof(uh->HealthStatusBuffer)); 2457 1.7.2.2 nathanw } 2458 1.7.2.2 nathanw 2459 1.7.2.2 nathanw return (rv); 2460 1.7.2.2 nathanw } 2461
Indexes created Mon Oct 13 05:10:05 GMT 2025