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mlyreg.h revision 1.1.32.1
      1  1.1.32.1  kent /*	$NetBSD: mlyreg.h,v 1.1.32.1 2005/04/29 11:29:07 kent Exp $	*/
      2       1.1    ad 
      3       1.1    ad /*-
      4       1.1    ad  * Copyright (c) 2001 The NetBSD Foundation, Inc.
      5       1.1    ad  * All rights reserved.
      6       1.1    ad  *
      7       1.1    ad  * This code is derived from software contributed to The NetBSD Foundation
      8       1.1    ad  * by Andrew Doran, Thor Lancelot Simon, and Eric Haszlakiewicz.
      9       1.1    ad  *
     10       1.1    ad  * Redistribution and use in source and binary forms, with or without
     11       1.1    ad  * modification, are permitted provided that the following conditions
     12       1.1    ad  * are met:
     13       1.1    ad  * 1. Redistributions of source code must retain the above copyright
     14       1.1    ad  *    notice, this list of conditions and the following disclaimer.
     15       1.1    ad  * 2. Redistributions in binary form must reproduce the above copyright
     16       1.1    ad  *    notice, this list of conditions and the following disclaimer in the
     17       1.1    ad  *    documentation and/or other materials provided with the distribution.
     18       1.1    ad  * 3. All advertising materials mentioning features or use of this software
     19       1.1    ad  *    must display the following acknowledgement:
     20       1.1    ad  *        This product includes software developed by the NetBSD
     21       1.1    ad  *        Foundation, Inc. and its contributors.
     22       1.1    ad  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23       1.1    ad  *    contributors may be used to endorse or promote products derived
     24       1.1    ad  *    from this software without specific prior written permission.
     25       1.1    ad  *
     26       1.1    ad  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27       1.1    ad  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28       1.1    ad  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29       1.1    ad  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30       1.1    ad  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31       1.1    ad  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32       1.1    ad  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33       1.1    ad  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34       1.1    ad  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35       1.1    ad  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36       1.1    ad  * POSSIBILITY OF SUCH DAMAGE.
     37       1.1    ad  */
     38       1.1    ad 
     39       1.1    ad /*-
     40       1.1    ad  * Copyright (c) 2000 Michael Smith
     41       1.1    ad  * Copyright (c) 2000 BSDi
     42       1.1    ad  * All rights reserved.
     43       1.1    ad  *
     44       1.1    ad  * Redistribution and use in source and binary forms, with or without
     45       1.1    ad  * modification, are permitted provided that the following conditions
     46       1.1    ad  * are met:
     47       1.1    ad  * 1. Redistributions of source code must retain the above copyright
     48       1.1    ad  *    notice, this list of conditions and the following disclaimer.
     49       1.1    ad  * 2. Redistributions in binary form must reproduce the above copyright
     50       1.1    ad  *    notice, this list of conditions and the following disclaimer in the
     51       1.1    ad  *    documentation and/or other materials provided with the distribution.
     52       1.1    ad  *
     53       1.1    ad  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     54       1.1    ad  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     55       1.1    ad  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     56       1.1    ad  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     57       1.1    ad  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     58       1.1    ad  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     59       1.1    ad  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     60       1.1    ad  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     61       1.1    ad  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     62       1.1    ad  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     63       1.1    ad  * SUCH DAMAGE.
     64       1.1    ad  *
     65       1.1    ad  * from FreeBSD: mlyreg.h,v 1.1 2000/08/23 03:22:39 msmith Exp
     66       1.1    ad  */
     67       1.1    ad 
     68       1.1    ad /*
     69       1.1    ad  * Section numbers in this document refer to the Mylex "Firmware Software Interface"
     70       1.1    ad  * document ('FSI'), revision 0.11 04/11/00 unless otherwise qualified.
     71       1.1    ad  *
     72       1.1    ad  * Reference is made to the Mylex "Programming Guide for 6.x Controllers" document
     73       1.1    ad  * ('PG6'), document #771242 revision 0.02, 04/11/00
     74       1.1    ad  *
     75       1.1    ad  * Note that fields marked N/A are not supported by the PCI controllers, but are
     76       1.1    ad  * defined here to hold place in datastructures that are shared with the SCSI
     77       1.1    ad  * controllers.  Items not relevant to PCI controllers are not described here.
     78       1.1    ad  *
     79       1.1    ad  * Ordering of items in this file is a little odd due to the constraints of
     80       1.1    ad  * nested declarations.
     81       1.1    ad  */
     82       1.1    ad 
     83       1.1    ad #ifndef _PCI_MLYREG_H_
     84       1.1    ad #define	_PCI_MLYREG_H_
     85       1.1    ad 
     86       1.1    ad /*
     87       1.1    ad  * 2.1 (Scatter Gather List Format)
     88       1.1    ad  */
     89       1.1    ad struct mly_sg_entry {
     90       1.1    ad 	u_int64_t	physaddr;
     91       1.1    ad 	u_int64_t	length;
     92       1.1    ad } __attribute__ ((__packed__));
     93       1.1    ad 
     94       1.1    ad /*
     95       1.1    ad  * 5.2 System Device Access
     96       1.1    ad  *
     97       1.1    ad  * This is corroborated by the layout of the MDACIOCTL_GETCONTROLLERINFO data
     98       1.1    ad  * in 21.8
     99       1.1    ad  */
    100       1.1    ad #define	MLY_MAX_CHANNELS	6
    101       1.1    ad #define	MLY_MAX_TARGETS		16
    102       1.1    ad #define	MLY_MAX_LUNS		1
    103       1.1    ad 
    104       1.1    ad /*
    105       1.1    ad  * 8.1 Different Device States
    106       1.1    ad  */
    107       1.1    ad #define	MLY_DEVICE_STATE_OFFLINE	0x08	/* DEAD/OFFLINE */
    108       1.1    ad #define	MLY_DEVICE_STATE_UNCONFIGURED	0x00
    109       1.1    ad #define	MLY_DEVICE_STATE_ONLINE		0x01
    110       1.1    ad #define	MLY_DEVICE_STATE_CRITICAL	0x09
    111       1.1    ad #define	MLY_DEVICE_STATE_WRITEONLY	0x03
    112       1.1    ad #define	MLY_DEVICE_STATE_STANDBY	0x21
    113       1.1    ad #define	MLY_DEVICE_STATE_MISSING	0x04	/* or-ed with (ONLINE or WRITEONLY or STANDBY) */
    114       1.1    ad 
    115       1.1    ad /*
    116       1.1    ad  * 8.2 Device Type Field definitions
    117       1.1    ad  */
    118       1.1    ad #define	MLY_DEVICE_TYPE_RAID0		0x0	/* RAID 0 */
    119       1.1    ad #define	MLY_DEVICE_TYPE_RAID1		0x1	/* RAID 1 */
    120       1.1    ad #define	MLY_DEVICE_TYPE_RAID3		0x3	/* RAID 3 right asymmetric parity */
    121       1.1    ad #define	MLY_DEVICE_TYPE_RAID5		0x5	/* RAID 5 right asymmetric parity */
    122       1.1    ad #define	MLY_DEVICE_TYPE_RAID6		0x6	/* RAID 6 (Mylex RAID 6) */
    123       1.1    ad #define	MLY_DEVICE_TYPE_RAID7		0x7	/* RAID 7 (JBOD) */
    124       1.1    ad #define	MLY_DEVICE_TYPE_NEWSPAN		0x8	/* New Mylex SPAN */
    125       1.1    ad #define	MLY_DEVICE_TYPE_RAID3F		0x9	/* RAID 3 fixed parity */
    126       1.1    ad #define	MLY_DEVICE_TYPE_RAID3L		0xb	/* RAID 3 left symmetric parity */
    127       1.1    ad #define	MLY_DEVICE_TYPE_SPAN		0xc	/* current spanning implementation */
    128       1.1    ad #define	MLY_DEVICE_TYPE_RAID5L		0xd	/* RAID 5 left symmetric parity */
    129       1.1    ad #define	MLY_DEVICE_TYPE_RAIDE		0xe	/* RAID E (concatenation) */
    130       1.1    ad #define	MLY_DEVICE_TYPE_PHYSICAL	0xf	/* physical device */
    131       1.1    ad 
    132       1.1    ad /*
    133       1.1    ad  * 8.3 Stripe Size
    134       1.1    ad  */
    135       1.1    ad #define	MLY_STRIPE_ZERO		0x0	/* no stripe (RAID 1, RAID 7, etc) */
    136       1.1    ad #define	MLY_STRIPE_512b		0x1
    137       1.1    ad #define	MLY_STRIPE_1k		0x2
    138       1.1    ad #define	MLY_STRIPE_2k		0x3
    139       1.1    ad #define	MLY_STRIPE_4k		0x4
    140       1.1    ad #define	MLY_STRIPE_8k		0x5
    141       1.1    ad #define	MLY_STRIPE_16k		0x6
    142       1.1    ad #define	MLY_STRIPE_32k		0x7
    143       1.1    ad #define	MLY_STRIPE_64k		0x8
    144       1.1    ad #define	MLY_STRIPE_128k		0x9
    145       1.1    ad #define	MLY_STRIPE_256k		0xa
    146       1.1    ad #define	MLY_STRIPE_512k		0xb
    147       1.1    ad #define	MLY_STRIPE_1m		0xc
    148       1.1    ad 
    149       1.1    ad /*
    150       1.1    ad  * 8.4 Cacheline Size
    151       1.1    ad  */
    152       1.1    ad #define	MLY_CACHELINE_ZERO	0x0	/* caching cannot be enabled */
    153       1.1    ad #define	MLY_CACHELINE_512b	0x1
    154       1.1    ad #define	MLY_CACHELINE_1k	0x2
    155       1.1    ad #define	MLY_CACHELINE_2k	0x3
    156       1.1    ad #define	MLY_CACHELINE_4k	0x4
    157       1.1    ad #define	MLY_CACHELINE_8k	0x5
    158       1.1    ad #define	MLY_CACHELINE_16k	0x6
    159       1.1    ad #define	MLY_CACHELINE_32k	0x7
    160       1.1    ad #define	MLY_CACHELINE_64k	0x8
    161       1.1    ad 
    162       1.1    ad /*
    163       1.1    ad  * 8.5 Read/Write control
    164       1.1    ad  */
    165       1.1    ad #define	MLY_RWCtl_INITTED	(1<<7)	/* if set, the logical device is initialised */
    166       1.1    ad 			/* write control */
    167       1.1    ad #define	MLY_RWCtl_WCD		(0)	/* write cache disabled */
    168       1.1    ad #define	MLY_RWCtl_WDISABLE	(1<<3)	/* writing disabled */
    169       1.1    ad #define	MLY_RWCtl_WCE		(2<<3)	/* write cache enabled */
    170       1.1    ad #define	MLY_RWCtl_IWCE		(3<<3)	/* intelligent write cache enabled */
    171       1.1    ad 			/* read control */
    172       1.1    ad #define	MLY_RWCtl_RCD		(0)	/* read cache is disabled */
    173       1.1    ad #define	MLY_RWCtl_RCE		(1)	/* read cache enabled */
    174       1.1    ad #define	MLY_RWCtl_RAHEAD	(2)	/* readahead enabled */
    175       1.1    ad #define	MLY_RWCtl_IRAHEAD	(3)	/* intelligent readahead enabled */
    176       1.1    ad 
    177       1.1    ad /*
    178       1.1    ad  * 9.0 LUN Map Format
    179       1.1    ad  */
    180       1.1    ad struct mly_lun_map {
    181       1.1    ad 	u_int8_t	res1:4;
    182       1.1    ad 	u_int8_t	host_port_mapped:1;	/* this system drive visibile to host on this controller/port combination */
    183       1.1    ad 	u_int8_t	tid_valid:1;		/* target ID valid */
    184       1.1    ad 	u_int8_t	hid_valid:1;		/* host ID valid */
    185       1.1    ad 	u_int8_t	lun_valid:1;		/* LUN valid */
    186       1.1    ad 	u_int8_t	res2;
    187       1.1    ad 	u_int8_t	lun;			/* LUN */
    188       1.1    ad 	u_int8_t	tid;			/* TID */
    189       1.1    ad 	u_int8_t	hid[32];		/* HID (one bit for each host) */
    190       1.1    ad } __attribute__ ((__packed__));
    191       1.1    ad 
    192       1.1    ad /*
    193       1.1    ad  * 10.1 Controller Parameters
    194       1.1    ad  */
    195       1.1    ad struct mly_param_controller {
    196       1.1    ad 	u_int8_t	rdahen:1;				/* N/A */
    197       1.1    ad 	u_int8_t	bilodly:1;				/* N/A */
    198       1.1    ad 	u_int8_t   	fua_disable:1;
    199       1.1    ad 	u_int8_t	reass1s:1;				/* N/A */
    200       1.1    ad 	u_int8_t	truvrfy:1;				/* N/A */
    201       1.1    ad 	u_int8_t	dwtvrfy:1;				/* N/A */
    202       1.1    ad 	u_int8_t	background_initialisation:1;
    203       1.1    ad 	u_int8_t	clustering:1;				/* N/A */
    204       1.1    ad 
    205       1.1    ad 	u_int8_t	bios_disable:1;
    206       1.1    ad 	u_int8_t   	boot_from_cdrom:1;
    207       1.1    ad 	u_int8_t	drive_coercion:1;
    208       1.1    ad 	u_int8_t	write_same_disable:1;
    209       1.1    ad 	u_int8_t	hba_mode:1;				/* N/A */
    210       1.1    ad 	u_int8_t	bios_geometry:2;
    211       1.1    ad #define	MLY_BIOSGEOM_2G	0x0
    212       1.1    ad #define	MLY_BIOSGEOM_8G	0x1
    213       1.1    ad 	u_int8_t	res1:1;					/* N/A */
    214       1.1    ad 
    215       1.1    ad 	u_int8_t	res2[2];				/* N/A */
    216       1.1    ad 
    217       1.1    ad 	u_int8_t	v_dec:1;
    218       1.1    ad 	u_int8_t	safte:1;				/* N/A */
    219       1.1    ad 	u_int8_t	ses:1;					/* N/A */
    220       1.1    ad 	u_int8_t	res3:2;					/* N/A */
    221       1.1    ad 	u_int8_t	v_arm:1;
    222       1.1    ad 	u_int8_t	v_ofm:1;
    223       1.1    ad 	u_int8_t	res4:1;					/* N/A */
    224       1.1    ad 
    225       1.1    ad 	u_int8_t	rebuild_check_rate;
    226       1.1    ad 	u_int8_t	cache_line_size;			/* see 8.4 */
    227       1.1    ad 	u_int8_t	oem_code;
    228       1.1    ad #define	MLY_OEM_MYLEX	0x00
    229       1.1    ad #define	MLY_OEM_IBM	0x08
    230       1.1    ad #define	MLY_OEM_HP	0x0a
    231       1.1    ad #define	MLY_OEM_DEC	0x0c
    232       1.1    ad #define	MLY_OEM_SIEMENS	0x10
    233       1.1    ad #define	MLY_OEM_INTEL	0x12
    234       1.1    ad 	u_int8_t	spinup_mode;
    235       1.1    ad #define	MLY_SPIN_AUTO		0
    236       1.1    ad #define	MLY_SPIN_PWRSPIN	1
    237       1.1    ad #define	MLY_SPIN_WSSUSPIN	2
    238       1.1    ad 	u_int8_t	spinup_devices;
    239       1.1    ad 	u_int8_t	spinup_interval;
    240       1.1    ad 	u_int8_t	spinup_wait_time;
    241       1.1    ad 
    242       1.1    ad 	u_int8_t	res5:3;					/* N/A */
    243       1.1    ad 	u_int8_t	vutursns:1;				/* N/A */
    244       1.1    ad 	u_int8_t	dccfil:1;				/* N/A */
    245       1.1    ad 	u_int8_t	nopause:1;				/* N/A */
    246       1.1    ad 	u_int8_t	disqfull:1;				/* N/A */
    247       1.1    ad 	u_int8_t	disbusy:1;				/* N/A */
    248       1.1    ad 
    249       1.1    ad 	u_int8_t	res6:2;					/* N/A */
    250       1.1    ad 	u_int8_t	failover_node_name;			/* N/A */
    251       1.1    ad 	u_int8_t	res7:1;					/* N/A */
    252       1.1    ad 	u_int8_t	ftopo:3;				/* N/A */
    253       1.1    ad 	u_int8_t	disable_ups:1;				/* N/A */
    254       1.1    ad 
    255       1.1    ad 	u_int8_t	res8:1;					/* N/A */
    256       1.1    ad 	u_int8_t	propagate_reset:1;			/* N/A */
    257       1.1    ad 	u_int8_t	nonstd_mp_reset:1;			/* N/A */
    258       1.1    ad 	u_int8_t	res9:5;					/* N/A */
    259       1.1    ad 
    260       1.1    ad 	u_int8_t	res10;					/* N/A */
    261       1.1    ad 	u_int8_t	serial_port_baud_rate;			/* N/A */
    262       1.1    ad 	u_int8_t	serial_port_control;			/* N/A */
    263       1.1    ad 	u_int8_t	change_stripe_ok_developer_flag_only;	/* N/A */
    264       1.1    ad 
    265       1.1    ad 	u_int8_t	small_large_host_transfers:2;		/* N/A */
    266       1.1    ad 	u_int8_t	frame_control:2;			/* N/A */
    267       1.1    ad 	u_int8_t	pci_latency_control:2;			/* N/A */
    268       1.1    ad 	u_int8_t	treat_lip_as_reset:1;			/* N/A */
    269       1.1    ad 	u_int8_t	res11:1;				/* N/A */
    270       1.1    ad 
    271       1.1    ad 	u_int8_t	ms_autorest:1;				/* N/A */
    272       1.1    ad 	u_int8_t	res12:7;				/* N/A */
    273       1.1    ad 
    274       1.1    ad 	u_int8_t	ms_aa_fsim:1;				/* N/A */
    275       1.1    ad 	u_int8_t	ms_aa_ccach:1;				/* N/A */
    276       1.1    ad 	u_int8_t	ms_aa_fault_signals:1;			/* N/A */
    277       1.1    ad 	u_int8_t	ms_aa_c4_faults:1;			/* N/A */
    278       1.1    ad 	u_int8_t	ms_aa_host_reset_delay_mask:4;		/* N/A */
    279       1.1    ad 
    280       1.1    ad 	u_int8_t	ms_flg_simplex_no_rstcom:1;		/* N/A */
    281       1.1    ad 	u_int8_t	res13:7;				/* N/A */
    282       1.1    ad 
    283       1.1    ad 	u_int8_t	res14;					/* N/A */
    284       1.1    ad 	u_int8_t	hardloopid[2][2];			/* N/A */
    285       1.1    ad 	u_int8_t	ctrlname[2][16+1];			/* N/A */
    286       1.1    ad 	u_int8_t	initiator_id;
    287       1.1    ad 	u_int8_t	startup_option;
    288       1.1    ad #define	MLY_STARTUP_IF_NO_CHANGE	0x0
    289       1.1    ad #define	MLY_STARTUP_IF_NO_LUN_CHANGE	0x1
    290       1.1    ad #define	MLY_STARTUP_IF_NO_LUN_OFFLINE	0x2
    291       1.1    ad #define	MLY_STARTUP_IF_LUN0_NO_CHANGE	0x3
    292       1.1    ad #define	MLY_STARTUP_IF_LUN0_NOT_OFFLINE	0x4
    293       1.1    ad #define	MLY_STARTUP_ALWAYS		0x5
    294       1.1    ad 
    295       1.1    ad 	u_int8_t	res15[62];
    296       1.1    ad } __attribute__ ((__packed__));
    297       1.1    ad 
    298       1.1    ad /*
    299       1.1    ad  * 10.2 Physical Device Parameters
    300       1.1    ad  */
    301       1.1    ad struct mly_param_physical_device {
    302       1.1    ad 	u_int16_t	tags;
    303       1.1    ad 	u_int16_t	speed;
    304       1.1    ad 	u_int8_t	width;
    305       1.1    ad 	u_int8_t	combing:1;
    306       1.1    ad 	u_int8_t	res1:7;
    307       1.1    ad 	u_int8_t	res2[3];
    308       1.1    ad } __attribute__ ((__packed__));
    309       1.1    ad 
    310       1.1    ad /*
    311       1.1    ad  * 10.3 Logical Device Parameters
    312       1.1    ad  */
    313       1.1    ad struct mly_param_logical_device {
    314       1.1    ad 	u_int8_t	type;			/* see 8.2 */
    315       1.1    ad 	u_int8_t	state;			/* see 8.1 */
    316       1.1    ad 	u_int16_t	raid_device;
    317       1.1    ad 	u_int8_t	res1;
    318       1.1    ad 	u_int8_t	bios_geometry;		/* BIOS control word? */
    319       1.1    ad 	u_int8_t	stripe_size;		/* see 8.3 */
    320       1.1    ad 	u_int8_t	read_write_control;	/* see 8.5 */
    321       1.1    ad 	u_int8_t	res2[8];
    322       1.1    ad } __attribute__ ((__packed__));
    323       1.1    ad 
    324       1.1    ad /*
    325       1.1    ad  * 12.3 Health Status Buffer
    326       1.1    ad  *
    327       1.1    ad  * Pad to 128 bytes.
    328       1.1    ad  */
    329       1.1    ad struct mly_health_status {
    330       1.1    ad 	u_int32_t	uptime_us;				/* N/A */
    331       1.1    ad 	u_int32_t	uptime_ms;				/* N/A */
    332       1.1    ad 	u_int32_t	realtime;				/* N/A */
    333       1.1    ad 	u_int32_t	res1;					/* N/A */
    334       1.1    ad 	u_int32_t	change_counter;
    335       1.1    ad 	u_int32_t	res2;					/* N/A */
    336       1.1    ad 	u_int32_t	debug_message_index;			/* N/A */
    337       1.1    ad 	u_int32_t	bios_message_index;			/* N/A */
    338       1.1    ad 	u_int32_t	trace_page;				/* N/A */
    339       1.1    ad 	u_int32_t	profiler_page;				/* N/A */
    340       1.1    ad 	u_int32_t	next_event;
    341       1.1    ad 	u_int8_t	res3[4 + 16 + 64];			/* N/A */
    342       1.1    ad } __attribute__ ((__packed__));
    343       1.1    ad 
    344       1.1    ad /*
    345       1.1    ad  * 14.2 Timeout Bit Format
    346       1.1    ad  */
    347       1.1    ad #define	MLY_TIMEOUT_SECONDS	0x00
    348       1.1    ad #define	MLY_TIMEOUT_MINUTES	0x40
    349       1.1    ad #define	MLY_TIMEOUT_HOURS	0x80
    350       1.1    ad 
    351       1.1    ad /*
    352       1.1    ad  * 14.3 Operation Device
    353       1.1    ad  */
    354       1.1    ad #define	MLY_OPDEVICE_PHYSICAL_DEVICE		0x0
    355       1.1    ad #define	MLY_OPDEVICE_RAID_DEVICE		0x1
    356       1.1    ad #define	MLY_OPDEVICE_PHYSICAL_CHANNEL		0x2
    357       1.1    ad #define	MLY_OPDEVICE_RAID_CHANNEL		0x3
    358       1.1    ad #define	MLY_OPDEVICE_PHYSICAL_CONTROLLER	0x4
    359       1.1    ad #define	MLY_OPDEVICE_RAID_CONTROLLER		0x5
    360       1.1    ad #define	MLY_OPDEVICE_CONFIGURATION_GROUP	0x10
    361       1.1    ad 
    362       1.1    ad /*
    363       1.1    ad  * 14.4 Status Bit Format
    364       1.1    ad  *
    365       1.1    ad  * AKA Status Mailbox Format
    366       1.1    ad  *
    367       1.1    ad  * XXX format conflict between FSI and PG6 over the ordering of the
    368       1.1    ad  * status and sense length fields.
    369       1.1    ad  */
    370       1.1    ad struct mly_status {
    371       1.1    ad 	u_int16_t	command_id;
    372       1.1    ad 	u_int8_t	status;
    373       1.1    ad 	u_int8_t	sense_length;
    374       1.1    ad 	int32_t		residue;
    375       1.1    ad } __attribute__ ((__packed__));
    376       1.1    ad 
    377       1.1    ad /*
    378       1.1    ad  * 14.5 Command Control Bit (CCB) format
    379       1.1    ad  *
    380       1.1    ad  * This byte is unfortunately named.
    381       1.1    ad  */
    382       1.1    ad #define	MLY_CMDCTL_FORCE_UNIT_ACCESS	0x01
    383       1.1    ad #define	MLY_CMDCTL_DISABLE_PAGE_OUT	0x02
    384       1.1    ad #define	MLY_CMDCTL_EXTENDED_SG_TABLE	0x08
    385       1.1    ad #define	MLY_CMDCTL_DATA_DIRECTION	0x10
    386       1.1    ad #define	MLY_CMDCTL_NO_AUTO_SENSE	0x40
    387       1.1    ad #define	MLY_CMDCTL_DISABLE_DISCONNECT	0x80
    388       1.1    ad 
    389       1.1    ad /*
    390       1.1    ad  * 15.0 Commands
    391       1.1    ad  *
    392       1.1    ad  * We use the command names as given by Mylex
    393       1.1    ad  */
    394       1.1    ad #define	MDACMD_MEMCOPY		0x1	/* memory to memory copy */
    395       1.1    ad #define	MDACMD_SCSIPT		0x2	/* SCSI passthrough (small command) */
    396       1.1    ad #define	MDACMD_SCSILCPT		0x3	/* SCSI passthrough (large command) */
    397       1.1    ad #define	MDACMD_SCSI		0x4	/* SCSI command for logical/phyiscal device (small command) */
    398       1.1    ad #define	MDACMD_SCSILC		0x5	/* SCSI command for logical/phyiscal device (large command) */
    399       1.1    ad #define	MDACMD_IOCTL		0x20	/* Management command */
    400       1.1    ad #define	MDACMD_IOCTLCHECK	0x23	/* Validate management command (not implemented) */
    401       1.1    ad 
    402       1.1    ad /*
    403       1.1    ad  * 16.0 IOCTL command
    404       1.1    ad  *
    405       1.1    ad  * We use the IOCTL names as given by Mylex
    406       1.1    ad  * Note that only ioctls supported by the PCI controller family are listed
    407       1.1    ad  */
    408       1.1    ad #define	MDACIOCTL_GETCONTROLLERINFO		0x1
    409       1.1    ad #define	MDACIOCTL_GETLOGDEVINFOVALID		0x3
    410       1.1    ad #define	MDACIOCTL_GETPHYSDEVINFOVALID		0x5
    411       1.1    ad #define	MDACIOCTL_GETCONTROLLERSTATISTICS	0xb
    412       1.1    ad #define	MDACIOCTL_GETLOGDEVSTATISTICS		0xd
    413       1.1    ad #define	MDACIOCTL_GETPHYSDEVSTATISTICS		0xf
    414       1.1    ad #define	MDACIOCTL_GETHEALTHSTATUS		0x11
    415       1.1    ad #define	MDACIOCTL_GETEVENT			0x15
    416       1.1    ad /* flash update */
    417       1.1    ad #define	MDACIOCTL_STOREIMAGE			0x2c
    418       1.1    ad #define	MDACIOCTL_READIMAGE			0x2d
    419       1.1    ad #define	MDACIOCTL_FLASHIMAGES			0x2e
    420       1.1    ad /* battery backup unit */
    421       1.1    ad #define	MDACIOCTL_GET_SUBSYSTEM_DATA		0x70
    422       1.1    ad #define	MDACIOCTL_SET_SUBSYSTEM_DATA		0x71
    423       1.1    ad /* non-data commands */
    424       1.1    ad #define	MDACIOCTL_STARTDISOCVERY		0x81
    425       1.1    ad #define	MDACIOCTL_SETRAIDDEVSTATE		0x82
    426       1.1    ad #define	MDACIOCTL_INITPHYSDEVSTART		0x84
    427       1.1    ad #define	MDACIOCTL_INITPHYSDEVSTOP		0x85
    428       1.1    ad #define	MDACIOCTL_INITRAIDDEVSTART		0x86
    429       1.1    ad #define	MDACIOCTL_INITRAIDDEVSTOP		0x87
    430       1.1    ad #define	MDACIOCTL_REBUILDRAIDDEVSTART		0x88
    431       1.1    ad #define	MDACIOCTL_REBUILDRAIDDEVSTOP		0x89
    432       1.1    ad #define	MDACIOCTL_MAKECONSISTENTDATASTART	0x8a
    433       1.1    ad #define	MDACIOCTL_MAKECONSISTENTDATASTOP	0x8b
    434       1.1    ad #define	MDACIOCTL_CONSISTENCYCHECKSTART		0x8c
    435       1.1    ad #define	MDACIOCTL_CONSISTENCYCHECKSTOP		0x8d
    436       1.1    ad #define	MDACIOCTL_SETMEMORYMAILBOX		0x8e
    437       1.1    ad #define	MDACIOCTL_RESETDEVICE			0x90
    438       1.1    ad #define	MDACIOCTL_FLUSHDEVICEDATA		0x91
    439       1.1    ad #define	MDACIOCTL_PAUSEDEVICE			0x92
    440       1.1    ad #define	MDACIOCTL_UNPAUSEDEVICE			0x93
    441       1.1    ad #define	MDACIOCTL_LOCATEDEVICE			0x94
    442       1.1    ad #define	MDACIOCTL_SETMASTERSLAVEMODE		0x95
    443       1.1    ad #define	MDACIOCTL_SETREALTIMECLOCK		0xac
    444       1.1    ad /* RAID configuration */
    445       1.1    ad #define	MDACIOCTL_CREATENEWCONF			0xc0
    446       1.1    ad #define	MDACIOCTL_DELETERAIDDEV			0xc1
    447       1.1    ad #define	MDACIOCTL_REPLACEINTERNALDEV		0xc2
    448       1.1    ad #define	MDACIOCTL_RENAMERAIDDEV			0xc3
    449       1.1    ad #define	MDACIOCTL_ADDNEWCONF			0xc4
    450       1.1    ad #define	MDACIOCTL_XLATEPHYSDEVTORAIDDEV		0xc5
    451       1.1    ad #define	MDACIOCTL_MORE				0xc6
    452       1.1    ad #define	MDACIOCTL_SETPHYSDEVPARAMETER		0xc8
    453       1.1    ad #define	MDACIOCTL_GETPHYSDEVPARAMETER		0xc9
    454       1.1    ad #define	MDACIOCTL_CLEARCONF			0xca
    455       1.1    ad #define	MDACIOCTL_GETDEVCONFINFO		0xcb
    456       1.1    ad #define	MDACIOCTL_GETGROUPCONFINFO		0xcc
    457       1.1    ad #define	MDACIOCTL_GETFREESPACELIST		0xcd
    458       1.1    ad #define	MDACIOCTL_GETLOGDEVPARAMETER		0xce
    459       1.1    ad #define	MDACIOCTL_SETLOGDEVPARAMETER		0xcf
    460       1.1    ad #define	MDACIOCTL_GETCONTROLLERPARAMETER	0xd0
    461       1.1    ad #define	MDACIOCTL_SETCONTRLLERPARAMETER		0xd1
    462       1.1    ad #define	MDACIOCTL_CLEARCONFSUSPMODE		0xd2
    463       1.1    ad #define	MDACIOCTL_GETBDT_FOR_SYSDRIVE		0xe0
    464       1.1    ad 
    465       1.1    ad /*
    466       1.1    ad  * 17.1.4 Data Transfer Memory Address Without SG List
    467       1.1    ad  */
    468       1.1    ad struct mly_short_transfer {
    469       1.1    ad 	struct mly_sg_entry	sg[2];
    470       1.1    ad } __attribute__ ((__packed__));
    471       1.1    ad 
    472       1.1    ad /*
    473       1.1    ad  * 17.1.5 Data Transfer Memory Address With SG List
    474       1.1    ad  *
    475       1.1    ad  * Note that only the first s/g table is currently used.
    476       1.1    ad  */
    477       1.1    ad struct mly_sg_transfer {
    478       1.1    ad 	u_int16_t	entries[3];
    479       1.1    ad 	u_int16_t	res1;
    480       1.1    ad 	u_int64_t	table_physaddr[3];
    481       1.1    ad } __attribute__ ((__packed__));
    482       1.1    ad 
    483       1.1    ad /*
    484       1.1    ad  * 17.1.3 Data Transfer Memory Address Format
    485       1.1    ad  */
    486       1.1    ad union mly_cmd_transfer {
    487       1.1    ad 	struct mly_short_transfer	direct;
    488       1.1    ad 	struct mly_sg_transfer	indirect;
    489       1.1    ad };
    490       1.1    ad 
    491       1.1    ad /*
    492       1.1    ad  * 21.1  MDACIOCTL_SETREALTIMECLOCK
    493       1.1    ad  * 21.7  MDACIOCTL_GETHEALTHSTATUS
    494       1.1    ad  * 21.8  MDACIOCTL_GETCONTROLLERINFO
    495       1.1    ad  * 21.9  MDACIOCTL_GETLOGDEVINFOVALID
    496       1.1    ad  * 21.10 MDACIOCTL_GETPHYSDEVINFOVALID
    497       1.1    ad  * 21.11 MDACIOCTL_GETPHYSDEVSTATISTICS
    498       1.1    ad  * 21.12 MDACIOCTL_GETLOGDEVSTATISTICS
    499       1.1    ad  * 21.13 MDACIOCTL_GETCONTROLLERSTATISTICS
    500       1.1    ad  * 21.27 MDACIOCTL_GETBDT_FOR_SYSDRIVE
    501       1.1    ad  * 23.4  MDACIOCTL_CREATENEWCONF
    502       1.1    ad  * 23.5  MDACIOCTL_ADDNEWCONF
    503       1.1    ad  * 23.8  MDACIOCTL_GETDEVCONFINFO
    504       1.1    ad  * 23.9  MDACIOCTL_GETFREESPACELIST
    505       1.1    ad  * 24.1  MDACIOCTL_MORE
    506       1.1    ad  * 25.1  MDACIOCTL_GETPHYSDEVPARAMETER
    507       1.1    ad  * 25.2  MDACIOCTL_SETPHYSDEVPARAMETER
    508       1.1    ad  * 25.3  MDACIOCTL_GETLOGDEVPARAMETER
    509       1.1    ad  * 25.4  MDACIOCTL_SETLOGDEVPARAMETER
    510       1.1    ad  * 25.5  MDACIOCTL_GETCONTROLLERPARAMETER
    511       1.1    ad  * 25.6  MDACIOCTL_SETCONTROLLERPARAMETER
    512       1.1    ad  *
    513       1.1    ad  * These commands just transfer data
    514       1.1    ad  */
    515       1.1    ad struct mly_ioctl_param_data {
    516       1.1    ad 	u_int8_t	param[10];
    517       1.1    ad 	union mly_cmd_transfer	transfer;
    518       1.1    ad } __attribute__ ((__packed__));
    519       1.1    ad 
    520       1.1    ad /*
    521       1.1    ad  * 21.2 MDACIOCTL_SETMEMORYMAILBOX
    522       1.1    ad  */
    523       1.1    ad struct mly_ioctl_param_setmemorymailbox {
    524       1.1    ad 	u_int8_t	health_buffer_size;
    525       1.1    ad 	u_int8_t	res1;
    526       1.1    ad 	u_int64_t	health_buffer_physaddr;
    527       1.1    ad 	u_int64_t	command_mailbox_physaddr;
    528       1.1    ad 	u_int64_t	status_mailbox_physaddr;
    529       1.1    ad 	u_int64_t	res2[2];
    530       1.1    ad } __attribute__ ((__packed__));
    531       1.1    ad 
    532       1.1    ad /*
    533       1.1    ad  * 21.8.2 MDACIOCTL_GETCONTROLLERINFO: Data Format
    534       1.1    ad  */
    535       1.1    ad struct mly_ioctl_getcontrollerinfo {
    536       1.1    ad 	u_int8_t	res1;					/* N/A */
    537       1.1    ad 	u_int8_t	interface_type;
    538       1.1    ad 	u_int8_t	controller_type;
    539       1.1    ad 	u_int8_t	res2;					/* N/A */
    540       1.1    ad 	u_int16_t	interface_speed;
    541       1.1    ad 	u_int8_t	interface_width;
    542       1.1    ad 	u_int8_t	res3[9];				/* N/A */
    543       1.1    ad 	char		interface_name[16];
    544       1.1    ad 	char		controller_name[16];
    545       1.1    ad 	u_int8_t	res4[16];				/* N/A */
    546       1.1    ad 	/* firmware release information */
    547       1.1    ad 	u_int8_t	fw_major;
    548       1.1    ad 	u_int8_t	fw_minor;
    549       1.1    ad 	u_int8_t	fw_turn;
    550       1.1    ad 	u_int8_t	fw_build;
    551       1.1    ad 	u_int8_t	fw_day;
    552       1.1    ad 	u_int8_t	fw_month;
    553       1.1    ad 	u_int8_t	fw_century;
    554       1.1    ad 	u_int8_t	fw_year;
    555       1.1    ad 	/* hardware release information */
    556       1.1    ad 	u_int8_t	hw_revision;				/* N/A */
    557       1.1    ad 	u_int8_t	res5[3];				/* N/A */
    558       1.1    ad 	u_int8_t	hw_release_day;				/* N/A */
    559       1.1    ad 	u_int8_t	hw_release_month;			/* N/A */
    560       1.1    ad 	u_int8_t	hw_release_century;			/* N/A */
    561       1.1    ad 	u_int8_t	hw_release_year;			/* N/A */
    562       1.1    ad 	/* hardware manufacturing information */
    563       1.1    ad 	u_int8_t	batch_number;				/* N/A */
    564       1.1    ad 	u_int8_t	res6;					/* N/A */
    565       1.1    ad 	u_int8_t	plant_number;
    566       1.1    ad 	u_int8_t	res7;
    567       1.1    ad 	u_int8_t	hw_manuf_day;
    568       1.1    ad 	u_int8_t	hw_manuf_month;
    569       1.1    ad 	u_int8_t	hw_manuf_century;
    570       1.1    ad 	u_int8_t	hw_manuf_year;
    571       1.1    ad 	u_int8_t	max_pdd_per_xldd;
    572       1.1    ad 	u_int8_t	max_ildd_per_xldd;
    573       1.1    ad 	u_int16_t	nvram_size;
    574       1.1    ad 	u_int8_t	max_number_of_xld;			/* N/A */
    575       1.1    ad 	u_int8_t	res8[3];				/* N/A */
    576       1.1    ad 	/* unique information per controller */
    577       1.1    ad 	char		serial_number[16];
    578       1.1    ad 	u_int8_t	res9[16];				/* N/A */
    579       1.1    ad 	/* vendor information */
    580       1.1    ad 	u_int8_t	res10[3];				/* N/A */
    581       1.1    ad 	u_int8_t	oem_information;
    582       1.1    ad 	char		vendor_name[16];			/* N/A */
    583       1.1    ad 	/* other physical/controller/operation information */
    584       1.1    ad 	u_int8_t	bbu_present:1;
    585       1.1    ad 	u_int8_t	active_clustering:1;
    586       1.1    ad 	u_int8_t	res11:6;				/* N/A */
    587       1.1    ad 	u_int8_t	res12[3];				/* N/A */
    588       1.1    ad 	/* physical device scan information */
    589       1.1    ad 	u_int8_t	physical_scan_active:1;
    590       1.1    ad 	u_int8_t	res13:7;				/* N/A */
    591       1.1    ad 	u_int8_t	physical_scan_channel;
    592       1.1    ad 	u_int8_t	physical_scan_target;
    593       1.1    ad 	u_int8_t	physical_scan_lun;
    594       1.1    ad 	/* maximum command data transfer size */
    595       1.1    ad 	u_int16_t	maximum_block_count;
    596       1.1    ad 	u_int16_t	maximum_sg_entries;
    597       1.1    ad 	/* logical/physical device counts */
    598       1.1    ad 	u_int16_t	logical_devices_present;
    599       1.1    ad 	u_int16_t	logical_devices_critical;
    600       1.1    ad 	u_int16_t	logical_devices_offline;
    601       1.1    ad 	u_int16_t	physical_devices_present;
    602       1.1    ad 	u_int16_t	physical_disks_present;
    603       1.1    ad 	u_int16_t	physical_disks_critical;		/* N/A */
    604       1.1    ad 	u_int16_t	physical_disks_offline;
    605       1.1    ad 	u_int16_t	maximum_parallel_commands;
    606       1.1    ad 	/* channel and target ID information */
    607       1.1    ad 	u_int8_t	physical_channels_present;
    608       1.1    ad 	u_int8_t	virtual_channels_present;
    609       1.1    ad 	u_int8_t	physical_channels_possible;
    610       1.1    ad 	u_int8_t	virtual_channels_possible;
    611       1.1    ad 	u_int8_t	maximum_targets_possible[16];		/* N/A (6 and up) */
    612       1.1    ad 	u_int8_t	res14[12];				/* N/A */
    613       1.1    ad 	/* memory/cache information */
    614       1.1    ad 	u_int16_t	memory_size;
    615       1.1    ad 	u_int16_t	cache_size;
    616       1.1    ad 	u_int32_t	valid_cache_size;			/* N/A */
    617       1.1    ad 	u_int32_t	dirty_cache_size;			/* N/A */
    618       1.1    ad 	u_int16_t	memory_speed;
    619       1.1    ad 	u_int8_t	memory_width;
    620       1.1    ad 	u_int8_t	memory_type:5;
    621       1.1    ad 	u_int8_t	res15:1;				/* N/A */
    622       1.1    ad 	u_int8_t	memory_parity:1;
    623       1.1    ad 	u_int8_t	memory_ecc:1;
    624       1.1    ad 	char		memory_information[16];			/* N/A */
    625       1.1    ad 	/* execution memory information */
    626       1.1    ad 	u_int16_t	exmemory_size;
    627       1.1    ad 	u_int16_t	l2cache_size;				/* N/A */
    628       1.1    ad 	u_int8_t	res16[8];				/* N/A */
    629       1.1    ad 	u_int16_t	exmemory_speed;
    630       1.1    ad 	u_int8_t	exmemory_width;
    631       1.1    ad 	u_int8_t	exmemory_type:5;
    632       1.1    ad 	u_int8_t	res17:1;				/* N/A */
    633       1.1    ad 	u_int8_t	exmemory_parity:1;
    634       1.1    ad 	u_int8_t	exmemory_ecc:1;
    635       1.1    ad 	char		exmemory_name[16];			/* N/A */
    636       1.1    ad 	/* CPU information */
    637       1.1    ad 	struct {
    638       1.1    ad 		u_int16_t	speed;
    639       1.1    ad 		u_int8_t	type;
    640       1.1    ad 		u_int8_t	number;
    641       1.1    ad 		u_int8_t	res1[12];			/* N/A */
    642       1.1    ad 		char		name[16];			/* N/A */
    643       1.1    ad 	} cpu[2] __attribute__ ((__packed__));
    644       1.1    ad 	/* debugging/profiling/command time tracing information */
    645       1.1    ad 	u_int16_t	profiling_page;				/* N/A */
    646       1.1    ad 	u_int16_t	profiling_programs;			/* N/A */
    647       1.1    ad 	u_int16_t	time_trace_page;			/* N/A */
    648       1.1    ad 	u_int16_t	time_trace_programs;			/* N/A */
    649       1.1    ad 	u_int8_t	res18[8];				/* N/A */
    650       1.1    ad 	/* error counters on physical devices */
    651       1.1    ad 	u_int16_t	physical_device_bus_resets;		/* N/A */
    652       1.1    ad 	u_int16_t	physical_device_parity_errors;		/* N/A */
    653       1.1    ad 	u_int16_t	physical_device_soft_errors;		/* N/A */
    654       1.1    ad 	u_int16_t	physical_device_commands_failed;	/* N/A */
    655       1.1    ad 	u_int16_t	physical_device_miscellaneous_errors;	/* N/A */
    656       1.1    ad 	u_int16_t	physical_device_command_timeouts;	/* N/A */
    657       1.1    ad 	u_int16_t	physical_device_selection_timeouts;	/* N/A */
    658       1.1    ad 	u_int16_t	physical_device_retries;		/* N/A */
    659       1.1    ad 	u_int16_t	physical_device_aborts;			/* N/A */
    660       1.1    ad 	u_int16_t	physical_device_host_command_aborts;	/* N/A */
    661       1.1    ad 	u_int16_t	physical_device_PFAs_detected;		/* N/A */
    662       1.1    ad 	u_int16_t	physical_device_host_commands_failed;	/* N/A */
    663       1.1    ad 	u_int8_t	res19[8];				/* N/A */
    664       1.1    ad 	/* error counters on logical devices */
    665       1.1    ad 	u_int16_t	logical_device_soft_errors;		/* N/A */
    666       1.1    ad 	u_int16_t	logical_device_commands_failed;		/* N/A */
    667       1.1    ad 	u_int16_t	logical_device_host_command_aborts;	/* N/A */
    668       1.1    ad 	u_int16_t	res20;					/* N/A */
    669       1.1    ad 	/* error counters on controller */
    670       1.1    ad 	u_int16_t	controller_parity_ecc_errors;
    671       1.1    ad 	u_int16_t	controller_host_command_aborts;		/* N/A */
    672       1.1    ad 	u_int8_t	res21[4];				/* N/A */
    673       1.1    ad 	/* long duration activity information */
    674       1.1    ad 	u_int16_t	background_inits_active;
    675       1.1    ad 	u_int16_t	logical_inits_active;
    676       1.1    ad 	u_int16_t	physical_inits_active;
    677       1.1    ad 	u_int16_t	consistency_checks_active;
    678       1.1    ad 	u_int16_t	rebuilds_active;
    679       1.1    ad 	u_int16_t	MORE_active;
    680       1.1    ad 	u_int16_t	patrol_active;				/* N/A */
    681       1.1    ad 	u_int8_t	long_operation_status;			/* N/A */
    682       1.1    ad 	u_int8_t	res22;					/* N/A */
    683       1.1    ad 	/* flash ROM information */
    684       1.1    ad 	u_int8_t	flash_type;				/* N/A */
    685       1.1    ad 	u_int8_t	res23;					/* N/A */
    686       1.1    ad 	u_int16_t	flash_size;
    687       1.1    ad 	u_int32_t	flash_maximum_age;
    688       1.1    ad 	u_int32_t	flash_age;
    689       1.1    ad 	u_int8_t	res24[4];				/* N/A */
    690       1.1    ad 	char		flash_name[16];				/* N/A */
    691       1.1    ad 	/* firmware runtime information */
    692       1.1    ad 	u_int8_t	rebuild_rate;
    693       1.1    ad 	u_int8_t	background_init_rate;
    694       1.1    ad 	u_int8_t	init_rate;
    695       1.1    ad 	u_int8_t	consistency_check_rate;
    696       1.1    ad 	u_int8_t	res25[4];				/* N/A */
    697       1.1    ad 	u_int32_t	maximum_dp;
    698       1.1    ad 	u_int32_t	free_dp;
    699       1.1    ad 	u_int32_t	maximum_iop;
    700       1.1    ad 	u_int32_t	free_iop;
    701       1.1    ad 	u_int16_t	maximum_comb_length;
    702       1.1    ad 	u_int16_t	maximum_configuration_groups;
    703       1.1    ad 	u_int8_t	installation_abort:1;
    704       1.1    ad 	u_int8_t	maintenance:1;
    705       1.1    ad 	u_int8_t	res26:6;				/* N/A */
    706       1.1    ad 	u_int8_t	res27[3];				/* N/A */
    707       1.1    ad 	u_int8_t	res28[32 + 512];			/* N/A */
    708       1.1    ad } __attribute__ ((__packed__));
    709       1.1    ad 
    710       1.1    ad /*
    711       1.1    ad  * 21.9.2 MDACIOCTL_GETLOGDEVINFOVALID
    712       1.1    ad  */
    713       1.1    ad struct mly_ioctl_getlogdevinfovalid {
    714       1.1    ad 	u_int8_t	res1;					/* N/A */
    715       1.1    ad 	u_int8_t	channel;
    716       1.1    ad 	u_int8_t	target;
    717       1.1    ad 	u_int8_t	lun;
    718       1.1    ad 	u_int8_t	state;					/* see 8.1 */
    719       1.1    ad 	u_int8_t	raid_level;				/* see 8.2 */
    720       1.1    ad 	u_int8_t	stripe_size;				/* see 8.3 */
    721       1.1    ad 	u_int8_t	cache_line_size;			/* see 8.4 */
    722       1.1    ad 	u_int8_t	read_write_control;			/* see 8.5 */
    723       1.1    ad 	u_int8_t	consistency_check:1;
    724       1.1    ad 	u_int8_t	rebuild:1;
    725       1.1    ad 	u_int8_t	make_consistent:1;
    726       1.1    ad 	u_int8_t	initialisation:1;
    727       1.1    ad 	u_int8_t	migration:1;
    728       1.1    ad 	u_int8_t	patrol:1;
    729       1.1    ad 	u_int8_t	res2:2;					/* N/A */
    730       1.1    ad 	u_int8_t	ar5_limit;
    731       1.1    ad 	u_int8_t	ar5_algo;
    732       1.1    ad 	u_int16_t	logical_device_number;
    733       1.1    ad 	u_int16_t	bios_control;
    734       1.1    ad 	/* erorr counters */
    735       1.1    ad 	u_int16_t	soft_errors;				/* N/A */
    736       1.1    ad 	u_int16_t	commands_failed;			/* N/A */
    737       1.1    ad 	u_int16_t	host_command_aborts;			/* N/A */
    738       1.1    ad 	u_int16_t	deferred_write_errors;			/* N/A */
    739       1.1    ad 	u_int8_t	res3[8];				/* N/A */
    740       1.1    ad 	/* device size information */
    741       1.1    ad 	u_int8_t	res4[2];				/* N/A */
    742       1.1    ad 	u_int16_t	device_block_size;
    743       1.1    ad 	u_int32_t	original_device_size;			/* N/A */
    744       1.1    ad 	u_int32_t	device_size;		/* XXX "blocks or MB" Huh? */
    745       1.1    ad 	u_int8_t	res5[4];				/* N/A */
    746       1.1    ad 	char		device_name[32];			/* N/A */
    747       1.1    ad 	u_int8_t	inquiry[36];
    748       1.1    ad 	u_int8_t	res6[12];				/* N/A */
    749       1.1    ad 	u_int64_t	last_read_block;			/* N/A */
    750       1.1    ad 	u_int64_t	last_written_block;			/* N/A */
    751       1.1    ad 	u_int64_t	consistency_check_block;
    752       1.1    ad 	u_int64_t	rebuild_block;
    753       1.1    ad 	u_int64_t	make_consistent_block;
    754       1.1    ad 	u_int64_t	initialisation_block;
    755       1.1    ad 	u_int64_t	migration_block;
    756       1.1    ad 	u_int64_t	patrol_block;				/* N/A */
    757       1.1    ad 	u_int8_t	res7[64];				/* N/A */
    758       1.1    ad } __attribute__ ((__packed__));
    759       1.1    ad 
    760       1.1    ad /*
    761       1.1    ad  * 21.10.2 MDACIOCTL_GETPHYSDEVINFOVALID: Data Format
    762       1.1    ad  */
    763       1.1    ad struct mly_ioctl_getphysdevinfovalid {
    764       1.1    ad 	u_int8_t	res1;
    765       1.1    ad 	u_int8_t	channel;
    766       1.1    ad 	u_int8_t	target;
    767       1.1    ad 	u_int8_t	lun;
    768       1.1    ad 	u_int8_t	raid_ft:1;			/* configuration status */
    769       1.1    ad 	u_int8_t	res2:1;					/* N/A */
    770       1.1    ad 	u_int8_t	local:1;
    771       1.1    ad 	u_int8_t	res3:5;
    772       1.1    ad 	u_int8_t	host_dead:1;			/* multiple host/controller status *//* N/A */
    773       1.1    ad 	u_int8_t	host_connection_dead:1;			/* N/A */
    774       1.1    ad 	u_int8_t	res4:6;					/* N/A */
    775       1.1    ad 	u_int8_t	state;				/* see 8.1 */
    776       1.1    ad 	u_int8_t	width;
    777       1.1    ad 	u_int16_t	speed;
    778       1.1    ad 	/* multiported physical device information */
    779       1.1    ad 	u_int8_t	ports_available;			/* N/A */
    780       1.1    ad 	u_int8_t	ports_inuse;				/* N/A */
    781       1.1    ad 	u_int8_t	res5[4];
    782       1.1    ad 	u_int8_t	ether_address[16];			/* N/A */
    783       1.1    ad 	u_int16_t	command_tags;
    784       1.1    ad 	u_int8_t	consistency_check:1;			/* N/A */
    785       1.1    ad 	u_int8_t	rebuild:1;				/* N/A */
    786       1.1    ad 	u_int8_t	make_consistent:1;			/* N/A */
    787       1.1    ad 	u_int8_t	initialisation:1;
    788       1.1    ad 	u_int8_t	migration:1;				/* N/A */
    789       1.1    ad 	u_int8_t	patrol:1;				/* N/A */
    790       1.1    ad 	u_int8_t	res6:2;
    791       1.1    ad 	u_int8_t	long_operation_status;			/* N/A */
    792       1.1    ad 	u_int8_t	parity_errors;
    793       1.1    ad 	u_int8_t	soft_errors;
    794       1.1    ad 	u_int8_t	hard_errors;
    795       1.1    ad 	u_int8_t	miscellaneous_errors;
    796       1.1    ad 	u_int8_t	command_timeouts;			/* N/A */
    797       1.1    ad 	u_int8_t	retries;				/* N/A */
    798       1.1    ad 	u_int8_t	aborts;					/* N/A */
    799       1.1    ad 	u_int8_t	PFAs_detected;				/* N/A */
    800       1.1    ad 	u_int8_t	res7[6];
    801       1.1    ad 	u_int16_t	block_size;
    802       1.1    ad 	u_int32_t	original_device_size;		/* XXX "blocks or MB" Huh? */
    803       1.1    ad 	u_int32_t	device_size;			/* XXX "blocks or MB" Huh? */
    804       1.1    ad 	u_int8_t	res8[4];
    805       1.1    ad 	char		name[16];				/* N/A */
    806       1.1    ad 	u_int8_t	res9[16 + 32];
    807       1.1    ad 	u_int8_t	inquiry[36];
    808       1.1    ad 	u_int8_t	res10[12 + 16];
    809       1.1    ad 	u_int64_t	last_read_block;			/* N/A */
    810       1.1    ad 	u_int64_t	last_written_block;			/* N/A */
    811       1.1    ad 	u_int64_t	consistency_check_block;		/* N/A */
    812       1.1    ad 	u_int64_t	rebuild_block;				/* N/A */
    813       1.1    ad 	u_int64_t	make_consistent_block;			/* N/A */
    814       1.1    ad 	u_int64_t	initialisation_block;			/* N/A */
    815       1.1    ad 	u_int64_t	migration_block;			/* N/A */
    816       1.1    ad 	u_int64_t	patrol_block;				/* N/A */
    817       1.1    ad 	u_int8_t	res11[256];
    818       1.1    ad } __attribute__ ((__packed__));
    819       1.1    ad 
    820       1.1    ad union mly_devinfo {
    821       1.1    ad 	struct mly_ioctl_getlogdevinfovalid	logdev;
    822       1.1    ad 	struct mly_ioctl_getphysdevinfovalid	physdev;
    823       1.1    ad };
    824       1.1    ad 
    825       1.1    ad /*
    826       1.1    ad  * 21.11.2 MDACIOCTL_GETPHYSDEVSTATISTICS: Data Format
    827       1.1    ad  * 21.12.2 MDACIOCTL_GETLOGDEVSTATISTICS: Data Format
    828       1.1    ad  */
    829       1.1    ad struct mly_ioctl_getdevstatistics {
    830       1.1    ad 	u_int32_t	uptime_ms;			/* getphysedevstatistics only */
    831       1.1    ad 	u_int8_t	res1[5];				/* N/A */
    832       1.1    ad 	u_int8_t	channel;
    833       1.1    ad 	u_int8_t	target;
    834       1.1    ad 	u_int8_t	lun;
    835       1.1    ad 	u_int16_t	raid_device;			/* getlogdevstatistics only */
    836       1.1    ad 	u_int8_t	res2[2];				/* N/A */
    837       1.1    ad 	/* total read/write performance including cache data */
    838       1.1    ad 	u_int32_t	total_reads;
    839       1.1    ad 	u_int32_t	total_writes;
    840       1.1    ad 	u_int32_t	total_read_size;
    841       1.1    ad 	u_int32_t	total_write_size;
    842       1.1    ad 	/* cache read/write performance */
    843       1.1    ad 	u_int32_t	cache_reads;				/* N/A */
    844       1.1    ad 	u_int32_t	cache_writes;				/* N/A */
    845       1.1    ad 	u_int32_t	cache_read_size;			/* N/A */
    846       1.1    ad 	u_int32_t	cache_write_size;			/* N/A */
    847       1.1    ad 	/* commands active/wait information */
    848       1.1    ad 	u_int32_t	command_waits_done;			/* N/A */
    849       1.1    ad 	u_int16_t	active_commands;			/* N/A */
    850       1.1    ad 	u_int16_t	waiting_commands;			/* N/A */
    851       1.1    ad 	u_int8_t	res3[8];				/* N/A */
    852       1.1    ad } __attribute__ ((__packed__));
    853       1.1    ad 
    854       1.1    ad /*
    855       1.1    ad  * 21.13.2 MDACIOCTL_GETCONTROLLERSTATISTICS: Data Format
    856       1.1    ad  */
    857       1.1    ad struct mly_ioctl_getcontrollerstatistics {
    858       1.1    ad 	u_int32_t	uptime_ms;				/* N/A */
    859       1.1    ad 	u_int8_t	res1[12];				/* N/A */
    860       1.1    ad 	/* target physical device performance data information */
    861       1.1    ad 	u_int32_t	target_physical_device_interrupts;	/* N/A */
    862       1.1    ad 	u_int32_t	target_physical_device_stray_interrupts;/* N/A */
    863       1.1    ad 	u_int8_t	res2[8];				/* N/A */
    864       1.1    ad 	u_int32_t	target_physical_device_reads;		/* N/A */
    865       1.1    ad 	u_int32_t	target_physical_device_writes;		/* N/A */
    866       1.1    ad 	u_int32_t	target_physical_device_read_size;	/* N/A */
    867       1.1    ad 	u_int32_t	target_physical_device_write_size;	/* N/A */
    868       1.1    ad 	/* host system performance data information */
    869       1.1    ad 	u_int32_t	host_system_interrupts;			/* N/A */
    870       1.1    ad 	u_int32_t	host_system_stray_interrupts;		/* N/A */
    871       1.1    ad 	u_int32_t	host_system_sent_interrupts;		/* N/A */
    872       1.1    ad 	u_int8_t	res3[4];				/* N/A */
    873       1.1    ad 	u_int32_t	physical_device_reads;			/* N/A */
    874       1.1    ad 	u_int32_t	physical_device_writes;			/* N/A */
    875       1.1    ad 	u_int32_t	physical_device_read_size;		/* N/A */
    876       1.1    ad 	u_int32_t	physical_device_write_size;		/* N/A */
    877       1.1    ad 	u_int32_t	physical_device_cache_reads;		/* N/A */
    878       1.1    ad 	u_int32_t	physical_device_cache_writes;		/* N/A */
    879       1.1    ad 	u_int32_t	physical_device_cache_read_size;	/* N/A */
    880       1.1    ad 	u_int32_t	physical_device_cache_write_size;	/* N/A */
    881       1.1    ad 	u_int32_t	logical_device_reads;			/* N/A */
    882       1.1    ad 	u_int32_t	logical_device_writes;			/* N/A */
    883       1.1    ad 	u_int32_t	logical_device_read_size;		/* N/A */
    884       1.1    ad 	u_int32_t	logical_device_write_size;		/* N/A */
    885       1.1    ad 	u_int32_t	logical_device_cache_reads;		/* N/A */
    886       1.1    ad 	u_int32_t	logical_device_cache_writes;		/* N/A */
    887       1.1    ad 	u_int32_t	logical_device_cache_read_size;		/* N/A */
    888       1.1    ad 	u_int32_t	logical_device_cache_write_size;	/* N/A */
    889       1.1    ad 	u_int16_t	target_physical_device_commands_active;	/* N/A */
    890       1.1    ad 	u_int16_t	target_physical_device_commands_waiting;/* N/A */
    891       1.1    ad 	u_int16_t	host_system_commands_active;		/* N/A */
    892       1.1    ad 	u_int16_t	host_system_commands_waiting;		/* N/A */
    893       1.1    ad 	u_int8_t	res4[48 + 64];				/* N/A */
    894       1.1    ad } __attribute__ ((__packed__));
    895       1.1    ad 
    896       1.1    ad /*
    897       1.1    ad  * 21.2 MDACIOCTL_SETRAIDDEVSTATE
    898       1.1    ad  */
    899       1.1    ad struct mly_ioctl_param_setraiddevstate {
    900       1.1    ad 	u_int8_t	state;
    901       1.1    ad } __attribute__ ((__packed__));
    902       1.1    ad 
    903       1.1    ad /*
    904       1.1    ad  * 21.27.2 MDACIOCTL_GETBDT_FOR_SYSDRIVE: Data Format
    905       1.1    ad  */
    906       1.1    ad #define	MLY_MAX_BDT_ENTRIES	1022
    907       1.1    ad struct mly_ioctl_getbdt_for_sysdrive {
    908       1.1    ad 	u_int32_t	num_of_bdt_entries;
    909       1.1    ad 	u_int32_t	bad_data_block_address[MLY_MAX_BDT_ENTRIES];
    910       1.1    ad } __attribute__ ((__packed__));
    911       1.1    ad 
    912       1.1    ad /*
    913       1.1    ad  * 22.1 Physical Device Definition (PDD)
    914       1.1    ad  */
    915       1.1    ad struct mly_pdd {
    916       1.1    ad 	u_int8_t	type;				/* see 8.2 */
    917       1.1    ad 	u_int8_t	state;				/* see 8.1 */
    918       1.1    ad 	u_int16_t	raid_device;
    919       1.1    ad 	u_int32_t	device_size;			/* XXX "block or MB" Huh? */
    920       1.1    ad 	u_int8_t	controller;
    921       1.1    ad 	u_int8_t	channel;
    922       1.1    ad 	u_int8_t	target;
    923       1.1    ad 	u_int8_t	lun;
    924       1.1    ad 	u_int32_t	start_address;
    925       1.1    ad } __attribute__ ((__packed__));
    926       1.1    ad 
    927       1.1    ad /*
    928       1.1    ad  * 22.2 RAID Device Use Definition (UDD)
    929       1.1    ad  */
    930       1.1    ad struct mly_udd {
    931       1.1    ad 	u_int8_t	res1;
    932       1.1    ad 	u_int8_t	state;				/* see 8.1 */
    933       1.1    ad 	u_int16_t	raid_device;
    934       1.1    ad 	u_int32_t	start_address;
    935       1.1    ad } __attribute__ ((__packed__));
    936       1.1    ad 
    937       1.1    ad /*
    938       1.1    ad  * RAID Device Definition (LDD)
    939       1.1    ad  */
    940       1.1    ad struct mly_ldd {
    941       1.1    ad 	u_int8_t	type;				/* see 8.2 */
    942       1.1    ad 	u_int8_t	state;				/* see 8.1 */
    943       1.1    ad 	u_int16_t	raid_device;
    944       1.1    ad 	u_int32_t	device_size;			/* XXX "block or MB" Huh? */
    945       1.1    ad 	u_int8_t	devices_used_count;
    946       1.1    ad 	u_int8_t	stripe_size;			/* see 8.3 */
    947       1.1    ad 	u_int8_t	cache_line_size;		/* see 8.4 */
    948       1.1    ad 	u_int8_t	read_write_control;		/* see 8.5 */
    949       1.1    ad 	u_int32_t	devices_used_size;		/* XXX "block or MB" Huh? */
    950       1.1    ad 	u_int16_t	devices_used[32];		/* XXX actual size of this field unknown! */
    951       1.1    ad } __attribute__ ((__packed__));
    952       1.1    ad 
    953       1.1    ad /*
    954       1.1    ad  * Define a datastructure giving the smallest allocation that will hold
    955       1.1    ad  * a PDD, UDD or LDD for MDACIOCTL_GETDEVCONFINFO.
    956       1.1    ad  */
    957       1.1    ad struct mly_devconf_hdr {
    958       1.1    ad 	u_int8_t	type;				/* see 8.2 */
    959       1.1    ad 	u_int8_t	state;				/* see 8.1 */
    960       1.1    ad 	u_int16_t	raid_device;
    961       1.1    ad };
    962       1.1    ad 
    963       1.1    ad union mly_ioctl_devconfinfo {
    964       1.1    ad 	struct mly_pdd		pdd;
    965       1.1    ad 	struct mly_udd		udd;
    966       1.1    ad 	struct mly_ldd		ldd;
    967       1.1    ad 	struct mly_devconf_hdr	hdr;
    968       1.1    ad };
    969       1.1    ad 
    970       1.1    ad /*
    971       1.1    ad  * 22.3 MDACIOCTL_RENAMERAIDDEV
    972       1.1    ad  *
    973       1.1    ad  * XXX this command is listed as transferring data, but does not define the data.
    974       1.1    ad  */
    975       1.1    ad struct mly_ioctl_param_renameraiddev {
    976       1.1    ad 	u_int8_t	new_raid_device;
    977       1.1    ad } __attribute__ ((__packed__));
    978       1.1    ad 
    979       1.1    ad /*
    980       1.1    ad  * 23.6.2 MDACIOCTL_XLATEPHYSDEVTORAIDDEV
    981       1.1    ad  *
    982       1.1    ad  * XXX documentation suggests this format will change
    983       1.1    ad  */
    984       1.1    ad struct mly_ioctl_param_xlatephysdevtoraiddev {
    985       1.1    ad 	u_int16_t	raid_device;
    986       1.1    ad 	u_int8_t	res1[2];
    987       1.1    ad 	u_int8_t	controller;
    988       1.1    ad 	u_int8_t	channel;
    989       1.1    ad 	u_int8_t	target;
    990       1.1    ad 	u_int8_t	lun;
    991       1.1    ad } __attribute__ ((__packed__));
    992       1.1    ad 
    993       1.1    ad /*
    994       1.1    ad  * 23.7 MDACIOCTL_GETGROUPCONFINFO
    995       1.1    ad  */
    996       1.1    ad struct mly_ioctl_param_getgroupconfinfo {
    997       1.1    ad 	u_int16_t			group;
    998       1.1    ad 	u_int8_t			res1[8];
    999       1.1    ad 	union mly_cmd_transfer	transfer;
   1000       1.1    ad } __attribute__ ((__packed__));
   1001       1.1    ad 
   1002       1.1    ad /*
   1003       1.1    ad  * 23.9.2 MDACIOCTL_GETFREESPACELIST: Data Format
   1004       1.1    ad  *
   1005       1.1    ad  * The controller will populate as much of this structure as is provided,
   1006       1.1    ad  * or as is required to fully list the free space available.
   1007       1.1    ad  */
   1008       1.1    ad struct mly_ioctl_getfreespacelist_entry {
   1009       1.1    ad 	u_int16_t	raid_device;
   1010       1.1    ad 	u_int8_t	res1[6];
   1011       1.1    ad 	u_int32_t	address;		/* XXX "blocks or MB" Huh? */
   1012       1.1    ad 	u_int32_t	size;			/* XXX "blocks or MB" Huh? */
   1013       1.1    ad } __attribute__ ((__packed__));
   1014       1.1    ad 
   1015       1.1    ad struct mly_ioctl_getfrespacelist {
   1016       1.1    ad 	u_int16_t	returned_entries;
   1017       1.1    ad 	u_int16_t	total_entries;
   1018       1.1    ad 	u_int8_t	res1[12];
   1019       1.1    ad 	struct mly_ioctl_getfreespacelist_entry space[0];	/* expand to suit */
   1020       1.1    ad } __attribute__ ((__packed__));
   1021       1.1    ad 
   1022       1.1    ad /*
   1023       1.1    ad  * 27.1 MDACIOCTL_GETSUBSYSTEMDATA
   1024       1.1    ad  * 27.2 MDACIOCTL_SETSUBSYSTEMDATA
   1025       1.1    ad  *
   1026       1.1    ad  * PCI controller only supports a limited subset of the possible operations.
   1027       1.1    ad  *
   1028       1.1    ad  * XXX where does the status end up? (the command transfers no data)
   1029       1.1    ad  */
   1030       1.1    ad struct mly_ioctl_param_subsystemdata {
   1031       1.1    ad 	u_int8_t	operation:4;
   1032       1.1    ad #define	MLY_BBU_GETSTATUS	0x00
   1033       1.1    ad #define	MLY_BBU_SET_THRESHOLD	0x00	/* minutes in param[0,1] */
   1034       1.1    ad 	u_int8_t	subsystem:4;
   1035       1.1    ad #define	MLY_SUBSYSTEM_BBU	0x01
   1036       1.1    ad 	u_int	parameter[3];		/* only for SETSUBSYSTEMDATA */
   1037       1.1    ad } __attribute__ ((__packed__));
   1038       1.1    ad 
   1039       1.1    ad struct mly_ioctl_getsubsystemdata_bbustatus {
   1040       1.1    ad 	u_int16_t	current_power;
   1041       1.1    ad 	u_int16_t	maximum_power;
   1042       1.1    ad 	u_int16_t	power_threshold;
   1043       1.1    ad 	u_int8_t	charge_level;
   1044       1.1    ad 	u_int8_t	hardware_version;
   1045       1.1    ad 	u_int8_t	battery_type;
   1046       1.1    ad #define	MLY_BBU_TYPE_UNKNOWN	0x00
   1047       1.1    ad #define	MLY_BBU_TYPE_NICAD	0x01
   1048       1.1    ad #define	MLY_BBU_TYPE_MISSING	0xfe
   1049       1.1    ad 	u_int8_t	res1;
   1050       1.1    ad 	u_int8_t	operation_status;
   1051       1.1    ad #define	MLY_BBU_STATUS_NO_SYNC		0x01
   1052       1.1    ad #define	MLY_BBU_STATUS_OUT_OF_SYNC	0x02
   1053       1.1    ad #define	MLY_BBU_STATUS_FIRST_WARNING	0x04
   1054       1.1    ad #define	MLY_BBU_STATUS_SECOND_WARNING	0x08
   1055       1.1    ad #define	MLY_BBU_STATUS_RECONDITIONING	0x10
   1056       1.1    ad #define	MLY_BBU_STATUS_DISCHARGING	0x20
   1057       1.1    ad #define	MLY_BBU_STATUS_FASTCHARGING	0x40
   1058       1.1    ad 	u_int8_t	res2;
   1059       1.1    ad } __attribute__ ((__packed__));
   1060       1.1    ad 
   1061       1.1    ad /*
   1062       1.1    ad  * 28.9  MDACIOCTL_RESETDEVICE
   1063       1.1    ad  * 28.10 MDACIOCTL_FLUSHDEVICEDATA
   1064       1.1    ad  * 28.11 MDACIOCTL_PAUSEDEVICE
   1065       1.1    ad  * 28.12 MDACIOCTL_UNPAUSEDEVICE
   1066       1.1    ad  */
   1067       1.1    ad struct mly_ioctl_param_deviceoperation {
   1068       1.1    ad 	u_int8_t	operation_device;		/* see 14.3 */
   1069       1.1    ad } __attribute__ ((__packed__));
   1070       1.1    ad 
   1071       1.1    ad /*
   1072       1.1    ad  * 31.1 Event Data Format
   1073       1.1    ad  */
   1074       1.1    ad struct mly_event {
   1075       1.1    ad 	u_int32_t	sequence_number;
   1076       1.1    ad 	u_int32_t	timestamp;
   1077       1.1    ad 	u_int32_t	code;
   1078       1.1    ad 	u_int8_t	controller;
   1079       1.1    ad 	u_int8_t	channel;
   1080       1.1    ad 	u_int8_t	target;				/* also enclosure */
   1081       1.1    ad 	u_int8_t	lun;				/* also enclosure unit */
   1082       1.1    ad 	u_int8_t   	res1[4];
   1083       1.1    ad 	u_int32_t	param;
   1084       1.1    ad 	u_int8_t	sense[40];
   1085       1.1    ad } __attribute__ ((__packed__));
   1086       1.1    ad 
   1087       1.1    ad /*
   1088       1.1    ad  * 31.2 MDACIOCTL_GETEVENT
   1089       1.1    ad  */
   1090       1.1    ad struct mly_ioctl_param_getevent {
   1091       1.1    ad 	u_int16_t		sequence_number_low;
   1092       1.1    ad 	u_int8_t		res1[8];
   1093       1.1    ad 	union mly_cmd_transfer	transfer;
   1094       1.1    ad } __attribute__ ((__packed__));
   1095       1.1    ad 
   1096       1.1    ad union mly_ioctl_param {
   1097       1.1    ad 	struct mly_ioctl_param_data			data;
   1098       1.1    ad 	struct mly_ioctl_param_setmemorymailbox		setmemorymailbox;
   1099       1.1    ad 	struct mly_ioctl_param_setraiddevstate		setraiddevstate;
   1100       1.1    ad 	struct mly_ioctl_param_renameraiddev		renameraiddev;
   1101       1.1    ad 	struct mly_ioctl_param_xlatephysdevtoraiddev	xlatephysdevtoraiddev;
   1102       1.1    ad 	struct mly_ioctl_param_getgroupconfinfo		getgroupconfinfo;
   1103       1.1    ad 	struct mly_ioctl_param_subsystemdata		subsystemdata;
   1104       1.1    ad 	struct mly_ioctl_param_deviceoperation		deviceoperation;
   1105       1.1    ad 	struct mly_ioctl_param_getevent			getevent;
   1106       1.1    ad };
   1107       1.1    ad 
   1108       1.1    ad /*
   1109       1.1    ad  * 19 SCSI Command Format
   1110       1.1    ad  */
   1111       1.1    ad #define	MLY_PHYADDR(c, b, t, l)	\
   1112       1.1    ad 	((l) | ((t) << 8) | ((b) << 16) | ((c) << 19))
   1113       1.1    ad #define	MLY_LOGADDR(c, u)	\
   1114       1.1    ad 	((u) | ((c) << 19))
   1115       1.1    ad 
   1116       1.1    ad #define	MLY_LOGADDR_DEV(a)		(a & 0xffff)
   1117       1.1    ad #define	MLY_LOGADDR_CTLR(a)		(a >> 19)
   1118       1.1    ad 
   1119       1.1    ad #define	MLY_PHYADDR_LUN(a)		(a & 0xff)
   1120       1.1    ad #define	MLY_PHYADDR_TARGET(a)		((a >> 8) & 0xff)
   1121       1.1    ad #define	MLY_PHYADDR_CHANNEL(a)		((a >> 16) & 0x07)
   1122       1.1    ad #define	MLY_PHYADDR_CTLR(a)		((a >> 19) & 0x1f)
   1123       1.1    ad 
   1124       1.1    ad /*
   1125       1.1    ad  * struct mly_cmd_address_physical {
   1126       1.1    ad  *	u_int8_t			lun;
   1127       1.1    ad  *	u_int8_t			target;
   1128       1.1    ad  *	u_int8_t			channel:3;
   1129       1.1    ad  *	u_int8_t			controller:5;
   1130       1.1    ad  * } __attribute__ ((__packed__));
   1131       1.1    ad  *
   1132       1.1    ad  * struct mly_cmd_address_logical {
   1133       1.1    ad  *	u_int16_t			logdev;
   1134       1.1    ad  *	u_int8_t			res1:3;
   1135       1.1    ad  *	u_int8_t			controller:5;
   1136       1.1    ad  * } __attribute__ ((__packed__));
   1137       1.1    ad  */
   1138       1.1    ad 
   1139       1.1    ad struct mly_cmd_generic {
   1140       1.1    ad 	u_int16_t			command_id;
   1141       1.1    ad 	u_int8_t			opcode;
   1142       1.1    ad 	u_int8_t			command_control;
   1143       1.1    ad 	u_int32_t			data_size;
   1144       1.1    ad 	u_int64_t			sense_buffer_address;
   1145       1.1    ad 	u_int8_t			addr[3];
   1146       1.1    ad 	u_int8_t			timeout;
   1147       1.1    ad 	u_int8_t			maximum_sense_size;
   1148       1.1    ad 	u_int8_t			res1[11];
   1149       1.1    ad 	union mly_cmd_transfer	transfer;
   1150       1.1    ad } __attribute__ ((__packed__));
   1151  1.1.32.1  kent 
   1152       1.1    ad 
   1153       1.1    ad /*
   1154       1.1    ad  * 19.1 MDACMD_SCSI & MDACMD_SCSIPT
   1155       1.1    ad  */
   1156       1.1    ad #define	MLY_CMD_SCSI_SMALL_CDB	10
   1157       1.1    ad struct mly_cmd_scsi_small {
   1158       1.1    ad 	u_int16_t			command_id;
   1159       1.1    ad 	u_int8_t			opcode;
   1160       1.1    ad 	u_int8_t			command_control;
   1161       1.1    ad 	u_int32_t			data_size;
   1162       1.1    ad 	u_int64_t			sense_buffer_address;
   1163       1.1    ad 	u_int8_t			addr[3];
   1164       1.1    ad 	u_int8_t			timeout;
   1165       1.1    ad 	u_int8_t			maximum_sense_size;
   1166       1.1    ad 	u_int8_t			cdb_length;
   1167       1.1    ad 	u_int8_t			cdb[MLY_CMD_SCSI_SMALL_CDB];
   1168       1.1    ad 	union mly_cmd_transfer	transfer;
   1169       1.1    ad } __attribute__ ((__packed__));
   1170  1.1.32.1  kent 
   1171       1.1    ad /*
   1172       1.1    ad  * 19.2 MDACMD_SCSILC & MDACMD_SCSILCPT
   1173       1.1    ad  */
   1174       1.1    ad struct mly_cmd_scsi_large {
   1175       1.1    ad 	u_int16_t			command_id;
   1176       1.1    ad 	u_int8_t			opcode;
   1177       1.1    ad 	u_int8_t			command_control;
   1178       1.1    ad 	u_int32_t			data_size;
   1179       1.1    ad 	u_int64_t			sense_buffer_address;
   1180       1.1    ad 	u_int8_t			addr[3];
   1181       1.1    ad 	u_int8_t			timeout;
   1182       1.1    ad 	u_int8_t			maximum_sense_size;
   1183       1.1    ad 	u_int8_t			cdb_length;
   1184       1.1    ad 	u_int16_t			res1;
   1185       1.1    ad 	u_int64_t			cdb_physaddr;
   1186       1.1    ad 	union mly_cmd_transfer	transfer;
   1187       1.1    ad } __attribute__ ((__packed__));
   1188  1.1.32.1  kent 
   1189       1.1    ad /*
   1190       1.1    ad  * 20.1 IOCTL Command Format: Internal Bus
   1191       1.1    ad  */
   1192       1.1    ad struct mly_cmd_ioctl {
   1193       1.1    ad 	u_int16_t			command_id;
   1194       1.1    ad 	u_int8_t			opcode;
   1195       1.1    ad 	u_int8_t			command_control;
   1196       1.1    ad 	u_int32_t			data_size;
   1197       1.1    ad 	u_int64_t			sense_buffer_address;
   1198       1.1    ad 	u_int8_t			addr[3];
   1199       1.1    ad 	u_int8_t			timeout;
   1200       1.1    ad 	u_int8_t			maximum_sense_size;
   1201       1.1    ad 	u_int8_t			sub_ioctl;
   1202       1.1    ad 	union mly_ioctl_param		param;
   1203       1.1    ad } __attribute__ ((__packed__));
   1204       1.1    ad 
   1205       1.1    ad /*
   1206       1.1    ad  * PG6: 8.2.2
   1207       1.1    ad  */
   1208       1.1    ad struct mly_cmd_mmbox {
   1209       1.1    ad 	u_int32_t			flag;
   1210       1.1    ad 	u_int8_t			data[60];
   1211       1.1    ad } __attribute__ ((__packed__));
   1212       1.1    ad 
   1213       1.1    ad union mly_cmd_packet {
   1214       1.1    ad 	struct mly_cmd_generic		generic;
   1215       1.1    ad 	struct mly_cmd_scsi_small	scsi_small;
   1216       1.1    ad 	struct mly_cmd_scsi_large	scsi_large;
   1217       1.1    ad 	struct mly_cmd_ioctl		ioctl;
   1218       1.1    ad 	struct mly_cmd_mmbox		mmbox;
   1219       1.1    ad };
   1220       1.1    ad 
   1221       1.1    ad /*
   1222       1.1    ad  * PG6: 5.3
   1223       1.1    ad  */
   1224       1.1    ad #define	MLY_I960RX_COMMAND_MAILBOX	0x10
   1225       1.1    ad #define	MLY_I960RX_STATUS_MAILBOX	0x18
   1226       1.1    ad #define	MLY_I960RX_IDBR			0x20
   1227       1.1    ad #define	MLY_I960RX_ODBR			0x2c
   1228       1.1    ad #define	MLY_I960RX_ERROR_STATUS		0x2e
   1229       1.1    ad #define	MLY_I960RX_INTERRUPT_STATUS	0x30
   1230       1.1    ad #define	MLY_I960RX_INTERRUPT_MASK	0x34
   1231       1.1    ad 
   1232       1.1    ad #define	MLY_STRONGARM_COMMAND_MAILBOX	0x50
   1233       1.1    ad #define	MLY_STRONGARM_STATUS_MAILBOX	0x58
   1234       1.1    ad #define	MLY_STRONGARM_IDBR		0x60
   1235       1.1    ad #define	MLY_STRONGARM_ODBR		0x61
   1236       1.1    ad #define	MLY_STRONGARM_ERROR_STATUS	0x63
   1237       1.1    ad #define	MLY_STRONGARM_INTERRUPT_STATUS	0x30
   1238       1.1    ad #define	MLY_STRONGARM_INTERRUPT_MASK	0x34
   1239       1.1    ad 
   1240       1.1    ad /*
   1241       1.1    ad  * PG6: 5.4.3 Doorbell 0
   1242       1.1    ad  */
   1243       1.1    ad #define	MLY_HM_CMDSENT			(1<<0)
   1244       1.1    ad #define	MLY_HM_STSACK			(1<<1)
   1245       1.1    ad #define	MLY_SOFT_RST			(1<<3)
   1246       1.1    ad #define	MLY_AM_CMDSENT			(1<<4)
   1247       1.1    ad 
   1248       1.1    ad /*
   1249       1.1    ad  * PG6: 5.4.4 Doorbell 1
   1250       1.1    ad  *
   1251       1.1    ad  * Note that the documentation claims that these bits are set when the
   1252  1.1.32.1  kent  * status queue(s) are empty, wheras the Linux driver and experience
   1253       1.1    ad  * suggest they are set when there is status available.
   1254       1.1    ad  */
   1255       1.1    ad #define	MLY_HM_STSREADY			(1<<0)
   1256       1.1    ad #define	MLY_AM_STSREADY			(1<<1)
   1257       1.1    ad 
   1258       1.1    ad /*
   1259       1.1    ad  * PG6: 5.4.6 Doorbell 3
   1260       1.1    ad  */
   1261       1.1    ad #define	MLY_MSG_EMPTY			(1<<3)
   1262       1.1    ad #define	MLY_MSG_SPINUP			0x08
   1263       1.1    ad #define	MLY_MSG_RACE_RECOVERY_FAIL	0x60
   1264       1.1    ad #define	MLY_MSG_RACE_IN_PROGRESS	0x70
   1265       1.1    ad #define	MLY_MSG_RACE_ON_CRITICAL	0xb0
   1266       1.1    ad #define	MLY_MSG_PARITY_ERROR		0xf0
   1267       1.1    ad 
   1268       1.1    ad /*
   1269       1.1    ad  * PG6: 5.4.8 Outbound Interrupt Mask
   1270       1.1    ad  */
   1271       1.1    ad #define	MLY_INTERRUPT_MASK_DISABLE	0xff
   1272       1.1    ad #define	MLY_INTERRUPT_MASK_ENABLE	(0xff & ~(1<<2))
   1273       1.1    ad 
   1274       1.1    ad /*
   1275       1.1    ad  * PG6: 8.2 Advanced Mailbox Scheme
   1276       1.1    ad  *
   1277       1.1    ad  * Note that this must be allocated on a 4k boundary, and all internal
   1278       1.1    ad  * fields must also reside on a 4k boundary.
   1279       1.1    ad  * We could dynamically size this structure, but the extra effort
   1280       1.1    ad  * is probably unjustified.  Note that these buffers do not need to be
   1281       1.1    ad  * adjacent - we just group them to simplify allocation of the bus-visible
   1282       1.1    ad  * buffer.
   1283       1.1    ad  *
   1284       1.1    ad  * XXX Note that for some reason, if MLY_MMBOX_COMMANDS is > 64, the controller
   1285       1.1    ad  * fails to respond to the command at (MLY_MMBOX_COMMANDS - 64).  It's not
   1286       1.1    ad  * wrapping to 0 at this point (determined by experimentation).  This is not
   1287       1.1    ad  * consistent with the Linux driver's implementation.
   1288       1.1    ad  * Whilst it's handy to have lots of room for status returns in case we end up
   1289  1.1.32.1  kent  * being slow getting back to completed commands, it seems unlikely that we
   1290       1.1    ad  * would get 64 commands ahead of the controller on the submissions side, so
   1291       1.1    ad  * the current workaround is to simply limit the command ring to 64 entries.
   1292       1.1    ad  */
   1293       1.1    ad union mly_status_packet {
   1294       1.1    ad 	 struct mly_status		status;
   1295       1.1    ad 	 struct {
   1296       1.1    ad 		 u_int32_t		flag;
   1297       1.1    ad 		 u_int8_t		data[4];
   1298       1.1    ad 	 } __attribute__ ((__packed__)) mmbox;
   1299       1.1    ad };
   1300       1.1    ad union mly_health_region {
   1301       1.1    ad 	struct mly_health_status	status;
   1302       1.1    ad 	u_int8_t			pad[1024];
   1303       1.1    ad };
   1304       1.1    ad 
   1305       1.1    ad #define	MLY_MMBOX_COMMANDS		64
   1306       1.1    ad #define	MLY_MMBOX_STATUS		512
   1307       1.1    ad struct mly_mmbox {
   1308       1.1    ad 	union mly_cmd_packet	mmm_command[MLY_MMBOX_COMMANDS];
   1309       1.1    ad 	union mly_status_packet	mmm_status[MLY_MMBOX_STATUS];
   1310       1.1    ad 	union mly_health_region	mmm_health;
   1311       1.1    ad } __attribute__ ((__packed__));
   1312       1.1    ad 
   1313       1.1    ad #endif	/* !defined _PCI_MLYREG_H_ */
   1314