mpiireg.h revision 1.1
1 /* $NetBSD: mpiireg.h,v 1.1 2018/11/24 18:11:22 bouyer Exp $ */ 2 /* OpenBSD: mpii.c,v 1.51 2012/04/11 13:29:14 naddy Exp */ 3 /* 4 * Copyright (c) 2010 Mike Belopuhov <mkb (at) crypt.org.ru> 5 * Copyright (c) 2009 James Giannoules 6 * Copyright (c) 2005 - 2010 David Gwynne <dlg (at) openbsd.org> 7 * Copyright (c) 2005 - 2010 Marco Peereboom <marco (at) openbsd.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 #define MPII_DOORBELL (0x00) 23 /* doorbell read bits */ 24 #define MPII_DOORBELL_STATE (0xf<<28) /* ioc state */ 25 #define MPII_DOORBELL_STATE_RESET (0x0<<28) 26 #define MPII_DOORBELL_STATE_READY (0x1<<28) 27 #define MPII_DOORBELL_STATE_OPER (0x2<<28) 28 #define MPII_DOORBELL_STATE_FAULT (0x4<<28) 29 #define MPII_DOORBELL_INUSE (0x1<<27) /* doorbell used */ 30 #define MPII_DOORBELL_WHOINIT (0x7<<24) /* last to reset ioc */ 31 #define MPII_DOORBELL_WHOINIT_NOONE (0x0<<24) /* not initialized */ 32 #define MPII_DOORBELL_WHOINIT_SYSBIOS (0x1<<24) /* system bios */ 33 #define MPII_DOORBELL_WHOINIT_ROMBIOS (0x2<<24) /* rom bios */ 34 #define MPII_DOORBELL_WHOINIT_PCIPEER (0x3<<24) /* pci peer */ 35 #define MPII_DOORBELL_WHOINIT_DRIVER (0x4<<24) /* host driver */ 36 #define MPII_DOORBELL_WHOINIT_MANUFACT (0x5<<24) /* manufacturing */ 37 #define MPII_DOORBELL_FAULT (0xffff<<0) /* fault code */ 38 /* doorbell write bits */ 39 #define MPII_DOORBELL_FUNCTION_SHIFT (24) 40 #define MPII_DOORBELL_FUNCTION_MASK (0xff << MPII_DOORBELL_FUNCTION_SHIFT) 41 #define MPII_DOORBELL_FUNCTION(x) \ 42 (((x) << MPII_DOORBELL_FUNCTION_SHIFT) & MPII_DOORBELL_FUNCTION_MASK) 43 #define MPII_DOORBELL_DWORDS_SHIFT 16 44 #define MPII_DOORBELL_DWORDS_MASK (0xff << MPII_DOORBELL_DWORDS_SHIFT) 45 #define MPII_DOORBELL_DWORDS(x) \ 46 (((x) << MPII_DOORBELL_DWORDS_SHIFT) & MPII_DOORBELL_DWORDS_MASK) 47 #define MPII_DOORBELL_DATA_MASK (0xffff) 48 49 #define MPII_WRITESEQ (0x04) 50 #define MPII_WRITESEQ_KEY_VALUE_MASK (0x0000000f) /* key value */ 51 #define MPII_WRITESEQ_FLUSH (0x00) 52 #define MPII_WRITESEQ_1 (0x0f) 53 #define MPII_WRITESEQ_2 (0x04) 54 #define MPII_WRITESEQ_3 (0x0b) 55 #define MPII_WRITESEQ_4 (0x02) 56 #define MPII_WRITESEQ_5 (0x07) 57 #define MPII_WRITESEQ_6 (0x0d) 58 59 #define MPII_HOSTDIAG (0x08) 60 #define MPII_HOSTDIAG_BDS_MASK (0x00001800) /* boot device select */ 61 #define MPII_HOSTDIAG_BDS_DEFAULT (0<<11) /* default address map, flash */ 62 #define MPII_HOSTDIAG_BDS_HCDW (1<<11) /* host code and data window */ 63 #define MPII_HOSTDIAG_CLEARFBS (1<<10) /* clear flash bad sig */ 64 #define MPII_HOSTDIAG_FORCE_HCB_ONBOOT (1<<9) /* force host controlled boot */ 65 #define MPII_HOSTDIAG_HCB_MODE (1<<8) /* host controlled boot mode */ 66 #define MPII_HOSTDIAG_DWRE (1<<7) /* diag reg write enabled */ 67 #define MPII_HOSTDIAG_FBS (1<<6) /* flash bad sig */ 68 #define MPII_HOSTDIAG_RESET_HIST (1<<5) /* reset history */ 69 #define MPII_HOSTDIAG_DIAGWR_EN (1<<4) /* diagnostic write enabled */ 70 #define MPII_HOSTDIAG_RESET_ADAPTER (1<<2) /* reset adapter */ 71 #define MPII_HOSTDIAG_HOLD_IOC_RESET (1<<1) /* hold ioc in reset */ 72 #define MPII_HOSTDIAG_DIAGMEM_EN (1<<0) /* diag mem enable */ 73 74 #define MPII_DIAGRWDATA (0x10) 75 76 #define MPII_DIAGRWADDRLOW (0x14) 77 78 #define MPII_DIAGRWADDRHIGH (0x18) 79 80 #define MPII_INTR_STATUS (0x30) 81 #define MPII_INTR_STATUS_SYS2IOCDB (1<<31) /* ioc written to by host */ 82 #define MPII_INTR_STATUS_RESET (1<<30) /* physical ioc reset */ 83 #define MPII_INTR_STATUS_REPLY (1<<3) /* reply message interrupt */ 84 #define MPII_INTR_STATUS_IOC2SYSDB (1<<0) /* ioc write to doorbell */ 85 86 #define MPII_INTR_MASK (0x34) 87 #define MPII_INTR_MASK_RESET (1<<30) /* ioc reset intr mask */ 88 #define MPII_INTR_MASK_REPLY (1<<3) /* reply message intr mask */ 89 #define MPII_INTR_MASK_DOORBELL (1<<0) /* doorbell interrupt mask */ 90 91 #define MPII_DCR_DATA (0x38) 92 93 #define MPII_DCR_ADDRESS (0x3c) 94 95 #define MPII_REPLY_FREE_HOST_INDEX (0x48) 96 97 #define MPII_REPLY_POST_HOST_INDEX (0x6c) 98 99 #define MPII_HCB_SIZE (0x74) 100 101 #define MPII_HCB_ADDRESS_LOW (0x78) 102 #define MPII_HCB_ADDRESS_HIGH (0x7c) 103 104 #define MPII_REQ_DESCR_POST_LOW (0xc0) 105 #define MPII_REQ_DESCR_POST_HIGH (0xc4) 106 107 /* 108 * Scatter Gather Lists 109 */ 110 111 #define MPII_SGE_FL_LAST (0x1<<31) /* last element in segment */ 112 #define MPII_SGE_FL_EOB (0x1<<30) /* last element of buffer */ 113 #define MPII_SGE_FL_TYPE (0x3<<28) /* element type */ 114 #define MPII_SGE_FL_TYPE_SIMPLE (0x1<<28) /* simple element */ 115 #define MPII_SGE_FL_TYPE_CHAIN (0x3<<28) /* chain element */ 116 #define MPII_SGE_FL_TYPE_XACTCTX (0x0<<28) /* transaction context */ 117 #define MPII_SGE_FL_LOCAL (0x1<<27) /* local address */ 118 #define MPII_SGE_FL_DIR (0x1<<26) /* direction */ 119 #define MPII_SGE_FL_DIR_OUT (0x1<<26) 120 #define MPII_SGE_FL_DIR_IN (0x0<<26) 121 #define MPII_SGE_FL_SIZE (0x1<<25) /* address size */ 122 #define MPII_SGE_FL_SIZE_32 (0x0<<25) 123 #define MPII_SGE_FL_SIZE_64 (0x1<<25) 124 #define MPII_SGE_FL_EOL (0x1<<24) /* end of list */ 125 126 struct mpii_sge { 127 u_int32_t sg_hdr; 128 u_int32_t sg_lo_addr; 129 u_int32_t sg_hi_addr; 130 } __packed; 131 132 struct mpii_fw_tce { 133 u_int8_t reserved1; 134 u_int8_t context_size; 135 u_int8_t details_length; 136 u_int8_t flags; 137 138 u_int32_t reserved2; 139 140 u_int32_t image_offset; 141 142 u_int32_t image_size; 143 } __packed; 144 145 /* 146 * Messages 147 */ 148 149 /* functions */ 150 #define MPII_FUNCTION_SCSI_IO_REQUEST (0x00) 151 #define MPII_FUNCTION_SCSI_TASK_MGMT (0x01) 152 #define MPII_FUNCTION_IOC_INIT (0x02) 153 #define MPII_FUNCTION_IOC_FACTS (0x03) 154 #define MPII_FUNCTION_CONFIG (0x04) 155 #define MPII_FUNCTION_PORT_FACTS (0x05) 156 #define MPII_FUNCTION_PORT_ENABLE (0x06) 157 #define MPII_FUNCTION_EVENT_NOTIFICATION (0x07) 158 #define MPII_FUNCTION_EVENT_ACK (0x08) 159 #define MPII_FUNCTION_FW_DOWNLOAD (0x09) 160 #define MPII_FUNCTION_TARGET_CMD_BUFFER_POST (0x0a) 161 #define MPII_FUNCTION_TARGET_ASSIST (0x0b) 162 #define MPII_FUNCTION_TARGET_STATUS_SEND (0x0c) 163 #define MPII_FUNCTION_TARGET_MODE_ABORT (0x0d) 164 #define MPII_FUNCTION_FW_UPLOAD (0x12) 165 166 #define MPII_FUNCTION_RAID_ACTION (0x15) 167 #define MPII_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) 168 169 #define MPII_FUNCTION_TOOLBOX (0x17) 170 171 #define MPII_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) 172 173 #define MPII_FUNCTION_SMP_PASSTHROUGH (0x1a) 174 #define MPII_FUNCTION_SAS_IO_UNIT_CONTROL (0x1b) 175 #define MPII_FUNCTION_SATA_PASSTHROUGH (0x1c) 176 177 #define MPII_FUNCTION_DIAG_BUFFER_POST (0x1d) 178 #define MPII_FUNCTION_DIAG_RELEASE (0x1e) 179 180 #define MPII_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) 181 #define MPII_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) 182 183 #define MPII_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 184 #define MPII_FUNCTION_IO_UNIT_RESET (0x41) 185 #define MPII_FUNCTION_HANDSHAKE (0x42) 186 187 /* Common IOCStatus values for all replies */ 188 #define MPII_IOCSTATUS_MASK (0x7fff) 189 #define MPII_IOCSTATUS_SUCCESS (0x0000) 190 #define MPII_IOCSTATUS_INVALID_FUNCTION (0x0001) 191 #define MPII_IOCSTATUS_BUSY (0x0002) 192 #define MPII_IOCSTATUS_INVALID_SGL (0x0003) 193 #define MPII_IOCSTATUS_INTERNAL_ERROR (0x0004) 194 #define MPII_IOCSTATUS_INVALID_VPID (0x0005) 195 #define MPII_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 196 #define MPII_IOCSTATUS_INVALID_FIELD (0x0007) 197 #define MPII_IOCSTATUS_INVALID_STATE (0x0008) 198 #define MPII_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 199 /* Config IOCStatus values */ 200 #define MPII_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 201 #define MPII_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 202 #define MPII_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 203 #define MPII_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 204 #define MPII_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 205 #define MPII_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 206 /* SCSIIO Reply initiator values */ 207 #define MPII_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 208 #define MPII_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 209 #define MPII_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 210 #define MPII_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 211 #define MPII_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 212 #define MPII_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 213 #define MPII_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 214 #define MPII_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 215 #define MPII_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 216 #define MPII_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004a) 217 #define MPII_IOCSTATUS_SCSI_IOC_TERMINATED (0x004b) 218 #define MPII_IOCSTATUS_SCSI_EXT_TERMINATED (0x004c) 219 /* For use by SCSI Initiator and SCSI Target end-to-end data protection */ 220 #define MPII_IOCSTATUS_EEDP_GUARD_ERROR (0x004d) 221 #define MPII_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004e) 222 #define MPII_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004f) 223 /* SCSI (SPI & FCP) target values */ 224 #define MPII_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 225 #define MPII_IOCSTATUS_TARGET_ABORTED (0x0063) 226 #define MPII_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 227 #define MPII_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 228 #define MPII_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006a) 229 #define MPII_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006d) 230 #define MPII_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006e) 231 #define MPII_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006f) 232 #define MPII_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 233 #define MPII_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 234 /* Serial Attached SCSI values */ 235 #define MPII_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 236 #define MPII_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 237 /* Diagnostic Tools values */ 238 #define MPII_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00a0) 239 240 #define MPII_REP_IOCLOGINFO_TYPE (0xf<<28) 241 #define MPII_REP_IOCLOGINFO_TYPE_NONE (0x0<<28) 242 #define MPII_REP_IOCLOGINFO_TYPE_SCSI (0x1<<28) 243 #define MPII_REP_IOCLOGINFO_TYPE_FC (0x2<<28) 244 #define MPII_REP_IOCLOGINFO_TYPE_SAS (0x3<<28) 245 #define MPII_REP_IOCLOGINFO_TYPE_ISCSI (0x4<<28) 246 #define MPII_REP_IOCLOGINFO_DATA (0x0fffffff) 247 248 /* event notification types */ 249 #define MPII_EVENT_NONE (0x00) 250 #define MPII_EVENT_LOG_DATA (0x01) 251 #define MPII_EVENT_STATE_CHANGE (0x02) 252 #define MPII_EVENT_HARD_RESET_RECEIVED (0x05) 253 #define MPII_EVENT_EVENT_CHANGE (0x0a) 254 #define MPII_EVENT_TASK_SET_FULL (0x0e) 255 #define MPII_EVENT_SAS_DEVICE_STATUS_CHANGE (0x0f) 256 #define MPII_EVENT_IR_OPERATION_STATUS (0x14) 257 #define MPII_EVENT_SAS_DISCOVERY (0x16) 258 #define MPII_EVENT_SAS_BROADCAST_PRIMITIVE (0x17) 259 #define MPII_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x18) 260 #define MPII_EVENT_SAS_INIT_TABLE_OVERFLOW (0x19) 261 #define MPII_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x1c) 262 #define MPII_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x1d) 263 #define MPII_EVENT_IR_VOLUME (0x1e) 264 #define MPII_EVENT_IR_PHYSICAL_DISK (0x1f) 265 #define MPII_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x20) 266 #define MPII_EVENT_LOG_ENTRY_ADDED (0x21) 267 268 /* messages */ 269 270 #define MPII_WHOINIT_NOONE (0x00) 271 #define MPII_WHOINIT_SYSTEM_BIOS (0x01) 272 #define MPII_WHOINIT_ROM_BIOS (0x02) 273 #define MPII_WHOINIT_PCI_PEER (0x03) 274 #define MPII_WHOINIT_HOST_DRIVER (0x04) 275 #define MPII_WHOINIT_MANUFACTURER (0x05) 276 277 /* default messages */ 278 279 struct mpii_msg_request { 280 u_int8_t reserved1; 281 u_int8_t reserved2; 282 u_int8_t chain_offset; 283 u_int8_t function; 284 285 u_int8_t reserved3; 286 u_int8_t reserved4; 287 u_int8_t reserved5; 288 u_int8_t msg_flags; 289 290 u_int8_t vp_id; 291 u_int8_t vf_id; 292 u_int16_t reserved6; 293 } __packed; 294 295 struct mpii_msg_reply { 296 u_int16_t reserved1; 297 u_int8_t msg_length; 298 u_int8_t function; 299 300 u_int16_t reserved2; 301 u_int8_t reserved3; 302 u_int8_t msg_flags; 303 304 u_int8_t vp_id; 305 u_int8_t vf_if; 306 u_int16_t reserved4; 307 308 u_int16_t reserved5; 309 u_int16_t ioc_status; 310 311 u_int32_t ioc_loginfo; 312 } __packed; 313 314 /* ioc init */ 315 316 struct mpii_msg_iocinit_request { 317 u_int8_t whoinit; 318 u_int8_t reserved1; 319 u_int8_t chain_offset; 320 u_int8_t function; 321 322 u_int16_t reserved2; 323 u_int8_t reserved3; 324 u_int8_t msg_flags; 325 326 u_int8_t vp_id; 327 u_int8_t vf_id; 328 u_int16_t reserved4; 329 330 u_int8_t msg_version_min; 331 u_int8_t msg_version_maj; 332 u_int8_t hdr_version_unit; 333 u_int8_t hdr_version_dev; 334 335 u_int32_t reserved5; 336 337 u_int32_t reserved6; 338 339 u_int16_t reserved7; 340 u_int16_t system_request_frame_size; 341 342 u_int16_t reply_descriptor_post_queue_depth; 343 u_int16_t reply_free_queue_depth; 344 345 u_int32_t sense_buffer_address_high; 346 347 u_int32_t system_reply_address_high; 348 349 u_int64_t system_request_frame_base_address; 350 351 u_int64_t reply_descriptor_post_queue_address; 352 353 u_int64_t reply_free_queue_address; 354 355 u_int64_t timestamp; 356 } __packed; 357 358 struct mpii_msg_iocinit_reply { 359 u_int8_t whoinit; 360 u_int8_t reserved1; 361 u_int8_t msg_length; 362 u_int8_t function; 363 364 u_int16_t reserved2; 365 u_int8_t reserved3; 366 u_int8_t msg_flags; 367 368 u_int8_t vp_id; 369 u_int8_t vf_id; 370 u_int16_t reserved4; 371 372 u_int16_t reserved5; 373 u_int16_t ioc_status; 374 375 u_int32_t ioc_loginfo; 376 } __packed; 377 378 struct mpii_msg_iocfacts_request { 379 u_int16_t reserved1; 380 u_int8_t chain_offset; 381 u_int8_t function; 382 383 u_int16_t reserved2; 384 u_int8_t reserved3; 385 u_int8_t msg_flags; 386 387 u_int8_t vp_id; 388 u_int8_t vf_id; 389 u_int16_t reserved4; 390 } __packed; 391 392 struct mpii_msg_iocfacts_reply { 393 u_int8_t msg_version_min; 394 u_int8_t msg_version_maj; 395 u_int8_t msg_length; 396 u_int8_t function; 397 398 u_int8_t header_version_dev; 399 u_int8_t header_version_unit; 400 u_int8_t ioc_number; 401 u_int8_t msg_flags; 402 403 u_int8_t vp_id; 404 u_int8_t vf_id; 405 u_int16_t reserved1; 406 407 u_int16_t ioc_exceptions; 408 #define MPII_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (1<<0) 409 #define MPII_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (1<<1) 410 #define MPII_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (1<<2) 411 #define MPII_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (1<<3) 412 #define MPII_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (1<<4) 413 #define MPII_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAC (1<<8) 414 /* XXX JPG BOOT_STATUS in bits[7:5] */ 415 /* XXX JPG all these #defines need to be fixed up */ 416 u_int16_t ioc_status; 417 418 u_int32_t ioc_loginfo; 419 420 u_int8_t max_chain_depth; 421 u_int8_t whoinit; 422 u_int8_t number_of_ports; 423 u_int8_t reserved2; 424 425 u_int16_t request_credit; 426 u_int16_t product_id; 427 428 u_int32_t ioc_capabilities; 429 #define MPII_IOCFACTS_CAPABILITY_EVENT_REPLAY (1<<13) 430 #define MPII_IOCFACTS_CAPABILITY_INTEGRATED_RAID (1<<12) 431 #define MPII_IOCFACTS_CAPABILITY_TLR (1<<11) 432 #define MPII_IOCFACTS_CAPABILITY_MULTICAST (1<<8) 433 #define MPII_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (1<<7) 434 #define MPII_IOCFACTS_CAPABILITY_EEDP (1<<6) 435 #define MPII_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (1<<4) 436 #define MPII_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (1<<3) 437 #define MPII_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (1<<2) 438 439 u_int8_t fw_version_dev; 440 u_int8_t fw_version_unit; 441 u_int8_t fw_version_min; 442 u_int8_t fw_version_maj; 443 444 u_int16_t ioc_request_frame_size; 445 u_int16_t reserved3; 446 447 u_int16_t max_initiators; 448 u_int16_t max_targets; 449 450 u_int16_t max_sas_expanders; 451 u_int16_t max_enclosures; 452 453 u_int16_t protocol_flags; 454 u_int16_t high_priority_credit; 455 456 u_int16_t max_reply_descriptor_post_queue_depth; 457 u_int8_t reply_frame_size; 458 u_int8_t max_volumes; 459 460 u_int16_t max_dev_handle; 461 u_int16_t max_persistent_entries; 462 463 u_int32_t reserved4; 464 } __packed; 465 466 struct mpii_msg_portfacts_request { 467 u_int16_t reserved1; 468 u_int8_t chain_offset; 469 u_int8_t function; 470 471 u_int16_t reserved2; 472 u_int8_t port_number; 473 u_int8_t msg_flags; 474 475 u_int8_t vp_id; 476 u_int8_t vf_id; 477 u_int16_t reserved3; 478 } __packed; 479 480 struct mpii_msg_portfacts_reply { 481 u_int16_t reserved1; 482 u_int8_t msg_length; 483 u_int8_t function; 484 485 u_int16_t reserved2; 486 u_int8_t port_number; 487 u_int8_t msg_flags; 488 489 u_int8_t vp_id; 490 u_int8_t vf_id; 491 u_int16_t reserved3; 492 493 u_int16_t reserved4; 494 u_int16_t ioc_status; 495 496 u_int32_t ioc_loginfo; 497 498 u_int8_t reserved5; 499 u_int8_t port_type; 500 #define MPII_PORTFACTS_PORTTYPE_INACTIVE (0x00) 501 #define MPII_PORTFACTS_PORTTYPE_FC (0x10) 502 #define MPII_PORTFACTS_PORTTYPE_ISCSI (0x20) 503 #define MPII_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 504 #define MPII_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 505 u_int16_t reserved6; 506 507 u_int16_t max_posted_cmd_buffers; 508 u_int16_t reserved7; 509 } __packed; 510 511 struct mpii_msg_portenable_request { 512 u_int16_t reserved1; 513 u_int8_t chain_offset; 514 u_int8_t function; 515 516 u_int8_t reserved2; 517 u_int8_t port_flags; 518 u_int8_t reserved3; 519 u_int8_t msg_flags; 520 521 u_int8_t vp_id; 522 u_int8_t vf_id; 523 u_int16_t reserved4; 524 } __packed; 525 526 struct mpii_msg_portenable_reply { 527 u_int16_t reserved1; 528 u_int8_t msg_length; 529 u_int8_t function; 530 531 u_int8_t reserved2; 532 u_int8_t port_flags; 533 u_int8_t reserved3; 534 u_int8_t msg_flags; 535 536 u_int8_t vp_id; 537 u_int8_t vf_id; 538 u_int16_t reserved4; 539 540 u_int16_t reserved5; 541 u_int16_t ioc_status; 542 543 u_int32_t ioc_loginfo; 544 } __packed; 545 546 struct mpii_msg_event_request { 547 u_int16_t reserved1; 548 u_int8_t chain_offset; 549 u_int8_t function; 550 551 u_int16_t reserved2; 552 u_int8_t reserved3; 553 u_int8_t msg_flags; 554 555 u_int8_t vp_id; 556 u_int8_t vf_id; 557 u_int16_t reserved4; 558 559 u_int32_t reserved5; 560 561 u_int32_t reserved6; 562 563 u_int32_t event_masks[4]; 564 565 u_int16_t sas_broadcase_primitive_masks; 566 u_int16_t reserved7; 567 568 u_int32_t reserved8; 569 } __packed; 570 571 struct mpii_msg_event_reply { 572 u_int16_t event_data_length; 573 u_int8_t msg_length; 574 u_int8_t function; 575 576 u_int16_t reserved1; 577 u_int8_t ack_required; 578 #define MPII_EVENT_ACK_REQUIRED (0x01) 579 u_int8_t msg_flags; 580 #define MPII_EVENT_FLAGS_REPLY_KEPT (1<<7) 581 582 u_int8_t vp_id; 583 u_int8_t vf_id; 584 u_int16_t reserved2; 585 586 u_int16_t reserved3; 587 u_int16_t ioc_status; 588 589 u_int32_t ioc_loginfo; 590 591 u_int16_t event; 592 u_int16_t reserved4; 593 594 u_int32_t event_context; 595 596 /* event data follows */ 597 } __packed; 598 599 struct mpii_msg_eventack_request { 600 u_int16_t reserved1; 601 u_int8_t chain_offset; 602 u_int8_t function; 603 604 u_int8_t reserved2[3]; 605 u_int8_t msg_flags; 606 607 u_int8_t vp_id; 608 u_int8_t vf_id; 609 u_int16_t reserved3; 610 611 u_int16_t event; 612 u_int16_t reserved4; 613 614 u_int32_t event_context; 615 } __packed; 616 617 struct mpii_msg_eventack_reply { 618 u_int16_t reserved1; 619 u_int8_t msg_length; 620 u_int8_t function; 621 622 u_int8_t reserved2[3]; 623 u_int8_t msg_flags; 624 625 u_int8_t vp_id; 626 u_int8_t vf_id; 627 u_int16_t reserved3; 628 629 u_int16_t reserved4; 630 u_int16_t ioc_status; 631 632 u_int32_t ioc_loginfo; 633 } __packed; 634 635 struct mpii_msg_fwupload_request { 636 u_int8_t image_type; 637 #define MPII_FWUPLOAD_IMAGETYPE_IOC_FW (0x00) 638 #define MPII_FWUPLOAD_IMAGETYPE_NV_FW (0x01) 639 #define MPII_FWUPLOAD_IMAGETYPE_NV_BACKUP (0x05) 640 #define MPII_FWUPLOAD_IMAGETYPE_NV_MANUFACTURING (0x06) 641 #define MPII_FWUPLOAD_IMAGETYPE_NV_CONFIG_1 (0x07) 642 #define MPII_FWUPLOAD_IMAGETYPE_NV_CONFIG_2 (0x08) 643 #define MPII_FWUPLOAD_IMAGETYPE_NV_MEGARAID (0x09) 644 #define MPII_FWUPLOAD_IMAGETYPE_NV_COMPLETE (0x0a) 645 #define MPII_FWUPLOAD_IMAGETYPE_COMMON_BOOT_BLOCK (0x0b) 646 u_int8_t reserved1; 647 u_int8_t chain_offset; 648 u_int8_t function; 649 650 u_int8_t reserved2[3]; 651 u_int8_t msg_flags; 652 653 u_int8_t vp_id; 654 u_int8_t vf_id; 655 u_int16_t reserved3; 656 657 u_int32_t reserved4; 658 659 u_int32_t reserved5; 660 661 struct mpii_fw_tce tce; 662 663 /* followed by an sgl */ 664 } __packed; 665 666 struct mpii_msg_fwupload_reply { 667 u_int8_t image_type; 668 u_int8_t reserved1; 669 u_int8_t msg_length; 670 u_int8_t function; 671 672 u_int8_t reserved2[3]; 673 u_int8_t msg_flags; 674 675 u_int8_t vp_id; 676 u_int8_t vf_id; 677 u_int16_t reserved3; 678 679 u_int16_t reserved4; 680 u_int16_t ioc_status; 681 682 u_int32_t ioc_loginfo; 683 684 u_int32_t actual_image_size; 685 } __packed; 686 687 struct mpii_msg_scsi_io { 688 u_int16_t dev_handle; 689 u_int8_t chain_offset; 690 u_int8_t function; 691 692 u_int16_t reserved1; 693 u_int8_t reserved2; 694 u_int8_t msg_flags; 695 696 u_int8_t vp_id; 697 u_int8_t vf_id; 698 u_int16_t reserved3; 699 700 u_int32_t sense_buffer_low_address; 701 702 u_int16_t sgl_flags; 703 u_int8_t sense_buffer_length; 704 u_int8_t reserved4; 705 706 u_int8_t sgl_offset0; 707 u_int8_t sgl_offset1; 708 u_int8_t sgl_offset2; 709 u_int8_t sgl_offset3; 710 711 u_int32_t skip_count; 712 713 u_int32_t data_length; 714 715 u_int32_t bidirectional_data_length; 716 717 u_int16_t io_flags; 718 u_int16_t eedp_flags; 719 720 u_int32_t eedp_block_size; 721 722 u_int32_t secondary_reference_tag; 723 724 u_int16_t secondary_application_tag; 725 u_int16_t application_tag_translation_mask; 726 727 u_int16_t lun[4]; 728 729 /* the following 16 bits are defined in MPI2 as the control field */ 730 u_int8_t reserved5; 731 u_int8_t tagging; 732 #define MPII_SCSIIO_ATTR_SIMPLE_Q (0x0) 733 #define MPII_SCSIIO_ATTR_HEAD_OF_Q (0x1) 734 #define MPII_SCSIIO_ATTR_ORDERED_Q (0x2) 735 #define MPII_SCSIIO_ATTR_ACA_Q (0x4) 736 #define MPII_SCSIIO_ATTR_UNTAGGED (0x5) 737 #define MPII_SCSIIO_ATTR_NO_DISCONNECT (0x7) 738 u_int8_t reserved6; 739 u_int8_t direction; 740 #define MPII_SCSIIO_DIR_NONE (0x0) 741 #define MPII_SCSIIO_DIR_WRITE (0x1) 742 #define MPII_SCSIIO_DIR_READ (0x2) 743 744 #define MPII_CDB_LEN (32) 745 u_int8_t cdb[MPII_CDB_LEN]; 746 747 /* followed by an sgl */ 748 } __packed; 749 750 struct mpii_msg_scsi_io_error { 751 u_int16_t dev_handle; 752 u_int8_t msg_length; 753 u_int8_t function; 754 755 u_int16_t reserved1; 756 u_int8_t reserved2; 757 u_int8_t msg_flags; 758 759 u_int8_t vp_id; 760 u_int8_t vf_id; 761 u_int16_t reserved3; 762 763 u_int8_t scsi_status; 764 765 #define MPII_SCSIIO_ERR_STATUS_SUCCESS (0x00) 766 #define MPII_SCSIIO_ERR_STATUS_CHECK_COND (0x02) 767 #define MPII_SCSIIO_ERR_STATUS_BUSY (0x04) 768 #define MPII_SCSIIO_ERR_STATUS_INTERMEDIATE (0x08) 769 #define MPII_SCSIIO_ERR_STATUS_INTERMEDIATE_CONDMET (0x10) 770 #define MPII_SCSIIO_ERR_STATUS_RESERVATION_CONFLICT (0x14) 771 #define MPII_SCSIIO_ERR_STATUS_CMD_TERM (0x22) 772 #define MPII_SCSIIO_ERR_STATUS_TASK_SET_FULL (0x28) 773 #define MPII_SCSIIO_ERR_STATUS_ACA_ACTIVE (0x30) 774 #define MPII_SCSIIO_ERR_STATUS_TASK_ABORTED (0x40) 775 776 u_int8_t scsi_state; 777 #define MPII_SCSIIO_ERR_STATE_AUTOSENSE_VALID (1<<0) 778 #define MPII_SCSIIO_ERR_STATE_AUTOSENSE_FAILED (1<<1) 779 #define MPII_SCSIIO_ERR_STATE_NO_SCSI_STATUS (1<<2) 780 #define MPII_SCSIIO_ERR_STATE_TERMINATED (1<<3) 781 #define MPII_SCSIIO_ERR_STATE_RESPONSE_INFO_VALID (1<<4) 782 #define MPII_SCSIIO_ERR_STATE_QUEUE_TAG_REJECTED (0xffff) 783 u_int16_t ioc_status; 784 785 u_int32_t ioc_loginfo; 786 787 u_int32_t transfer_count; 788 789 u_int32_t sense_count; 790 791 u_int32_t response_info; 792 793 u_int16_t task_tag; 794 u_int16_t reserved4; 795 796 u_int32_t bidirectional_transfer_count; 797 798 u_int32_t reserved5; 799 800 u_int32_t reserved6; 801 } __packed; 802 803 struct mpii_request_descr { 804 u_int8_t request_flags; 805 #define MPII_REQ_DESCR_TYPE_MASK (0x0e) 806 #define MPII_REQ_DESCR_SCSI_IO (0x00) 807 #define MPII_REQ_DESCR_SCSI_TARGET (0x02) 808 #define MPII_REQ_DESCR_HIGH_PRIORITY (0x06) 809 #define MPII_REQ_DESCR_DEFAULT (0x08) 810 u_int8_t vf_id; 811 u_int16_t smid; 812 813 u_int16_t lmid; 814 u_int16_t dev_handle; 815 } __packed; 816 817 struct mpii_reply_descr { 818 u_int8_t reply_flags; 819 #define MPII_REPLY_DESCR_TYPE_MASK (0x0f) 820 #define MPII_REPLY_DESCR_SCSI_IO_SUCCESS (0x00) 821 #define MPII_REPLY_DESCR_ADDRESS_REPLY (0x01) 822 #define MPII_REPLY_DESCR_TARGET_ASSIST_SUCCESS (0x02) 823 #define MPII_REPLY_DESCR_TARGET_COMMAND_BUFFER (0x03) 824 #define MPII_REPLY_DESCR_UNUSED (0x0f) 825 u_int8_t vf_id; 826 u_int16_t smid; 827 828 union { 829 u_int32_t data; 830 u_int32_t frame_addr; /* Address Reply */ 831 }; 832 } __packed; 833 834 struct mpii_request_header { 835 u_int16_t function_dependent1; 836 u_int8_t chain_offset; 837 u_int8_t function; 838 839 u_int16_t function_dependent2; 840 u_int8_t function_dependent3; 841 u_int8_t message_flags; 842 843 u_int8_t vp_id; 844 u_int8_t vf_id; 845 u_int16_t reserved; 846 } __packed; 847 848 struct mpii_msg_scsi_task_request { 849 u_int16_t dev_handle; 850 u_int8_t chain_offset; 851 u_int8_t function; 852 853 u_int8_t reserved1; 854 u_int8_t task_type; 855 #define MPII_SCSI_TASK_ABORT_TASK (0x01) 856 #define MPII_SCSI_TASK_ABRT_TASK_SET (0x02) 857 #define MPII_SCSI_TASK_TARGET_RESET (0x03) 858 #define MPII_SCSI_TASK_RESET_BUS (0x04) 859 #define MPII_SCSI_TASK_LOGICAL_UNIT_RESET (0x05) 860 u_int8_t reserved2; 861 u_int8_t msg_flags; 862 863 u_int8_t vp_id; 864 u_int8_t vf_id; 865 u_int16_t reserved3; 866 867 u_int16_t lun[4]; 868 869 u_int32_t reserved4[7]; 870 871 u_int16_t task_mid; 872 u_int16_t reserved5; 873 } __packed; 874 875 struct mpii_msg_scsi_task_reply { 876 u_int16_t dev_handle; 877 u_int8_t msg_length; 878 u_int8_t function; 879 880 u_int8_t response_code; 881 u_int8_t task_type; 882 u_int8_t reserved1; 883 u_int8_t msg_flags; 884 885 u_int8_t vp_id; 886 u_int8_t vf_id; 887 u_int16_t reserved2; 888 889 u_int16_t reserved3; 890 u_int16_t ioc_status; 891 892 u_int32_t ioc_loginfo; 893 894 u_int32_t termination_count; 895 } __packed; 896 897 struct mpii_msg_sas_oper_request { 898 u_int8_t operation; 899 #define MPII_SAS_OP_CLEAR_PERSISTENT (0x02) 900 #define MPII_SAS_OP_PHY_LINK_RESET (0x06) 901 #define MPII_SAS_OP_PHY_HARD_RESET (0x07) 902 #define MPII_SAS_OP_PHY_CLEAR_ERROR_LOG (0x08) 903 #define MPII_SAS_OP_SEND_PRIMITIVE (0x0a) 904 #define MPII_SAS_OP_FORCE_FULL_DISCOVERY (0x0b) 905 #define MPII_SAS_OP_TRANSMIT_PORT_SELECT (0x0c) 906 #define MPII_SAS_OP_REMOVE_DEVICE (0x0d) 907 #define MPII_SAS_OP_LOOKUP_MAPPING (0x0e) 908 #define MPII_SAS_OP_SET_IOC_PARAM (0x0f) 909 u_int8_t reserved1; 910 u_int8_t chain_offset; 911 u_int8_t function; 912 913 u_int16_t dev_handle; 914 u_int8_t ioc_param; 915 u_int8_t msg_flags; 916 917 u_int8_t vp_id; 918 u_int8_t vf_id; 919 u_int16_t reserved2; 920 921 u_int16_t reserved3; 922 u_int8_t phy_num; 923 u_int8_t prim_flags; 924 925 u_int32_t primitive; 926 927 u_int8_t lookup_method; 928 #define MPII_SAS_LOOKUP_METHOD_SAS_ADDR (0x01) 929 #define MPII_SAS_LOOKUP_METHOD_SAS_ENCL (0x02) 930 #define MPII_SAS_LOOKUP_METHOD_SAS_DEVNAME (0x03) 931 u_int8_t reserved4; 932 u_int16_t slot_num; 933 934 u_int64_t lookup_addr; 935 936 u_int32_t ioc_param_value; 937 938 u_int64_t reserved5; 939 } __packed; 940 941 struct mpii_msg_sas_oper_reply { 942 u_int8_t operation; 943 u_int8_t reserved1; 944 u_int8_t chain_offset; 945 u_int8_t function; 946 947 u_int16_t dev_handle; 948 u_int8_t ioc_param; 949 u_int8_t msg_flags; 950 951 u_int8_t vp_id; 952 u_int8_t vf_id; 953 u_int16_t reserved2; 954 955 u_int16_t reserved3; 956 u_int16_t ioc_status; 957 958 u_int32_t ioc_loginfo; 959 } __packed; 960 961 struct mpii_msg_raid_action_request { 962 u_int8_t action; 963 #define MPII_RAID_ACTION_CHANGE_VOL_WRITE_CACHE (0x17) 964 u_int8_t reserved1; 965 u_int8_t chain_offset; 966 u_int8_t function; 967 968 u_int16_t vol_dev_handle; 969 u_int8_t phys_disk_num; 970 u_int8_t msg_flags; 971 972 u_int8_t vp_id; 973 u_int8_t vf_if; 974 u_int16_t reserved2; 975 976 u_int32_t reserved3; 977 978 u_int32_t action_data; 979 #define MPII_RAID_VOL_WRITE_CACHE_MASK (0x03) 980 #define MPII_RAID_VOL_WRITE_CACHE_DISABLE (0x01) 981 #define MPII_RAID_VOL_WRITE_CACHE_ENABLE (0x02) 982 983 struct mpii_sge action_sge; 984 } __packed; 985 986 struct mpii_msg_raid_action_reply { 987 u_int8_t action; 988 u_int8_t reserved1; 989 u_int8_t chain_offset; 990 u_int8_t function; 991 992 u_int16_t vol_dev_handle; 993 u_int8_t phys_disk_num; 994 u_int8_t msg_flags; 995 996 u_int8_t vp_id; 997 u_int8_t vf_if; 998 u_int16_t reserved2; 999 1000 u_int16_t reserved3; 1001 u_int16_t ioc_status; 1002 1003 u_int32_t action_data[5]; 1004 } __packed; 1005 1006 struct mpii_cfg_hdr { 1007 u_int8_t page_version; 1008 u_int8_t page_length; 1009 u_int8_t page_number; 1010 u_int8_t page_type; 1011 #define MPII_CONFIG_REQ_PAGE_TYPE_ATTRIBUTE (0xf0) 1012 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 1013 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 1014 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 1015 1016 #define MPII_CONFIG_REQ_PAGE_TYPE_MASK (0x0f) 1017 #define MPII_CONFIG_REQ_PAGE_TYPE_IO_UNIT (0x00) 1018 #define MPII_CONFIG_REQ_PAGE_TYPE_IOC (0x01) 1019 #define MPII_CONFIG_REQ_PAGE_TYPE_BIOS (0x02) 1020 #define MPII_CONFIG_REQ_PAGE_TYPE_RAID_VOL (0x08) 1021 #define MPII_CONFIG_REQ_PAGE_TYPE_MANUFACTURING (0x09) 1022 #define MPII_CONFIG_REQ_PAGE_TYPE_RAID_PD (0x0a) 1023 #define MPII_CONFIG_REQ_PAGE_TYPE_EXTENDED (0x0f) 1024 } __packed; 1025 1026 struct mpii_ecfg_hdr { 1027 u_int8_t page_version; 1028 u_int8_t reserved1; 1029 u_int8_t page_number; 1030 u_int8_t page_type; 1031 1032 u_int16_t ext_page_length; 1033 u_int8_t ext_page_type; 1034 #define MPII_CONFIG_REQ_PAGE_TYPE_SAS_DEVICE (0x12) 1035 #define MPII_CONFIG_REQ_PAGE_TYPE_RAID_CONFIG (0x16) 1036 #define MPII_CONFIG_REQ_PAGE_TYPE_DRIVER_MAPPING (0x17) 1037 u_int8_t reserved2; 1038 } __packed; 1039 1040 struct mpii_msg_config_request { 1041 u_int8_t action; 1042 #define MPII_CONFIG_REQ_ACTION_PAGE_HEADER (0x00) 1043 #define MPII_CONFIG_REQ_ACTION_PAGE_READ_CURRENT (0x01) 1044 #define MPII_CONFIG_REQ_ACTION_PAGE_WRITE_CURRENT (0x02) 1045 #define MPII_CONFIG_REQ_ACTION_PAGE_DEFAULT (0x03) 1046 #define MPII_CONFIG_REQ_ACTION_PAGE_WRITE_NVRAM (0x04) 1047 #define MPII_CONFIG_REQ_ACTION_PAGE_READ_DEFAULT (0x05) 1048 #define MPII_CONFIG_REQ_ACTION_PAGE_READ_NVRAM (0x06) 1049 u_int8_t sgl_flags; 1050 u_int8_t chain_offset; 1051 u_int8_t function; 1052 1053 u_int16_t ext_page_len; 1054 u_int8_t ext_page_type; 1055 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_IO_UNIT (0x10) 1056 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_EXPANDER (0x11) 1057 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_DEVICE (0x12) 1058 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_PHY (0x13) 1059 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_LOG (0x14) 1060 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 1061 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 1062 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 1063 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 1064 u_int8_t msg_flags; 1065 1066 u_int8_t vp_id; 1067 u_int8_t vf_id; 1068 u_int16_t reserved1; 1069 1070 u_int32_t reserved2[2]; 1071 1072 struct mpii_cfg_hdr config_header; 1073 1074 u_int32_t page_address; 1075 /* XXX lots of defns here */ 1076 1077 struct mpii_sge page_buffer; 1078 } __packed; 1079 1080 struct mpii_msg_config_reply { 1081 u_int8_t action; 1082 u_int8_t sgl_flags; 1083 u_int8_t msg_length; 1084 u_int8_t function; 1085 1086 u_int16_t ext_page_length; 1087 u_int8_t ext_page_type; 1088 u_int8_t msg_flags; 1089 1090 u_int8_t vp_id; 1091 u_int8_t vf_id; 1092 u_int16_t reserved1; 1093 1094 u_int16_t reserved2; 1095 u_int16_t ioc_status; 1096 1097 u_int32_t ioc_loginfo; 1098 1099 struct mpii_cfg_hdr config_header; 1100 } __packed; 1101 1102 struct mpii_cfg_manufacturing_pg0 { 1103 struct mpii_cfg_hdr config_header; 1104 1105 char chip_name[16]; 1106 char chip_revision[8]; 1107 char board_name[16]; 1108 char board_assembly[16]; 1109 char board_tracer_number[16]; 1110 } __packed; 1111 1112 struct mpii_cfg_ioc_pg1 { 1113 struct mpii_cfg_hdr config_header; 1114 1115 u_int32_t flags; 1116 1117 u_int32_t coalescing_timeout; 1118 #define MPII_CFG_IOC_1_REPLY_COALESCING (1<<0) 1119 1120 u_int8_t coalescing_depth; 1121 u_int8_t pci_slot_num; 1122 u_int8_t pci_bus_num; 1123 u_int8_t pci_domain_segment; 1124 1125 u_int32_t reserved1; 1126 1127 u_int32_t reserved2; 1128 } __packed; 1129 1130 struct mpii_cfg_ioc_pg3 { 1131 struct mpii_cfg_hdr config_header; 1132 1133 u_int8_t no_phys_disks; 1134 u_int8_t reserved[3]; 1135 1136 /* followed by a list of mpii_cfg_raid_physdisk structs */ 1137 } __packed; 1138 1139 struct mpii_cfg_ioc_pg8 { 1140 struct mpii_cfg_hdr config_header; 1141 1142 u_int8_t num_devs_per_enclosure; 1143 u_int8_t reserved1; 1144 u_int16_t reserved2; 1145 1146 u_int16_t max_persistent_entries; 1147 u_int16_t max_num_physical_mapped_ids; 1148 1149 u_int16_t flags; 1150 #define MPII_IOC_PG8_FLAGS_DA_START_SLOT_1 (1<<5) 1151 #define MPII_IOC_PG8_FLAGS_RESERVED_TARGETID_0 (1<<4) 1152 #define MPII_IOC_PG8_FLAGS_MAPPING_MODE_MASK (0x0000000e) 1153 #define MPII_IOC_PG8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0<<1) 1154 #define MPII_IOC_PG8_FLAGS_ENCLOSURE_SLOT_MAPPING (1<<1) 1155 #define MPII_IOC_PG8_FLAGS_DISABLE_PERSISTENT_MAPPING (1<<0) 1156 #define MPII_IOC_PG8_FLAGS_ENABLE_PERSISTENT_MAPPING (0<<0) 1157 u_int16_t reserved3; 1158 1159 u_int16_t ir_volume_mapping_flags; 1160 #define MPII_IOC_PG8_IRFLAGS_VOLUME_MAPPING_MODE_MASK (0x00000003) 1161 #define MPII_IOC_PG8_IRFLAGS_LOW_VOLUME_MAPPING (0<<0) 1162 #define MPII_IOC_PG8_IRFLAGS_HIGH_VOLUME_MAPPING (1<<0) 1163 u_int16_t reserved4; 1164 1165 u_int32_t reserved5; 1166 } __packed; 1167 1168 struct mpii_cfg_raid_physdisk { 1169 u_int8_t phys_disk_id; 1170 u_int8_t phys_disk_bus; 1171 u_int8_t phys_disk_ioc; 1172 u_int8_t phys_disk_num; 1173 } __packed; 1174 1175 struct mpii_cfg_fc_port_pg0 { 1176 struct mpii_cfg_hdr config_header; 1177 1178 u_int32_t flags; 1179 1180 u_int8_t mpii_port_nr; 1181 u_int8_t link_type; 1182 u_int8_t port_state; 1183 u_int8_t reserved1; 1184 1185 u_int32_t port_id; 1186 1187 u_int64_t wwnn; 1188 1189 u_int64_t wwpn; 1190 1191 u_int32_t supported_service_class; 1192 1193 u_int32_t supported_speeds; 1194 1195 u_int32_t current_speed; 1196 1197 u_int32_t max_frame_size; 1198 1199 u_int64_t fabric_wwnn; 1200 1201 u_int64_t fabric_wwpn; 1202 1203 u_int32_t discovered_port_count; 1204 1205 u_int32_t max_initiators; 1206 1207 u_int8_t max_aliases_supported; 1208 u_int8_t max_hard_aliases_supported; 1209 u_int8_t num_current_aliases; 1210 u_int8_t reserved2; 1211 } __packed; 1212 1213 struct mpii_cfg_fc_port_pg1 { 1214 struct mpii_cfg_hdr config_header; 1215 1216 u_int32_t flags; 1217 1218 u_int64_t noseepromwwnn; 1219 1220 u_int64_t noseepromwwpn; 1221 1222 u_int8_t hard_alpa; 1223 u_int8_t link_config; 1224 u_int8_t topology_config; 1225 u_int8_t alt_connector; 1226 1227 u_int8_t num_req_aliases; 1228 u_int8_t rr_tov; 1229 u_int8_t initiator_dev_to; 1230 u_int8_t initiator_lo_pend_to; 1231 } __packed; 1232 1233 struct mpii_cfg_fc_device_pg0 { 1234 struct mpii_cfg_hdr config_header; 1235 1236 u_int64_t wwnn; 1237 1238 u_int64_t wwpn; 1239 1240 u_int32_t port_id; 1241 1242 u_int8_t protocol; 1243 u_int8_t flags; 1244 u_int16_t bb_credit; 1245 1246 u_int16_t max_rx_frame_size; 1247 u_int8_t adisc_hard_alpa; 1248 u_int8_t port_nr; 1249 1250 u_int8_t fc_ph_low_version; 1251 u_int8_t fc_ph_high_version; 1252 u_int8_t current_target_id; 1253 u_int8_t current_bus; 1254 } __packed; 1255 1256 #define MPII_CFG_RAID_VOL_ADDR_HANDLE (1<<28) 1257 1258 struct mpii_cfg_raid_vol_pg0 { 1259 struct mpii_cfg_hdr config_header; 1260 1261 u_int16_t volume_handle; 1262 u_int8_t volume_state; 1263 #define MPII_CFG_RAID_VOL_0_STATE_MISSING (0x00) 1264 #define MPII_CFG_RAID_VOL_0_STATE_FAILED (0x01) 1265 #define MPII_CFG_RAID_VOL_0_STATE_INITIALIZING (0x02) 1266 #define MPII_CFG_RAID_VOL_0_STATE_ONLINE (0x03) 1267 #define MPII_CFG_RAID_VOL_0_STATE_DEGRADED (0x04) 1268 #define MPII_CFG_RAID_VOL_0_STATE_OPTIMAL (0x05) 1269 u_int8_t volume_type; 1270 #define MPII_CFG_RAID_VOL_0_TYPE_RAID0 (0x00) 1271 #define MPII_CFG_RAID_VOL_0_TYPE_RAID1E (0x01) 1272 #define MPII_CFG_RAID_VOL_0_TYPE_RAID1 (0x02) 1273 #define MPII_CFG_RAID_VOL_0_TYPE_RAID10 (0x05) 1274 #define MPII_CFG_RAID_VOL_0_TYPE_UNKNOWN (0xff) 1275 1276 u_int32_t volume_status; 1277 #define MPII_CFG_RAID_VOL_0_STATUS_SCRUB (1<<20) 1278 #define MPII_CFG_RAID_VOL_0_STATUS_RESYNC (1<<16) 1279 1280 u_int16_t volume_settings; 1281 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_MASK (0x3<<0) 1282 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_UNCHANGED (0x0<<0) 1283 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_DISABLED (0x1<<0) 1284 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_ENABLED (0x2<<0) 1285 1286 u_int8_t hot_spare_pool; 1287 u_int8_t reserved1; 1288 1289 u_int64_t max_lba; 1290 1291 u_int32_t stripe_size; 1292 1293 u_int16_t block_size; 1294 u_int16_t reserved2; 1295 1296 u_int8_t phys_disk_types; 1297 u_int8_t resync_rate; 1298 u_int16_t data_scrub_rate; 1299 1300 u_int8_t num_phys_disks; 1301 u_int16_t reserved3; 1302 u_int8_t inactive_status; 1303 #define MPII_CFG_RAID_VOL_0_INACTIVE_UNKNOWN (0x00) 1304 #define MPII_CFG_RAID_VOL_0_INACTIVE_STALE_META (0x01) 1305 #define MPII_CFG_RAID_VOL_0_INACTIVE_FOREIGN_VOL (0x02) 1306 #define MPII_CFG_RAID_VOL_0_INACTIVE_NO_RESOURCES (0x03) 1307 #define MPII_CFG_RAID_VOL_0_INACTIVE_CLONED_VOL (0x04) 1308 #define MPII_CFG_RAID_VOL_0_INACTIVE_INSUF_META (0x05) 1309 1310 /* followed by a list of mpii_cfg_raid_vol_pg0_physdisk structs */ 1311 } __packed; 1312 1313 struct mpii_cfg_raid_vol_pg0_physdisk { 1314 u_int8_t raid_set_num; 1315 u_int8_t phys_disk_map; 1316 u_int8_t phys_disk_num; 1317 u_int8_t reserved; 1318 } __packed; 1319 1320 struct mpii_cfg_raid_vol_pg1 { 1321 struct mpii_cfg_hdr config_header; 1322 1323 u_int8_t volume_id; 1324 u_int8_t volume_bus; 1325 u_int8_t volume_ioc; 1326 u_int8_t reserved1; 1327 1328 u_int8_t guid[24]; 1329 1330 u_int8_t name[32]; 1331 1332 u_int64_t wwid; 1333 1334 u_int32_t reserved2; 1335 1336 u_int32_t reserved3; 1337 } __packed; 1338 1339 #define MPII_CFG_RAID_PHYS_DISK_ADDR_NUMBER (1<<28) 1340 1341 struct mpii_cfg_raid_physdisk_pg0 { 1342 struct mpii_cfg_hdr config_header; 1343 1344 u_int16_t dev_handle; 1345 u_int8_t reserved1; 1346 u_int8_t phys_disk_num; 1347 1348 u_int8_t enc_id; 1349 u_int8_t enc_bus; 1350 u_int8_t hot_spare_pool; 1351 u_int8_t enc_type; 1352 #define MPII_CFG_RAID_PHYDISK_0_ENCTYPE_NONE (0x0) 1353 #define MPII_CFG_RAID_PHYDISK_0_ENCTYPE_SAFTE (0x1) 1354 #define MPII_CFG_RAID_PHYDISK_0_ENCTYPE_SES (0x2) 1355 1356 u_int32_t reserved2; 1357 1358 u_int8_t vendor_id[8]; 1359 1360 u_int8_t product_id[16]; 1361 1362 u_int8_t product_rev[4]; 1363 1364 u_int8_t serial[32]; 1365 1366 u_int32_t reserved3; 1367 1368 u_int8_t phys_disk_state; 1369 #define MPII_CFG_RAID_PHYDISK_0_STATE_NOTCONFIGURED (0x00) 1370 #define MPII_CFG_RAID_PHYDISK_0_STATE_NOTCOMPATIBLE (0x01) 1371 #define MPII_CFG_RAID_PHYDISK_0_STATE_OFFLINE (0x02) 1372 #define MPII_CFG_RAID_PHYDISK_0_STATE_ONLINE (0x03) 1373 #define MPII_CFG_RAID_PHYDISK_0_STATE_HOTSPARE (0x04) 1374 #define MPII_CFG_RAID_PHYDISK_0_STATE_DEGRADED (0x05) 1375 #define MPII_CFG_RAID_PHYDISK_0_STATE_REBUILDING (0x06) 1376 #define MPII_CFG_RAID_PHYDISK_0_STATE_OPTIMAL (0x07) 1377 u_int8_t offline_reason; 1378 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_MISSING (0x01) 1379 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_FAILED (0x03) 1380 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_INITIALIZING (0x04) 1381 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_REQUESTED (0x05) 1382 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_FAILEDREQ (0x06) 1383 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_OTHER (0xff) 1384 1385 u_int8_t incompat_reason; 1386 u_int8_t phys_disk_attrs; 1387 1388 u_int32_t phys_disk_status; 1389 #define MPII_CFG_RAID_PHYDISK_0_STATUS_OUTOFSYNC (1<<0) 1390 #define MPII_CFG_RAID_PHYDISK_0_STATUS_QUIESCED (1<<1) 1391 1392 u_int64_t dev_max_lba; 1393 1394 u_int64_t host_max_lba; 1395 1396 u_int64_t coerced_max_lba; 1397 1398 u_int16_t block_size; 1399 u_int16_t reserved4; 1400 1401 u_int32_t reserved5; 1402 } __packed; 1403 1404 struct mpii_cfg_raid_physdisk_pg1 { 1405 struct mpii_cfg_hdr config_header; 1406 1407 u_int8_t num_phys_disk_paths; 1408 u_int8_t phys_disk_num; 1409 u_int16_t reserved1; 1410 1411 u_int32_t reserved2; 1412 1413 /* followed by mpii_cfg_raid_physdisk_path structs */ 1414 } __packed; 1415 1416 struct mpii_cfg_raid_physdisk_path { 1417 u_int8_t phys_disk_id; 1418 u_int8_t phys_disk_bus; 1419 u_int16_t reserved1; 1420 1421 u_int64_t wwwid; 1422 1423 u_int64_t owner_wwid; 1424 1425 u_int8_t ownder_id; 1426 u_int8_t reserved2; 1427 u_int16_t flags; 1428 #define MPII_CFG_RAID_PHYDISK_PATH_INVALID (1<<0) 1429 #define MPII_CFG_RAID_PHYDISK_PATH_BROKEN (1<<1) 1430 } __packed; 1431 1432 #define MPII_CFG_SAS_DEV_ADDR_NEXT (0<<28) 1433 #define MPII_CFG_SAS_DEV_ADDR_BUS (1<<28) 1434 #define MPII_CFG_SAS_DEV_ADDR_HANDLE (2<<28) 1435 1436 struct mpii_cfg_sas_dev_pg0 { 1437 struct mpii_ecfg_hdr config_header; 1438 1439 u_int16_t slot; 1440 u_int16_t enc_handle; 1441 1442 u_int64_t sas_addr; 1443 1444 u_int16_t parent_dev_handle; 1445 u_int8_t phy_num; 1446 u_int8_t access_status; 1447 1448 u_int16_t dev_handle; 1449 u_int8_t target; 1450 u_int8_t bus; 1451 1452 u_int32_t device_info; 1453 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE (0x7) 1454 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_NONE (0x0) 1455 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_END (0x1) 1456 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_EDGE_EXPANDER (0x2) 1457 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_FANOUT_EXPANDER (0x3) 1458 #define MPII_CFG_SAS_DEV_0_DEVINFO_SATA_HOST (1<<3) 1459 #define MPII_CFG_SAS_DEV_0_DEVINFO_SMP_INITIATOR (1<<4) 1460 #define MPII_CFG_SAS_DEV_0_DEVINFO_STP_INITIATOR (1<<5) 1461 #define MPII_CFG_SAS_DEV_0_DEVINFO_SSP_INITIATOR (1<<6) 1462 #define MPII_CFG_SAS_DEV_0_DEVINFO_SATA_DEVICE (1<<7) 1463 #define MPII_CFG_SAS_DEV_0_DEVINFO_SMP_TARGET (1<<8) 1464 #define MPII_CFG_SAS_DEV_0_DEVINFO_STP_TARGET (1<<9) 1465 #define MPII_CFG_SAS_DEV_0_DEVINFO_SSP_TARGET (1<<10) 1466 #define MPII_CFG_SAS_DEV_0_DEVINFO_DIRECT_ATTACHED (1<<11) 1467 #define MPII_CFG_SAS_DEV_0_DEVINFO_LSI_DEVICE (1<<12) 1468 #define MPII_CFG_SAS_DEV_0_DEVINFO_ATAPI_DEVICE (1<<13) 1469 #define MPII_CFG_SAS_DEV_0_DEVINFO_SEP_DEVICE (1<<14) 1470 1471 u_int16_t flags; 1472 #define MPII_CFG_SAS_DEV_0_FLAGS_DEV_PRESENT (1<<0) 1473 #define MPII_CFG_SAS_DEV_0_FLAGS_DEV_MAPPED (1<<1) 1474 #define MPII_CFG_SAS_DEV_0_FLAGS_DEV_MAPPED_PERSISTENT (1<<2) 1475 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_PORT_SELECTOR (1<<3) 1476 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_FUA (1<<4) 1477 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_NCQ (1<<5) 1478 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_SMART (1<<6) 1479 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_LBA48 (1<<7) 1480 #define MPII_CFG_SAS_DEV_0_FLAGS_UNSUPPORTED (1<<8) 1481 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_SETTINGS (1<<9) 1482 u_int8_t physical_port; 1483 u_int8_t max_port_conn; 1484 1485 u_int64_t device_name; 1486 1487 u_int8_t port_groups; 1488 u_int8_t dma_group; 1489 u_int8_t ctrl_group; 1490 u_int8_t reserved1; 1491 1492 u_int64_t reserved2; 1493 } __packed; 1494 1495 #define MPII_CFG_RAID_CONFIG_ACTIVE_CONFIG (2<<28) 1496 1497 struct mpii_cfg_raid_config_pg0 { 1498 struct mpii_ecfg_hdr config_header; 1499 1500 u_int8_t num_hot_spares; 1501 u_int8_t num_phys_disks; 1502 u_int8_t num_volumes; 1503 u_int8_t config_num; 1504 1505 u_int32_t flags; 1506 #define MPII_CFG_RAID_CONFIG_0_FLAGS_NATIVE (0<<0) 1507 #define MPII_CFG_RAID_CONFIG_0_FLAGS_FOREIGN (1<<0) 1508 1509 u_int32_t config_guid[6]; 1510 1511 u_int32_t reserved1; 1512 1513 u_int8_t num_elements; 1514 u_int8_t reserved2[3]; 1515 1516 /* followed by struct mpii_raid_config_element structs */ 1517 } __packed; 1518 1519 struct mpii_raid_config_element { 1520 u_int16_t element_flags; 1521 #define MPII_RAID_CONFIG_ELEMENT_FLAG_VOLUME (0x0) 1522 #define MPII_RAID_CONFIG_ELEMENT_FLAG_VOLUME_PHYS_DISK (0x1) 1523 #define MPII_RAID_CONFIG_ELEMENT_FLAG_HSP_PHYS_DISK (0x2) 1524 #define MPII_RAID_CONFIG_ELEMENT_ONLINE_CE_PHYS_DISK (0x3) 1525 u_int16_t vol_dev_handle; 1526 1527 u_int8_t hot_spare_pool; 1528 u_int8_t phys_disk_num; 1529 u_int16_t phys_disk_dev_handle; 1530 } __packed; 1531 1532 struct mpii_cfg_dpm_pg0 { 1533 struct mpii_ecfg_hdr config_header; 1534 #define MPII_DPM_ADDRESS_FORM_MASK (0xf0000000) 1535 #define MPII_DPM_ADDRESS_FORM_ENTRY_RANGE (0x00000000) 1536 #define MPII_DPM_ADDRESS_ENTRY_COUNT_MASK (0x0fff0000) 1537 #define MPII_DPM_ADDRESS_ENTRY_COUNT_SHIFT (16) 1538 #define MPII_DPM_ADDRESS_START_ENTRY_MASK (0x0000ffff) 1539 1540 /* followed by struct mpii_dpm_entry structs */ 1541 } __packed; 1542 1543 struct mpii_dpm_entry { 1544 u_int64_t physical_identifier; 1545 1546 u_int16_t mapping_information; 1547 u_int16_t device_index; 1548 1549 u_int32_t physical_bits_mapping; 1550 1551 u_int32_t reserved1; 1552 } __packed; 1553 1554 struct mpii_evt_sas_discovery { 1555 u_int8_t flags; 1556 #define MPII_EVENT_SAS_DISC_FLAGS_DEV_CHANGE_MASK (1<<1) 1557 #define MPII_EVENT_SAS_DISC_FLAGS_DEV_CHANGE_NO_CHANGE (0<<1) 1558 #define MPII_EVENT_SAS_DISC_FLAGS_DEV_CHANGE_CHANGE (1<<1) 1559 #define MPII_EVENT_SAS_DISC_FLAGS_DISC_IN_PROG_MASK (1<<0) 1560 #define MPII_EVENT_SAS_DISC_FLAGS_DISC_NOT_IN_PROGRESS (1<<0) 1561 #define MPII_EVENT_SAS_DISC_FLAGS_DISC_IN_PROGRESS (0<<0) 1562 u_int8_t reason_code; 1563 #define MPII_EVENT_SAS_DISC_REASON_CODE_STARTED (0x01) 1564 #define MPII_EVENT_SAS_DISC_REASON_CODE_COMPLETED (0x02) 1565 u_int8_t physical_port; 1566 u_int8_t reserved1; 1567 1568 u_int32_t discovery_status; 1569 } __packed; 1570 1571 struct mpii_evt_ir_status { 1572 u_int16_t vol_dev_handle; 1573 u_int16_t reserved1; 1574 1575 u_int8_t operation; 1576 #define MPII_EVENT_IR_RAIDOP_RESYNC (0x00) 1577 #define MPII_EVENT_IR_RAIDOP_OCE (0x01) 1578 #define MPII_EVENT_IR_RAIDOP_CONS_CHECK (0x02) 1579 #define MPII_EVENT_IR_RAIDOP_BG_INIT (0x03) 1580 #define MPII_EVENT_IR_RAIDOP_MAKE_CONS (0x04) 1581 u_int8_t percent; 1582 u_int16_t reserved2; 1583 1584 u_int32_t reserved3; 1585 }; 1586 1587 struct mpii_evt_ir_volume { 1588 u_int16_t vol_dev_handle; 1589 u_int8_t reason_code; 1590 #define MPII_EVENT_IR_VOL_RC_SETTINGS_CHANGED (0x01) 1591 #define MPII_EVENT_IR_VOL_RC_STATUS_CHANGED (0x02) 1592 #define MPII_EVENT_IR_VOL_RC_STATE_CHANGED (0x03) 1593 u_int8_t reserved1; 1594 1595 u_int32_t new_value; 1596 u_int32_t prev_value; 1597 } __packed; 1598 1599 struct mpii_evt_ir_physical_disk { 1600 u_int16_t reserved1; 1601 u_int8_t reason_code; 1602 #define MPII_EVENT_IR_PD_RC_SETTINGS_CHANGED (0x01) 1603 #define MPII_EVENT_IR_PD_RC_STATUS_FLAGS_CHANGED (0x02) 1604 #define MPII_EVENT_IR_PD_RC_STATUS_CHANGED (0x03) 1605 u_int8_t phys_disk_num; 1606 1607 u_int16_t phys_disk_dev_handle; 1608 u_int16_t reserved2; 1609 1610 u_int16_t slot; 1611 u_int16_t enclosure_handle; 1612 1613 u_int32_t new_value; 1614 u_int32_t previous_value; 1615 } __packed; 1616 1617 struct mpii_evt_sas_tcl { 1618 u_int16_t enclosure_handle; 1619 u_int16_t expander_handle; 1620 1621 u_int8_t num_phys; 1622 u_int8_t reserved1[3]; 1623 1624 u_int8_t num_entries; 1625 u_int8_t start_phy_num; 1626 u_int8_t expn_status; 1627 #define MPII_EVENT_SAS_TOPO_ES_ADDED (0x01) 1628 #define MPII_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 1629 #define MPII_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 1630 #define MPII_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 1631 u_int8_t physical_port; 1632 1633 /* followed by num_entries number of struct mpii_evt_phy_entry */ 1634 } __packed; 1635 1636 struct mpii_evt_phy_entry { 1637 u_int16_t dev_handle; 1638 u_int8_t link_rate; 1639 u_int8_t phy_status; 1640 #define MPII_EVENT_SAS_TOPO_PS_RC_MASK (0x0f) 1641 #define MPII_EVENT_SAS_TOPO_PS_RC_ADDED (0x01) 1642 #define MPII_EVENT_SAS_TOPO_PS_RC_MISSING (0x02) 1643 } __packed; 1644 1645 struct mpii_evt_ir_cfg_change_list { 1646 u_int8_t num_elements; 1647 u_int16_t reserved; 1648 u_int8_t config_num; 1649 1650 u_int32_t flags; 1651 #define MPII_EVT_IR_CFG_CHANGE_LIST_FOREIGN (0x1) 1652 1653 /* followed by num_elements struct mpii_evt_ir_cfg_elements */ 1654 } __packed; 1655 1656 struct mpii_evt_ir_cfg_element { 1657 u_int16_t element_flags; 1658 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_MASK (0xf) 1659 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_VOLUME (0x0) 1660 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_VOLUME_DISK (0x1) 1661 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_HOT_SPARE (0x2) 1662 u_int16_t vol_dev_handle; 1663 1664 u_int8_t reason_code; 1665 #define MPII_EVT_IR_CFG_ELEMENT_RC_ADDED (0x01) 1666 #define MPII_EVT_IR_CFG_ELEMENT_RC_REMOVED (0x02) 1667 #define MPII_EVT_IR_CFG_ELEMENT_RC_NO_CHANGE (0x03) 1668 #define MPII_EVT_IR_CFG_ELEMENT_RC_HIDE (0x04) 1669 #define MPII_EVT_IR_CFG_ELEMENT_RC_UNHIDE (0x05) 1670 #define MPII_EVT_IR_CFG_ELEMENT_RC_VOLUME_CREATED (0x06) 1671 #define MPII_EVT_IR_CFG_ELEMENT_RC_VOLUME_DELETED (0x07) 1672 #define MPII_EVT_IR_CFG_ELEMENT_RC_PD_CREATED (0x08) 1673 #define MPII_EVT_IR_CFG_ELEMENT_RC_PD_DELETED (0x09) 1674 u_int8_t phys_disk_num; 1675 u_int16_t phys_disk_dev_handle; 1676 } __packed; 1677
Indexes created Tue Sep 30 11:09:46 GMT 2025