mpiireg.h revision 1.2
1 /* $NetBSD: mpiireg.h,v 1.2 2018/12/03 22:34:36 bouyer Exp $ */ 2 /* $OpenBSD: mpiireg.h,v 1.13 2018/06/19 10:32:41 jmatthew Exp $ */ 3 /* 4 * Copyright (c) 2010 Mike Belopuhov 5 * Copyright (c) 2009 James Giannoules 6 * Copyright (c) 2005 - 2010 David Gwynne <dlg (at) openbsd.org> 7 * Copyright (c) 2005 - 2010 Marco Peereboom <marco (at) openbsd.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 #define MPII_DOORBELL (0x00) 23 /* doorbell read bits */ 24 #define MPII_DOORBELL_STATE (0xf<<28) /* ioc state */ 25 #define MPII_DOORBELL_STATE_RESET (0x0<<28) 26 #define MPII_DOORBELL_STATE_READY (0x1<<28) 27 #define MPII_DOORBELL_STATE_OPER (0x2<<28) 28 #define MPII_DOORBELL_STATE_FAULT (0x4<<28) 29 #define MPII_DOORBELL_INUSE (0x1<<27) /* doorbell used */ 30 #define MPII_DOORBELL_WHOINIT (0x7<<24) /* last to reset ioc */ 31 #define MPII_DOORBELL_WHOINIT_NOONE (0x0<<24) /* not initialized */ 32 #define MPII_DOORBELL_WHOINIT_SYSBIOS (0x1<<24) /* system bios */ 33 #define MPII_DOORBELL_WHOINIT_ROMBIOS (0x2<<24) /* rom bios */ 34 #define MPII_DOORBELL_WHOINIT_PCIPEER (0x3<<24) /* pci peer */ 35 #define MPII_DOORBELL_WHOINIT_DRIVER (0x4<<24) /* host driver */ 36 #define MPII_DOORBELL_WHOINIT_MANUFACT (0x5<<24) /* manufacturing */ 37 #define MPII_DOORBELL_FAULT (0xffff<<0) /* fault code */ 38 /* doorbell write bits */ 39 #define MPII_DOORBELL_FUNCTION_SHIFT (24) 40 #define MPII_DOORBELL_FUNCTION_MASK (0xff << MPII_DOORBELL_FUNCTION_SHIFT) 41 #define MPII_DOORBELL_FUNCTION(x) \ 42 (((x) << MPII_DOORBELL_FUNCTION_SHIFT) & MPII_DOORBELL_FUNCTION_MASK) 43 #define MPII_DOORBELL_DWORDS_SHIFT 16 44 #define MPII_DOORBELL_DWORDS_MASK (0xff << MPII_DOORBELL_DWORDS_SHIFT) 45 #define MPII_DOORBELL_DWORDS(x) \ 46 (((x) << MPII_DOORBELL_DWORDS_SHIFT) & MPII_DOORBELL_DWORDS_MASK) 47 #define MPII_DOORBELL_DATA_MASK (0xffff) 48 49 #define MPII_WRITESEQ (0x04) 50 #define MPII_WRITESEQ_KEY_VALUE_MASK (0x0000000f) /* key value */ 51 #define MPII_WRITESEQ_FLUSH (0x00) 52 #define MPII_WRITESEQ_1 (0x0f) 53 #define MPII_WRITESEQ_2 (0x04) 54 #define MPII_WRITESEQ_3 (0x0b) 55 #define MPII_WRITESEQ_4 (0x02) 56 #define MPII_WRITESEQ_5 (0x07) 57 #define MPII_WRITESEQ_6 (0x0d) 58 59 #define MPII_HOSTDIAG (0x08) 60 #define MPII_HOSTDIAG_BDS_MASK (0x00001800) /* boot device select */ 61 #define MPII_HOSTDIAG_BDS_DEFAULT (0<<11) /* default address map, flash */ 62 #define MPII_HOSTDIAG_BDS_HCDW (1<<11) /* host code and data window */ 63 #define MPII_HOSTDIAG_CLEARFBS (1<<10) /* clear flash bad sig */ 64 #define MPII_HOSTDIAG_FORCE_HCB_ONBOOT (1<<9) /* force host controlled boot */ 65 #define MPII_HOSTDIAG_HCB_MODE (1<<8) /* host controlled boot mode */ 66 #define MPII_HOSTDIAG_DWRE (1<<7) /* diag reg write enabled */ 67 #define MPII_HOSTDIAG_FBS (1<<6) /* flash bad sig */ 68 #define MPII_HOSTDIAG_RESET_HIST (1<<5) /* reset history */ 69 #define MPII_HOSTDIAG_DIAGWR_EN (1<<4) /* diagnostic write enabled */ 70 #define MPII_HOSTDIAG_RESET_ADAPTER (1<<2) /* reset adapter */ 71 #define MPII_HOSTDIAG_HOLD_IOC_RESET (1<<1) /* hold ioc in reset */ 72 #define MPII_HOSTDIAG_DIAGMEM_EN (1<<0) /* diag mem enable */ 73 74 #define MPII_DIAGRWDATA (0x10) 75 76 #define MPII_DIAGRWADDRLOW (0x14) 77 78 #define MPII_DIAGRWADDRHIGH (0x18) 79 80 #define MPII_INTR_STATUS (0x30) 81 #define MPII_INTR_STATUS_SYS2IOCDB (1<<31) /* ioc written to by host */ 82 #define MPII_INTR_STATUS_RESET (1<<30) /* physical ioc reset */ 83 #define MPII_INTR_STATUS_REPLY (1<<3) /* reply message interrupt */ 84 #define MPII_INTR_STATUS_IOC2SYSDB (1<<0) /* ioc write to doorbell */ 85 86 #define MPII_INTR_MASK (0x34) 87 #define MPII_INTR_MASK_RESET (1<<30) /* ioc reset intr mask */ 88 #define MPII_INTR_MASK_REPLY (1<<3) /* reply message intr mask */ 89 #define MPII_INTR_MASK_DOORBELL (1<<0) /* doorbell interrupt mask */ 90 91 #define MPII_DCR_DATA (0x38) 92 93 #define MPII_DCR_ADDRESS (0x3c) 94 95 #define MPII_REPLY_FREE_HOST_INDEX (0x48) 96 97 #define MPII_REPLY_POST_HOST_INDEX (0x6c) 98 99 #define MPII_HCB_SIZE (0x74) 100 101 #define MPII_HCB_ADDRESS_LOW (0x78) 102 #define MPII_HCB_ADDRESS_HIGH (0x7c) 103 104 #define MPII_REQ_DESCR_POST_LOW (0xc0) 105 #define MPII_REQ_DESCR_POST_HIGH (0xc4) 106 107 /* 108 * Scatter Gather Lists 109 */ 110 111 #define MPII_SGE_FL_LAST (0x1<<31) /* last element in segment */ 112 #define MPII_SGE_FL_EOB (0x1<<30) /* last element of buffer */ 113 #define MPII_SGE_FL_TYPE (0x3<<28) /* element type */ 114 #define MPII_SGE_FL_TYPE_SIMPLE (0x1<<28) /* simple element */ 115 #define MPII_SGE_FL_TYPE_CHAIN (0x3<<28) /* chain element */ 116 #define MPII_SGE_FL_TYPE_XACTCTX (0x0<<28) /* transaction context */ 117 #define MPII_SGE_FL_LOCAL (0x1<<27) /* local address */ 118 #define MPII_SGE_FL_DIR (0x1<<26) /* direction */ 119 #define MPII_SGE_FL_DIR_OUT (0x1<<26) 120 #define MPII_SGE_FL_DIR_IN (0x0<<26) 121 #define MPII_SGE_FL_SIZE (0x1<<25) /* address size */ 122 #define MPII_SGE_FL_SIZE_32 (0x0<<25) 123 #define MPII_SGE_FL_SIZE_64 (0x1<<25) 124 #define MPII_SGE_FL_EOL (0x1<<24) /* end of list */ 125 126 struct mpii_sge { 127 u_int32_t sg_hdr; 128 u_int32_t sg_addr_lo; 129 u_int32_t sg_addr_hi; 130 } __packed __aligned(4); 131 132 /* 133 * SAS3 (IEEE) Scatter Gather Lists 134 */ 135 136 #define MPII_IEEE_SGE_ADDR_MASK (0x03) 137 #define MPII_IEEE_SGE_ADDR_SYSTEM (0x00) 138 #define MPII_IEEE_SGE_ADDR_IOCDDR (0x01) 139 #define MPII_IEEE_SGE_ADDR_IOCPLB (0x02) 140 #define MPII_IEEE_SGE_ADDR_IOCPLBNTA (0x03) 141 #define MPII_IEEE_SGE_END_OF_LIST (0x40) 142 #define MPII_IEEE_SGE_CHAIN_ELEMENT (0x80) 143 144 struct mpii_ieee_sge { 145 u_int64_t sg_addr; 146 u_int32_t sg_len; 147 u_int16_t _reserved; 148 u_int8_t sg_next_chain_offset; 149 u_int8_t sg_flags; 150 } __packed __aligned(8); 151 152 struct mpii_fw_tce { 153 u_int8_t reserved1; 154 u_int8_t context_size; 155 u_int8_t details_length; 156 u_int8_t flags; 157 158 u_int32_t reserved2; 159 160 u_int32_t image_offset; 161 162 u_int32_t image_size; 163 } __packed __aligned(4); 164 165 /* 166 * Messages 167 */ 168 169 /* functions */ 170 #define MPII_FUNCTION_SCSI_IO_REQUEST (0x00) 171 #define MPII_FUNCTION_SCSI_TASK_MGMT (0x01) 172 #define MPII_FUNCTION_IOC_INIT (0x02) 173 #define MPII_FUNCTION_IOC_FACTS (0x03) 174 #define MPII_FUNCTION_CONFIG (0x04) 175 #define MPII_FUNCTION_PORT_FACTS (0x05) 176 #define MPII_FUNCTION_PORT_ENABLE (0x06) 177 #define MPII_FUNCTION_EVENT_NOTIFICATION (0x07) 178 #define MPII_FUNCTION_EVENT_ACK (0x08) 179 #define MPII_FUNCTION_FW_DOWNLOAD (0x09) 180 #define MPII_FUNCTION_TARGET_CMD_BUFFER_POST (0x0a) 181 #define MPII_FUNCTION_TARGET_ASSIST (0x0b) 182 #define MPII_FUNCTION_TARGET_STATUS_SEND (0x0c) 183 #define MPII_FUNCTION_TARGET_MODE_ABORT (0x0d) 184 #define MPII_FUNCTION_FW_UPLOAD (0x12) 185 186 #define MPII_FUNCTION_RAID_ACTION (0x15) 187 #define MPII_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) 188 189 #define MPII_FUNCTION_TOOLBOX (0x17) 190 191 #define MPII_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) 192 193 #define MPII_FUNCTION_SMP_PASSTHROUGH (0x1a) 194 #define MPII_FUNCTION_SAS_IO_UNIT_CONTROL (0x1b) 195 #define MPII_FUNCTION_SATA_PASSTHROUGH (0x1c) 196 197 #define MPII_FUNCTION_DIAG_BUFFER_POST (0x1d) 198 #define MPII_FUNCTION_DIAG_RELEASE (0x1e) 199 200 #define MPII_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) 201 #define MPII_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) 202 203 #define MPII_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 204 #define MPII_FUNCTION_IO_UNIT_RESET (0x41) 205 #define MPII_FUNCTION_HANDSHAKE (0x42) 206 207 /* Common IOCStatus values for all replies */ 208 #define MPII_IOCSTATUS_MASK (0x7fff) 209 #define MPII_IOCSTATUS_SUCCESS (0x0000) 210 #define MPII_IOCSTATUS_INVALID_FUNCTION (0x0001) 211 #define MPII_IOCSTATUS_BUSY (0x0002) 212 #define MPII_IOCSTATUS_INVALID_SGL (0x0003) 213 #define MPII_IOCSTATUS_INTERNAL_ERROR (0x0004) 214 #define MPII_IOCSTATUS_INVALID_VPID (0x0005) 215 #define MPII_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 216 #define MPII_IOCSTATUS_INVALID_FIELD (0x0007) 217 #define MPII_IOCSTATUS_INVALID_STATE (0x0008) 218 #define MPII_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 219 /* Config IOCStatus values */ 220 #define MPII_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 221 #define MPII_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 222 #define MPII_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 223 #define MPII_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 224 #define MPII_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 225 #define MPII_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 226 /* SCSIIO Reply initiator values */ 227 #define MPII_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 228 #define MPII_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 229 #define MPII_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 230 #define MPII_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 231 #define MPII_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 232 #define MPII_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 233 #define MPII_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 234 #define MPII_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 235 #define MPII_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 236 #define MPII_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004a) 237 #define MPII_IOCSTATUS_SCSI_IOC_TERMINATED (0x004b) 238 #define MPII_IOCSTATUS_SCSI_EXT_TERMINATED (0x004c) 239 /* For use by SCSI Initiator and SCSI Target end-to-end data protection */ 240 #define MPII_IOCSTATUS_EEDP_GUARD_ERROR (0x004d) 241 #define MPII_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004e) 242 #define MPII_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004f) 243 /* SCSI (SPI & FCP) target values */ 244 #define MPII_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 245 #define MPII_IOCSTATUS_TARGET_ABORTED (0x0063) 246 #define MPII_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 247 #define MPII_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 248 #define MPII_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006a) 249 #define MPII_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006d) 250 #define MPII_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006e) 251 #define MPII_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006f) 252 #define MPII_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 253 #define MPII_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 254 /* Serial Attached SCSI values */ 255 #define MPII_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 256 #define MPII_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 257 /* Diagnostic Tools values */ 258 #define MPII_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00a0) 259 260 #define MPII_REP_IOCLOGINFO_TYPE (0xf<<28) 261 #define MPII_REP_IOCLOGINFO_TYPE_NONE (0x0<<28) 262 #define MPII_REP_IOCLOGINFO_TYPE_SCSI (0x1<<28) 263 #define MPII_REP_IOCLOGINFO_TYPE_FC (0x2<<28) 264 #define MPII_REP_IOCLOGINFO_TYPE_SAS (0x3<<28) 265 #define MPII_REP_IOCLOGINFO_TYPE_ISCSI (0x4<<28) 266 #define MPII_REP_IOCLOGINFO_DATA (0x0fffffff) 267 268 /* event notification types */ 269 #define MPII_EVENT_NONE (0x00) 270 #define MPII_EVENT_LOG_DATA (0x01) 271 #define MPII_EVENT_STATE_CHANGE (0x02) 272 #define MPII_EVENT_HARD_RESET_RECEIVED (0x05) 273 #define MPII_EVENT_EVENT_CHANGE (0x0a) 274 #define MPII_EVENT_TASK_SET_FULL (0x0e) 275 #define MPII_EVENT_SAS_DEVICE_STATUS_CHANGE (0x0f) 276 #define MPII_EVENT_IR_OPERATION_STATUS (0x14) 277 #define MPII_EVENT_SAS_DISCOVERY (0x16) 278 #define MPII_EVENT_SAS_BROADCAST_PRIMITIVE (0x17) 279 #define MPII_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x18) 280 #define MPII_EVENT_SAS_INIT_TABLE_OVERFLOW (0x19) 281 #define MPII_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x1c) 282 #define MPII_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x1d) 283 #define MPII_EVENT_IR_VOLUME (0x1e) 284 #define MPII_EVENT_IR_PHYSICAL_DISK (0x1f) 285 #define MPII_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x20) 286 #define MPII_EVENT_LOG_ENTRY_ADDED (0x21) 287 288 /* messages */ 289 290 #define MPII_WHOINIT_NOONE (0x00) 291 #define MPII_WHOINIT_SYSTEM_BIOS (0x01) 292 #define MPII_WHOINIT_ROM_BIOS (0x02) 293 #define MPII_WHOINIT_PCI_PEER (0x03) 294 #define MPII_WHOINIT_HOST_DRIVER (0x04) 295 #define MPII_WHOINIT_MANUFACTURER (0x05) 296 297 /* default messages */ 298 299 struct mpii_msg_request { 300 u_int8_t reserved1; 301 u_int8_t reserved2; 302 u_int8_t chain_offset; 303 u_int8_t function; 304 305 u_int8_t reserved3; 306 u_int8_t reserved4; 307 u_int8_t reserved5; 308 u_int8_t msg_flags; 309 310 u_int8_t vp_id; 311 u_int8_t vf_id; 312 u_int16_t reserved6; 313 } __packed __aligned(4); 314 315 struct mpii_msg_reply { 316 u_int16_t reserved1; 317 u_int8_t msg_length; 318 u_int8_t function; 319 320 u_int16_t reserved2; 321 u_int8_t reserved3; 322 u_int8_t msg_flags; 323 324 u_int8_t vp_id; 325 u_int8_t vf_if; 326 u_int16_t reserved4; 327 328 u_int16_t reserved5; 329 u_int16_t ioc_status; 330 331 u_int32_t ioc_loginfo; 332 } __packed __aligned(4); 333 334 /* ioc init */ 335 336 struct mpii_msg_iocinit_request { 337 u_int8_t whoinit; 338 u_int8_t reserved1; 339 u_int8_t chain_offset; 340 u_int8_t function; 341 342 u_int16_t reserved2; 343 u_int8_t reserved3; 344 u_int8_t msg_flags; 345 346 u_int8_t vp_id; 347 u_int8_t vf_id; 348 u_int16_t reserved4; 349 350 u_int8_t msg_version_min; 351 u_int8_t msg_version_maj; 352 u_int8_t hdr_version_unit; 353 u_int8_t hdr_version_dev; 354 355 u_int32_t reserved5; 356 357 u_int32_t reserved6; 358 359 u_int16_t reserved7; 360 u_int16_t system_request_frame_size; 361 362 u_int16_t reply_descriptor_post_queue_depth; 363 u_int16_t reply_free_queue_depth; 364 365 u_int32_t sense_buffer_address_high; 366 367 u_int32_t system_reply_address_high; 368 369 u_int32_t system_request_frame_base_address_lo; 370 u_int32_t system_request_frame_base_address_hi; 371 372 u_int32_t reply_descriptor_post_queue_address_lo; 373 u_int32_t reply_descriptor_post_queue_address_hi; 374 375 u_int32_t reply_free_queue_address_lo; 376 u_int32_t reply_free_queue_address_hi; 377 378 u_int64_t timestamp; 379 } __packed __aligned(4); 380 381 struct mpii_msg_iocinit_reply { 382 u_int8_t whoinit; 383 u_int8_t reserved1; 384 u_int8_t msg_length; 385 u_int8_t function; 386 387 u_int16_t reserved2; 388 u_int8_t reserved3; 389 u_int8_t msg_flags; 390 391 u_int8_t vp_id; 392 u_int8_t vf_id; 393 u_int16_t reserved4; 394 395 u_int16_t reserved5; 396 u_int16_t ioc_status; 397 398 u_int32_t ioc_loginfo; 399 } __packed __aligned(4); 400 401 struct mpii_msg_iocfacts_request { 402 u_int16_t reserved1; 403 u_int8_t chain_offset; 404 u_int8_t function; 405 406 u_int16_t reserved2; 407 u_int8_t reserved3; 408 u_int8_t msg_flags; 409 410 u_int8_t vp_id; 411 u_int8_t vf_id; 412 u_int16_t reserved4; 413 } __packed __aligned(4); 414 415 struct mpii_msg_iocfacts_reply { 416 u_int8_t msg_version_min; 417 u_int8_t msg_version_maj; 418 u_int8_t msg_length; 419 u_int8_t function; 420 421 u_int8_t header_version_dev; 422 u_int8_t header_version_unit; 423 u_int8_t ioc_number; 424 u_int8_t msg_flags; 425 426 u_int8_t vp_id; 427 u_int8_t vf_id; 428 u_int16_t reserved1; 429 430 u_int16_t ioc_exceptions; 431 #define MPII_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (1<<0) 432 #define MPII_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (1<<1) 433 #define MPII_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (1<<2) 434 #define MPII_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (1<<3) 435 #define MPII_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (1<<4) 436 #define MPII_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAC (1<<8) 437 /* XXX JPG BOOT_STATUS in bits[7:5] */ 438 /* XXX JPG all these #defines need to be fixed up */ 439 u_int16_t ioc_status; 440 441 u_int32_t ioc_loginfo; 442 443 u_int8_t max_chain_depth; 444 u_int8_t whoinit; 445 u_int8_t number_of_ports; 446 u_int8_t reserved2; 447 448 u_int16_t request_credit; 449 u_int16_t product_id; 450 451 u_int32_t ioc_capabilities; 452 #define MPII_IOCFACTS_CAPABILITY_EVENT_REPLAY (1<<13) 453 #define MPII_IOCFACTS_CAPABILITY_INTEGRATED_RAID (1<<12) 454 #define MPII_IOCFACTS_CAPABILITY_TLR (1<<11) 455 #define MPII_IOCFACTS_CAPABILITY_MULTICAST (1<<8) 456 #define MPII_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (1<<7) 457 #define MPII_IOCFACTS_CAPABILITY_EEDP (1<<6) 458 #define MPII_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (1<<4) 459 #define MPII_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (1<<3) 460 #define MPII_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (1<<2) 461 462 u_int8_t fw_version_dev; 463 u_int8_t fw_version_unit; 464 u_int8_t fw_version_min; 465 u_int8_t fw_version_maj; 466 467 u_int16_t ioc_request_frame_size; 468 u_int16_t reserved3; 469 470 u_int16_t max_initiators; 471 u_int16_t max_targets; 472 473 u_int16_t max_sas_expanders; 474 u_int16_t max_enclosures; 475 476 u_int16_t protocol_flags; 477 u_int16_t high_priority_credit; 478 479 u_int16_t max_reply_descriptor_post_queue_depth; 480 u_int8_t reply_frame_size; 481 u_int8_t max_volumes; 482 483 u_int16_t max_dev_handle; 484 u_int16_t max_persistent_entries; 485 486 u_int32_t reserved4; 487 } __packed __aligned(4); 488 489 struct mpii_msg_portfacts_request { 490 u_int16_t reserved1; 491 u_int8_t chain_offset; 492 u_int8_t function; 493 494 u_int16_t reserved2; 495 u_int8_t port_number; 496 u_int8_t msg_flags; 497 498 u_int8_t vp_id; 499 u_int8_t vf_id; 500 u_int16_t reserved3; 501 } __packed __aligned(4); 502 503 struct mpii_msg_portfacts_reply { 504 u_int16_t reserved1; 505 u_int8_t msg_length; 506 u_int8_t function; 507 508 u_int16_t reserved2; 509 u_int8_t port_number; 510 u_int8_t msg_flags; 511 512 u_int8_t vp_id; 513 u_int8_t vf_id; 514 u_int16_t reserved3; 515 516 u_int16_t reserved4; 517 u_int16_t ioc_status; 518 519 u_int32_t ioc_loginfo; 520 521 u_int8_t reserved5; 522 u_int8_t port_type; 523 #define MPII_PORTFACTS_PORTTYPE_INACTIVE (0x00) 524 #define MPII_PORTFACTS_PORTTYPE_FC (0x10) 525 #define MPII_PORTFACTS_PORTTYPE_ISCSI (0x20) 526 #define MPII_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 527 #define MPII_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 528 #define MPII_PORTFACTS_PORTTYPE_TRI_MODE (0x40) 529 u_int16_t reserved6; 530 531 u_int16_t max_posted_cmd_buffers; 532 u_int16_t reserved7; 533 } __packed __aligned(4); 534 535 struct mpii_msg_portenable_request { 536 u_int16_t reserved1; 537 u_int8_t chain_offset; 538 u_int8_t function; 539 540 u_int8_t reserved2; 541 u_int8_t port_flags; 542 u_int8_t reserved3; 543 u_int8_t msg_flags; 544 545 u_int8_t vp_id; 546 u_int8_t vf_id; 547 u_int16_t reserved4; 548 } __packed __aligned(4); 549 550 struct mpii_msg_portenable_reply { 551 u_int16_t reserved1; 552 u_int8_t msg_length; 553 u_int8_t function; 554 555 u_int8_t reserved2; 556 u_int8_t port_flags; 557 u_int8_t reserved3; 558 u_int8_t msg_flags; 559 560 u_int8_t vp_id; 561 u_int8_t vf_id; 562 u_int16_t reserved4; 563 564 u_int16_t reserved5; 565 u_int16_t ioc_status; 566 567 u_int32_t ioc_loginfo; 568 } __packed __aligned(4); 569 570 struct mpii_msg_event_request { 571 u_int16_t reserved1; 572 u_int8_t chain_offset; 573 u_int8_t function; 574 575 u_int16_t reserved2; 576 u_int8_t reserved3; 577 u_int8_t msg_flags; 578 579 u_int8_t vp_id; 580 u_int8_t vf_id; 581 u_int16_t reserved4; 582 583 u_int32_t reserved5; 584 585 u_int32_t reserved6; 586 587 u_int32_t event_masks[4]; 588 589 u_int16_t sas_broadcase_primitive_masks; 590 u_int16_t reserved7; 591 592 u_int32_t reserved8; 593 } __packed __aligned(4); 594 595 struct mpii_msg_event_reply { 596 u_int16_t event_data_length; 597 u_int8_t msg_length; 598 u_int8_t function; 599 600 u_int16_t reserved1; 601 u_int8_t ack_required; 602 #define MPII_EVENT_ACK_REQUIRED (0x01) 603 u_int8_t msg_flags; 604 #define MPII_EVENT_FLAGS_REPLY_KEPT (1<<7) 605 606 u_int8_t vp_id; 607 u_int8_t vf_id; 608 u_int16_t reserved2; 609 610 u_int16_t reserved3; 611 u_int16_t ioc_status; 612 613 u_int32_t ioc_loginfo; 614 615 u_int16_t event; 616 u_int16_t reserved4; 617 618 u_int32_t event_context; 619 620 /* event data follows */ 621 } __packed __aligned(4); 622 623 struct mpii_msg_eventack_request { 624 u_int16_t reserved1; 625 u_int8_t chain_offset; 626 u_int8_t function; 627 628 u_int8_t reserved2[3]; 629 u_int8_t msg_flags; 630 631 u_int8_t vp_id; 632 u_int8_t vf_id; 633 u_int16_t reserved3; 634 635 u_int16_t event; 636 u_int16_t reserved4; 637 638 u_int32_t event_context; 639 } __packed __aligned(4); 640 641 struct mpii_msg_eventack_reply { 642 u_int16_t reserved1; 643 u_int8_t msg_length; 644 u_int8_t function; 645 646 u_int8_t reserved2[3]; 647 u_int8_t msg_flags; 648 649 u_int8_t vp_id; 650 u_int8_t vf_id; 651 u_int16_t reserved3; 652 653 u_int16_t reserved4; 654 u_int16_t ioc_status; 655 656 u_int32_t ioc_loginfo; 657 } __packed __aligned(4); 658 659 struct mpii_msg_fwupload_request { 660 u_int8_t image_type; 661 #define MPII_FWUPLOAD_IMAGETYPE_IOC_FW (0x00) 662 #define MPII_FWUPLOAD_IMAGETYPE_NV_FW (0x01) 663 #define MPII_FWUPLOAD_IMAGETYPE_NV_BACKUP (0x05) 664 #define MPII_FWUPLOAD_IMAGETYPE_NV_MANUFACTURING (0x06) 665 #define MPII_FWUPLOAD_IMAGETYPE_NV_CONFIG_1 (0x07) 666 #define MPII_FWUPLOAD_IMAGETYPE_NV_CONFIG_2 (0x08) 667 #define MPII_FWUPLOAD_IMAGETYPE_NV_MEGARAID (0x09) 668 #define MPII_FWUPLOAD_IMAGETYPE_NV_COMPLETE (0x0a) 669 #define MPII_FWUPLOAD_IMAGETYPE_COMMON_BOOT_BLOCK (0x0b) 670 u_int8_t reserved1; 671 u_int8_t chain_offset; 672 u_int8_t function; 673 674 u_int8_t reserved2[3]; 675 u_int8_t msg_flags; 676 677 u_int8_t vp_id; 678 u_int8_t vf_id; 679 u_int16_t reserved3; 680 681 u_int32_t reserved4; 682 683 u_int32_t reserved5; 684 685 struct mpii_fw_tce tce; 686 687 /* followed by an sgl */ 688 } __packed __aligned(4); 689 690 struct mpii_msg_fwupload_reply { 691 u_int8_t image_type; 692 u_int8_t reserved1; 693 u_int8_t msg_length; 694 u_int8_t function; 695 696 u_int8_t reserved2[3]; 697 u_int8_t msg_flags; 698 699 u_int8_t vp_id; 700 u_int8_t vf_id; 701 u_int16_t reserved3; 702 703 u_int16_t reserved4; 704 u_int16_t ioc_status; 705 706 u_int32_t ioc_loginfo; 707 708 u_int32_t actual_image_size; 709 } __packed __aligned(4); 710 711 struct mpii_msg_scsi_io { 712 u_int16_t dev_handle; 713 u_int8_t chain_offset; 714 u_int8_t function; 715 716 u_int16_t reserved1; 717 u_int8_t reserved2; 718 u_int8_t msg_flags; 719 720 u_int8_t vp_id; 721 u_int8_t vf_id; 722 u_int16_t reserved3; 723 724 u_int32_t sense_buffer_low_address; 725 726 u_int16_t sgl_flags; 727 u_int8_t sense_buffer_length; 728 u_int8_t reserved4; 729 730 u_int8_t sgl_offset0; 731 u_int8_t sgl_offset1; 732 u_int8_t sgl_offset2; 733 u_int8_t sgl_offset3; 734 735 u_int32_t skip_count; 736 737 u_int32_t data_length; 738 739 u_int32_t bidirectional_data_length; 740 741 u_int16_t io_flags; 742 u_int16_t eedp_flags; 743 744 u_int32_t eedp_block_size; 745 746 u_int32_t secondary_reference_tag; 747 748 u_int16_t secondary_application_tag; 749 u_int16_t application_tag_translation_mask; 750 751 u_int16_t lun[4]; 752 753 /* the following 16 bits are defined in MPI2 as the control field */ 754 u_int8_t reserved5; 755 u_int8_t tagging; 756 #define MPII_SCSIIO_ATTR_SIMPLE_Q (0x0) 757 #define MPII_SCSIIO_ATTR_HEAD_OF_Q (0x1) 758 #define MPII_SCSIIO_ATTR_ORDERED_Q (0x2) 759 #define MPII_SCSIIO_ATTR_ACA_Q (0x4) 760 #define MPII_SCSIIO_ATTR_UNTAGGED (0x5) 761 #define MPII_SCSIIO_ATTR_NO_DISCONNECT (0x7) 762 u_int8_t reserved6; 763 u_int8_t direction; 764 #define MPII_SCSIIO_DIR_NONE (0x0) 765 #define MPII_SCSIIO_DIR_WRITE (0x1) 766 #define MPII_SCSIIO_DIR_READ (0x2) 767 768 #define MPII_CDB_LEN (32) 769 u_int8_t cdb[MPII_CDB_LEN]; 770 771 /* followed by an sgl */ 772 } __packed __aligned(4); 773 774 struct mpii_msg_scsi_io_error { 775 u_int16_t dev_handle; 776 u_int8_t msg_length; 777 u_int8_t function; 778 779 u_int16_t reserved1; 780 u_int8_t reserved2; 781 u_int8_t msg_flags; 782 783 u_int8_t vp_id; 784 u_int8_t vf_id; 785 u_int16_t reserved3; 786 787 u_int8_t scsi_status; 788 #define MPII_SCSIIO_STATUS_GOOD (0x00) 789 #define MPII_SCSIIO_STATUS_CHECK_COND (0x02) 790 #define MPII_SCSIIO_STATUS_COND_MET (0x04) 791 #define MPII_SCSIIO_STATUS_BUSY (0x08) 792 #define MPII_SCSIIO_STATUS_INTERMEDIATE (0x10) 793 #define MPII_SCSIIO_STATUS_INTERMEDIATE_CONDMET (0x14) 794 #define MPII_SCSIIO_STATUS_RESERVATION_CONFLICT (0x18) 795 #define MPII_SCSIIO_STATUS_CMD_TERM (0x22) 796 #define MPII_SCSIIO_STATUS_TASK_SET_FULL (0x28) 797 #define MPII_SCSIIO_STATUS_ACA_ACTIVE (0x30) 798 #define MPII_SCSIIO_STATUS_TASK_ABORTED (0x40) 799 u_int8_t scsi_state; 800 #define MPII_SCSIIO_STATE_AUTOSENSE_VALID (1<<0) 801 #define MPII_SCSIIO_STATE_AUTOSENSE_FAILED (1<<1) 802 #define MPII_SCSIIO_STATE_NO_SCSI_STATUS (1<<2) 803 #define MPII_SCSIIO_STATE_TERMINATED (1<<3) 804 #define MPII_SCSIIO_STATE_RESPONSE_INFO_VALID (1<<4) 805 u_int16_t ioc_status; 806 807 u_int32_t ioc_loginfo; 808 809 u_int32_t transfer_count; 810 811 u_int32_t sense_count; 812 813 u_int32_t response_info; 814 815 u_int16_t task_tag; 816 u_int16_t reserved4; 817 818 u_int32_t bidirectional_transfer_count; 819 820 u_int32_t reserved5; 821 822 u_int32_t reserved6; 823 } __packed __aligned(4); 824 825 struct mpii_request_descr { 826 u_int8_t request_flags; 827 #define MPII_REQ_DESCR_TYPE_MASK (0x0e) 828 #define MPII_REQ_DESCR_SCSI_IO (0x00) 829 #define MPII_REQ_DESCR_SCSI_TARGET (0x02) 830 #define MPII_REQ_DESCR_HIGH_PRIORITY (0x06) 831 #define MPII_REQ_DESCR_DEFAULT (0x08) 832 u_int8_t vf_id; 833 u_int16_t smid; 834 835 u_int16_t lmid; 836 u_int16_t dev_handle; 837 } __packed __aligned(8); 838 839 struct mpii_reply_descr { 840 u_int8_t reply_flags; 841 #define MPII_REPLY_DESCR_TYPE_MASK (0x0f) 842 #define MPII_REPLY_DESCR_SCSI_IO_SUCCESS (0x00) 843 #define MPII_REPLY_DESCR_ADDRESS_REPLY (0x01) 844 #define MPII_REPLY_DESCR_TARGET_ASSIST_SUCCESS (0x02) 845 #define MPII_REPLY_DESCR_TARGET_COMMAND_BUFFER (0x03) 846 #define MPII_REPLY_DESCR_UNUSED (0x0f) 847 u_int8_t vf_id; 848 u_int16_t smid; 849 850 union { 851 u_int32_t data; 852 u_int32_t frame_addr; /* Address Reply */ 853 }; 854 } __packed __aligned(8); 855 856 struct mpii_request_header { 857 u_int16_t function_dependent1; 858 u_int8_t chain_offset; 859 u_int8_t function; 860 861 u_int16_t function_dependent2; 862 u_int8_t function_dependent3; 863 u_int8_t message_flags; 864 865 u_int8_t vp_id; 866 u_int8_t vf_id; 867 u_int16_t reserved; 868 } __packed __aligned(4); 869 870 struct mpii_msg_scsi_task_request { 871 u_int16_t dev_handle; 872 u_int8_t chain_offset; 873 u_int8_t function; 874 875 u_int8_t reserved1; 876 u_int8_t task_type; 877 #define MPII_SCSI_TASK_ABORT_TASK (0x01) 878 #define MPII_SCSI_TASK_ABRT_TASK_SET (0x02) 879 #define MPII_SCSI_TASK_TARGET_RESET (0x03) 880 #define MPII_SCSI_TASK_RESET_BUS (0x04) 881 #define MPII_SCSI_TASK_LOGICAL_UNIT_RESET (0x05) 882 u_int8_t reserved2; 883 u_int8_t msg_flags; 884 885 u_int8_t vp_id; 886 u_int8_t vf_id; 887 u_int16_t reserved3; 888 889 u_int16_t lun[4]; 890 891 u_int32_t reserved4[7]; 892 893 u_int16_t task_mid; 894 u_int16_t reserved5; 895 } __packed __aligned(4); 896 897 struct mpii_msg_scsi_task_reply { 898 u_int16_t dev_handle; 899 u_int8_t msg_length; 900 u_int8_t function; 901 902 u_int8_t response_code; 903 u_int8_t task_type; 904 u_int8_t reserved1; 905 u_int8_t msg_flags; 906 907 u_int8_t vp_id; 908 u_int8_t vf_id; 909 u_int16_t reserved2; 910 911 u_int16_t reserved3; 912 u_int16_t ioc_status; 913 914 u_int32_t ioc_loginfo; 915 916 u_int32_t termination_count; 917 } __packed __aligned(4); 918 919 struct mpii_msg_sas_oper_request { 920 u_int8_t operation; 921 #define MPII_SAS_OP_CLEAR_PERSISTENT (0x02) 922 #define MPII_SAS_OP_PHY_LINK_RESET (0x06) 923 #define MPII_SAS_OP_PHY_HARD_RESET (0x07) 924 #define MPII_SAS_OP_PHY_CLEAR_ERROR_LOG (0x08) 925 #define MPII_SAS_OP_SEND_PRIMITIVE (0x0a) 926 #define MPII_SAS_OP_FORCE_FULL_DISCOVERY (0x0b) 927 #define MPII_SAS_OP_TRANSMIT_PORT_SELECT (0x0c) 928 #define MPII_SAS_OP_REMOVE_DEVICE (0x0d) 929 #define MPII_SAS_OP_LOOKUP_MAPPING (0x0e) 930 #define MPII_SAS_OP_SET_IOC_PARAM (0x0f) 931 u_int8_t reserved1; 932 u_int8_t chain_offset; 933 u_int8_t function; 934 935 u_int16_t dev_handle; 936 u_int8_t ioc_param; 937 u_int8_t msg_flags; 938 939 u_int8_t vp_id; 940 u_int8_t vf_id; 941 u_int16_t reserved2; 942 943 u_int16_t reserved3; 944 u_int8_t phy_num; 945 u_int8_t prim_flags; 946 947 u_int32_t primitive; 948 949 u_int8_t lookup_method; 950 #define MPII_SAS_LOOKUP_METHOD_SAS_ADDR (0x01) 951 #define MPII_SAS_LOOKUP_METHOD_SAS_ENCL (0x02) 952 #define MPII_SAS_LOOKUP_METHOD_SAS_DEVNAME (0x03) 953 u_int8_t reserved4; 954 u_int16_t slot_num; 955 956 u_int64_t lookup_addr; 957 958 u_int32_t ioc_param_value; 959 960 u_int64_t reserved5; 961 } __packed __aligned(4); 962 963 struct mpii_msg_sas_oper_reply { 964 u_int8_t operation; 965 u_int8_t reserved1; 966 u_int8_t chain_offset; 967 u_int8_t function; 968 969 u_int16_t dev_handle; 970 u_int8_t ioc_param; 971 u_int8_t msg_flags; 972 973 u_int8_t vp_id; 974 u_int8_t vf_id; 975 u_int16_t reserved2; 976 977 u_int16_t reserved3; 978 u_int16_t ioc_status; 979 980 u_int32_t ioc_loginfo; 981 } __packed __aligned(4); 982 983 struct mpii_msg_raid_action_request { 984 u_int8_t action; 985 #define MPII_RAID_ACTION_CHANGE_VOL_WRITE_CACHE (0x17) 986 u_int8_t reserved1; 987 u_int8_t chain_offset; 988 u_int8_t function; 989 990 u_int16_t vol_dev_handle; 991 u_int8_t phys_disk_num; 992 u_int8_t msg_flags; 993 994 u_int8_t vp_id; 995 u_int8_t vf_if; 996 u_int16_t reserved2; 997 998 u_int32_t reserved3; 999 1000 u_int32_t action_data; 1001 #define MPII_RAID_VOL_WRITE_CACHE_MASK (0x03) 1002 #define MPII_RAID_VOL_WRITE_CACHE_DISABLE (0x01) 1003 #define MPII_RAID_VOL_WRITE_CACHE_ENABLE (0x02) 1004 1005 struct mpii_sge action_sge; 1006 } __packed __aligned(4); 1007 1008 struct mpii_msg_raid_action_reply { 1009 u_int8_t action; 1010 u_int8_t reserved1; 1011 u_int8_t chain_offset; 1012 u_int8_t function; 1013 1014 u_int16_t vol_dev_handle; 1015 u_int8_t phys_disk_num; 1016 u_int8_t msg_flags; 1017 1018 u_int8_t vp_id; 1019 u_int8_t vf_if; 1020 u_int16_t reserved2; 1021 1022 u_int16_t reserved3; 1023 u_int16_t ioc_status; 1024 1025 u_int32_t action_data[5]; 1026 } __packed __aligned(4); 1027 1028 struct mpii_cfg_hdr { 1029 u_int8_t page_version; 1030 u_int8_t page_length; 1031 u_int8_t page_number; 1032 u_int8_t page_type; 1033 #define MPII_CONFIG_REQ_PAGE_TYPE_ATTRIBUTE (0xf0) 1034 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 1035 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 1036 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 1037 1038 #define MPII_CONFIG_REQ_PAGE_TYPE_MASK (0x0f) 1039 #define MPII_CONFIG_REQ_PAGE_TYPE_IO_UNIT (0x00) 1040 #define MPII_CONFIG_REQ_PAGE_TYPE_IOC (0x01) 1041 #define MPII_CONFIG_REQ_PAGE_TYPE_BIOS (0x02) 1042 #define MPII_CONFIG_REQ_PAGE_TYPE_RAID_VOL (0x08) 1043 #define MPII_CONFIG_REQ_PAGE_TYPE_MANUFACTURING (0x09) 1044 #define MPII_CONFIG_REQ_PAGE_TYPE_RAID_PD (0x0a) 1045 #define MPII_CONFIG_REQ_PAGE_TYPE_EXTENDED (0x0f) 1046 } __packed __aligned(4); 1047 1048 struct mpii_ecfg_hdr { 1049 u_int8_t page_version; 1050 u_int8_t reserved1; 1051 u_int8_t page_number; 1052 u_int8_t page_type; 1053 1054 u_int16_t ext_page_length; 1055 u_int8_t ext_page_type; 1056 #define MPII_CONFIG_REQ_PAGE_TYPE_SAS_DEVICE (0x12) 1057 #define MPII_CONFIG_REQ_PAGE_TYPE_RAID_CONFIG (0x16) 1058 #define MPII_CONFIG_REQ_PAGE_TYPE_DRIVER_MAPPING (0x17) 1059 u_int8_t reserved2; 1060 } __packed __aligned(4); 1061 1062 /* config page address formats */ 1063 #define MPII_PGAD_SAS_DEVICE_FORM_MASK (0xf0000000) 1064 #define MPII_PGAD_SAS_DEVICE_FORM_GET_NEXT_HANDLE (0x00000000) 1065 #define MPII_PGAD_SAS_DEVICE_FORM_HANDLE (0x20000000) 1066 1067 #define MPII_PGAD_SAS_DEVICE_HANDLE_MASK (0x0000ffff) 1068 1069 struct mpii_msg_config_request { 1070 u_int8_t action; 1071 #define MPII_CONFIG_REQ_ACTION_PAGE_HEADER (0x00) 1072 #define MPII_CONFIG_REQ_ACTION_PAGE_READ_CURRENT (0x01) 1073 #define MPII_CONFIG_REQ_ACTION_PAGE_WRITE_CURRENT (0x02) 1074 #define MPII_CONFIG_REQ_ACTION_PAGE_DEFAULT (0x03) 1075 #define MPII_CONFIG_REQ_ACTION_PAGE_WRITE_NVRAM (0x04) 1076 #define MPII_CONFIG_REQ_ACTION_PAGE_READ_DEFAULT (0x05) 1077 #define MPII_CONFIG_REQ_ACTION_PAGE_READ_NVRAM (0x06) 1078 u_int8_t sgl_flags; 1079 u_int8_t chain_offset; 1080 u_int8_t function; 1081 1082 u_int16_t ext_page_len; 1083 u_int8_t ext_page_type; 1084 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_IO_UNIT (0x10) 1085 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_EXPANDER (0x11) 1086 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_DEVICE (0x12) 1087 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_PHY (0x13) 1088 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_LOG (0x14) 1089 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 1090 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 1091 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 1092 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 1093 u_int8_t msg_flags; 1094 1095 u_int8_t vp_id; 1096 u_int8_t vf_id; 1097 u_int16_t reserved1; 1098 1099 u_int32_t reserved2[2]; 1100 1101 struct mpii_cfg_hdr config_header; 1102 1103 u_int32_t page_address; 1104 /* XXX lots of defns here */ 1105 1106 struct mpii_sge page_buffer; 1107 } __packed __aligned(4); 1108 1109 struct mpii_msg_config_reply { 1110 u_int8_t action; 1111 u_int8_t sgl_flags; 1112 u_int8_t msg_length; 1113 u_int8_t function; 1114 1115 u_int16_t ext_page_length; 1116 u_int8_t ext_page_type; 1117 u_int8_t msg_flags; 1118 1119 u_int8_t vp_id; 1120 u_int8_t vf_id; 1121 u_int16_t reserved1; 1122 1123 u_int16_t reserved2; 1124 u_int16_t ioc_status; 1125 1126 u_int32_t ioc_loginfo; 1127 1128 struct mpii_cfg_hdr config_header; 1129 } __packed __aligned(4); 1130 1131 struct mpii_cfg_manufacturing_pg0 { 1132 struct mpii_cfg_hdr config_header; 1133 1134 char chip_name[16]; 1135 char chip_revision[8]; 1136 char board_name[16]; 1137 char board_assembly[16]; 1138 char board_tracer_number[16]; 1139 } __packed __aligned(4); 1140 1141 struct mpii_cfg_ioc_pg1 { 1142 struct mpii_cfg_hdr config_header; 1143 1144 u_int32_t flags; 1145 1146 u_int32_t coalescing_timeout; 1147 #define MPII_CFG_IOC_1_REPLY_COALESCING (1<<0) 1148 1149 u_int8_t coalescing_depth; 1150 u_int8_t pci_slot_num; 1151 u_int8_t pci_bus_num; 1152 u_int8_t pci_domain_segment; 1153 1154 u_int32_t reserved1; 1155 1156 u_int32_t reserved2; 1157 } __packed __aligned(4); 1158 1159 struct mpii_cfg_ioc_pg3 { 1160 struct mpii_cfg_hdr config_header; 1161 1162 u_int8_t no_phys_disks; 1163 u_int8_t reserved[3]; 1164 1165 /* followed by a list of mpii_cfg_raid_physdisk structs */ 1166 } __packed __aligned(4); 1167 1168 struct mpii_cfg_ioc_pg8 { 1169 struct mpii_cfg_hdr config_header; 1170 1171 u_int8_t num_devs_per_enclosure; 1172 u_int8_t reserved1; 1173 u_int16_t reserved2; 1174 1175 u_int16_t max_persistent_entries; 1176 u_int16_t max_num_physical_mapped_ids; 1177 1178 u_int16_t flags; 1179 #define MPII_IOC_PG8_FLAGS_DA_START_SLOT_1 (1<<5) 1180 #define MPII_IOC_PG8_FLAGS_RESERVED_TARGETID_0 (1<<4) 1181 #define MPII_IOC_PG8_FLAGS_MAPPING_MODE_MASK (0x0000000e) 1182 #define MPII_IOC_PG8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0<<1) 1183 #define MPII_IOC_PG8_FLAGS_ENCLOSURE_SLOT_MAPPING (1<<1) 1184 #define MPII_IOC_PG8_FLAGS_DISABLE_PERSISTENT_MAPPING (1<<0) 1185 #define MPII_IOC_PG8_FLAGS_ENABLE_PERSISTENT_MAPPING (0<<0) 1186 u_int16_t reserved3; 1187 1188 u_int16_t ir_volume_mapping_flags; 1189 #define MPII_IOC_PG8_IRFLAGS_VOLUME_MAPPING_MODE_MASK (0x00000003) 1190 #define MPII_IOC_PG8_IRFLAGS_LOW_VOLUME_MAPPING (0<<0) 1191 #define MPII_IOC_PG8_IRFLAGS_HIGH_VOLUME_MAPPING (1<<0) 1192 u_int16_t reserved4; 1193 1194 u_int32_t reserved5; 1195 } __packed __aligned(4); 1196 1197 struct mpii_cfg_raid_physdisk { 1198 u_int8_t phys_disk_id; 1199 u_int8_t phys_disk_bus; 1200 u_int8_t phys_disk_ioc; 1201 u_int8_t phys_disk_num; 1202 } __packed __aligned(4); 1203 1204 struct mpii_cfg_fc_port_pg0 { 1205 struct mpii_cfg_hdr config_header; 1206 1207 u_int32_t flags; 1208 1209 u_int8_t mpii_port_nr; 1210 u_int8_t link_type; 1211 u_int8_t port_state; 1212 u_int8_t reserved1; 1213 1214 u_int32_t port_id; 1215 1216 u_int64_t wwnn; 1217 1218 u_int64_t wwpn; 1219 1220 u_int32_t supported_service_class; 1221 1222 u_int32_t supported_speeds; 1223 1224 u_int32_t current_speed; 1225 1226 u_int32_t max_frame_size; 1227 1228 u_int64_t fabric_wwnn; 1229 1230 u_int64_t fabric_wwpn; 1231 1232 u_int32_t discovered_port_count; 1233 1234 u_int32_t max_initiators; 1235 1236 u_int8_t max_aliases_supported; 1237 u_int8_t max_hard_aliases_supported; 1238 u_int8_t num_current_aliases; 1239 u_int8_t reserved2; 1240 } __packed __aligned(4); 1241 1242 struct mpii_cfg_fc_port_pg1 { 1243 struct mpii_cfg_hdr config_header; 1244 1245 u_int32_t flags; 1246 1247 u_int64_t noseepromwwnn; 1248 1249 u_int64_t noseepromwwpn; 1250 1251 u_int8_t hard_alpa; 1252 u_int8_t link_config; 1253 u_int8_t topology_config; 1254 u_int8_t alt_connector; 1255 1256 u_int8_t num_req_aliases; 1257 u_int8_t rr_tov; 1258 u_int8_t initiator_dev_to; 1259 u_int8_t initiator_lo_pend_to; 1260 } __packed __aligned(4); 1261 1262 struct mpii_cfg_fc_device_pg0 { 1263 struct mpii_cfg_hdr config_header; 1264 1265 u_int64_t wwnn; 1266 1267 u_int64_t wwpn; 1268 1269 u_int32_t port_id; 1270 1271 u_int8_t protocol; 1272 u_int8_t flags; 1273 u_int16_t bb_credit; 1274 1275 u_int16_t max_rx_frame_size; 1276 u_int8_t adisc_hard_alpa; 1277 u_int8_t port_nr; 1278 1279 u_int8_t fc_ph_low_version; 1280 u_int8_t fc_ph_high_version; 1281 u_int8_t current_target_id; 1282 u_int8_t current_bus; 1283 } __packed __aligned(4); 1284 1285 #define MPII_CFG_RAID_VOL_ADDR_HANDLE (1<<28) 1286 1287 struct mpii_cfg_raid_vol_pg0 { 1288 struct mpii_cfg_hdr config_header; 1289 1290 u_int16_t volume_handle; 1291 u_int8_t volume_state; 1292 #define MPII_CFG_RAID_VOL_0_STATE_MISSING (0x00) 1293 #define MPII_CFG_RAID_VOL_0_STATE_FAILED (0x01) 1294 #define MPII_CFG_RAID_VOL_0_STATE_INITIALIZING (0x02) 1295 #define MPII_CFG_RAID_VOL_0_STATE_ONLINE (0x03) 1296 #define MPII_CFG_RAID_VOL_0_STATE_DEGRADED (0x04) 1297 #define MPII_CFG_RAID_VOL_0_STATE_OPTIMAL (0x05) 1298 u_int8_t volume_type; 1299 #define MPII_CFG_RAID_VOL_0_TYPE_RAID0 (0x00) 1300 #define MPII_CFG_RAID_VOL_0_TYPE_RAID1E (0x01) 1301 #define MPII_CFG_RAID_VOL_0_TYPE_RAID1 (0x02) 1302 #define MPII_CFG_RAID_VOL_0_TYPE_RAID10 (0x05) 1303 #define MPII_CFG_RAID_VOL_0_TYPE_UNKNOWN (0xff) 1304 1305 u_int32_t volume_status; 1306 #define MPII_CFG_RAID_VOL_0_STATUS_SCRUB (1<<20) 1307 #define MPII_CFG_RAID_VOL_0_STATUS_RESYNC (1<<16) 1308 1309 u_int16_t volume_settings; 1310 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_MASK (0x3<<0) 1311 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_UNCHANGED (0x0<<0) 1312 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_DISABLED (0x1<<0) 1313 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_ENABLED (0x2<<0) 1314 1315 u_int8_t hot_spare_pool; 1316 u_int8_t reserved1; 1317 1318 u_int64_t max_lba; 1319 1320 u_int32_t stripe_size; 1321 1322 u_int16_t block_size; 1323 u_int16_t reserved2; 1324 1325 u_int8_t phys_disk_types; 1326 u_int8_t resync_rate; 1327 u_int16_t data_scrub_rate; 1328 1329 u_int8_t num_phys_disks; 1330 u_int16_t reserved3; 1331 u_int8_t inactive_status; 1332 #define MPII_CFG_RAID_VOL_0_INACTIVE_UNKNOWN (0x00) 1333 #define MPII_CFG_RAID_VOL_0_INACTIVE_STALE_META (0x01) 1334 #define MPII_CFG_RAID_VOL_0_INACTIVE_FOREIGN_VOL (0x02) 1335 #define MPII_CFG_RAID_VOL_0_INACTIVE_NO_RESOURCES (0x03) 1336 #define MPII_CFG_RAID_VOL_0_INACTIVE_CLONED_VOL (0x04) 1337 #define MPII_CFG_RAID_VOL_0_INACTIVE_INSUF_META (0x05) 1338 1339 /* followed by a list of mpii_cfg_raid_vol_pg0_physdisk structs */ 1340 } __packed __aligned(4); 1341 1342 struct mpii_cfg_raid_vol_pg0_physdisk { 1343 u_int8_t raid_set_num; 1344 u_int8_t phys_disk_map; 1345 u_int8_t phys_disk_num; 1346 u_int8_t reserved; 1347 } __packed __aligned(4); 1348 1349 struct mpii_cfg_raid_vol_pg1 { 1350 struct mpii_cfg_hdr config_header; 1351 1352 u_int8_t volume_id; 1353 u_int8_t volume_bus; 1354 u_int8_t volume_ioc; 1355 u_int8_t reserved1; 1356 1357 u_int8_t guid[24]; 1358 1359 u_int8_t name[32]; 1360 1361 u_int64_t wwid; 1362 1363 u_int32_t reserved2; 1364 1365 u_int32_t reserved3; 1366 } __packed __aligned(4); 1367 1368 #define MPII_CFG_RAID_PHYS_DISK_ADDR_NUMBER (1<<28) 1369 1370 struct mpii_cfg_raid_physdisk_pg0 { 1371 struct mpii_cfg_hdr config_header; 1372 1373 u_int16_t dev_handle; 1374 u_int8_t reserved1; 1375 u_int8_t phys_disk_num; 1376 1377 u_int8_t enc_id; 1378 u_int8_t enc_bus; 1379 u_int8_t hot_spare_pool; 1380 u_int8_t enc_type; 1381 #define MPII_CFG_RAID_PHYDISK_0_ENCTYPE_NONE (0x0) 1382 #define MPII_CFG_RAID_PHYDISK_0_ENCTYPE_SAFTE (0x1) 1383 #define MPII_CFG_RAID_PHYDISK_0_ENCTYPE_SES (0x2) 1384 1385 u_int32_t reserved2; 1386 1387 u_int8_t vendor_id[8]; 1388 1389 u_int8_t product_id[16]; 1390 1391 u_int8_t product_rev[4]; 1392 1393 u_int8_t serial[32]; 1394 1395 u_int32_t reserved3; 1396 1397 u_int8_t phys_disk_state; 1398 #define MPII_CFG_RAID_PHYDISK_0_STATE_NOTCONFIGURED (0x00) 1399 #define MPII_CFG_RAID_PHYDISK_0_STATE_NOTCOMPATIBLE (0x01) 1400 #define MPII_CFG_RAID_PHYDISK_0_STATE_OFFLINE (0x02) 1401 #define MPII_CFG_RAID_PHYDISK_0_STATE_ONLINE (0x03) 1402 #define MPII_CFG_RAID_PHYDISK_0_STATE_HOTSPARE (0x04) 1403 #define MPII_CFG_RAID_PHYDISK_0_STATE_DEGRADED (0x05) 1404 #define MPII_CFG_RAID_PHYDISK_0_STATE_REBUILDING (0x06) 1405 #define MPII_CFG_RAID_PHYDISK_0_STATE_OPTIMAL (0x07) 1406 u_int8_t offline_reason; 1407 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_MISSING (0x01) 1408 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_FAILED (0x03) 1409 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_INITIALIZING (0x04) 1410 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_REQUESTED (0x05) 1411 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_FAILEDREQ (0x06) 1412 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_OTHER (0xff) 1413 1414 u_int8_t incompat_reason; 1415 u_int8_t phys_disk_attrs; 1416 1417 u_int32_t phys_disk_status; 1418 #define MPII_CFG_RAID_PHYDISK_0_STATUS_OUTOFSYNC (1<<0) 1419 #define MPII_CFG_RAID_PHYDISK_0_STATUS_QUIESCED (1<<1) 1420 1421 u_int64_t dev_max_lba; 1422 1423 u_int64_t host_max_lba; 1424 1425 u_int64_t coerced_max_lba; 1426 1427 u_int16_t block_size; 1428 u_int16_t reserved4; 1429 1430 u_int32_t reserved5; 1431 } __packed __aligned(4); 1432 1433 struct mpii_cfg_raid_physdisk_pg1 { 1434 struct mpii_cfg_hdr config_header; 1435 1436 u_int8_t num_phys_disk_paths; 1437 u_int8_t phys_disk_num; 1438 u_int16_t reserved1; 1439 1440 u_int32_t reserved2; 1441 1442 /* followed by mpii_cfg_raid_physdisk_path structs */ 1443 } __packed __aligned(4); 1444 1445 struct mpii_cfg_raid_physdisk_path { 1446 u_int8_t phys_disk_id; 1447 u_int8_t phys_disk_bus; 1448 u_int16_t reserved1; 1449 1450 u_int64_t wwwid; 1451 1452 u_int64_t owner_wwid; 1453 1454 u_int8_t ownder_id; 1455 u_int8_t reserved2; 1456 u_int16_t flags; 1457 #define MPII_CFG_RAID_PHYDISK_PATH_INVALID (1<<0) 1458 #define MPII_CFG_RAID_PHYDISK_PATH_BROKEN (1<<1) 1459 } __packed __aligned(4); 1460 1461 #define MPII_CFG_SAS_DEV_ADDR_NEXT (0<<28) 1462 #define MPII_CFG_SAS_DEV_ADDR_BUS (1<<28) 1463 #define MPII_CFG_SAS_DEV_ADDR_HANDLE (2<<28) 1464 1465 struct mpii_cfg_sas_dev_pg0 { 1466 struct mpii_ecfg_hdr config_header; 1467 1468 u_int16_t slot; 1469 u_int16_t enc_handle; 1470 1471 u_int64_t sas_addr; 1472 1473 u_int16_t parent_dev_handle; 1474 u_int8_t phy_num; 1475 u_int8_t access_status; 1476 1477 u_int16_t dev_handle; 1478 u_int8_t target; 1479 u_int8_t bus; 1480 1481 u_int32_t device_info; 1482 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE (0x7) 1483 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_NONE (0x0) 1484 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_END (0x1) 1485 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_EDGE_EXPANDER (0x2) 1486 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_FANOUT_EXPANDER (0x3) 1487 #define MPII_CFG_SAS_DEV_0_DEVINFO_SATA_HOST (1<<3) 1488 #define MPII_CFG_SAS_DEV_0_DEVINFO_SMP_INITIATOR (1<<4) 1489 #define MPII_CFG_SAS_DEV_0_DEVINFO_STP_INITIATOR (1<<5) 1490 #define MPII_CFG_SAS_DEV_0_DEVINFO_SSP_INITIATOR (1<<6) 1491 #define MPII_CFG_SAS_DEV_0_DEVINFO_SATA_DEVICE (1<<7) 1492 #define MPII_CFG_SAS_DEV_0_DEVINFO_SMP_TARGET (1<<8) 1493 #define MPII_CFG_SAS_DEV_0_DEVINFO_STP_TARGET (1<<9) 1494 #define MPII_CFG_SAS_DEV_0_DEVINFO_SSP_TARGET (1<<10) 1495 #define MPII_CFG_SAS_DEV_0_DEVINFO_DIRECT_ATTACHED (1<<11) 1496 #define MPII_CFG_SAS_DEV_0_DEVINFO_LSI_DEVICE (1<<12) 1497 #define MPII_CFG_SAS_DEV_0_DEVINFO_ATAPI_DEVICE (1<<13) 1498 #define MPII_CFG_SAS_DEV_0_DEVINFO_SEP_DEVICE (1<<14) 1499 1500 u_int16_t flags; 1501 #define MPII_CFG_SAS_DEV_0_FLAGS_DEV_PRESENT (1<<0) 1502 #define MPII_CFG_SAS_DEV_0_FLAGS_DEV_MAPPED (1<<1) 1503 #define MPII_CFG_SAS_DEV_0_FLAGS_DEV_MAPPED_PERSISTENT (1<<2) 1504 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_PORT_SELECTOR (1<<3) 1505 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_FUA (1<<4) 1506 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_NCQ (1<<5) 1507 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_SMART (1<<6) 1508 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_LBA48 (1<<7) 1509 #define MPII_CFG_SAS_DEV_0_FLAGS_UNSUPPORTED (1<<8) 1510 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_SETTINGS (1<<9) 1511 u_int8_t physical_port; 1512 u_int8_t max_port_conn; 1513 1514 u_int64_t device_name; 1515 1516 u_int8_t port_groups; 1517 u_int8_t dma_group; 1518 u_int8_t ctrl_group; 1519 u_int8_t reserved1; 1520 1521 u_int64_t reserved2; 1522 } __packed __aligned(4); 1523 1524 #define MPII_CFG_RAID_CONFIG_ACTIVE_CONFIG (2<<28) 1525 1526 struct mpii_cfg_raid_config_pg0 { 1527 struct mpii_ecfg_hdr config_header; 1528 1529 u_int8_t num_hot_spares; 1530 u_int8_t num_phys_disks; 1531 u_int8_t num_volumes; 1532 u_int8_t config_num; 1533 1534 u_int32_t flags; 1535 #define MPII_CFG_RAID_CONFIG_0_FLAGS_NATIVE (0<<0) 1536 #define MPII_CFG_RAID_CONFIG_0_FLAGS_FOREIGN (1<<0) 1537 1538 u_int32_t config_guid[6]; 1539 1540 u_int32_t reserved1; 1541 1542 u_int8_t num_elements; 1543 u_int8_t reserved2[3]; 1544 1545 /* followed by struct mpii_raid_config_element structs */ 1546 } __packed __aligned(4); 1547 1548 struct mpii_raid_config_element { 1549 u_int16_t element_flags; 1550 #define MPII_RAID_CONFIG_ELEMENT_FLAG_VOLUME (0x0) 1551 #define MPII_RAID_CONFIG_ELEMENT_FLAG_VOLUME_PHYS_DISK (0x1) 1552 #define MPII_RAID_CONFIG_ELEMENT_FLAG_HSP_PHYS_DISK (0x2) 1553 #define MPII_RAID_CONFIG_ELEMENT_ONLINE_CE_PHYS_DISK (0x3) 1554 u_int16_t vol_dev_handle; 1555 1556 u_int8_t hot_spare_pool; 1557 u_int8_t phys_disk_num; 1558 u_int16_t phys_disk_dev_handle; 1559 } __packed __aligned(4); 1560 1561 struct mpii_cfg_dpm_pg0 { 1562 struct mpii_ecfg_hdr config_header; 1563 #define MPII_DPM_ADDRESS_FORM_MASK (0xf0000000) 1564 #define MPII_DPM_ADDRESS_FORM_ENTRY_RANGE (0x00000000) 1565 #define MPII_DPM_ADDRESS_ENTRY_COUNT_MASK (0x0fff0000) 1566 #define MPII_DPM_ADDRESS_ENTRY_COUNT_SHIFT (16) 1567 #define MPII_DPM_ADDRESS_START_ENTRY_MASK (0x0000ffff) 1568 1569 /* followed by struct mpii_dpm_entry structs */ 1570 } __packed __aligned(4); 1571 1572 struct mpii_dpm_entry { 1573 u_int64_t physical_identifier; 1574 1575 u_int16_t mapping_information; 1576 u_int16_t device_index; 1577 1578 u_int32_t physical_bits_mapping; 1579 1580 u_int32_t reserved1; 1581 } __packed __aligned(4); 1582 1583 struct mpii_evt_sas_discovery { 1584 u_int8_t flags; 1585 #define MPII_EVENT_SAS_DISC_FLAGS_DEV_CHANGE_MASK (1<<1) 1586 #define MPII_EVENT_SAS_DISC_FLAGS_DEV_CHANGE_NO_CHANGE (0<<1) 1587 #define MPII_EVENT_SAS_DISC_FLAGS_DEV_CHANGE_CHANGE (1<<1) 1588 #define MPII_EVENT_SAS_DISC_FLAGS_DISC_IN_PROG_MASK (1<<0) 1589 #define MPII_EVENT_SAS_DISC_FLAGS_DISC_NOT_IN_PROGRESS (1<<0) 1590 #define MPII_EVENT_SAS_DISC_FLAGS_DISC_IN_PROGRESS (0<<0) 1591 u_int8_t reason_code; 1592 #define MPII_EVENT_SAS_DISC_REASON_CODE_STARTED (0x01) 1593 #define MPII_EVENT_SAS_DISC_REASON_CODE_COMPLETED (0x02) 1594 u_int8_t physical_port; 1595 u_int8_t reserved1; 1596 1597 u_int32_t discovery_status; 1598 } __packed __aligned(4); 1599 1600 struct mpii_evt_ir_status { 1601 u_int16_t vol_dev_handle; 1602 u_int16_t reserved1; 1603 1604 u_int8_t operation; 1605 #define MPII_EVENT_IR_RAIDOP_RESYNC (0x00) 1606 #define MPII_EVENT_IR_RAIDOP_OCE (0x01) 1607 #define MPII_EVENT_IR_RAIDOP_CONS_CHECK (0x02) 1608 #define MPII_EVENT_IR_RAIDOP_BG_INIT (0x03) 1609 #define MPII_EVENT_IR_RAIDOP_MAKE_CONS (0x04) 1610 u_int8_t percent; 1611 u_int16_t reserved2; 1612 1613 u_int32_t reserved3; 1614 }; 1615 1616 struct mpii_evt_ir_volume { 1617 u_int16_t vol_dev_handle; 1618 u_int8_t reason_code; 1619 #define MPII_EVENT_IR_VOL_RC_SETTINGS_CHANGED (0x01) 1620 #define MPII_EVENT_IR_VOL_RC_STATUS_CHANGED (0x02) 1621 #define MPII_EVENT_IR_VOL_RC_STATE_CHANGED (0x03) 1622 u_int8_t reserved1; 1623 1624 u_int32_t new_value; 1625 u_int32_t prev_value; 1626 } __packed __aligned(4); 1627 1628 struct mpii_evt_ir_physical_disk { 1629 u_int16_t reserved1; 1630 u_int8_t reason_code; 1631 #define MPII_EVENT_IR_PD_RC_SETTINGS_CHANGED (0x01) 1632 #define MPII_EVENT_IR_PD_RC_STATUS_FLAGS_CHANGED (0x02) 1633 #define MPII_EVENT_IR_PD_RC_STATUS_CHANGED (0x03) 1634 u_int8_t phys_disk_num; 1635 1636 u_int16_t phys_disk_dev_handle; 1637 u_int16_t reserved2; 1638 1639 u_int16_t slot; 1640 u_int16_t enclosure_handle; 1641 1642 u_int32_t new_value; 1643 u_int32_t previous_value; 1644 } __packed __aligned(4); 1645 1646 struct mpii_evt_sas_tcl { 1647 u_int16_t enclosure_handle; 1648 u_int16_t expander_handle; 1649 1650 u_int8_t num_phys; 1651 u_int8_t reserved1[3]; 1652 1653 u_int8_t num_entries; 1654 u_int8_t start_phy_num; 1655 u_int8_t expn_status; 1656 #define MPII_EVENT_SAS_TOPO_ES_ADDED (0x01) 1657 #define MPII_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 1658 #define MPII_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 1659 #define MPII_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 1660 u_int8_t physical_port; 1661 1662 /* followed by num_entries number of struct mpii_evt_phy_entry */ 1663 } __packed __aligned(4); 1664 1665 struct mpii_evt_phy_entry { 1666 u_int16_t dev_handle; 1667 u_int8_t link_rate; 1668 u_int8_t phy_status; 1669 #define MPII_EVENT_SAS_TOPO_PS_RC_MASK (0x0f) 1670 #define MPII_EVENT_SAS_TOPO_PS_RC_ADDED (0x01) 1671 #define MPII_EVENT_SAS_TOPO_PS_RC_MISSING (0x02) 1672 } __packed __aligned(4); 1673 1674 struct mpii_evt_ir_cfg_change_list { 1675 u_int8_t num_elements; 1676 u_int16_t reserved; 1677 u_int8_t config_num; 1678 1679 u_int32_t flags; 1680 #define MPII_EVT_IR_CFG_CHANGE_LIST_FOREIGN (0x1) 1681 1682 /* followed by num_elements struct mpii_evt_ir_cfg_elements */ 1683 } __packed __aligned(4); 1684 1685 struct mpii_evt_ir_cfg_element { 1686 u_int16_t element_flags; 1687 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_MASK (0xf) 1688 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_VOLUME (0x0) 1689 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_VOLUME_DISK (0x1) 1690 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_HOT_SPARE (0x2) 1691 u_int16_t vol_dev_handle; 1692 1693 u_int8_t reason_code; 1694 #define MPII_EVT_IR_CFG_ELEMENT_RC_ADDED (0x01) 1695 #define MPII_EVT_IR_CFG_ELEMENT_RC_REMOVED (0x02) 1696 #define MPII_EVT_IR_CFG_ELEMENT_RC_NO_CHANGE (0x03) 1697 #define MPII_EVT_IR_CFG_ELEMENT_RC_HIDE (0x04) 1698 #define MPII_EVT_IR_CFG_ELEMENT_RC_UNHIDE (0x05) 1699 #define MPII_EVT_IR_CFG_ELEMENT_RC_VOLUME_CREATED (0x06) 1700 #define MPII_EVT_IR_CFG_ELEMENT_RC_VOLUME_DELETED (0x07) 1701 #define MPII_EVT_IR_CFG_ELEMENT_RC_PD_CREATED (0x08) 1702 #define MPII_EVT_IR_CFG_ELEMENT_RC_PD_DELETED (0x09) 1703 u_int8_t phys_disk_num; 1704 u_int16_t phys_disk_dev_handle; 1705 } __packed __aligned(4); 1706
Indexes created Tue Sep 30 11:09:46 GMT 2025