mvsata_pci.c revision 1.1.2.4
1 1.1.2.4 yamt /* $NetBSD: mvsata_pci.c,v 1.1.2.4 2010/08/11 22:53:50 yamt Exp $ */ 2 1.1.2.2 yamt /* 3 1.1.2.2 yamt * Copyright (c) 2008 KIYOHARA Takashi 4 1.1.2.2 yamt * All rights reserved. 5 1.1.2.2 yamt * 6 1.1.2.2 yamt * Redistribution and use in source and binary forms, with or without 7 1.1.2.2 yamt * modification, are permitted provided that the following conditions 8 1.1.2.2 yamt * are met: 9 1.1.2.2 yamt * 1. Redistributions of source code must retain the above copyright 10 1.1.2.2 yamt * notice, this list of conditions and the following disclaimer. 11 1.1.2.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 12 1.1.2.2 yamt * notice, this list of conditions and the following disclaimer in the 13 1.1.2.2 yamt * documentation and/or other materials provided with the distribution. 14 1.1.2.2 yamt * 15 1.1.2.2 yamt * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 1.1.2.2 yamt * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 1.1.2.2 yamt * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 1.1.2.2 yamt * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 1.1.2.2 yamt * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 1.1.2.2 yamt * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 1.1.2.2 yamt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 1.1.2.2 yamt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 1.1.2.2 yamt * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 1.1.2.2 yamt * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 1.1.2.2 yamt * POSSIBILITY OF SUCH DAMAGE. 26 1.1.2.2 yamt */ 27 1.1.2.2 yamt 28 1.1.2.2 yamt #include <sys/cdefs.h> 29 1.1.2.4 yamt __KERNEL_RCSID(0, "$NetBSD: mvsata_pci.c,v 1.1.2.4 2010/08/11 22:53:50 yamt Exp $"); 30 1.1.2.2 yamt 31 1.1.2.2 yamt #include <sys/param.h> 32 1.1.2.2 yamt #include <sys/bus.h> 33 1.1.2.2 yamt #include <sys/device.h> 34 1.1.2.2 yamt #include <sys/errno.h> 35 1.1.2.2 yamt #include <sys/pmf.h> 36 1.1.2.2 yamt 37 1.1.2.2 yamt #include <dev/pci/pcivar.h> 38 1.1.2.2 yamt #include <dev/pci/pcidevs.h> 39 1.1.2.2 yamt #include <dev/pci/pciidereg.h> 40 1.1.2.2 yamt #include <dev/pci/pciidevar.h> 41 1.1.2.2 yamt 42 1.1.2.2 yamt #include <dev/ic/mvsatareg.h> 43 1.1.2.2 yamt #include <dev/ic/mvsatavar.h> 44 1.1.2.2 yamt 45 1.1.2.2 yamt #define MVSATA_PCI_HCARBITER_SPACE_OFFSET 0x20000 46 1.1.2.2 yamt 47 1.1.2.2 yamt #define MVSATA_PCI_COMMAND 0x00c00 48 1.1.2.2 yamt #define MVSATA_PCI_COMMAND_MWRITECOMBINE (1 << 4) 49 1.1.2.2 yamt #define MVSATA_PCI_COMMAND_MREADCOMBINE (1 << 5) 50 1.1.2.2 yamt #define MVSATA_PCI_SERRMASK 0x00c28 51 1.1.2.2 yamt #define MVSATA_PCI_MSITRIGGER 0x00c38 52 1.1.2.2 yamt #define MVSATA_PCI_MODE 0x00d00 53 1.1.2.2 yamt #define MVSATA_PCI_DISCTIMER 0x00d04 54 1.1.2.2 yamt #define MVSATA_PCI_EROMBAR 0x00d2c 55 1.1.2.2 yamt #define MVSATA_PCI_MAINCS 0x00d30 56 1.1.2.2 yamt #define MVSATA_PCI_MAINCS_SPM (1 << 2) /* stop pci master */ 57 1.1.2.2 yamt #define MVSATA_PCI_MAINCS_PME (1 << 3) /* pci master empty */ 58 1.1.2.2 yamt #define MVSATA_PCI_MAINCS_GSR (1 << 4) /* glab soft reset */ 59 1.1.2.2 yamt #define MVSATA_PCI_E_IRQCAUSE 0x01900 60 1.1.2.2 yamt #define MVSATA_PCI_E_IRQMASK 0x01910 61 1.1.2.2 yamt #define MVSATA_PCI_XBARTIMEOUT 0x01d04 62 1.1.2.2 yamt #define MVSATA_PCI_ERRLOWADDR 0x01d40 63 1.1.2.2 yamt #define MVSATA_PCI_ERRHIGHADDR 0x01d44 64 1.1.2.2 yamt #define MVSATA_PCI_ERRATTRIBUTE 0x01d48 65 1.1.2.2 yamt #define MVSATA_PCI_ERRCOMMAND 0x01d50 66 1.1.2.2 yamt #define MVSATA_PCI_IRQCAUSE 0x01d58 67 1.1.2.2 yamt #define MVSATA_PCI_IRQMASK 0x01d5c 68 1.1.2.2 yamt #define MVSATA_PCI_MAINIRQCAUSE 0x01d60 69 1.1.2.2 yamt #define MVSATA_PCI_MAINIRQMASK 0x01d64 70 1.1.2.2 yamt #define MVSATA_PCI_MAINIRQ_SATAERR(hc, port) \ 71 1.1.2.2 yamt (1 << (((port) << 1) + (hc) * 9)) 72 1.1.2.2 yamt #define MVSATA_PCI_MAINIRQ_SATADONE(hc, port) \ 73 1.1.2.2 yamt (1 << (((port) << 1) + (hc) * 9 + 1)) 74 1.1.2.2 yamt #define MVSATA_PCI_MAINIRQ_SATACOALDONE(hc) (1 << ((hc) * 9 + 8)) 75 1.1.2.2 yamt #define MVSATA_PCI_MAINIRQ_PCI (1 << 18) 76 1.1.2.2 yamt #define MVSATA_PCI_FLASHCTL 0x1046c 77 1.1.2.2 yamt #define MVSATA_PCI_GPIOPORTCTL 0x104f0 78 1.1.2.2 yamt #define MVSATA_PCI_RESETCFG 0x180d8 79 1.1.2.2 yamt 80 1.1.2.2 yamt #define MVSATA_PCI_DEV(psc) (psc->psc_sc.sc_wdcdev.sc_atac.atac_dev) 81 1.1.2.2 yamt 82 1.1.2.2 yamt 83 1.1.2.2 yamt struct mvsata_pci_softc { 84 1.1.2.2 yamt struct mvsata_softc psc_sc; 85 1.1.2.2 yamt 86 1.1.2.2 yamt pci_chipset_tag_t psc_pc; 87 1.1.2.2 yamt pcitag_t psc_tag; 88 1.1.2.2 yamt 89 1.1.2.2 yamt bus_space_tag_t psc_iot; 90 1.1.2.2 yamt bus_space_handle_t psc_ioh; 91 1.1.2.2 yamt 92 1.1.2.2 yamt void *psc_ih; 93 1.1.2.2 yamt }; 94 1.1.2.2 yamt 95 1.1.2.2 yamt 96 1.1.2.2 yamt static int mvsata_pci_match(device_t, struct cfdata *, void *); 97 1.1.2.2 yamt static void mvsata_pci_attach(device_t, device_t, void *); 98 1.1.2.2 yamt static int mvsata_pci_detach(device_t, int); 99 1.1.2.2 yamt 100 1.1.2.2 yamt static int mvsata_pci_intr(void *); 101 1.1.2.3 yamt static bool mvsata_pci_resume(device_t, const pmf_qual_t *qual); 102 1.1.2.2 yamt 103 1.1.2.2 yamt static int mvsata_pci_sreset(struct mvsata_softc *); 104 1.1.2.2 yamt static int mvsata_pci_misc_reset(struct mvsata_softc *); 105 1.1.2.2 yamt static void mvsata_pci_enable_intr(struct mvsata_port *, int); 106 1.1.2.2 yamt 107 1.1.2.2 yamt 108 1.1.2.2 yamt CFATTACH_DECL_NEW(mvsata_pci, sizeof(struct mvsata_pci_softc), 109 1.1.2.2 yamt mvsata_pci_match, mvsata_pci_attach, mvsata_pci_detach, NULL); 110 1.1.2.2 yamt 111 1.1.2.4 yamt struct mvsata_product mvsata_pci_products[] = { 112 1.1.2.4 yamt #define PCI_VP(v, p) PCI_VENDOR_ ## v, PCI_PRODUCT_ ## v ## _ ## p 113 1.1.2.4 yamt { PCI_VP(MARVELL, 88SX5040), 1, 4, gen1, 0 }, 114 1.1.2.4 yamt { PCI_VP(MARVELL, 88SX5041), 1, 4, gen1, 0 }, 115 1.1.2.4 yamt { PCI_VP(MARVELL, 88SX5080), 2, 4, gen1, 0 }, 116 1.1.2.4 yamt { PCI_VP(MARVELL, 88SX5081), 2, 4, gen1, 0 }, 117 1.1.2.4 yamt { PCI_VP(MARVELL, 88SX6040), 1, 4, gen2, 0 }, 118 1.1.2.4 yamt { PCI_VP(MARVELL, 88SX6041), 1, 4, gen2, 0 }, 119 1.1.2.4 yamt { PCI_VP(MARVELL, 88SX6042), 1, 4, gen2e, 0 }, 120 1.1.2.4 yamt { PCI_VP(MARVELL, 88SX6080), 2, 4, gen2, MVSATA_FLAGS_PCIE }, 121 1.1.2.4 yamt { PCI_VP(MARVELL, 88SX6081), 2, 4, gen2, MVSATA_FLAGS_PCIE }, 122 1.1.2.4 yamt { PCI_VP(ADP2, 1420SA), 2, 4, gen2, MVSATA_FLAGS_PCIE }, 123 1.1.2.4 yamt { PCI_VP(MARVELL, 88SX7042), 1, 4, gen2e, 0 }, 124 1.1.2.4 yamt { PCI_VP(ADP2, 1430SA), 1, 4, gen2e, 0 }, 125 1.1.2.4 yamt { PCI_VP(TRIONES, ROCKETRAID_2310), 1, 4, gen2e, 0 }, 126 1.1.2.4 yamt #undef PCI_VP 127 1.1.2.4 yamt }; 128 1.1.2.4 yamt 129 1.1.2.2 yamt 130 1.1.2.2 yamt /* 131 1.1.2.2 yamt * mvsata_pci_match() 132 1.1.2.2 yamt * This function returns 2, because mvsata is high priority more than pciide. 133 1.1.2.2 yamt */ 134 1.1.2.2 yamt static int 135 1.1.2.2 yamt mvsata_pci_match(device_t parent, struct cfdata *match, void *aux) 136 1.1.2.2 yamt { 137 1.1.2.2 yamt struct pci_attach_args *pa = aux; 138 1.1.2.4 yamt int i; 139 1.1.2.2 yamt 140 1.1.2.4 yamt for (i = 0; i < __arraycount(mvsata_pci_products); i++) 141 1.1.2.4 yamt if (PCI_VENDOR(pa->pa_id) == mvsata_pci_products[i].vendor && 142 1.1.2.4 yamt PCI_PRODUCT(pa->pa_id) == mvsata_pci_products[i].model) 143 1.1.2.2 yamt return 2; 144 1.1.2.2 yamt return 0; 145 1.1.2.2 yamt } 146 1.1.2.2 yamt 147 1.1.2.2 yamt static void 148 1.1.2.2 yamt mvsata_pci_attach(device_t parent, device_t self, void *aux) 149 1.1.2.2 yamt { 150 1.1.2.2 yamt struct pci_attach_args *pa = aux; 151 1.1.2.2 yamt struct mvsata_pci_softc *psc = device_private(self); 152 1.1.2.2 yamt struct mvsata_softc *sc = &psc->psc_sc; 153 1.1.2.2 yamt pci_intr_handle_t intrhandle; 154 1.1.2.2 yamt pcireg_t csr; 155 1.1.2.2 yamt bus_size_t size; 156 1.1.2.2 yamt uint32_t reg, mask; 157 1.1.2.4 yamt int read_pre_amps, hc, port, rv, i; 158 1.1.2.2 yamt char devinfo[256]; 159 1.1.2.2 yamt const char *intrstr; 160 1.1.2.2 yamt 161 1.1.2.2 yamt sc->sc_wdcdev.sc_atac.atac_dev = self; 162 1.1.2.2 yamt sc->sc_model = PCI_PRODUCT(pa->pa_id); 163 1.1.2.2 yamt sc->sc_rev = PCI_REVISION(pa->pa_class); 164 1.1.2.2 yamt sc->sc_dmat = pa->pa_dmat; 165 1.1.2.2 yamt sc->sc_enable_intr = mvsata_pci_enable_intr; 166 1.1.2.2 yamt 167 1.1.2.2 yamt pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 168 1.1.2.2 yamt aprint_naive(": Marvell Serial-ATA Host Controller\n"); 169 1.1.2.2 yamt aprint_normal(": %s\n", devinfo); 170 1.1.2.2 yamt 171 1.1.2.2 yamt /* Map I/O register */ 172 1.1.2.2 yamt if (pci_mapreg_map(pa, PCI_MAPREG_START, 173 1.1.2.2 yamt PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 174 1.1.2.2 yamt &psc->psc_iot, &psc->psc_ioh, NULL, &size) != 0) { 175 1.1.2.2 yamt aprint_error_dev(self, "can't map registers\n"); 176 1.1.2.2 yamt return; 177 1.1.2.2 yamt } 178 1.1.2.2 yamt psc->psc_pc = pa->pa_pc; 179 1.1.2.2 yamt psc->psc_tag = pa->pa_tag; 180 1.1.2.2 yamt 181 1.1.2.2 yamt if (bus_space_subregion(psc->psc_iot, psc->psc_ioh, 182 1.1.2.2 yamt MVSATA_PCI_HCARBITER_SPACE_OFFSET, 183 1.1.2.2 yamt size - MVSATA_PCI_HCARBITER_SPACE_OFFSET, &sc->sc_ioh)) { 184 1.1.2.2 yamt aprint_error_dev(self, "can't subregion registers\n"); 185 1.1.2.2 yamt return; 186 1.1.2.2 yamt } 187 1.1.2.2 yamt sc->sc_iot = psc->psc_iot; 188 1.1.2.2 yamt 189 1.1.2.2 yamt /* Enable device */ 190 1.1.2.2 yamt csr = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 191 1.1.2.2 yamt csr |= PCI_COMMAND_MASTER_ENABLE; 192 1.1.2.2 yamt pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG, csr); 193 1.1.2.2 yamt 194 1.1.2.2 yamt if (pci_intr_map(pa, &intrhandle) != 0) { 195 1.1.2.2 yamt aprint_error_dev(self, "couldn't map interrupt\n"); 196 1.1.2.2 yamt return; 197 1.1.2.2 yamt } 198 1.1.2.2 yamt intrstr = pci_intr_string(psc->psc_pc, intrhandle); 199 1.1.2.2 yamt psc->psc_ih = pci_intr_establish(psc->psc_pc, intrhandle, IPL_BIO, 200 1.1.2.2 yamt mvsata_pci_intr, sc); 201 1.1.2.2 yamt if (psc->psc_ih == NULL) { 202 1.1.2.2 yamt aprint_error_dev(self, "couldn't establish interrupt\n"); 203 1.1.2.2 yamt return; 204 1.1.2.2 yamt } 205 1.1.2.2 yamt aprint_normal_dev(self, "interrupting at %s\n", 206 1.1.2.2 yamt intrstr ? intrstr : "unknown interrupt"); 207 1.1.2.2 yamt 208 1.1.2.2 yamt /* 209 1.1.2.2 yamt * Check if TWSI serial ROM initialization was triggered. 210 1.1.2.2 yamt * If so, then PRE/AMP configuration probably are set after 211 1.1.2.2 yamt * reset by serial ROM. If not then override the PRE/AMP 212 1.1.2.2 yamt * values. 213 1.1.2.2 yamt */ 214 1.1.2.2 yamt reg = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_RESETCFG); 215 1.1.2.2 yamt read_pre_amps = (reg & 0x00000001) ? 1 : 0; 216 1.1.2.2 yamt 217 1.1.2.4 yamt for (i = 0; i < __arraycount(mvsata_pci_products); i++) 218 1.1.2.4 yamt if (PCI_VENDOR(pa->pa_id) == mvsata_pci_products[i].vendor && 219 1.1.2.4 yamt PCI_PRODUCT(pa->pa_id) == mvsata_pci_products[i].model) 220 1.1.2.4 yamt break; 221 1.1.2.4 yamt KASSERT(i < __arraycount(mvsata_pci_products)); 222 1.1.2.4 yamt 223 1.1.2.4 yamt rv = mvsata_attach(sc, &mvsata_pci_products[i], 224 1.1.2.4 yamt mvsata_pci_sreset, mvsata_pci_misc_reset, read_pre_amps); 225 1.1.2.2 yamt if (rv != 0) { 226 1.1.2.2 yamt pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 227 1.1.2.2 yamt return; 228 1.1.2.2 yamt } 229 1.1.2.2 yamt 230 1.1.2.2 yamt mask = MVSATA_PCI_MAINIRQ_PCI; 231 1.1.2.2 yamt for (hc = 0; hc < sc->sc_hc; hc++) 232 1.1.2.2 yamt for (port = 0; port < sc->sc_port; port++) 233 1.1.2.2 yamt mask |= 234 1.1.2.2 yamt MVSATA_PCI_MAINIRQ_SATAERR(hc, port) | 235 1.1.2.2 yamt MVSATA_PCI_MAINIRQ_SATADONE(hc, port); 236 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINIRQMASK, 237 1.1.2.2 yamt mask); 238 1.1.2.2 yamt 239 1.1.2.2 yamt if (!pmf_device_register(self, NULL, mvsata_pci_resume)) 240 1.1.2.2 yamt aprint_error_dev(self, "couldn't establish power handler\n"); 241 1.1.2.2 yamt } 242 1.1.2.2 yamt 243 1.1.2.2 yamt static int 244 1.1.2.2 yamt mvsata_pci_detach(device_t self, int flags) 245 1.1.2.2 yamt { 246 1.1.2.2 yamt struct mvsata_pci_softc *psc = device_private(self); 247 1.1.2.2 yamt 248 1.1.2.2 yamt /* XXXX: needs reset ? */ 249 1.1.2.2 yamt 250 1.1.2.2 yamt pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 251 1.1.2.2 yamt pmf_device_deregister(self); 252 1.1.2.2 yamt return 0; 253 1.1.2.2 yamt } 254 1.1.2.2 yamt 255 1.1.2.2 yamt static int 256 1.1.2.2 yamt mvsata_pci_intr(void *arg) 257 1.1.2.2 yamt { 258 1.1.2.2 yamt struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)arg; 259 1.1.2.2 yamt struct mvsata_softc *sc = &psc->psc_sc; 260 1.1.2.2 yamt uint32_t cause; 261 1.1.2.2 yamt int hc, port, handled = 0; 262 1.1.2.2 yamt 263 1.1.2.2 yamt cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 264 1.1.2.2 yamt MVSATA_PCI_MAINIRQCAUSE); 265 1.1.2.2 yamt for (hc = 0; hc < sc->sc_hc; hc++) 266 1.1.2.2 yamt for (port = 0; port < sc->sc_port; port++) 267 1.1.2.2 yamt if (cause & MVSATA_PCI_MAINIRQ_SATAERR(hc, port)) { 268 1.1.2.2 yamt struct mvsata_port *mvport; 269 1.1.2.2 yamt 270 1.1.2.2 yamt mvport = sc->sc_hcs[hc].hc_ports[port]; 271 1.1.2.2 yamt handled |= mvsata_error(mvport); 272 1.1.2.2 yamt } 273 1.1.2.2 yamt for (hc = 0; hc < sc->sc_hc; hc++) 274 1.1.2.2 yamt if (cause & 275 1.1.2.2 yamt (MVSATA_PCI_MAINIRQ_SATADONE(hc, 0) | 276 1.1.2.2 yamt MVSATA_PCI_MAINIRQ_SATADONE(hc, 1) | 277 1.1.2.2 yamt MVSATA_PCI_MAINIRQ_SATADONE(hc, 2) | 278 1.1.2.2 yamt MVSATA_PCI_MAINIRQ_SATADONE(hc, 3))) 279 1.1.2.2 yamt handled |= mvsata_intr(&sc->sc_hcs[hc]); 280 1.1.2.2 yamt 281 1.1.2.2 yamt if (cause & MVSATA_PCI_MAINIRQ_PCI) { 282 1.1.2.2 yamt uint32_t pe_cause; 283 1.1.2.2 yamt 284 1.1.2.2 yamt if (sc->sc_flags & MVSATA_FLAGS_PCIE) { 285 1.1.2.2 yamt pe_cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 286 1.1.2.2 yamt MVSATA_PCI_E_IRQCAUSE); 287 1.1.2.2 yamt aprint_error_dev(MVSATA_PCI_DEV(psc), 288 1.1.2.2 yamt "PCIe error: 0x%x\n", pe_cause); 289 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 290 1.1.2.2 yamt MVSATA_PCI_E_IRQCAUSE, ~pe_cause); 291 1.1.2.2 yamt } else { 292 1.1.2.2 yamt pe_cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 293 1.1.2.2 yamt MVSATA_PCI_IRQCAUSE); 294 1.1.2.2 yamt aprint_error_dev(MVSATA_PCI_DEV(psc), 295 1.1.2.2 yamt "PCI error: 0x%x\n", pe_cause); 296 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 297 1.1.2.2 yamt MVSATA_PCI_IRQCAUSE, ~pe_cause); 298 1.1.2.2 yamt } 299 1.1.2.2 yamt 300 1.1.2.2 yamt handled = 1; /* XXXXX */ 301 1.1.2.2 yamt } 302 1.1.2.2 yamt 303 1.1.2.2 yamt return handled; 304 1.1.2.2 yamt } 305 1.1.2.2 yamt 306 1.1.2.2 yamt static bool 307 1.1.2.3 yamt mvsata_pci_resume(device_t dev, const pmf_qual_t *qual) 308 1.1.2.2 yamt { 309 1.1.2.2 yamt 310 1.1.2.2 yamt /* not yet... */ 311 1.1.2.2 yamt 312 1.1.2.2 yamt return true; 313 1.1.2.2 yamt } 314 1.1.2.2 yamt 315 1.1.2.2 yamt 316 1.1.2.2 yamt static int 317 1.1.2.2 yamt mvsata_pci_sreset(struct mvsata_softc *sc) 318 1.1.2.2 yamt { 319 1.1.2.2 yamt struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)sc; 320 1.1.2.2 yamt uint32_t val; 321 1.1.2.2 yamt int i; 322 1.1.2.2 yamt 323 1.1.2.2 yamt val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS); 324 1.1.2.2 yamt val |= MVSATA_PCI_MAINCS_SPM; 325 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, val); 326 1.1.2.2 yamt 327 1.1.2.2 yamt for (i = 0; i < 1000; i++) { 328 1.1.2.2 yamt delay(1); 329 1.1.2.2 yamt val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 330 1.1.2.2 yamt MVSATA_PCI_MAINCS); 331 1.1.2.2 yamt if (val & MVSATA_PCI_MAINCS_PME) 332 1.1.2.2 yamt break; 333 1.1.2.2 yamt } 334 1.1.2.2 yamt if (!(val & MVSATA_PCI_MAINCS_PME)) { 335 1.1.2.2 yamt aprint_error_dev(MVSATA_PCI_DEV(psc), 336 1.1.2.2 yamt "PCI master won't flush\n"); 337 1.1.2.2 yamt return -1; 338 1.1.2.2 yamt } 339 1.1.2.2 yamt 340 1.1.2.2 yamt /* reset */ 341 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, 342 1.1.2.2 yamt val | MVSATA_PCI_MAINCS_GSR); 343 1.1.2.2 yamt val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS); 344 1.1.2.2 yamt delay(5); 345 1.1.2.2 yamt if (!(val & MVSATA_PCI_MAINCS_GSR)) { 346 1.1.2.2 yamt aprint_error_dev(MVSATA_PCI_DEV(psc), 347 1.1.2.2 yamt "can't set global reset\n"); 348 1.1.2.2 yamt return -1; 349 1.1.2.2 yamt } 350 1.1.2.2 yamt 351 1.1.2.2 yamt /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 352 1.1.2.2 yamt val &= ~(MVSATA_PCI_MAINCS_GSR | MVSATA_PCI_MAINCS_SPM); 353 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, val); 354 1.1.2.2 yamt val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS); 355 1.1.2.2 yamt delay(5); 356 1.1.2.2 yamt if (val & MVSATA_PCI_MAINCS_GSR) { 357 1.1.2.2 yamt aprint_error_dev(MVSATA_PCI_DEV(psc), 358 1.1.2.2 yamt "can't set global reset\n"); 359 1.1.2.2 yamt return -1; 360 1.1.2.2 yamt } 361 1.1.2.2 yamt 362 1.1.2.2 yamt return 0; 363 1.1.2.2 yamt } 364 1.1.2.2 yamt 365 1.1.2.2 yamt static int 366 1.1.2.2 yamt mvsata_pci_misc_reset(struct mvsata_softc *sc) 367 1.1.2.2 yamt { 368 1.1.2.2 yamt struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)sc; 369 1.1.2.2 yamt #define MVSATA_PCI_COMMAND_DEFAULT 0x0107e371 370 1.1.2.2 yamt #define MVSATA_PCI_COMMAND_PCI_CONVENTIONAL_ONLY 0x800003e0 371 1.1.2.2 yamt uint32_t val, pci_command = MVSATA_PCI_COMMAND_DEFAULT; 372 1.1.2.2 yamt 373 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_FLASHCTL, 374 1.1.2.2 yamt 0x0fcfffff); 375 1.1.2.2 yamt 376 1.1.2.2 yamt if (sc->sc_gen == gen2 || sc->sc_gen == gen2e) { 377 1.1.2.2 yamt val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 378 1.1.2.2 yamt MVSATA_PCI_GPIOPORTCTL); 379 1.1.2.2 yamt val &= 0x3; 380 1.1.2.2 yamt #if 0 381 1.1.2.2 yamt val |= 0x00000060; 382 1.1.2.2 yamt #else /* XXXX */ 383 1.1.2.2 yamt val |= 0x00000070; 384 1.1.2.2 yamt #endif 385 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 386 1.1.2.2 yamt MVSATA_PCI_GPIOPORTCTL, val); 387 1.1.2.2 yamt } 388 1.1.2.2 yamt 389 1.1.2.2 yamt if (sc->sc_gen == gen1) { 390 1.1.2.2 yamt /* Expansion ROM BAR Enable */ 391 1.1.2.2 yamt val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 392 1.1.2.2 yamt MVSATA_PCI_EROMBAR); 393 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 394 1.1.2.2 yamt MVSATA_PCI_EROMBAR, val | 0x00000001); 395 1.1.2.2 yamt } 396 1.1.2.2 yamt 397 1.1.2.2 yamt if (sc->sc_flags & MVSATA_FLAGS_PCIE) { 398 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 399 1.1.2.2 yamt MVSATA_PCI_MAINIRQMASK, 0); 400 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 401 1.1.2.2 yamt MVSATA_PCI_E_IRQCAUSE, 0); 402 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 403 1.1.2.2 yamt MVSATA_PCI_E_IRQMASK, 0); 404 1.1.2.2 yamt } else { 405 1.1.2.2 yamt val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 406 1.1.2.2 yamt MVSATA_PCI_MODE); 407 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 408 1.1.2.2 yamt MVSATA_PCI_MODE, val & 0xff00ffff); 409 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 410 1.1.2.2 yamt MVSATA_PCI_DISCTIMER, 0); 411 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 412 1.1.2.2 yamt MVSATA_PCI_MSITRIGGER, 0); 413 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 414 1.1.2.2 yamt MVSATA_PCI_XBARTIMEOUT, 0x000100ff); 415 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 416 1.1.2.2 yamt MVSATA_PCI_MAINIRQMASK, 0); 417 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 418 1.1.2.2 yamt MVSATA_PCI_SERRMASK, 0); 419 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 420 1.1.2.2 yamt MVSATA_PCI_IRQCAUSE, 0); 421 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 422 1.1.2.2 yamt MVSATA_PCI_IRQMASK, 0); 423 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 424 1.1.2.2 yamt MVSATA_PCI_ERRLOWADDR, 0); 425 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 426 1.1.2.2 yamt MVSATA_PCI_ERRHIGHADDR, 0); 427 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 428 1.1.2.2 yamt MVSATA_PCI_ERRATTRIBUTE, 0); 429 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 430 1.1.2.2 yamt MVSATA_PCI_ERRCOMMAND, 0); 431 1.1.2.2 yamt } 432 1.1.2.2 yamt 433 1.1.2.2 yamt /* Enable LED */ 434 1.1.2.2 yamt if (sc->sc_gen == gen1) { 435 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 436 1.1.2.2 yamt MVSATA_PCI_GPIOPORTCTL, 0); 437 1.1.2.2 yamt 438 1.1.2.2 yamt /* XXXX: 50xxB2 errata ? */ 439 1.1.2.2 yamt #if 0 440 1.1.2.2 yamt if (sc->sc_rev == 3) { 441 1.1.2.2 yamt int port; 442 1.1.2.2 yamt 443 1.1.2.2 yamt val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 444 1.1.2.2 yamt MVSATA_PCI_GPIOPORTCTL); 445 1.1.2.2 yamt 446 1.1.2.2 yamt /* XXXX: check HDD connected */ 447 1.1.2.2 yamt 448 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 449 1.1.2.2 yamt MVSATA_PCI_GPIOPORTCTL, val); 450 1.1.2.2 yamt } 451 1.1.2.2 yamt #endif 452 1.1.2.2 yamt 453 1.1.2.2 yamt /* Disable Flash controller clock */ 454 1.1.2.2 yamt val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 455 1.1.2.2 yamt MVSATA_PCI_EROMBAR); 456 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 457 1.1.2.2 yamt MVSATA_PCI_EROMBAR, val & ~0x00000001); 458 1.1.2.2 yamt } else 459 1.1.2.2 yamt #if 0 460 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 461 1.1.2.2 yamt MVSATA_PCI_GPIOPORTCTL, 0x00000060); 462 1.1.2.2 yamt #else /* XXXX */ 463 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 464 1.1.2.2 yamt MVSATA_PCI_GPIOPORTCTL, 0x00000070); 465 1.1.2.2 yamt #endif 466 1.1.2.2 yamt 467 1.1.2.2 yamt if (sc->sc_flags & MVSATA_FLAGS_PCIE) 468 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 469 1.1.2.2 yamt MVSATA_PCI_E_IRQMASK, 0x0000070a); 470 1.1.2.2 yamt else { 471 1.1.2.2 yamt val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 472 1.1.2.2 yamt MVSATA_PCI_MODE); 473 1.1.2.2 yamt if ((val & 0x30) >> 4) { /* PCI-X */ 474 1.1.2.2 yamt int mv60x1b2 = 475 1.1.2.2 yamt ((sc->sc_model == PCI_PRODUCT_MARVELL_88SX6041 || 476 1.1.2.2 yamt sc->sc_model == PCI_PRODUCT_MARVELL_88SX6081) && 477 1.1.2.2 yamt sc->sc_rev == 7); 478 1.1.2.2 yamt 479 1.1.2.2 yamt pci_command &= 480 1.1.2.2 yamt ~MVSATA_PCI_COMMAND_PCI_CONVENTIONAL_ONLY; 481 1.1.2.2 yamt if (sc->sc_gen == gen1 || mv60x1b2) 482 1.1.2.2 yamt pci_command &= 483 1.1.2.2 yamt ~MVSATA_PCI_COMMAND_MWRITECOMBINE; 484 1.1.2.2 yamt } else 485 1.1.2.2 yamt if (sc->sc_gen == gen1) 486 1.1.2.2 yamt pci_command &= 487 1.1.2.2 yamt ~(MVSATA_PCI_COMMAND_MWRITECOMBINE | 488 1.1.2.2 yamt MVSATA_PCI_COMMAND_MREADCOMBINE); 489 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 490 1.1.2.2 yamt MVSATA_PCI_COMMAND, pci_command); 491 1.1.2.2 yamt 492 1.1.2.2 yamt #define MVSATA_PCI_INTERRUPT_MASK 0x00d77fe6 493 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 494 1.1.2.2 yamt MVSATA_PCI_SERRMASK, MVSATA_PCI_INTERRUPT_MASK); 495 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, 496 1.1.2.2 yamt MVSATA_PCI_IRQMASK, MVSATA_PCI_INTERRUPT_MASK); 497 1.1.2.2 yamt } 498 1.1.2.2 yamt 499 1.1.2.2 yamt return 0; 500 1.1.2.2 yamt } 501 1.1.2.2 yamt 502 1.1.2.2 yamt static void 503 1.1.2.2 yamt mvsata_pci_enable_intr(struct mvsata_port *mvport, int on) 504 1.1.2.2 yamt { 505 1.1.2.2 yamt struct mvsata_pci_softc *psc = 506 1.1.2.2 yamt device_private(mvport->port_ata_channel.ch_atac->atac_dev); 507 1.1.2.2 yamt uint32_t mask; 508 1.1.2.2 yamt int hc = mvport->port_hc->hc, port = mvport->port; 509 1.1.2.2 yamt 510 1.1.2.2 yamt mask = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 511 1.1.2.2 yamt MVSATA_PCI_MAINIRQMASK); 512 1.1.2.2 yamt if (on) 513 1.1.2.2 yamt mask |= MVSATA_PCI_MAINIRQ_SATADONE(hc, port); 514 1.1.2.2 yamt else 515 1.1.2.2 yamt mask &= ~MVSATA_PCI_MAINIRQ_SATADONE(hc, port); 516 1.1.2.2 yamt bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINIRQMASK, 517 1.1.2.2 yamt mask); 518 1.1.2.2 yamt } 519
Indexes created Thu Oct 02 14:10:14 GMT 2025