mvsata_pci.c revision 1.6
1 /* $NetBSD: mvsata_pci.c,v 1.6 2011/01/31 16:30:48 jakllsch Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata_pci.c,v 1.6 2011/01/31 16:30:48 jakllsch Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/device.h> 34 #include <sys/errno.h> 35 #include <sys/pmf.h> 36 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcidevs.h> 39 #include <dev/pci/pciidereg.h> 40 #include <dev/pci/pciidevar.h> 41 42 #include <dev/ic/mvsatareg.h> 43 #include <dev/ic/mvsatavar.h> 44 45 #define MVSATA_PCI_HCARBITER_SPACE_OFFSET 0x20000 46 47 #define MVSATA_PCI_COMMAND 0x00c00 48 #define MVSATA_PCI_COMMAND_MWRITECOMBINE (1 << 4) 49 #define MVSATA_PCI_COMMAND_MREADCOMBINE (1 << 5) 50 #define MVSATA_PCI_SERRMASK 0x00c28 51 #define MVSATA_PCI_MSITRIGGER 0x00c38 52 #define MVSATA_PCI_MODE 0x00d00 53 #define MVSATA_PCI_DISCTIMER 0x00d04 54 #define MVSATA_PCI_EROMBAR 0x00d2c 55 #define MVSATA_PCI_MAINCS 0x00d30 56 #define MVSATA_PCI_MAINCS_SPM (1 << 2) /* stop pci master */ 57 #define MVSATA_PCI_MAINCS_PME (1 << 3) /* pci master empty */ 58 #define MVSATA_PCI_MAINCS_GSR (1 << 4) /* glab soft reset */ 59 #define MVSATA_PCI_E_IRQCAUSE 0x01900 60 #define MVSATA_PCI_E_IRQMASK 0x01910 61 #define MVSATA_PCI_XBARTIMEOUT 0x01d04 62 #define MVSATA_PCI_ERRLOWADDR 0x01d40 63 #define MVSATA_PCI_ERRHIGHADDR 0x01d44 64 #define MVSATA_PCI_ERRATTRIBUTE 0x01d48 65 #define MVSATA_PCI_ERRCOMMAND 0x01d50 66 #define MVSATA_PCI_IRQCAUSE 0x01d58 67 #define MVSATA_PCI_IRQMASK 0x01d5c 68 #define MVSATA_PCI_MAINIRQCAUSE 0x01d60 69 #define MVSATA_PCI_MAINIRQMASK 0x01d64 70 #define MVSATA_PCI_MAINIRQ_SATAERR(hc, port) \ 71 (1 << (((port) << 1) + (hc) * 9)) 72 #define MVSATA_PCI_MAINIRQ_SATADONE(hc, port) \ 73 (1 << (((port) << 1) + (hc) * 9 + 1)) 74 #define MVSATA_PCI_MAINIRQ_SATACOALDONE(hc) (1 << ((hc) * 9 + 8)) 75 #define MVSATA_PCI_MAINIRQ_PCI (1 << 18) 76 #define MVSATA_PCI_FLASHCTL 0x1046c 77 #define MVSATA_PCI_GPIOPORTCTL 0x104f0 78 #define MVSATA_PCI_RESETCFG 0x180d8 79 80 #define MVSATA_PCI_DEV(psc) (psc->psc_sc.sc_wdcdev.sc_atac.atac_dev) 81 82 83 struct mvsata_pci_softc { 84 struct mvsata_softc psc_sc; 85 86 pci_chipset_tag_t psc_pc; 87 pcitag_t psc_tag; 88 89 bus_space_tag_t psc_iot; 90 bus_space_handle_t psc_ioh; 91 92 void *psc_ih; 93 }; 94 95 96 static int mvsata_pci_match(device_t, struct cfdata *, void *); 97 static void mvsata_pci_attach(device_t, device_t, void *); 98 static int mvsata_pci_detach(device_t, int); 99 100 static int mvsata_pci_intr(void *); 101 static bool mvsata_pci_resume(device_t, const pmf_qual_t *qual); 102 103 static int mvsata_pci_sreset(struct mvsata_softc *); 104 static int mvsata_pci_misc_reset(struct mvsata_softc *); 105 static void mvsata_pci_enable_intr(struct mvsata_port *, int); 106 107 108 CFATTACH_DECL_NEW(mvsata_pci, sizeof(struct mvsata_pci_softc), 109 mvsata_pci_match, mvsata_pci_attach, mvsata_pci_detach, NULL); 110 111 struct mvsata_product mvsata_pci_products[] = { 112 #define PCI_VP(v, p) PCI_VENDOR_ ## v, PCI_PRODUCT_ ## v ## _ ## p 113 { PCI_VP(MARVELL, 88SX5040), 1, 4, gen1, 0 }, 114 { PCI_VP(MARVELL, 88SX5041), 1, 4, gen1, 0 }, 115 { PCI_VP(MARVELL, 88SX5080), 2, 4, gen1, 0 }, 116 { PCI_VP(MARVELL, 88SX5081), 2, 4, gen1, 0 }, 117 { PCI_VP(MARVELL, 88SX6040), 1, 4, gen2, 0 }, 118 { PCI_VP(MARVELL, 88SX6041), 1, 4, gen2, 0 }, 119 { PCI_VP(ADP2, 1420SA), 1, 4, gen2, 0 }, /* 88SX6041 */ 120 { PCI_VP(MARVELL, 88SX6042), 1, 4, gen2e, 0 }, 121 { PCI_VP(MARVELL, 88SX6080), 2, 4, gen2, MVSATA_FLAGS_PCIE }, 122 { PCI_VP(MARVELL, 88SX6081), 2, 4, gen2, MVSATA_FLAGS_PCIE }, 123 { PCI_VP(MARVELL, 88SX7042), 1, 4, gen2e, 0 }, 124 { PCI_VP(ADP2, 1430SA), 1, 4, gen2e, 0 }, /* 88SX7042 */ 125 { PCI_VP(TRIONES, ROCKETRAID_2310), 1, 4, gen2e, 0 }, 126 #undef PCI_VP 127 }; 128 129 130 /* 131 * mvsata_pci_match() 132 * This function returns 2, because mvsata is high priority more than pciide. 133 */ 134 static int 135 mvsata_pci_match(device_t parent, struct cfdata *match, void *aux) 136 { 137 struct pci_attach_args *pa = aux; 138 int i; 139 140 for (i = 0; i < __arraycount(mvsata_pci_products); i++) 141 if (PCI_VENDOR(pa->pa_id) == mvsata_pci_products[i].vendor && 142 PCI_PRODUCT(pa->pa_id) == mvsata_pci_products[i].model) 143 return 2; 144 return 0; 145 } 146 147 static void 148 mvsata_pci_attach(device_t parent, device_t self, void *aux) 149 { 150 struct pci_attach_args *pa = aux; 151 struct mvsata_pci_softc *psc = device_private(self); 152 struct mvsata_softc *sc = &psc->psc_sc; 153 pci_intr_handle_t intrhandle; 154 pcireg_t csr; 155 bus_size_t size; 156 uint32_t reg, mask; 157 int read_pre_amps, hc, port, rv, i; 158 char devinfo[256]; 159 const char *intrstr; 160 161 sc->sc_wdcdev.sc_atac.atac_dev = self; 162 sc->sc_model = PCI_PRODUCT(pa->pa_id); 163 sc->sc_rev = PCI_REVISION(pa->pa_class); 164 sc->sc_dmat = pa->pa_dmat; 165 sc->sc_enable_intr = mvsata_pci_enable_intr; 166 167 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 168 aprint_naive(": Marvell Serial-ATA Host Controller\n"); 169 aprint_normal(": %s\n", devinfo); 170 171 /* Map I/O register */ 172 if (pci_mapreg_map(pa, PCI_MAPREG_START, 173 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 174 &psc->psc_iot, &psc->psc_ioh, NULL, &size) != 0) { 175 aprint_error_dev(self, "can't map registers\n"); 176 return; 177 } 178 psc->psc_pc = pa->pa_pc; 179 psc->psc_tag = pa->pa_tag; 180 181 if (bus_space_subregion(psc->psc_iot, psc->psc_ioh, 182 MVSATA_PCI_HCARBITER_SPACE_OFFSET, 183 size - MVSATA_PCI_HCARBITER_SPACE_OFFSET, &sc->sc_ioh)) { 184 aprint_error_dev(self, "can't subregion registers\n"); 185 return; 186 } 187 sc->sc_iot = psc->psc_iot; 188 189 /* Enable device */ 190 csr = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 191 csr |= PCI_COMMAND_MASTER_ENABLE; 192 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG, csr); 193 194 if (pci_intr_map(pa, &intrhandle) != 0) { 195 aprint_error_dev(self, "couldn't map interrupt\n"); 196 return; 197 } 198 intrstr = pci_intr_string(psc->psc_pc, intrhandle); 199 psc->psc_ih = pci_intr_establish(psc->psc_pc, intrhandle, IPL_BIO, 200 mvsata_pci_intr, sc); 201 if (psc->psc_ih == NULL) { 202 aprint_error_dev(self, "couldn't establish interrupt\n"); 203 return; 204 } 205 aprint_normal_dev(self, "interrupting at %s\n", 206 intrstr ? intrstr : "unknown interrupt"); 207 208 /* 209 * Check if TWSI serial ROM initialization was triggered. 210 * If so, then PRE/AMP configuration probably are set after 211 * reset by serial ROM. If not then override the PRE/AMP 212 * values. 213 */ 214 reg = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_RESETCFG); 215 read_pre_amps = (reg & 0x00000001) ? 1 : 0; 216 217 for (i = 0; i < __arraycount(mvsata_pci_products); i++) 218 if (PCI_VENDOR(pa->pa_id) == mvsata_pci_products[i].vendor && 219 PCI_PRODUCT(pa->pa_id) == mvsata_pci_products[i].model) 220 break; 221 KASSERT(i < __arraycount(mvsata_pci_products)); 222 223 rv = mvsata_attach(sc, &mvsata_pci_products[i], 224 mvsata_pci_sreset, mvsata_pci_misc_reset, read_pre_amps); 225 if (rv != 0) { 226 pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 227 return; 228 } 229 230 mask = MVSATA_PCI_MAINIRQ_PCI; 231 for (hc = 0; hc < sc->sc_hc; hc++) 232 for (port = 0; port < sc->sc_port; port++) 233 mask |= 234 MVSATA_PCI_MAINIRQ_SATAERR(hc, port) | 235 MVSATA_PCI_MAINIRQ_SATADONE(hc, port); 236 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINIRQMASK, 237 mask); 238 239 if (!pmf_device_register(self, NULL, mvsata_pci_resume)) 240 aprint_error_dev(self, "couldn't establish power handler\n"); 241 } 242 243 static int 244 mvsata_pci_detach(device_t self, int flags) 245 { 246 struct mvsata_pci_softc *psc = device_private(self); 247 248 /* XXXX: needs reset ? */ 249 250 pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 251 pmf_device_deregister(self); 252 return 0; 253 } 254 255 static int 256 mvsata_pci_intr(void *arg) 257 { 258 struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)arg; 259 struct mvsata_softc *sc = &psc->psc_sc; 260 uint32_t cause; 261 int hc, port, handled = 0; 262 263 cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 264 MVSATA_PCI_MAINIRQCAUSE); 265 for (hc = 0; hc < sc->sc_hc; hc++) 266 for (port = 0; port < sc->sc_port; port++) 267 if (cause & MVSATA_PCI_MAINIRQ_SATAERR(hc, port)) { 268 struct mvsata_port *mvport; 269 270 mvport = sc->sc_hcs[hc].hc_ports[port]; 271 handled |= mvsata_error(mvport); 272 } 273 for (hc = 0; hc < sc->sc_hc; hc++) 274 if (cause & 275 (MVSATA_PCI_MAINIRQ_SATADONE(hc, 0) | 276 MVSATA_PCI_MAINIRQ_SATADONE(hc, 1) | 277 MVSATA_PCI_MAINIRQ_SATADONE(hc, 2) | 278 MVSATA_PCI_MAINIRQ_SATADONE(hc, 3))) 279 handled |= mvsata_intr(&sc->sc_hcs[hc]); 280 281 if (cause & MVSATA_PCI_MAINIRQ_PCI) { 282 uint32_t pe_cause; 283 284 if (sc->sc_flags & MVSATA_FLAGS_PCIE) { 285 pe_cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 286 MVSATA_PCI_E_IRQCAUSE); 287 aprint_error_dev(MVSATA_PCI_DEV(psc), 288 "PCIe error: 0x%x\n", pe_cause); 289 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 290 MVSATA_PCI_E_IRQCAUSE, ~pe_cause); 291 } else { 292 pe_cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 293 MVSATA_PCI_IRQCAUSE); 294 aprint_error_dev(MVSATA_PCI_DEV(psc), 295 "PCI error: 0x%x\n", pe_cause); 296 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 297 MVSATA_PCI_IRQCAUSE, ~pe_cause); 298 } 299 300 handled = 1; /* XXXXX */ 301 } 302 303 return handled; 304 } 305 306 static bool 307 mvsata_pci_resume(device_t dev, const pmf_qual_t *qual) 308 { 309 310 /* not yet... */ 311 312 return true; 313 } 314 315 316 static int 317 mvsata_pci_sreset(struct mvsata_softc *sc) 318 { 319 struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)sc; 320 uint32_t val; 321 int i; 322 323 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS); 324 val |= MVSATA_PCI_MAINCS_SPM; 325 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, val); 326 327 for (i = 0; i < 1000; i++) { 328 delay(1); 329 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 330 MVSATA_PCI_MAINCS); 331 if (val & MVSATA_PCI_MAINCS_PME) 332 break; 333 } 334 if (!(val & MVSATA_PCI_MAINCS_PME)) { 335 aprint_error_dev(MVSATA_PCI_DEV(psc), 336 "PCI master won't flush\n"); 337 return -1; 338 } 339 340 /* reset */ 341 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, 342 val | MVSATA_PCI_MAINCS_GSR); 343 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS); 344 delay(5); 345 if (!(val & MVSATA_PCI_MAINCS_GSR)) { 346 aprint_error_dev(MVSATA_PCI_DEV(psc), 347 "can't set global reset\n"); 348 return -1; 349 } 350 351 /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 352 val &= ~(MVSATA_PCI_MAINCS_GSR | MVSATA_PCI_MAINCS_SPM); 353 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, val); 354 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS); 355 delay(5); 356 if (val & MVSATA_PCI_MAINCS_GSR) { 357 aprint_error_dev(MVSATA_PCI_DEV(psc), 358 "can't set global reset\n"); 359 return -1; 360 } 361 362 return 0; 363 } 364 365 static int 366 mvsata_pci_misc_reset(struct mvsata_softc *sc) 367 { 368 struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)sc; 369 #define MVSATA_PCI_COMMAND_DEFAULT 0x0107e371 370 #define MVSATA_PCI_COMMAND_PCI_CONVENTIONAL_ONLY 0x800003e0 371 uint32_t val, pci_command = MVSATA_PCI_COMMAND_DEFAULT; 372 373 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_FLASHCTL, 374 0x0fcfffff); 375 376 if (sc->sc_gen == gen2 || sc->sc_gen == gen2e) { 377 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 378 MVSATA_PCI_GPIOPORTCTL); 379 val &= 0x3; 380 #if 0 381 val |= 0x00000060; 382 #else /* XXXX */ 383 val |= 0x00000070; 384 #endif 385 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 386 MVSATA_PCI_GPIOPORTCTL, val); 387 } 388 389 if (sc->sc_gen == gen1) { 390 /* Expansion ROM BAR Enable */ 391 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 392 MVSATA_PCI_EROMBAR); 393 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 394 MVSATA_PCI_EROMBAR, val | 0x00000001); 395 } 396 397 if (sc->sc_flags & MVSATA_FLAGS_PCIE) { 398 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 399 MVSATA_PCI_MAINIRQMASK, 0); 400 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 401 MVSATA_PCI_E_IRQCAUSE, 0); 402 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 403 MVSATA_PCI_E_IRQMASK, 0); 404 } else { 405 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 406 MVSATA_PCI_MODE); 407 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 408 MVSATA_PCI_MODE, val & 0xff00ffff); 409 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 410 MVSATA_PCI_DISCTIMER, 0); 411 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 412 MVSATA_PCI_MSITRIGGER, 0); 413 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 414 MVSATA_PCI_XBARTIMEOUT, 0x000100ff); 415 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 416 MVSATA_PCI_MAINIRQMASK, 0); 417 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 418 MVSATA_PCI_SERRMASK, 0); 419 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 420 MVSATA_PCI_IRQCAUSE, 0); 421 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 422 MVSATA_PCI_IRQMASK, 0); 423 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 424 MVSATA_PCI_ERRLOWADDR, 0); 425 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 426 MVSATA_PCI_ERRHIGHADDR, 0); 427 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 428 MVSATA_PCI_ERRATTRIBUTE, 0); 429 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 430 MVSATA_PCI_ERRCOMMAND, 0); 431 } 432 433 /* Enable LED */ 434 if (sc->sc_gen == gen1) { 435 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 436 MVSATA_PCI_GPIOPORTCTL, 0); 437 438 /* XXXX: 50xxB2 errata ? */ 439 #if 0 440 if (sc->sc_rev == 3) { 441 int port; 442 443 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 444 MVSATA_PCI_GPIOPORTCTL); 445 446 /* XXXX: check HDD connected */ 447 448 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 449 MVSATA_PCI_GPIOPORTCTL, val); 450 } 451 #endif 452 453 /* Disable Flash controller clock */ 454 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 455 MVSATA_PCI_EROMBAR); 456 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 457 MVSATA_PCI_EROMBAR, val & ~0x00000001); 458 } else 459 #if 0 460 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 461 MVSATA_PCI_GPIOPORTCTL, 0x00000060); 462 #else /* XXXX */ 463 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 464 MVSATA_PCI_GPIOPORTCTL, 0x00000070); 465 #endif 466 467 if (sc->sc_flags & MVSATA_FLAGS_PCIE) 468 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 469 MVSATA_PCI_E_IRQMASK, 0x0000070a); 470 else { 471 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 472 MVSATA_PCI_MODE); 473 if ((val & 0x30) >> 4) { /* PCI-X */ 474 int mv60x1b2 = 475 ((sc->sc_model == PCI_PRODUCT_MARVELL_88SX6041 || 476 sc->sc_model == PCI_PRODUCT_MARVELL_88SX6081) && 477 sc->sc_rev == 7); 478 479 pci_command &= 480 ~MVSATA_PCI_COMMAND_PCI_CONVENTIONAL_ONLY; 481 if (sc->sc_gen == gen1 || mv60x1b2) 482 pci_command &= 483 ~MVSATA_PCI_COMMAND_MWRITECOMBINE; 484 } else 485 if (sc->sc_gen == gen1) 486 pci_command &= 487 ~(MVSATA_PCI_COMMAND_MWRITECOMBINE | 488 MVSATA_PCI_COMMAND_MREADCOMBINE); 489 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 490 MVSATA_PCI_COMMAND, pci_command); 491 492 #define MVSATA_PCI_INTERRUPT_MASK 0x00d77fe6 493 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 494 MVSATA_PCI_SERRMASK, MVSATA_PCI_INTERRUPT_MASK); 495 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 496 MVSATA_PCI_IRQMASK, MVSATA_PCI_INTERRUPT_MASK); 497 } 498 499 return 0; 500 } 501 502 static void 503 mvsata_pci_enable_intr(struct mvsata_port *mvport, int on) 504 { 505 struct mvsata_pci_softc *psc = 506 device_private(mvport->port_ata_channel.ch_atac->atac_dev); 507 uint32_t mask; 508 int hc = mvport->port_hc->hc, port = mvport->port; 509 510 mask = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 511 MVSATA_PCI_MAINIRQMASK); 512 if (on) 513 mask |= MVSATA_PCI_MAINIRQ_SATADONE(hc, port); 514 else 515 mask &= ~MVSATA_PCI_MAINIRQ_SATADONE(hc, port); 516 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINIRQMASK, 517 mask); 518 } 519
Indexes created Mon Sep 29 21:09:56 GMT 2025