mvsata_pci.c revision 1.6.8.1
1 /* $NetBSD: mvsata_pci.c,v 1.6.8.1 2012/02/18 07:34:45 mrg Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata_pci.c,v 1.6.8.1 2012/02/18 07:34:45 mrg Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/device.h> 34 #include <sys/errno.h> 35 #include <sys/pmf.h> 36 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcidevs.h> 39 #include <dev/pci/pciidereg.h> 40 #include <dev/pci/pciidevar.h> 41 42 #include <dev/ic/mvsatareg.h> 43 #include <dev/ic/mvsatavar.h> 44 45 #define MVSATA_PCI_HCARBITER_SPACE_OFFSET 0x20000 46 47 #define MVSATA_PCI_COMMAND 0x00c00 48 #define MVSATA_PCI_COMMAND_MWRITECOMBINE (1 << 4) 49 #define MVSATA_PCI_COMMAND_MREADCOMBINE (1 << 5) 50 #define MVSATA_PCI_SERRMASK 0x00c28 51 #define MVSATA_PCI_MSITRIGGER 0x00c38 52 #define MVSATA_PCI_MODE 0x00d00 53 #define MVSATA_PCI_DISCTIMER 0x00d04 54 #define MVSATA_PCI_EROMBAR 0x00d2c 55 #define MVSATA_PCI_MAINCS 0x00d30 56 #define MVSATA_PCI_MAINCS_SPM (1 << 2) /* stop pci master */ 57 #define MVSATA_PCI_MAINCS_PME (1 << 3) /* pci master empty */ 58 #define MVSATA_PCI_MAINCS_GSR (1 << 4) /* glab soft reset */ 59 #define MVSATA_PCI_E_IRQCAUSE 0x01900 60 #define MVSATA_PCI_E_IRQMASK 0x01910 61 #define MVSATA_PCI_XBARTIMEOUT 0x01d04 62 #define MVSATA_PCI_ERRLOWADDR 0x01d40 63 #define MVSATA_PCI_ERRHIGHADDR 0x01d44 64 #define MVSATA_PCI_ERRATTRIBUTE 0x01d48 65 #define MVSATA_PCI_ERRCOMMAND 0x01d50 66 #define MVSATA_PCI_IRQCAUSE 0x01d58 67 #define MVSATA_PCI_IRQMASK 0x01d5c 68 #define MVSATA_PCI_MAINIRQCAUSE 0x01d60 69 #define MVSATA_PCI_MAINIRQMASK 0x01d64 70 #define MVSATA_PCI_MAINIRQ_SATAERR(hc, port) \ 71 (1 << (((port) << 1) + (hc) * 9)) 72 #define MVSATA_PCI_MAINIRQ_SATADONE(hc, port) \ 73 (1 << (((port) << 1) + (hc) * 9 + 1)) 74 #define MVSATA_PCI_MAINIRQ_SATACOALDONE(hc) (1 << ((hc) * 9 + 8)) 75 #define MVSATA_PCI_MAINIRQ_PCI (1 << 18) 76 #define MVSATA_PCI_FLASHCTL 0x1046c 77 #define MVSATA_PCI_GPIOPORTCTL 0x104f0 78 #define MVSATA_PCI_RESETCFG 0x180d8 79 80 #define MVSATA_PCI_DEV(psc) (psc->psc_sc.sc_wdcdev.sc_atac.atac_dev) 81 82 83 struct mvsata_pci_softc { 84 struct mvsata_softc psc_sc; 85 86 pci_chipset_tag_t psc_pc; 87 pcitag_t psc_tag; 88 89 bus_space_tag_t psc_iot; 90 bus_space_handle_t psc_ioh; 91 92 void *psc_ih; 93 }; 94 95 96 static int mvsata_pci_match(device_t, struct cfdata *, void *); 97 static void mvsata_pci_attach(device_t, device_t, void *); 98 static int mvsata_pci_detach(device_t, int); 99 100 static int mvsata_pci_intr(void *); 101 static bool mvsata_pci_resume(device_t, const pmf_qual_t *qual); 102 103 static int mvsata_pci_sreset(struct mvsata_softc *); 104 static int mvsata_pci_misc_reset(struct mvsata_softc *); 105 static void mvsata_pci_enable_intr(struct mvsata_port *, int); 106 107 108 CFATTACH_DECL_NEW(mvsata_pci, sizeof(struct mvsata_pci_softc), 109 mvsata_pci_match, mvsata_pci_attach, mvsata_pci_detach, NULL); 110 111 struct mvsata_product mvsata_pci_products[] = { 112 #define PCI_VP(v, p) PCI_VENDOR_ ## v, PCI_PRODUCT_ ## v ## _ ## p 113 { PCI_VP(MARVELL, 88SX5040), 1, 4, gen1, 0 }, 114 { PCI_VP(MARVELL, 88SX5041), 1, 4, gen1, 0 }, 115 { PCI_VP(MARVELL, 88SX5080), 2, 4, gen1, 0 }, 116 { PCI_VP(MARVELL, 88SX5081), 2, 4, gen1, 0 }, 117 { PCI_VP(MARVELL, 88SX6040), 1, 4, gen2, 0 }, 118 { PCI_VP(MARVELL, 88SX6041), 1, 4, gen2, 0 }, 119 { PCI_VP(ADP2, 1420SA), 1, 4, gen2, 0 }, /* 88SX6041 */ 120 { PCI_VP(MARVELL, 88SX6042), 1, 4, gen2e, 0 }, 121 { PCI_VP(MARVELL, 88SX6080), 2, 4, gen2, MVSATA_FLAGS_PCIE }, 122 { PCI_VP(MARVELL, 88SX6081), 2, 4, gen2, MVSATA_FLAGS_PCIE }, 123 { PCI_VP(MARVELL, 88SX7042), 1, 4, gen2e, 0 }, 124 { PCI_VP(ADP2, 1430SA), 1, 4, gen2e, 0 }, /* 88SX7042 */ 125 { PCI_VP(TRIONES, ROCKETRAID_2310), 1, 4, gen2e, 0 }, 126 #undef PCI_VP 127 }; 128 129 130 /* 131 * mvsata_pci_match() 132 * This function returns 2, because mvsata is high priority more than pciide. 133 */ 134 static int 135 mvsata_pci_match(device_t parent, struct cfdata *match, void *aux) 136 { 137 struct pci_attach_args *pa = aux; 138 int i; 139 140 for (i = 0; i < __arraycount(mvsata_pci_products); i++) 141 if (PCI_VENDOR(pa->pa_id) == mvsata_pci_products[i].vendor && 142 PCI_PRODUCT(pa->pa_id) == mvsata_pci_products[i].model) 143 return 2; 144 return 0; 145 } 146 147 static void 148 mvsata_pci_attach(device_t parent, device_t self, void *aux) 149 { 150 struct pci_attach_args *pa = aux; 151 struct mvsata_pci_softc *psc = device_private(self); 152 struct mvsata_softc *sc = &psc->psc_sc; 153 pci_intr_handle_t intrhandle; 154 pcireg_t csr; 155 bus_size_t size; 156 uint32_t reg, mask; 157 int read_pre_amps, hc, port, rv, i; 158 const char *intrstr; 159 160 sc->sc_wdcdev.sc_atac.atac_dev = self; 161 sc->sc_model = PCI_PRODUCT(pa->pa_id); 162 sc->sc_rev = PCI_REVISION(pa->pa_class); 163 sc->sc_dmat = pa->pa_dmat; 164 sc->sc_enable_intr = mvsata_pci_enable_intr; 165 166 pci_aprint_devinfo(pa, "Marvell Serial-ATA Host Controller"); 167 168 /* Map I/O register */ 169 if (pci_mapreg_map(pa, PCI_MAPREG_START, 170 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 171 &psc->psc_iot, &psc->psc_ioh, NULL, &size) != 0) { 172 aprint_error_dev(self, "can't map registers\n"); 173 return; 174 } 175 psc->psc_pc = pa->pa_pc; 176 psc->psc_tag = pa->pa_tag; 177 178 if (bus_space_subregion(psc->psc_iot, psc->psc_ioh, 179 MVSATA_PCI_HCARBITER_SPACE_OFFSET, 180 size - MVSATA_PCI_HCARBITER_SPACE_OFFSET, &sc->sc_ioh)) { 181 aprint_error_dev(self, "can't subregion registers\n"); 182 return; 183 } 184 sc->sc_iot = psc->psc_iot; 185 186 /* Enable device */ 187 csr = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 188 csr |= PCI_COMMAND_MASTER_ENABLE; 189 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG, csr); 190 191 if (pci_intr_map(pa, &intrhandle) != 0) { 192 aprint_error_dev(self, "couldn't map interrupt\n"); 193 return; 194 } 195 intrstr = pci_intr_string(psc->psc_pc, intrhandle); 196 psc->psc_ih = pci_intr_establish(psc->psc_pc, intrhandle, IPL_BIO, 197 mvsata_pci_intr, sc); 198 if (psc->psc_ih == NULL) { 199 aprint_error_dev(self, "couldn't establish interrupt\n"); 200 return; 201 } 202 aprint_normal_dev(self, "interrupting at %s\n", 203 intrstr ? intrstr : "unknown interrupt"); 204 205 /* 206 * Check if TWSI serial ROM initialization was triggered. 207 * If so, then PRE/AMP configuration probably are set after 208 * reset by serial ROM. If not then override the PRE/AMP 209 * values. 210 */ 211 reg = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_RESETCFG); 212 read_pre_amps = (reg & 0x00000001) ? 1 : 0; 213 214 for (i = 0; i < __arraycount(mvsata_pci_products); i++) 215 if (PCI_VENDOR(pa->pa_id) == mvsata_pci_products[i].vendor && 216 PCI_PRODUCT(pa->pa_id) == mvsata_pci_products[i].model) 217 break; 218 KASSERT(i < __arraycount(mvsata_pci_products)); 219 220 rv = mvsata_attach(sc, &mvsata_pci_products[i], 221 mvsata_pci_sreset, mvsata_pci_misc_reset, read_pre_amps); 222 if (rv != 0) { 223 pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 224 return; 225 } 226 227 mask = MVSATA_PCI_MAINIRQ_PCI; 228 for (hc = 0; hc < sc->sc_hc; hc++) 229 for (port = 0; port < sc->sc_port; port++) 230 mask |= 231 MVSATA_PCI_MAINIRQ_SATAERR(hc, port) | 232 MVSATA_PCI_MAINIRQ_SATADONE(hc, port); 233 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINIRQMASK, 234 mask); 235 236 if (!pmf_device_register(self, NULL, mvsata_pci_resume)) 237 aprint_error_dev(self, "couldn't establish power handler\n"); 238 } 239 240 static int 241 mvsata_pci_detach(device_t self, int flags) 242 { 243 struct mvsata_pci_softc *psc = device_private(self); 244 245 /* XXXX: needs reset ? */ 246 247 pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 248 pmf_device_deregister(self); 249 return 0; 250 } 251 252 static int 253 mvsata_pci_intr(void *arg) 254 { 255 struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)arg; 256 struct mvsata_softc *sc = &psc->psc_sc; 257 uint32_t cause; 258 int hc, port, handled = 0; 259 260 cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 261 MVSATA_PCI_MAINIRQCAUSE); 262 for (hc = 0; hc < sc->sc_hc; hc++) 263 for (port = 0; port < sc->sc_port; port++) 264 if (cause & MVSATA_PCI_MAINIRQ_SATAERR(hc, port)) { 265 struct mvsata_port *mvport; 266 267 mvport = sc->sc_hcs[hc].hc_ports[port]; 268 handled |= mvsata_error(mvport); 269 } 270 for (hc = 0; hc < sc->sc_hc; hc++) 271 if (cause & 272 (MVSATA_PCI_MAINIRQ_SATADONE(hc, 0) | 273 MVSATA_PCI_MAINIRQ_SATADONE(hc, 1) | 274 MVSATA_PCI_MAINIRQ_SATADONE(hc, 2) | 275 MVSATA_PCI_MAINIRQ_SATADONE(hc, 3))) 276 handled |= mvsata_intr(&sc->sc_hcs[hc]); 277 278 if (cause & MVSATA_PCI_MAINIRQ_PCI) { 279 uint32_t pe_cause; 280 281 if (sc->sc_flags & MVSATA_FLAGS_PCIE) { 282 pe_cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 283 MVSATA_PCI_E_IRQCAUSE); 284 aprint_error_dev(MVSATA_PCI_DEV(psc), 285 "PCIe error: 0x%x\n", pe_cause); 286 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 287 MVSATA_PCI_E_IRQCAUSE, ~pe_cause); 288 } else { 289 pe_cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 290 MVSATA_PCI_IRQCAUSE); 291 aprint_error_dev(MVSATA_PCI_DEV(psc), 292 "PCI error: 0x%x\n", pe_cause); 293 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 294 MVSATA_PCI_IRQCAUSE, ~pe_cause); 295 } 296 297 handled = 1; /* XXXXX */ 298 } 299 300 return handled; 301 } 302 303 static bool 304 mvsata_pci_resume(device_t dev, const pmf_qual_t *qual) 305 { 306 307 /* not yet... */ 308 309 return true; 310 } 311 312 313 static int 314 mvsata_pci_sreset(struct mvsata_softc *sc) 315 { 316 struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)sc; 317 uint32_t val; 318 int i; 319 320 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS); 321 val |= MVSATA_PCI_MAINCS_SPM; 322 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, val); 323 324 for (i = 0; i < 1000; i++) { 325 delay(1); 326 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 327 MVSATA_PCI_MAINCS); 328 if (val & MVSATA_PCI_MAINCS_PME) 329 break; 330 } 331 if (!(val & MVSATA_PCI_MAINCS_PME)) { 332 aprint_error_dev(MVSATA_PCI_DEV(psc), 333 "PCI master won't flush\n"); 334 return -1; 335 } 336 337 /* reset */ 338 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, 339 val | MVSATA_PCI_MAINCS_GSR); 340 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS); 341 delay(5); 342 if (!(val & MVSATA_PCI_MAINCS_GSR)) { 343 aprint_error_dev(MVSATA_PCI_DEV(psc), 344 "can't set global reset\n"); 345 return -1; 346 } 347 348 /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 349 val &= ~(MVSATA_PCI_MAINCS_GSR | MVSATA_PCI_MAINCS_SPM); 350 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, val); 351 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS); 352 delay(5); 353 if (val & MVSATA_PCI_MAINCS_GSR) { 354 aprint_error_dev(MVSATA_PCI_DEV(psc), 355 "can't set global reset\n"); 356 return -1; 357 } 358 359 return 0; 360 } 361 362 static int 363 mvsata_pci_misc_reset(struct mvsata_softc *sc) 364 { 365 struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)sc; 366 #define MVSATA_PCI_COMMAND_DEFAULT 0x0107e371 367 #define MVSATA_PCI_COMMAND_PCI_CONVENTIONAL_ONLY 0x800003e0 368 uint32_t val, pci_command = MVSATA_PCI_COMMAND_DEFAULT; 369 370 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_FLASHCTL, 371 0x0fcfffff); 372 373 if (sc->sc_gen == gen2 || sc->sc_gen == gen2e) { 374 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 375 MVSATA_PCI_GPIOPORTCTL); 376 val &= 0x3; 377 #if 0 378 val |= 0x00000060; 379 #else /* XXXX */ 380 val |= 0x00000070; 381 #endif 382 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 383 MVSATA_PCI_GPIOPORTCTL, val); 384 } 385 386 if (sc->sc_gen == gen1) { 387 /* Expansion ROM BAR Enable */ 388 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 389 MVSATA_PCI_EROMBAR); 390 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 391 MVSATA_PCI_EROMBAR, val | 0x00000001); 392 } 393 394 if (sc->sc_flags & MVSATA_FLAGS_PCIE) { 395 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 396 MVSATA_PCI_MAINIRQMASK, 0); 397 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 398 MVSATA_PCI_E_IRQCAUSE, 0); 399 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 400 MVSATA_PCI_E_IRQMASK, 0); 401 } else { 402 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 403 MVSATA_PCI_MODE); 404 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 405 MVSATA_PCI_MODE, val & 0xff00ffff); 406 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 407 MVSATA_PCI_DISCTIMER, 0); 408 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 409 MVSATA_PCI_MSITRIGGER, 0); 410 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 411 MVSATA_PCI_XBARTIMEOUT, 0x000100ff); 412 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 413 MVSATA_PCI_MAINIRQMASK, 0); 414 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 415 MVSATA_PCI_SERRMASK, 0); 416 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 417 MVSATA_PCI_IRQCAUSE, 0); 418 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 419 MVSATA_PCI_IRQMASK, 0); 420 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 421 MVSATA_PCI_ERRLOWADDR, 0); 422 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 423 MVSATA_PCI_ERRHIGHADDR, 0); 424 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 425 MVSATA_PCI_ERRATTRIBUTE, 0); 426 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 427 MVSATA_PCI_ERRCOMMAND, 0); 428 } 429 430 /* Enable LED */ 431 if (sc->sc_gen == gen1) { 432 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 433 MVSATA_PCI_GPIOPORTCTL, 0); 434 435 /* XXXX: 50xxB2 errata ? */ 436 #if 0 437 if (sc->sc_rev == 3) { 438 int port; 439 440 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 441 MVSATA_PCI_GPIOPORTCTL); 442 443 /* XXXX: check HDD connected */ 444 445 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 446 MVSATA_PCI_GPIOPORTCTL, val); 447 } 448 #endif 449 450 /* Disable Flash controller clock */ 451 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 452 MVSATA_PCI_EROMBAR); 453 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 454 MVSATA_PCI_EROMBAR, val & ~0x00000001); 455 } else 456 #if 0 457 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 458 MVSATA_PCI_GPIOPORTCTL, 0x00000060); 459 #else /* XXXX */ 460 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 461 MVSATA_PCI_GPIOPORTCTL, 0x00000070); 462 #endif 463 464 if (sc->sc_flags & MVSATA_FLAGS_PCIE) 465 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 466 MVSATA_PCI_E_IRQMASK, 0x0000070a); 467 else { 468 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 469 MVSATA_PCI_MODE); 470 if ((val & 0x30) >> 4) { /* PCI-X */ 471 int mv60x1b2 = 472 ((sc->sc_model == PCI_PRODUCT_MARVELL_88SX6041 || 473 sc->sc_model == PCI_PRODUCT_MARVELL_88SX6081) && 474 sc->sc_rev == 7); 475 476 pci_command &= 477 ~MVSATA_PCI_COMMAND_PCI_CONVENTIONAL_ONLY; 478 if (sc->sc_gen == gen1 || mv60x1b2) 479 pci_command &= 480 ~MVSATA_PCI_COMMAND_MWRITECOMBINE; 481 } else 482 if (sc->sc_gen == gen1) 483 pci_command &= 484 ~(MVSATA_PCI_COMMAND_MWRITECOMBINE | 485 MVSATA_PCI_COMMAND_MREADCOMBINE); 486 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 487 MVSATA_PCI_COMMAND, pci_command); 488 489 #define MVSATA_PCI_INTERRUPT_MASK 0x00d77fe6 490 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 491 MVSATA_PCI_SERRMASK, MVSATA_PCI_INTERRUPT_MASK); 492 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 493 MVSATA_PCI_IRQMASK, MVSATA_PCI_INTERRUPT_MASK); 494 } 495 496 return 0; 497 } 498 499 static void 500 mvsata_pci_enable_intr(struct mvsata_port *mvport, int on) 501 { 502 struct mvsata_pci_softc *psc = 503 device_private(mvport->port_ata_channel.ch_atac->atac_dev); 504 uint32_t mask; 505 int hc = mvport->port_hc->hc, port = mvport->port; 506 507 mask = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 508 MVSATA_PCI_MAINIRQMASK); 509 if (on) 510 mask |= MVSATA_PCI_MAINIRQ_SATADONE(hc, port); 511 else 512 mask &= ~MVSATA_PCI_MAINIRQ_SATADONE(hc, port); 513 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINIRQMASK, 514 mask); 515 } 516
Indexes created Thu Oct 02 10:09:58 GMT 2025