nvme_pci.c revision 1.2.2.2
1 1.2.2.2 skrll /* $NetBSD: nvme_pci.c,v 1.2.2.2 2016/05/29 08:44:22 skrll Exp $ */ 2 1.2.2.2 skrll /* $OpenBSD: nvme_pci.c,v 1.3 2016/04/14 11:18:32 dlg Exp $ */ 3 1.2.2.2 skrll 4 1.2.2.2 skrll /* 5 1.2.2.2 skrll * Copyright (c) 2014 David Gwynne <dlg (at) openbsd.org> 6 1.2.2.2 skrll * 7 1.2.2.2 skrll * Permission to use, copy, modify, and distribute this software for any 8 1.2.2.2 skrll * purpose with or without fee is hereby granted, provided that the above 9 1.2.2.2 skrll * copyright notice and this permission notice appear in all copies. 10 1.2.2.2 skrll * 11 1.2.2.2 skrll * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 1.2.2.2 skrll * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 1.2.2.2 skrll * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 1.2.2.2 skrll * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 1.2.2.2 skrll * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 1.2.2.2 skrll * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 1.2.2.2 skrll * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 1.2.2.2 skrll */ 19 1.2.2.2 skrll 20 1.2.2.2 skrll /*- 21 1.2.2.2 skrll * Copyright (C) 2016 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 1.2.2.2 skrll * All rights reserved. 23 1.2.2.2 skrll * 24 1.2.2.2 skrll * Redistribution and use in source and binary forms, with or without 25 1.2.2.2 skrll * modification, are permitted provided that the following conditions 26 1.2.2.2 skrll * are met: 27 1.2.2.2 skrll * 1. Redistributions of source code must retain the above copyright 28 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer. 29 1.2.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 30 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer in the 31 1.2.2.2 skrll * documentation and/or other materials provided with the distribution. 32 1.2.2.2 skrll * 33 1.2.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 1.2.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 1.2.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 1.2.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 1.2.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 38 1.2.2.2 skrll * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 1.2.2.2 skrll * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 1.2.2.2 skrll * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 1.2.2.2 skrll * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 42 1.2.2.2 skrll * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 1.2.2.2 skrll */ 44 1.2.2.2 skrll 45 1.2.2.2 skrll #include <sys/cdefs.h> 46 1.2.2.2 skrll __KERNEL_RCSID(0, "$NetBSD: nvme_pci.c,v 1.2.2.2 2016/05/29 08:44:22 skrll Exp $"); 47 1.2.2.2 skrll 48 1.2.2.2 skrll #include <sys/param.h> 49 1.2.2.2 skrll #include <sys/systm.h> 50 1.2.2.2 skrll #include <sys/kernel.h> 51 1.2.2.2 skrll #include <sys/device.h> 52 1.2.2.2 skrll #include <sys/bitops.h> 53 1.2.2.2 skrll #include <sys/bus.h> 54 1.2.2.2 skrll #include <sys/cpu.h> 55 1.2.2.2 skrll #include <sys/interrupt.h> 56 1.2.2.2 skrll #include <sys/kmem.h> 57 1.2.2.2 skrll #include <sys/pmf.h> 58 1.2.2.2 skrll 59 1.2.2.2 skrll #include <dev/pci/pcireg.h> 60 1.2.2.2 skrll #include <dev/pci/pcivar.h> 61 1.2.2.2 skrll 62 1.2.2.2 skrll #include <dev/ic/nvmereg.h> 63 1.2.2.2 skrll #include <dev/ic/nvmevar.h> 64 1.2.2.2 skrll 65 1.2.2.2 skrll int nvme_pci_force_intx = 0; 66 1.2.2.2 skrll int nvme_pci_mpsafe = 0; 67 1.2.2.2 skrll int nvme_pci_mq = 1; /* INTx: ioq=1, MSI/MSI-X: ioq=ncpu */ 68 1.2.2.2 skrll 69 1.2.2.2 skrll #define NVME_PCI_BAR 0x10 70 1.2.2.2 skrll 71 1.2.2.2 skrll struct nvme_pci_softc { 72 1.2.2.2 skrll struct nvme_softc psc_nvme; 73 1.2.2.2 skrll 74 1.2.2.2 skrll pci_chipset_tag_t psc_pc; 75 1.2.2.2 skrll pci_intr_handle_t *psc_intrs; 76 1.2.2.2 skrll int psc_nintrs; 77 1.2.2.2 skrll }; 78 1.2.2.2 skrll 79 1.2.2.2 skrll static int nvme_pci_match(device_t, cfdata_t, void *); 80 1.2.2.2 skrll static void nvme_pci_attach(device_t, device_t, void *); 81 1.2.2.2 skrll static int nvme_pci_detach(device_t, int); 82 1.2.2.2 skrll 83 1.2.2.2 skrll CFATTACH_DECL3_NEW(nvme_pci, sizeof(struct nvme_pci_softc), 84 1.2.2.2 skrll nvme_pci_match, nvme_pci_attach, nvme_pci_detach, NULL, NULL, 85 1.2.2.2 skrll nvme_childdet, DVF_DETACH_SHUTDOWN); 86 1.2.2.2 skrll 87 1.2.2.2 skrll static int nvme_pci_intr_establish(struct nvme_softc *, 88 1.2.2.2 skrll uint16_t, struct nvme_queue *); 89 1.2.2.2 skrll static int nvme_pci_intr_disestablish(struct nvme_softc *, uint16_t); 90 1.2.2.2 skrll static int nvme_pci_setup_intr(struct pci_attach_args *, 91 1.2.2.2 skrll struct nvme_pci_softc *); 92 1.2.2.2 skrll 93 1.2.2.2 skrll static int 94 1.2.2.2 skrll nvme_pci_match(device_t parent, cfdata_t match, void *aux) 95 1.2.2.2 skrll { 96 1.2.2.2 skrll struct pci_attach_args *pa = aux; 97 1.2.2.2 skrll 98 1.2.2.2 skrll if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 99 1.2.2.2 skrll PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_NVM && 100 1.2.2.2 skrll PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_NVM_NVME) 101 1.2.2.2 skrll return 1; 102 1.2.2.2 skrll 103 1.2.2.2 skrll return 0; 104 1.2.2.2 skrll } 105 1.2.2.2 skrll 106 1.2.2.2 skrll static void 107 1.2.2.2 skrll nvme_pci_attach(device_t parent, device_t self, void *aux) 108 1.2.2.2 skrll { 109 1.2.2.2 skrll struct nvme_pci_softc *psc = device_private(self); 110 1.2.2.2 skrll struct nvme_softc *sc = &psc->psc_nvme; 111 1.2.2.2 skrll struct pci_attach_args *pa = aux; 112 1.2.2.2 skrll pcireg_t memtype; 113 1.2.2.2 skrll bus_addr_t memaddr; 114 1.2.2.2 skrll int flags, msixoff; 115 1.2.2.2 skrll int nq, error; 116 1.2.2.2 skrll 117 1.2.2.2 skrll sc->sc_dev = self; 118 1.2.2.2 skrll psc->psc_pc = pa->pa_pc; 119 1.2.2.2 skrll if (pci_dma64_available(pa)) 120 1.2.2.2 skrll sc->sc_dmat = pa->pa_dmat64; 121 1.2.2.2 skrll else 122 1.2.2.2 skrll sc->sc_dmat = pa->pa_dmat; 123 1.2.2.2 skrll 124 1.2.2.2 skrll pci_aprint_devinfo(pa, NULL); 125 1.2.2.2 skrll 126 1.2.2.2 skrll /* Map registers */ 127 1.2.2.2 skrll memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NVME_PCI_BAR); 128 1.2.2.2 skrll if (PCI_MAPREG_TYPE(memtype) != PCI_MAPREG_TYPE_MEM) { 129 1.2.2.2 skrll aprint_error_dev(self, "invalid type (type=0x%x)\n", memtype); 130 1.2.2.2 skrll return; 131 1.2.2.2 skrll } 132 1.2.2.2 skrll sc->sc_iot = pa->pa_memt; 133 1.2.2.2 skrll error = pci_mapreg_info(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, 134 1.2.2.2 skrll memtype, &memaddr, &sc->sc_ios, &flags); 135 1.2.2.2 skrll if (error) { 136 1.2.2.2 skrll aprint_error_dev(self, "can't get map info\n"); 137 1.2.2.2 skrll return; 138 1.2.2.2 skrll } 139 1.2.2.2 skrll if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &msixoff, 140 1.2.2.2 skrll NULL)) { 141 1.2.2.2 skrll pcireg_t msixtbl; 142 1.2.2.2 skrll uint32_t table_offset; 143 1.2.2.2 skrll int bir; 144 1.2.2.2 skrll 145 1.2.2.2 skrll msixtbl = pci_conf_read(pa->pa_pc, pa->pa_tag, 146 1.2.2.2 skrll msixoff + PCI_MSIX_TBLOFFSET); 147 1.2.2.2 skrll table_offset = msixtbl & PCI_MSIX_TBLOFFSET_MASK; 148 1.2.2.2 skrll bir = msixtbl & PCI_MSIX_PBABIR_MASK; 149 1.2.2.2 skrll if (bir == 0) { 150 1.2.2.2 skrll sc->sc_ios = table_offset; 151 1.2.2.2 skrll } 152 1.2.2.2 skrll } 153 1.2.2.2 skrll error = bus_space_map(sc->sc_iot, memaddr, sc->sc_ios, flags, 154 1.2.2.2 skrll &sc->sc_ioh); 155 1.2.2.2 skrll if (error != 0) { 156 1.2.2.2 skrll aprint_error_dev(self, "can't map mem space (error=%d)\n", 157 1.2.2.2 skrll error); 158 1.2.2.2 skrll return; 159 1.2.2.2 skrll } 160 1.2.2.2 skrll 161 1.2.2.2 skrll /* Establish interrupts */ 162 1.2.2.2 skrll if (nvme_pci_setup_intr(pa, psc) != 0) { 163 1.2.2.2 skrll aprint_error_dev(self, "unable to allocate interrupt\n"); 164 1.2.2.2 skrll goto unmap; 165 1.2.2.2 skrll } 166 1.2.2.2 skrll sc->sc_intr_establish = nvme_pci_intr_establish; 167 1.2.2.2 skrll sc->sc_intr_disestablish = nvme_pci_intr_disestablish; 168 1.2.2.2 skrll 169 1.2.2.2 skrll nq = sc->sc_nq + (sc->sc_use_mq ? 1 : 0); 170 1.2.2.2 skrll sc->sc_ih = kmem_zalloc(sizeof(*sc->sc_ih) * nq, KM_SLEEP); 171 1.2.2.2 skrll if (sc->sc_ih == NULL) { 172 1.2.2.2 skrll aprint_error_dev(self, "unable to allocate ih memory\n"); 173 1.2.2.2 skrll goto intr_release; 174 1.2.2.2 skrll } 175 1.2.2.2 skrll 176 1.2.2.2 skrll if (nvme_attach(sc) != 0) { 177 1.2.2.2 skrll /* error printed by nvme_attach() */ 178 1.2.2.2 skrll goto intr_free; 179 1.2.2.2 skrll } 180 1.2.2.2 skrll 181 1.2.2.2 skrll if (!pmf_device_register(self, NULL, NULL)) 182 1.2.2.2 skrll aprint_error_dev(self, "couldn't establish power handler\n"); 183 1.2.2.2 skrll 184 1.2.2.2 skrll SET(sc->sc_flags, NVME_F_ATTACHED); 185 1.2.2.2 skrll return; 186 1.2.2.2 skrll 187 1.2.2.2 skrll intr_free: 188 1.2.2.2 skrll kmem_free(sc->sc_ih, sizeof(*sc->sc_ih) * sc->sc_nq); 189 1.2.2.2 skrll sc->sc_nq = 0; 190 1.2.2.2 skrll intr_release: 191 1.2.2.2 skrll pci_intr_release(pa->pa_pc, psc->psc_intrs, psc->psc_nintrs); 192 1.2.2.2 skrll psc->psc_nintrs = 0; 193 1.2.2.2 skrll unmap: 194 1.2.2.2 skrll bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 195 1.2.2.2 skrll sc->sc_ios = 0; 196 1.2.2.2 skrll } 197 1.2.2.2 skrll 198 1.2.2.2 skrll static int 199 1.2.2.2 skrll nvme_pci_detach(device_t self, int flags) 200 1.2.2.2 skrll { 201 1.2.2.2 skrll struct nvme_pci_softc *psc = device_private(self); 202 1.2.2.2 skrll struct nvme_softc *sc = &psc->psc_nvme; 203 1.2.2.2 skrll int i, nq, error; 204 1.2.2.2 skrll 205 1.2.2.2 skrll if (!ISSET(sc->sc_flags, NVME_F_ATTACHED)) 206 1.2.2.2 skrll return 0; 207 1.2.2.2 skrll 208 1.2.2.2 skrll error = nvme_detach(sc, flags); 209 1.2.2.2 skrll if (error) 210 1.2.2.2 skrll return error; 211 1.2.2.2 skrll 212 1.2.2.2 skrll nq = sc->sc_nq + (sc->sc_use_mq ? 1 : 0); 213 1.2.2.2 skrll if (!sc->sc_use_mq) { 214 1.2.2.2 skrll for (i = 0; i < nq; i++) 215 1.2.2.2 skrll pci_intr_disestablish(psc->psc_pc, sc->sc_ih[i]); 216 1.2.2.2 skrll } 217 1.2.2.2 skrll kmem_free(sc->sc_ih, sizeof(*sc->sc_ih) * nq); 218 1.2.2.2 skrll pci_intr_release(psc->psc_pc, psc->psc_intrs, psc->psc_nintrs); 219 1.2.2.2 skrll bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 220 1.2.2.2 skrll return 0; 221 1.2.2.2 skrll } 222 1.2.2.2 skrll 223 1.2.2.2 skrll static int 224 1.2.2.2 skrll nvme_pci_intr_establish(struct nvme_softc *sc, uint16_t qid, 225 1.2.2.2 skrll struct nvme_queue *q) 226 1.2.2.2 skrll { 227 1.2.2.2 skrll struct nvme_pci_softc *psc = (struct nvme_pci_softc *)sc; 228 1.2.2.2 skrll char intr_xname[INTRDEVNAMEBUF]; 229 1.2.2.2 skrll char intrbuf[PCI_INTRSTR_LEN]; 230 1.2.2.2 skrll const char *intrstr = NULL; 231 1.2.2.2 skrll int (*ih_func)(void *); 232 1.2.2.2 skrll void *ih_arg; 233 1.2.2.2 skrll kcpuset_t *affinity; 234 1.2.2.2 skrll cpuid_t affinity_to; 235 1.2.2.2 skrll int error; 236 1.2.2.2 skrll 237 1.2.2.2 skrll if (!sc->sc_use_mq && qid > 0) 238 1.2.2.2 skrll return 0; 239 1.2.2.2 skrll 240 1.2.2.2 skrll KASSERT(sc->sc_ih[qid] == NULL); 241 1.2.2.2 skrll 242 1.2.2.2 skrll if (nvme_pci_mpsafe) { 243 1.2.2.2 skrll pci_intr_setattr(psc->psc_pc, &psc->psc_intrs[qid], 244 1.2.2.2 skrll PCI_INTR_MPSAFE, true); 245 1.2.2.2 skrll } 246 1.2.2.2 skrll if (!sc->sc_use_mq) { 247 1.2.2.2 skrll snprintf(intr_xname, sizeof(intr_xname), "%s", 248 1.2.2.2 skrll device_xname(sc->sc_dev)); 249 1.2.2.2 skrll ih_arg = sc; 250 1.2.2.2 skrll ih_func = nvme_intr; 251 1.2.2.2 skrll } else { 252 1.2.2.2 skrll if (qid == 0) { 253 1.2.2.2 skrll snprintf(intr_xname, sizeof(intr_xname), "%s adminq", 254 1.2.2.2 skrll device_xname(sc->sc_dev)); 255 1.2.2.2 skrll } else { 256 1.2.2.2 skrll snprintf(intr_xname, sizeof(intr_xname), "%s ioq%d", 257 1.2.2.2 skrll device_xname(sc->sc_dev), qid); 258 1.2.2.2 skrll } 259 1.2.2.2 skrll ih_arg = q; 260 1.2.2.2 skrll if (pci_intr_type(psc->psc_intrs[qid]) == PCI_INTR_TYPE_MSIX) 261 1.2.2.2 skrll ih_func = nvme_mq_msix_intr; 262 1.2.2.2 skrll else 263 1.2.2.2 skrll ih_func = nvme_mq_msi_intr; 264 1.2.2.2 skrll } 265 1.2.2.2 skrll sc->sc_ih[qid] = pci_intr_establish_xname(psc->psc_pc, 266 1.2.2.2 skrll psc->psc_intrs[qid], IPL_BIO, ih_func, ih_arg, intr_xname); 267 1.2.2.2 skrll if (sc->sc_ih[qid] == NULL) { 268 1.2.2.2 skrll aprint_error_dev(sc->sc_dev, 269 1.2.2.2 skrll "unable to establish %s interrupt\n", intr_xname); 270 1.2.2.2 skrll return 1; 271 1.2.2.2 skrll } 272 1.2.2.2 skrll intrstr = pci_intr_string(psc->psc_pc, psc->psc_intrs[qid], intrbuf, 273 1.2.2.2 skrll sizeof(intrbuf)); 274 1.2.2.2 skrll if (!sc->sc_use_mq) { 275 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 276 1.2.2.2 skrll } else if (qid == 0) { 277 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, 278 1.2.2.2 skrll "for admin queue interrupting at %s\n", intrstr); 279 1.2.2.2 skrll } else if (!nvme_pci_mpsafe) { 280 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, 281 1.2.2.2 skrll "for io queue %d interrupting at %s\n", qid, intrstr); 282 1.2.2.2 skrll } else { 283 1.2.2.2 skrll kcpuset_create(&affinity, true); 284 1.2.2.2 skrll affinity_to = (qid - 1) % ncpu; 285 1.2.2.2 skrll kcpuset_set(affinity, affinity_to); 286 1.2.2.2 skrll error = interrupt_distribute(sc->sc_ih[qid], affinity, NULL); 287 1.2.2.2 skrll kcpuset_destroy(affinity); 288 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, 289 1.2.2.2 skrll "for io queue %d interrupting at %s", qid, intrstr); 290 1.2.2.2 skrll if (error == 0) 291 1.2.2.2 skrll aprint_normal(" affinity to cpu%lu", affinity_to); 292 1.2.2.2 skrll aprint_normal("\n"); 293 1.2.2.2 skrll } 294 1.2.2.2 skrll return 0; 295 1.2.2.2 skrll } 296 1.2.2.2 skrll 297 1.2.2.2 skrll static int 298 1.2.2.2 skrll nvme_pci_intr_disestablish(struct nvme_softc *sc, uint16_t qid) 299 1.2.2.2 skrll { 300 1.2.2.2 skrll struct nvme_pci_softc *psc = (struct nvme_pci_softc *)sc; 301 1.2.2.2 skrll 302 1.2.2.2 skrll if (!sc->sc_use_mq && qid > 0) 303 1.2.2.2 skrll return 0; 304 1.2.2.2 skrll 305 1.2.2.2 skrll KASSERT(sc->sc_ih[qid] != NULL); 306 1.2.2.2 skrll 307 1.2.2.2 skrll pci_intr_disestablish(psc->psc_pc, sc->sc_ih[qid]); 308 1.2.2.2 skrll sc->sc_ih[qid] = NULL; 309 1.2.2.2 skrll 310 1.2.2.2 skrll return 0; 311 1.2.2.2 skrll } 312 1.2.2.2 skrll 313 1.2.2.2 skrll static int 314 1.2.2.2 skrll nvme_pci_setup_intr(struct pci_attach_args *pa, struct nvme_pci_softc *psc) 315 1.2.2.2 skrll { 316 1.2.2.2 skrll struct nvme_softc *sc = &psc->psc_nvme; 317 1.2.2.2 skrll pci_intr_handle_t *ihps; 318 1.2.2.2 skrll int counts[PCI_INTR_TYPE_SIZE], alloced_counts[PCI_INTR_TYPE_SIZE]; 319 1.2.2.2 skrll int max_type, intr_type; 320 1.2.2.2 skrll int error; 321 1.2.2.2 skrll 322 1.2.2.2 skrll if (nvme_pci_force_intx) { 323 1.2.2.2 skrll max_type = PCI_INTR_TYPE_INTX; 324 1.2.2.2 skrll goto force_intx; 325 1.2.2.2 skrll } 326 1.2.2.2 skrll 327 1.2.2.2 skrll /* MSI-X */ 328 1.2.2.2 skrll max_type = PCI_INTR_TYPE_MSIX; 329 1.2.2.2 skrll counts[PCI_INTR_TYPE_MSIX] = min(pci_msix_count(pa->pa_pc, pa->pa_tag), 330 1.2.2.2 skrll ncpu + 1); 331 1.2.2.2 skrll if (counts[PCI_INTR_TYPE_MSIX] > 0) { 332 1.2.2.2 skrll memset(alloced_counts, 0, sizeof(alloced_counts)); 333 1.2.2.2 skrll alloced_counts[PCI_INTR_TYPE_MSIX] = counts[PCI_INTR_TYPE_MSIX]; 334 1.2.2.2 skrll if (pci_intr_alloc(pa, &ihps, alloced_counts, 335 1.2.2.2 skrll PCI_INTR_TYPE_MSIX)) { 336 1.2.2.2 skrll counts[PCI_INTR_TYPE_MSIX] = 0; 337 1.2.2.2 skrll } else { 338 1.2.2.2 skrll counts[PCI_INTR_TYPE_MSIX] = 339 1.2.2.2 skrll alloced_counts[PCI_INTR_TYPE_MSIX]; 340 1.2.2.2 skrll pci_intr_release(pa->pa_pc, ihps, 341 1.2.2.2 skrll alloced_counts[PCI_INTR_TYPE_MSIX]); 342 1.2.2.2 skrll } 343 1.2.2.2 skrll } 344 1.2.2.2 skrll if (counts[PCI_INTR_TYPE_MSIX] < 2) { 345 1.2.2.2 skrll counts[PCI_INTR_TYPE_MSIX] = 0; 346 1.2.2.2 skrll max_type = PCI_INTR_TYPE_MSI; 347 1.2.2.2 skrll } else if (!nvme_pci_mq || !nvme_pci_mpsafe) { 348 1.2.2.2 skrll counts[PCI_INTR_TYPE_MSIX] = 2; /* adminq + 1 ioq */ 349 1.2.2.2 skrll } 350 1.2.2.2 skrll 351 1.2.2.2 skrll retry_msi: 352 1.2.2.2 skrll /* MSI */ 353 1.2.2.2 skrll counts[PCI_INTR_TYPE_MSI] = pci_msi_count(pa->pa_pc, pa->pa_tag); 354 1.2.2.2 skrll if (counts[PCI_INTR_TYPE_MSI] > 0) { 355 1.2.2.2 skrll while (counts[PCI_INTR_TYPE_MSI] > ncpu + 1) { 356 1.2.2.2 skrll if (counts[PCI_INTR_TYPE_MSI] / 2 <= ncpu + 1) 357 1.2.2.2 skrll break; 358 1.2.2.2 skrll counts[PCI_INTR_TYPE_MSI] /= 2; 359 1.2.2.2 skrll } 360 1.2.2.2 skrll memset(alloced_counts, 0, sizeof(alloced_counts)); 361 1.2.2.2 skrll alloced_counts[PCI_INTR_TYPE_MSI] = counts[PCI_INTR_TYPE_MSI]; 362 1.2.2.2 skrll if (pci_intr_alloc(pa, &ihps, alloced_counts, 363 1.2.2.2 skrll PCI_INTR_TYPE_MSI)) { 364 1.2.2.2 skrll counts[PCI_INTR_TYPE_MSI] = 0; 365 1.2.2.2 skrll } else { 366 1.2.2.2 skrll counts[PCI_INTR_TYPE_MSI] = 367 1.2.2.2 skrll alloced_counts[PCI_INTR_TYPE_MSI]; 368 1.2.2.2 skrll pci_intr_release(pa->pa_pc, ihps, 369 1.2.2.2 skrll alloced_counts[PCI_INTR_TYPE_MSI]); 370 1.2.2.2 skrll } 371 1.2.2.2 skrll } 372 1.2.2.2 skrll if (counts[PCI_INTR_TYPE_MSI] < 1) { 373 1.2.2.2 skrll counts[PCI_INTR_TYPE_MSI] = 0; 374 1.2.2.2 skrll if (max_type == PCI_INTR_TYPE_MSI) 375 1.2.2.2 skrll max_type = PCI_INTR_TYPE_INTX; 376 1.2.2.2 skrll } else if (!nvme_pci_mq || !nvme_pci_mpsafe) { 377 1.2.2.2 skrll if (counts[PCI_INTR_TYPE_MSI] > 2) 378 1.2.2.2 skrll counts[PCI_INTR_TYPE_MSI] = 2; /* adminq + 1 ioq */ 379 1.2.2.2 skrll } 380 1.2.2.2 skrll 381 1.2.2.2 skrll force_intx: 382 1.2.2.2 skrll /* INTx */ 383 1.2.2.2 skrll counts[PCI_INTR_TYPE_INTX] = 1; 384 1.2.2.2 skrll 385 1.2.2.2 skrll memcpy(alloced_counts, counts, sizeof(counts)); 386 1.2.2.2 skrll error = pci_intr_alloc(pa, &ihps, alloced_counts, max_type); 387 1.2.2.2 skrll if (error) { 388 1.2.2.2 skrll if (max_type != PCI_INTR_TYPE_INTX) { 389 1.2.2.2 skrll retry: 390 1.2.2.2 skrll memset(counts, 0, sizeof(counts)); 391 1.2.2.2 skrll if (max_type == PCI_INTR_TYPE_MSIX) { 392 1.2.2.2 skrll max_type = PCI_INTR_TYPE_MSI; 393 1.2.2.2 skrll goto retry_msi; 394 1.2.2.2 skrll } else { 395 1.2.2.2 skrll max_type = PCI_INTR_TYPE_INTX; 396 1.2.2.2 skrll goto force_intx; 397 1.2.2.2 skrll } 398 1.2.2.2 skrll } 399 1.2.2.2 skrll return error; 400 1.2.2.2 skrll } 401 1.2.2.2 skrll 402 1.2.2.2 skrll intr_type = pci_intr_type(ihps[0]); 403 1.2.2.2 skrll if (alloced_counts[intr_type] < counts[intr_type]) { 404 1.2.2.2 skrll if (intr_type != PCI_INTR_TYPE_INTX) { 405 1.2.2.2 skrll pci_intr_release(pa->pa_pc, ihps, 406 1.2.2.2 skrll alloced_counts[intr_type]); 407 1.2.2.2 skrll max_type = intr_type; 408 1.2.2.2 skrll goto retry; 409 1.2.2.2 skrll } 410 1.2.2.2 skrll return EBUSY; 411 1.2.2.2 skrll } 412 1.2.2.2 skrll 413 1.2.2.2 skrll psc->psc_intrs = ihps; 414 1.2.2.2 skrll psc->psc_nintrs = alloced_counts[intr_type]; 415 1.2.2.2 skrll if (intr_type == PCI_INTR_TYPE_MSI) { 416 1.2.2.2 skrll if (alloced_counts[intr_type] > ncpu + 1) 417 1.2.2.2 skrll alloced_counts[intr_type] = ncpu + 1; 418 1.2.2.2 skrll } 419 1.2.2.2 skrll sc->sc_use_mq = alloced_counts[intr_type] > 1; 420 1.2.2.2 skrll sc->sc_nq = sc->sc_use_mq ? alloced_counts[intr_type] - 1 : 1; 421 1.2.2.2 skrll return 0; 422 1.2.2.2 skrll } 423
Indexes created Fri Oct 03 02:09:57 GMT 2025