nvme_pci.c revision 1.11
1 /* $NetBSD: nvme_pci.c,v 1.11 2016/09/17 20:12:53 jdolecek Exp $ */ 2 /* $OpenBSD: nvme_pci.c,v 1.3 2016/04/14 11:18:32 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2014 David Gwynne <dlg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (C) 2016 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 38 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 42 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: nvme_pci.c,v 1.11 2016/09/17 20:12:53 jdolecek Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/device.h> 52 #include <sys/bitops.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/interrupt.h> 56 #include <sys/kmem.h> 57 #include <sys/pmf.h> 58 #include <sys/module.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 63 #include <dev/ic/nvmereg.h> 64 #include <dev/ic/nvmevar.h> 65 66 int nvme_pci_force_intx = 0; 67 int nvme_pci_mpsafe = 0; 68 int nvme_pci_mq = 1; /* INTx: ioq=1, MSI/MSI-X: ioq=ncpu */ 69 70 #define NVME_PCI_BAR 0x10 71 72 #ifndef __HAVE_PCI_MSI_MSIX 73 #define pci_intr_release(pc, intrs, nintrs) \ 74 kmem_free(intrs, sizeof(*intrs) * nintrs) 75 #define pci_intr_establish_xname(pc, ih, level, intrhand, intrarg, xname) \ 76 pci_intr_establish(pc, ih, level, intrhand, intrarg) 77 #endif 78 79 struct nvme_pci_softc { 80 struct nvme_softc psc_nvme; 81 82 pci_chipset_tag_t psc_pc; 83 pci_intr_handle_t *psc_intrs; 84 int psc_nintrs; 85 }; 86 87 static int nvme_pci_match(device_t, cfdata_t, void *); 88 static void nvme_pci_attach(device_t, device_t, void *); 89 static int nvme_pci_detach(device_t, int); 90 91 CFATTACH_DECL3_NEW(nvme_pci, sizeof(struct nvme_pci_softc), 92 nvme_pci_match, nvme_pci_attach, nvme_pci_detach, NULL, NULL, 93 nvme_childdet, DVF_DETACH_SHUTDOWN); 94 95 static int nvme_pci_intr_establish(struct nvme_softc *, 96 uint16_t, struct nvme_queue *); 97 static int nvme_pci_intr_disestablish(struct nvme_softc *, uint16_t); 98 static int nvme_pci_setup_intr(struct pci_attach_args *, 99 struct nvme_pci_softc *); 100 101 static int 102 nvme_pci_match(device_t parent, cfdata_t match, void *aux) 103 { 104 struct pci_attach_args *pa = aux; 105 106 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 107 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_NVM && 108 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_NVM_NVME) 109 return 1; 110 111 return 0; 112 } 113 114 static void 115 nvme_pci_attach(device_t parent, device_t self, void *aux) 116 { 117 struct nvme_pci_softc *psc = device_private(self); 118 struct nvme_softc *sc = &psc->psc_nvme; 119 struct pci_attach_args *pa = aux; 120 pcireg_t memtype, reg; 121 bus_addr_t memaddr; 122 int flags, error; 123 #ifdef __HAVE_PCI_MSI_MSIX 124 int msixoff; 125 #endif 126 127 sc->sc_dev = self; 128 psc->psc_pc = pa->pa_pc; 129 if (pci_dma64_available(pa)) 130 sc->sc_dmat = pa->pa_dmat64; 131 else 132 sc->sc_dmat = pa->pa_dmat; 133 134 pci_aprint_devinfo(pa, NULL); 135 136 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 137 if ((reg & PCI_COMMAND_MASTER_ENABLE) == 0) { 138 reg |= PCI_COMMAND_MASTER_ENABLE; 139 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 140 } 141 142 /* Map registers */ 143 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NVME_PCI_BAR); 144 if (PCI_MAPREG_TYPE(memtype) != PCI_MAPREG_TYPE_MEM) { 145 aprint_error_dev(self, "invalid type (type=0x%x)\n", memtype); 146 return; 147 } 148 sc->sc_iot = pa->pa_memt; 149 error = pci_mapreg_info(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, 150 memtype, &memaddr, &sc->sc_ios, &flags); 151 if (error) { 152 aprint_error_dev(self, "can't get map info\n"); 153 return; 154 } 155 156 #ifdef __HAVE_PCI_MSI_MSIX 157 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &msixoff, 158 NULL)) { 159 pcireg_t msixtbl; 160 uint32_t table_offset; 161 int bir; 162 163 msixtbl = pci_conf_read(pa->pa_pc, pa->pa_tag, 164 msixoff + PCI_MSIX_TBLOFFSET); 165 table_offset = msixtbl & PCI_MSIX_TBLOFFSET_MASK; 166 bir = msixtbl & PCI_MSIX_PBABIR_MASK; 167 if (bir == 0) { 168 sc->sc_ios = table_offset; 169 } 170 } 171 #endif /* __HAVE_PCI_MSI_MSIX */ 172 173 error = bus_space_map(sc->sc_iot, memaddr, sc->sc_ios, flags, 174 &sc->sc_ioh); 175 if (error != 0) { 176 aprint_error_dev(self, "can't map mem space (error=%d)\n", 177 error); 178 return; 179 } 180 181 /* Establish interrupts */ 182 if (nvme_pci_setup_intr(pa, psc) != 0) { 183 aprint_error_dev(self, "unable to allocate interrupt\n"); 184 goto unmap; 185 } 186 sc->sc_intr_establish = nvme_pci_intr_establish; 187 sc->sc_intr_disestablish = nvme_pci_intr_disestablish; 188 189 sc->sc_ih = kmem_zalloc(sizeof(*sc->sc_ih) * psc->psc_nintrs, KM_SLEEP); 190 if (sc->sc_ih == NULL) { 191 aprint_error_dev(self, "unable to allocate ih memory\n"); 192 goto intr_release; 193 } 194 195 sc->sc_softih = kmem_zalloc(sizeof(*sc->sc_softih) * psc->psc_nintrs, 196 KM_SLEEP); 197 if (sc->sc_softih == NULL) { 198 aprint_error_dev(self, "unable to allocate softih memory\n"); 199 goto intr_free; 200 } 201 202 if (nvme_attach(sc) != 0) { 203 /* error printed by nvme_attach() */ 204 goto softintr_free; 205 } 206 207 if (!pmf_device_register(self, NULL, NULL)) 208 aprint_error_dev(self, "couldn't establish power handler\n"); 209 210 SET(sc->sc_flags, NVME_F_ATTACHED); 211 return; 212 213 softintr_free: 214 kmem_free(sc->sc_softih, sizeof(*sc->sc_softih) * psc->psc_nintrs); 215 intr_free: 216 kmem_free(sc->sc_ih, sizeof(*sc->sc_ih) * psc->psc_nintrs); 217 sc->sc_nq = 0; 218 intr_release: 219 pci_intr_release(pa->pa_pc, psc->psc_intrs, psc->psc_nintrs); 220 psc->psc_nintrs = 0; 221 unmap: 222 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 223 sc->sc_ios = 0; 224 } 225 226 static int 227 nvme_pci_detach(device_t self, int flags) 228 { 229 struct nvme_pci_softc *psc = device_private(self); 230 struct nvme_softc *sc = &psc->psc_nvme; 231 int error; 232 233 if (!ISSET(sc->sc_flags, NVME_F_ATTACHED)) 234 return 0; 235 236 error = nvme_detach(sc, flags); 237 if (error) 238 return error; 239 240 kmem_free(sc->sc_ih, sizeof(*sc->sc_ih) * psc->psc_nintrs); 241 pci_intr_release(psc->psc_pc, psc->psc_intrs, psc->psc_nintrs); 242 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 243 return 0; 244 } 245 246 static int 247 nvme_pci_intr_establish(struct nvme_softc *sc, uint16_t qid, 248 struct nvme_queue *q) 249 { 250 struct nvme_pci_softc *psc = (struct nvme_pci_softc *)sc; 251 char intr_xname[INTRDEVNAMEBUF]; 252 char intrbuf[PCI_INTRSTR_LEN]; 253 const char *intrstr = NULL; 254 int (*ih_func)(void *); 255 void *ih_arg; 256 #ifdef __HAVE_PCI_MSI_MSIX 257 int error; 258 #endif 259 260 KASSERT(sc->sc_use_mq || qid == NVME_ADMIN_Q); 261 KASSERT(sc->sc_ih[qid] == NULL); 262 263 if (nvme_pci_mpsafe) { 264 pci_intr_setattr(psc->psc_pc, &psc->psc_intrs[qid], 265 PCI_INTR_MPSAFE, true); 266 } 267 268 #ifdef __HAVE_PCI_MSI_MSIX 269 if (!sc->sc_use_mq) { 270 #endif 271 snprintf(intr_xname, sizeof(intr_xname), "%s", 272 device_xname(sc->sc_dev)); 273 ih_arg = sc; 274 ih_func = nvme_intr; 275 #ifdef __HAVE_PCI_MSI_MSIX 276 } 277 else { 278 if (qid == NVME_ADMIN_Q) { 279 snprintf(intr_xname, sizeof(intr_xname), "%s adminq", 280 device_xname(sc->sc_dev)); 281 } else { 282 snprintf(intr_xname, sizeof(intr_xname), "%s ioq%d", 283 device_xname(sc->sc_dev), qid); 284 } 285 ih_arg = q; 286 if (pci_intr_type(psc->psc_pc, psc->psc_intrs[qid]) 287 == PCI_INTR_TYPE_MSIX) 288 ih_func = nvme_mq_msix_intr; 289 else 290 ih_func = nvme_mq_msi_intr; 291 } 292 #endif /* __HAVE_PCI_MSI_MSIX */ 293 sc->sc_ih[qid] = pci_intr_establish_xname(psc->psc_pc, 294 psc->psc_intrs[qid], IPL_BIO, ih_func, ih_arg, intr_xname); 295 if (sc->sc_ih[qid] == NULL) { 296 aprint_error_dev(sc->sc_dev, 297 "unable to establish %s interrupt\n", intr_xname); 298 return 1; 299 } 300 intrstr = pci_intr_string(psc->psc_pc, psc->psc_intrs[qid], intrbuf, 301 sizeof(intrbuf)); 302 if (!sc->sc_use_mq) { 303 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 304 } 305 #ifdef __HAVE_PCI_MSI_MSIX 306 else if (qid == NVME_ADMIN_Q) { 307 aprint_normal_dev(sc->sc_dev, 308 "for admin queue interrupting at %s\n", intrstr); 309 } else if (!nvme_pci_mpsafe) { 310 aprint_normal_dev(sc->sc_dev, 311 "for io queue %d interrupting at %s\n", qid, intrstr); 312 } else { 313 kcpuset_t *affinity; 314 cpuid_t affinity_to; 315 316 kcpuset_create(&affinity, true); 317 affinity_to = (qid - 1) % ncpu; 318 kcpuset_set(affinity, affinity_to); 319 error = interrupt_distribute(sc->sc_ih[qid], affinity, NULL); 320 kcpuset_destroy(affinity); 321 aprint_normal_dev(sc->sc_dev, 322 "for io queue %d interrupting at %s", qid, intrstr); 323 if (error == 0) 324 aprint_normal(" affinity to cpu%lu", affinity_to); 325 aprint_normal("\n"); 326 } 327 #endif 328 return 0; 329 } 330 331 static int 332 nvme_pci_intr_disestablish(struct nvme_softc *sc, uint16_t qid) 333 { 334 struct nvme_pci_softc *psc = (struct nvme_pci_softc *)sc; 335 336 if (!sc->sc_use_mq && qid > 0) 337 return 0; 338 339 KASSERT(sc->sc_ih[qid] != NULL); 340 341 pci_intr_disestablish(psc->psc_pc, sc->sc_ih[qid]); 342 sc->sc_ih[qid] = NULL; 343 344 return 0; 345 } 346 347 static int 348 nvme_pci_setup_intr(struct pci_attach_args *pa, struct nvme_pci_softc *psc) 349 { 350 struct nvme_softc *sc = &psc->psc_nvme; 351 #ifdef __HAVE_PCI_MSI_MSIX 352 int error; 353 int counts[PCI_INTR_TYPE_SIZE], alloced_counts[PCI_INTR_TYPE_SIZE]; 354 pci_intr_handle_t *ihps; 355 int max_type, intr_type; 356 #else 357 pci_intr_handle_t ih; 358 #endif /* __HAVE_PCI_MSI_MSIX */ 359 360 #ifdef __HAVE_PCI_MSI_MSIX 361 if (nvme_pci_force_intx) { 362 max_type = PCI_INTR_TYPE_INTX; 363 goto force_intx; 364 } 365 366 /* MSI-X */ 367 max_type = PCI_INTR_TYPE_MSIX; 368 counts[PCI_INTR_TYPE_MSIX] = min(pci_msix_count(pa->pa_pc, pa->pa_tag), 369 ncpu + 1); 370 if (counts[PCI_INTR_TYPE_MSIX] > 0) { 371 memset(alloced_counts, 0, sizeof(alloced_counts)); 372 alloced_counts[PCI_INTR_TYPE_MSIX] = counts[PCI_INTR_TYPE_MSIX]; 373 if (pci_intr_alloc(pa, &ihps, alloced_counts, 374 PCI_INTR_TYPE_MSIX)) { 375 counts[PCI_INTR_TYPE_MSIX] = 0; 376 } else { 377 counts[PCI_INTR_TYPE_MSIX] = 378 alloced_counts[PCI_INTR_TYPE_MSIX]; 379 pci_intr_release(pa->pa_pc, ihps, 380 alloced_counts[PCI_INTR_TYPE_MSIX]); 381 } 382 } 383 if (counts[PCI_INTR_TYPE_MSIX] < 2) { 384 counts[PCI_INTR_TYPE_MSIX] = 0; 385 max_type = PCI_INTR_TYPE_MSI; 386 } else if (!nvme_pci_mq || !nvme_pci_mpsafe) { 387 counts[PCI_INTR_TYPE_MSIX] = 2; /* adminq + 1 ioq */ 388 } 389 390 retry_msi: 391 /* MSI */ 392 counts[PCI_INTR_TYPE_MSI] = pci_msi_count(pa->pa_pc, pa->pa_tag); 393 if (counts[PCI_INTR_TYPE_MSI] > 0) { 394 while (counts[PCI_INTR_TYPE_MSI] > ncpu + 1) { 395 if (counts[PCI_INTR_TYPE_MSI] / 2 <= ncpu + 1) 396 break; 397 counts[PCI_INTR_TYPE_MSI] /= 2; 398 } 399 memset(alloced_counts, 0, sizeof(alloced_counts)); 400 alloced_counts[PCI_INTR_TYPE_MSI] = counts[PCI_INTR_TYPE_MSI]; 401 if (pci_intr_alloc(pa, &ihps, alloced_counts, 402 PCI_INTR_TYPE_MSI)) { 403 counts[PCI_INTR_TYPE_MSI] = 0; 404 } else { 405 counts[PCI_INTR_TYPE_MSI] = 406 alloced_counts[PCI_INTR_TYPE_MSI]; 407 pci_intr_release(pa->pa_pc, ihps, 408 alloced_counts[PCI_INTR_TYPE_MSI]); 409 } 410 } 411 if (counts[PCI_INTR_TYPE_MSI] < 1) { 412 counts[PCI_INTR_TYPE_MSI] = 0; 413 if (max_type == PCI_INTR_TYPE_MSI) 414 max_type = PCI_INTR_TYPE_INTX; 415 } else if (!nvme_pci_mq || !nvme_pci_mpsafe) { 416 if (counts[PCI_INTR_TYPE_MSI] > 2) 417 counts[PCI_INTR_TYPE_MSI] = 2; /* adminq + 1 ioq */ 418 } 419 420 force_intx: 421 /* INTx */ 422 counts[PCI_INTR_TYPE_INTX] = 1; 423 424 memcpy(alloced_counts, counts, sizeof(counts)); 425 error = pci_intr_alloc(pa, &ihps, alloced_counts, max_type); 426 if (error) { 427 if (max_type != PCI_INTR_TYPE_INTX) { 428 retry: 429 memset(counts, 0, sizeof(counts)); 430 if (max_type == PCI_INTR_TYPE_MSIX) { 431 max_type = PCI_INTR_TYPE_MSI; 432 goto retry_msi; 433 } else { 434 max_type = PCI_INTR_TYPE_INTX; 435 goto force_intx; 436 } 437 } 438 return error; 439 } 440 441 intr_type = pci_intr_type(pa->pa_pc, ihps[0]); 442 if (alloced_counts[intr_type] < counts[intr_type]) { 443 if (intr_type != PCI_INTR_TYPE_INTX) { 444 pci_intr_release(pa->pa_pc, ihps, 445 alloced_counts[intr_type]); 446 max_type = intr_type; 447 goto retry; 448 } 449 return EBUSY; 450 } 451 452 psc->psc_intrs = ihps; 453 psc->psc_nintrs = alloced_counts[intr_type]; 454 if (intr_type == PCI_INTR_TYPE_MSI) { 455 if (alloced_counts[intr_type] > ncpu + 1) 456 alloced_counts[intr_type] = ncpu + 1; 457 } 458 sc->sc_use_mq = alloced_counts[intr_type] > 1; 459 sc->sc_nq = sc->sc_use_mq ? alloced_counts[intr_type] - 1 : 1; 460 461 #else /* !__HAVE_PCI_MSI_MSIX */ 462 if (pci_intr_map(pa, &ih)) { 463 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 464 return EBUSY; 465 } 466 467 psc->psc_intrs = kmem_zalloc(sizeof(ih), KM_SLEEP); 468 psc->psc_intrs[0] = ih; 469 psc->psc_nintrs = 1; 470 sc->sc_use_mq = 0; 471 sc->sc_nq = 1; 472 #endif /* __HAVE_PCI_MSI_MSIX */ 473 474 return 0; 475 } 476 477 MODULE(MODULE_CLASS_DRIVER, nvme, "pci,dk_subr"); 478 479 #ifdef _MODULE 480 #include "ioconf.c" 481 482 extern const struct bdevsw ld_bdevsw; 483 extern const struct cdevsw ld_cdevsw; 484 #endif 485 486 static int 487 nvme_modcmd(modcmd_t cmd, void *opaque) 488 { 489 #ifdef _MODULE 490 devmajor_t cmajor, bmajor; 491 #endif 492 int error = 0; 493 494 switch (cmd) { 495 case MODULE_CMD_INIT: 496 #ifdef _MODULE 497 /* devsw must be done before configuring the actual device, 498 * otherwise ldattach() fails 499 */ 500 bmajor = cmajor = NODEVMAJOR; 501 error = devsw_attach(ld_cd.cd_name, &ld_bdevsw, &bmajor, 502 &ld_cdevsw, &cmajor); 503 if (error) { 504 aprint_error("%s: unable to register devsw\n", 505 ld_cd.cd_name); 506 return error; 507 } 508 509 error = config_init_component(cfdriver_ioconf_nvme_pci, 510 cfattach_ioconf_nvme_pci, cfdata_ioconf_nvme_pci); 511 if (error) 512 return error; 513 514 #endif 515 return error; 516 case MODULE_CMD_FINI: 517 #ifdef _MODULE 518 error = config_fini_component(cfdriver_ioconf_nvme_pci, 519 cfattach_ioconf_nvme_pci, cfdata_ioconf_nvme_pci); 520 if (error) 521 return error; 522 523 devsw_detach(&ld_bdevsw, &ld_cdevsw); 524 #endif 525 return error; 526 default: 527 return ENOTTY; 528 } 529 } 530
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