nvme_pci.c revision 1.29
1 /* $NetBSD: nvme_pci.c,v 1.29 2020/07/29 07:14:45 jdolecek Exp $ */ 2 /* $OpenBSD: nvme_pci.c,v 1.3 2016/04/14 11:18:32 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2014 David Gwynne <dlg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (C) 2016 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 38 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 42 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: nvme_pci.c,v 1.29 2020/07/29 07:14:45 jdolecek Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/device.h> 52 #include <sys/bitops.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/interrupt.h> 56 #include <sys/kmem.h> 57 #include <sys/pmf.h> 58 #include <sys/module.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/ic/nvmereg.h> 65 #include <dev/ic/nvmevar.h> 66 67 int nvme_pci_force_intx = 0; 68 int nvme_pci_mpsafe = 1; 69 int nvme_pci_mq = 1; /* INTx: ioq=1, MSI/MSI-X: ioq=ncpu */ 70 71 #define NVME_PCI_BAR 0x10 72 73 struct nvme_pci_softc { 74 struct nvme_softc psc_nvme; 75 76 pci_chipset_tag_t psc_pc; 77 pci_intr_handle_t *psc_intrs; 78 int psc_nintrs; 79 }; 80 81 static int nvme_pci_match(device_t, cfdata_t, void *); 82 static void nvme_pci_attach(device_t, device_t, void *); 83 static int nvme_pci_detach(device_t, int); 84 static int nvme_pci_rescan(device_t, const char *, const int *); 85 86 CFATTACH_DECL3_NEW(nvme_pci, sizeof(struct nvme_pci_softc), 87 nvme_pci_match, nvme_pci_attach, nvme_pci_detach, NULL, nvme_pci_rescan, 88 nvme_childdet, DVF_DETACH_SHUTDOWN); 89 90 static int nvme_pci_intr_establish(struct nvme_softc *, 91 uint16_t, struct nvme_queue *); 92 static int nvme_pci_intr_disestablish(struct nvme_softc *, uint16_t); 93 static int nvme_pci_setup_intr(struct pci_attach_args *, 94 struct nvme_pci_softc *); 95 96 static const struct nvme_pci_quirk { 97 pci_vendor_id_t vendor; 98 pci_product_id_t product; 99 uint32_t quirks; 100 } nvme_pci_quirks[] = { 101 { PCI_VENDOR_HGST, PCI_PRODUCT_HGST_SN100, 102 NVME_QUIRK_DELAY_B4_CHK_RDY }, 103 { PCI_VENDOR_HGST, PCI_PRODUCT_HGST_SN200, 104 NVME_QUIRK_DELAY_B4_CHK_RDY }, 105 { PCI_VENDOR_BEIJING_MEMBLAZE, PCI_PRODUCT_BEIJING_MEMBLAZE_PBLAZE4, 106 NVME_QUIRK_DELAY_B4_CHK_RDY }, 107 { PCI_VENDOR_SAMSUNGELEC3, PCI_PRODUCT_SAMSUNGELEC3_172X, 108 NVME_QUIRK_DELAY_B4_CHK_RDY }, 109 { PCI_VENDOR_SAMSUNGELEC3, PCI_PRODUCT_SAMSUNGELEC3_172XAB, 110 NVME_QUIRK_DELAY_B4_CHK_RDY }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DC_P4500_SSD, 112 NVME_QUIRK_NOMSI }, 113 }; 114 115 static const struct nvme_pci_quirk * 116 nvme_pci_lookup_quirk(struct pci_attach_args *pa) 117 { 118 const struct nvme_pci_quirk *q; 119 int i; 120 121 for (i = 0; i < __arraycount(nvme_pci_quirks); i++) { 122 q = &nvme_pci_quirks[i]; 123 124 if (PCI_VENDOR(pa->pa_id) == q->vendor && 125 PCI_PRODUCT(pa->pa_id) == q->product) 126 return q; 127 } 128 return NULL; 129 } 130 131 static int 132 nvme_pci_match(device_t parent, cfdata_t match, void *aux) 133 { 134 struct pci_attach_args *pa = aux; 135 136 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 137 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_NVM && 138 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_NVM_NVME) 139 return 1; 140 141 return 0; 142 } 143 144 static void 145 nvme_pci_attach(device_t parent, device_t self, void *aux) 146 { 147 struct nvme_pci_softc *psc = device_private(self); 148 struct nvme_softc *sc = &psc->psc_nvme; 149 struct pci_attach_args *pa = aux; 150 const struct nvme_pci_quirk *quirk; 151 pcireg_t memtype, reg; 152 bus_addr_t memaddr; 153 int flags, error; 154 int msixoff; 155 156 sc->sc_dev = self; 157 psc->psc_pc = pa->pa_pc; 158 if (pci_dma64_available(pa)) 159 sc->sc_dmat = pa->pa_dmat64; 160 else 161 sc->sc_dmat = pa->pa_dmat; 162 163 quirk = nvme_pci_lookup_quirk(pa); 164 if (quirk != NULL) 165 sc->sc_quirks = quirk->quirks; 166 167 pci_aprint_devinfo(pa, NULL); 168 169 /* Map registers */ 170 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NVME_PCI_BAR); 171 if (PCI_MAPREG_TYPE(memtype) != PCI_MAPREG_TYPE_MEM) { 172 aprint_error_dev(self, "invalid type (type=0x%x)\n", memtype); 173 return; 174 } 175 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 176 if (((reg & PCI_COMMAND_MASTER_ENABLE) == 0) || 177 ((reg & PCI_COMMAND_MEM_ENABLE) == 0)) { 178 /* 179 * Enable address decoding for memory range in case BIOS or 180 * UEFI didn't set it. 181 */ 182 reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 183 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 184 reg); 185 } 186 187 sc->sc_iot = pa->pa_memt; 188 error = pci_mapreg_info(pa->pa_pc, pa->pa_tag, NVME_PCI_BAR, 189 memtype, &memaddr, &sc->sc_ios, &flags); 190 if (error) { 191 aprint_error_dev(self, "can't get map info\n"); 192 return; 193 } 194 195 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &msixoff, 196 NULL)) { 197 pcireg_t msixtbl; 198 uint32_t table_offset; 199 int bir; 200 201 msixtbl = pci_conf_read(pa->pa_pc, pa->pa_tag, 202 msixoff + PCI_MSIX_TBLOFFSET); 203 table_offset = msixtbl & PCI_MSIX_TBLOFFSET_MASK; 204 bir = msixtbl & PCI_MSIX_TBLBIR_MASK; 205 if (bir == PCI_MAPREG_NUM(NVME_PCI_BAR)) { 206 sc->sc_ios = table_offset; 207 } 208 } 209 210 error = bus_space_map(sc->sc_iot, memaddr, sc->sc_ios, flags, 211 &sc->sc_ioh); 212 if (error != 0) { 213 aprint_error_dev(self, "can't map mem space (error=%d)\n", 214 error); 215 return; 216 } 217 218 /* Establish interrupts */ 219 if (nvme_pci_setup_intr(pa, psc) != 0) { 220 aprint_error_dev(self, "unable to allocate interrupt\n"); 221 goto unmap; 222 } 223 sc->sc_intr_establish = nvme_pci_intr_establish; 224 sc->sc_intr_disestablish = nvme_pci_intr_disestablish; 225 226 sc->sc_ih = kmem_zalloc(sizeof(*sc->sc_ih) * psc->psc_nintrs, KM_SLEEP); 227 sc->sc_softih = kmem_zalloc( 228 sizeof(*sc->sc_softih) * psc->psc_nintrs, KM_SLEEP); 229 230 if (nvme_attach(sc) != 0) { 231 /* error printed by nvme_attach() */ 232 goto softintr_free; 233 } 234 235 if (!pmf_device_register(self, NULL, NULL)) 236 aprint_error_dev(self, "couldn't establish power handler\n"); 237 238 SET(sc->sc_flags, NVME_F_ATTACHED); 239 return; 240 241 softintr_free: 242 kmem_free(sc->sc_softih, sizeof(*sc->sc_softih) * psc->psc_nintrs); 243 kmem_free(sc->sc_ih, sizeof(*sc->sc_ih) * psc->psc_nintrs); 244 sc->sc_nq = 0; 245 pci_intr_release(pa->pa_pc, psc->psc_intrs, psc->psc_nintrs); 246 psc->psc_nintrs = 0; 247 unmap: 248 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 249 sc->sc_ios = 0; 250 } 251 252 static int 253 nvme_pci_rescan(device_t self, const char *attr, const int *flags) 254 { 255 256 return nvme_rescan(self, attr, flags); 257 } 258 259 static int 260 nvme_pci_detach(device_t self, int flags) 261 { 262 struct nvme_pci_softc *psc = device_private(self); 263 struct nvme_softc *sc = &psc->psc_nvme; 264 int error; 265 266 if (!ISSET(sc->sc_flags, NVME_F_ATTACHED)) 267 return 0; 268 269 error = nvme_detach(sc, flags); 270 if (error) 271 return error; 272 273 kmem_free(sc->sc_softih, sizeof(*sc->sc_softih) * psc->psc_nintrs); 274 sc->sc_softih = NULL; 275 276 kmem_free(sc->sc_ih, sizeof(*sc->sc_ih) * psc->psc_nintrs); 277 pci_intr_release(psc->psc_pc, psc->psc_intrs, psc->psc_nintrs); 278 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 279 return 0; 280 } 281 282 static int 283 nvme_pci_intr_establish(struct nvme_softc *sc, uint16_t qid, 284 struct nvme_queue *q) 285 { 286 struct nvme_pci_softc *psc = (struct nvme_pci_softc *)sc; 287 char intr_xname[INTRDEVNAMEBUF]; 288 char intrbuf[PCI_INTRSTR_LEN]; 289 const char *intrstr = NULL; 290 int (*ih_func)(void *); 291 void (*ih_func_soft)(void *); 292 void *ih_arg; 293 int error; 294 295 KASSERT(sc->sc_use_mq || qid == NVME_ADMIN_Q); 296 KASSERT(sc->sc_ih[qid] == NULL); 297 298 if (nvme_pci_mpsafe) { 299 pci_intr_setattr(psc->psc_pc, &psc->psc_intrs[qid], 300 PCI_INTR_MPSAFE, true); 301 } 302 303 if (!sc->sc_use_mq) { 304 snprintf(intr_xname, sizeof(intr_xname), "%s", 305 device_xname(sc->sc_dev)); 306 ih_arg = sc; 307 ih_func = nvme_intr; 308 ih_func_soft = nvme_softintr_intx; 309 } else { 310 if (qid == NVME_ADMIN_Q) { 311 snprintf(intr_xname, sizeof(intr_xname), "%s adminq", 312 device_xname(sc->sc_dev)); 313 } else { 314 snprintf(intr_xname, sizeof(intr_xname), "%s ioq%d", 315 device_xname(sc->sc_dev), qid); 316 } 317 ih_arg = q; 318 ih_func = nvme_intr_msi; 319 ih_func_soft = nvme_softintr_msi; 320 } 321 322 /* establish hardware interrupt */ 323 sc->sc_ih[qid] = pci_intr_establish_xname(psc->psc_pc, 324 psc->psc_intrs[qid], IPL_BIO, ih_func, ih_arg, intr_xname); 325 if (sc->sc_ih[qid] == NULL) { 326 aprint_error_dev(sc->sc_dev, 327 "unable to establish %s interrupt\n", intr_xname); 328 return 1; 329 } 330 331 /* establish also the software interrupt */ 332 sc->sc_softih[qid] = softint_establish( 333 SOFTINT_BIO|(nvme_pci_mpsafe ? SOFTINT_MPSAFE : 0), 334 ih_func_soft, q); 335 if (sc->sc_softih[qid] == NULL) { 336 pci_intr_disestablish(psc->psc_pc, sc->sc_ih[qid]); 337 sc->sc_ih[qid] = NULL; 338 339 aprint_error_dev(sc->sc_dev, 340 "unable to establish %s soft interrupt\n", 341 intr_xname); 342 return 1; 343 } 344 345 intrstr = pci_intr_string(psc->psc_pc, psc->psc_intrs[qid], intrbuf, 346 sizeof(intrbuf)); 347 if (!sc->sc_use_mq) { 348 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 349 } else if (qid == NVME_ADMIN_Q) { 350 aprint_normal_dev(sc->sc_dev, 351 "for admin queue interrupting at %s\n", intrstr); 352 } else if (!nvme_pci_mpsafe) { 353 aprint_normal_dev(sc->sc_dev, 354 "for io queue %d interrupting at %s\n", qid, intrstr); 355 } else { 356 kcpuset_t *affinity; 357 cpuid_t affinity_to; 358 359 kcpuset_create(&affinity, true); 360 affinity_to = (qid - 1) % ncpu; 361 kcpuset_set(affinity, affinity_to); 362 error = interrupt_distribute(sc->sc_ih[qid], affinity, NULL); 363 kcpuset_destroy(affinity); 364 aprint_normal_dev(sc->sc_dev, 365 "for io queue %d interrupting at %s", qid, intrstr); 366 if (error == 0) 367 aprint_normal(" affinity to cpu%lu", affinity_to); 368 aprint_normal("\n"); 369 } 370 return 0; 371 } 372 373 static int 374 nvme_pci_intr_disestablish(struct nvme_softc *sc, uint16_t qid) 375 { 376 struct nvme_pci_softc *psc = (struct nvme_pci_softc *)sc; 377 378 KASSERT(sc->sc_use_mq || qid == NVME_ADMIN_Q); 379 KASSERT(sc->sc_ih[qid] != NULL); 380 381 if (sc->sc_softih) { 382 softint_disestablish(sc->sc_softih[qid]); 383 sc->sc_softih[qid] = NULL; 384 } 385 386 pci_intr_disestablish(psc->psc_pc, sc->sc_ih[qid]); 387 sc->sc_ih[qid] = NULL; 388 389 return 0; 390 } 391 392 static int 393 nvme_pci_setup_intr(struct pci_attach_args *pa, struct nvme_pci_softc *psc) 394 { 395 struct nvme_softc *sc = &psc->psc_nvme; 396 int error; 397 int counts[PCI_INTR_TYPE_SIZE]; 398 pci_intr_handle_t *ihps; 399 int intr_type; 400 401 memset(counts, 0, sizeof(counts)); 402 403 if (nvme_pci_force_intx) 404 goto setup_intx; 405 406 /* MSI-X */ 407 counts[PCI_INTR_TYPE_MSIX] = uimin(pci_msix_count(pa->pa_pc, pa->pa_tag), 408 ncpu + 1); 409 if (counts[PCI_INTR_TYPE_MSIX] < 1) { 410 counts[PCI_INTR_TYPE_MSIX] = 0; 411 } else if (!nvme_pci_mq || !nvme_pci_mpsafe) { 412 if (counts[PCI_INTR_TYPE_MSIX] > 2) 413 counts[PCI_INTR_TYPE_MSIX] = 2; /* adminq + 1 ioq */ 414 } 415 416 /* MSI */ 417 if (sc->sc_quirks & NVME_QUIRK_NOMSI) 418 goto setup_intx; 419 counts[PCI_INTR_TYPE_MSI] = pci_msi_count(pa->pa_pc, pa->pa_tag); 420 if (counts[PCI_INTR_TYPE_MSI] > 0) { 421 while (counts[PCI_INTR_TYPE_MSI] > ncpu + 1) { 422 if (counts[PCI_INTR_TYPE_MSI] / 2 <= ncpu + 1) 423 break; 424 counts[PCI_INTR_TYPE_MSI] /= 2; 425 } 426 } 427 if (counts[PCI_INTR_TYPE_MSI] < 1) { 428 counts[PCI_INTR_TYPE_MSI] = 0; 429 } else if (!nvme_pci_mq || !nvme_pci_mpsafe) { 430 if (counts[PCI_INTR_TYPE_MSI] > 2) 431 counts[PCI_INTR_TYPE_MSI] = 2; /* adminq + 1 ioq */ 432 } 433 434 setup_intx: 435 /* INTx */ 436 counts[PCI_INTR_TYPE_INTX] = 1; 437 438 error = pci_intr_alloc(pa, &ihps, counts, PCI_INTR_TYPE_MSIX); 439 if (error) 440 return error; 441 442 intr_type = pci_intr_type(pa->pa_pc, ihps[0]); 443 444 psc->psc_intrs = ihps; 445 psc->psc_nintrs = counts[intr_type]; 446 if (intr_type == PCI_INTR_TYPE_MSI) { 447 if (counts[intr_type] > ncpu + 1) 448 counts[intr_type] = ncpu + 1; 449 } 450 sc->sc_use_mq = counts[intr_type] > 1; 451 sc->sc_nq = sc->sc_use_mq ? counts[intr_type] - 1 : 1; 452 453 return 0; 454 } 455 456 MODULE(MODULE_CLASS_DRIVER, nvme, "pci,dk_subr"); 457 458 #ifdef _MODULE 459 #include "ioconf.c" 460 #endif 461 462 static int 463 nvme_modcmd(modcmd_t cmd, void *opaque) 464 { 465 #ifdef _MODULE 466 devmajor_t cmajor, bmajor; 467 extern const struct cdevsw nvme_cdevsw; 468 #endif 469 int error = 0; 470 471 #ifdef _MODULE 472 switch (cmd) { 473 case MODULE_CMD_INIT: 474 error = config_init_component(cfdriver_ioconf_nvme_pci, 475 cfattach_ioconf_nvme_pci, cfdata_ioconf_nvme_pci); 476 if (error) 477 break; 478 479 bmajor = cmajor = NODEVMAJOR; 480 error = devsw_attach(nvme_cd.cd_name, NULL, &bmajor, 481 &nvme_cdevsw, &cmajor); 482 if (error) { 483 aprint_error("%s: unable to register devsw\n", 484 nvme_cd.cd_name); 485 /* do not abort, just /dev/nvme* will not work */ 486 } 487 break; 488 case MODULE_CMD_FINI: 489 devsw_detach(NULL, &nvme_cdevsw); 490 491 error = config_fini_component(cfdriver_ioconf_nvme_pci, 492 cfattach_ioconf_nvme_pci, cfdata_ioconf_nvme_pci); 493 break; 494 default: 495 break; 496 } 497 #endif 498 return error; 499 } 500
Indexes created Sun Sep 21 16:09:51 GMT 2025