nvme_pci.c revision 1.7
1 /* $NetBSD: nvme_pci.c,v 1.7 2016/09/16 23:20:31 pgoyette Exp $ */ 2 /* $OpenBSD: nvme_pci.c,v 1.3 2016/04/14 11:18:32 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2014 David Gwynne <dlg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (C) 2016 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 38 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 42 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: nvme_pci.c,v 1.7 2016/09/16 23:20:31 pgoyette Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/device.h> 52 #include <sys/bitops.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/interrupt.h> 56 #include <sys/kmem.h> 57 #include <sys/pmf.h> 58 #include <sys/module.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 63 #include <dev/ic/nvmereg.h> 64 #include <dev/ic/nvmevar.h> 65 66 int nvme_pci_force_intx = 0; 67 int nvme_pci_mpsafe = 0; 68 int nvme_pci_mq = 1; /* INTx: ioq=1, MSI/MSI-X: ioq=ncpu */ 69 70 #define NVME_PCI_BAR 0x10 71 72 struct nvme_pci_softc { 73 struct nvme_softc psc_nvme; 74 75 pci_chipset_tag_t psc_pc; 76 pci_intr_handle_t *psc_intrs; 77 int psc_nintrs; 78 }; 79 80 static int nvme_pci_match(device_t, cfdata_t, void *); 81 static void nvme_pci_attach(device_t, device_t, void *); 82 static int nvme_pci_detach(device_t, int); 83 84 CFATTACH_DECL3_NEW(nvme_pci, sizeof(struct nvme_pci_softc), 85 nvme_pci_match, nvme_pci_attach, nvme_pci_detach, NULL, NULL, 86 nvme_childdet, DVF_DETACH_SHUTDOWN); 87 88 static int nvme_pci_intr_establish(struct nvme_softc *, 89 uint16_t, struct nvme_queue *); 90 static int nvme_pci_intr_disestablish(struct nvme_softc *, uint16_t); 91 static int nvme_pci_setup_intr(struct pci_attach_args *, 92 struct nvme_pci_softc *); 93 94 static int 95 nvme_pci_match(device_t parent, cfdata_t match, void *aux) 96 { 97 struct pci_attach_args *pa = aux; 98 99 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 100 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_NVM && 101 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_NVM_NVME) 102 return 1; 103 104 return 0; 105 } 106 107 static void 108 nvme_pci_attach(device_t parent, device_t self, void *aux) 109 { 110 struct nvme_pci_softc *psc = device_private(self); 111 struct nvme_softc *sc = &psc->psc_nvme; 112 struct pci_attach_args *pa = aux; 113 pcireg_t memtype; 114 bus_addr_t memaddr; 115 int flags, msixoff; 116 int error; 117 118 sc->sc_dev = self; 119 psc->psc_pc = pa->pa_pc; 120 if (pci_dma64_available(pa)) 121 sc->sc_dmat = pa->pa_dmat64; 122 else 123 sc->sc_dmat = pa->pa_dmat; 124 125 pci_aprint_devinfo(pa, NULL); 126 127 /* Map registers */ 128 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NVME_PCI_BAR); 129 if (PCI_MAPREG_TYPE(memtype) != PCI_MAPREG_TYPE_MEM) { 130 aprint_error_dev(self, "invalid type (type=0x%x)\n", memtype); 131 return; 132 } 133 sc->sc_iot = pa->pa_memt; 134 error = pci_mapreg_info(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, 135 memtype, &memaddr, &sc->sc_ios, &flags); 136 if (error) { 137 aprint_error_dev(self, "can't get map info\n"); 138 return; 139 } 140 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &msixoff, 141 NULL)) { 142 pcireg_t msixtbl; 143 uint32_t table_offset; 144 int bir; 145 146 msixtbl = pci_conf_read(pa->pa_pc, pa->pa_tag, 147 msixoff + PCI_MSIX_TBLOFFSET); 148 table_offset = msixtbl & PCI_MSIX_TBLOFFSET_MASK; 149 bir = msixtbl & PCI_MSIX_PBABIR_MASK; 150 if (bir == 0) { 151 sc->sc_ios = table_offset; 152 } 153 } 154 error = bus_space_map(sc->sc_iot, memaddr, sc->sc_ios, flags, 155 &sc->sc_ioh); 156 if (error != 0) { 157 aprint_error_dev(self, "can't map mem space (error=%d)\n", 158 error); 159 return; 160 } 161 162 /* Establish interrupts */ 163 if (nvme_pci_setup_intr(pa, psc) != 0) { 164 aprint_error_dev(self, "unable to allocate interrupt\n"); 165 goto unmap; 166 } 167 sc->sc_intr_establish = nvme_pci_intr_establish; 168 sc->sc_intr_disestablish = nvme_pci_intr_disestablish; 169 170 sc->sc_ih = kmem_zalloc(sizeof(*sc->sc_ih) * psc->psc_nintrs, KM_SLEEP); 171 if (sc->sc_ih == NULL) { 172 aprint_error_dev(self, "unable to allocate ih memory\n"); 173 goto intr_release; 174 } 175 176 if (nvme_attach(sc) != 0) { 177 /* error printed by nvme_attach() */ 178 goto intr_free; 179 } 180 181 if (!pmf_device_register(self, NULL, NULL)) 182 aprint_error_dev(self, "couldn't establish power handler\n"); 183 184 SET(sc->sc_flags, NVME_F_ATTACHED); 185 return; 186 187 intr_free: 188 kmem_free(sc->sc_ih, sizeof(*sc->sc_ih) * psc->psc_nintrs); 189 sc->sc_nq = 0; 190 intr_release: 191 pci_intr_release(pa->pa_pc, psc->psc_intrs, psc->psc_nintrs); 192 psc->psc_nintrs = 0; 193 unmap: 194 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 195 sc->sc_ios = 0; 196 } 197 198 static int 199 nvme_pci_detach(device_t self, int flags) 200 { 201 struct nvme_pci_softc *psc = device_private(self); 202 struct nvme_softc *sc = &psc->psc_nvme; 203 int error; 204 205 if (!ISSET(sc->sc_flags, NVME_F_ATTACHED)) 206 return 0; 207 208 error = nvme_detach(sc, flags); 209 if (error) 210 return error; 211 212 kmem_free(sc->sc_ih, sizeof(*sc->sc_ih) * psc->psc_nintrs); 213 pci_intr_release(psc->psc_pc, psc->psc_intrs, psc->psc_nintrs); 214 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 215 return 0; 216 } 217 218 static int 219 nvme_pci_intr_establish(struct nvme_softc *sc, uint16_t qid, 220 struct nvme_queue *q) 221 { 222 struct nvme_pci_softc *psc = (struct nvme_pci_softc *)sc; 223 char intr_xname[INTRDEVNAMEBUF]; 224 char intrbuf[PCI_INTRSTR_LEN]; 225 const char *intrstr = NULL; 226 int (*ih_func)(void *); 227 void *ih_arg; 228 kcpuset_t *affinity; 229 cpuid_t affinity_to; 230 int error; 231 232 if (!sc->sc_use_mq && qid > 0) 233 return 0; 234 235 KASSERT(sc->sc_ih[qid] == NULL); 236 237 if (nvme_pci_mpsafe) { 238 pci_intr_setattr(psc->psc_pc, &psc->psc_intrs[qid], 239 PCI_INTR_MPSAFE, true); 240 } 241 if (!sc->sc_use_mq) { 242 snprintf(intr_xname, sizeof(intr_xname), "%s", 243 device_xname(sc->sc_dev)); 244 ih_arg = sc; 245 ih_func = nvme_intr; 246 } else { 247 if (qid == 0) { 248 snprintf(intr_xname, sizeof(intr_xname), "%s adminq", 249 device_xname(sc->sc_dev)); 250 } else { 251 snprintf(intr_xname, sizeof(intr_xname), "%s ioq%d", 252 device_xname(sc->sc_dev), qid); 253 } 254 ih_arg = q; 255 if (pci_intr_type(psc->psc_pc, psc->psc_intrs[qid]) 256 == PCI_INTR_TYPE_MSIX) 257 ih_func = nvme_mq_msix_intr; 258 else 259 ih_func = nvme_mq_msi_intr; 260 } 261 sc->sc_ih[qid] = pci_intr_establish_xname(psc->psc_pc, 262 psc->psc_intrs[qid], IPL_BIO, ih_func, ih_arg, intr_xname); 263 if (sc->sc_ih[qid] == NULL) { 264 aprint_error_dev(sc->sc_dev, 265 "unable to establish %s interrupt\n", intr_xname); 266 return 1; 267 } 268 intrstr = pci_intr_string(psc->psc_pc, psc->psc_intrs[qid], intrbuf, 269 sizeof(intrbuf)); 270 if (!sc->sc_use_mq) { 271 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 272 } else if (qid == NVME_ADMIN_Q) { 273 aprint_normal_dev(sc->sc_dev, 274 "for admin queue interrupting at %s\n", intrstr); 275 } else if (!nvme_pci_mpsafe) { 276 aprint_normal_dev(sc->sc_dev, 277 "for io queue %d interrupting at %s\n", qid, intrstr); 278 } else { 279 kcpuset_create(&affinity, true); 280 affinity_to = (qid - 1) % ncpu; 281 kcpuset_set(affinity, affinity_to); 282 error = interrupt_distribute(sc->sc_ih[qid], affinity, NULL); 283 kcpuset_destroy(affinity); 284 aprint_normal_dev(sc->sc_dev, 285 "for io queue %d interrupting at %s", qid, intrstr); 286 if (error == 0) 287 aprint_normal(" affinity to cpu%lu", affinity_to); 288 aprint_normal("\n"); 289 } 290 return 0; 291 } 292 293 static int 294 nvme_pci_intr_disestablish(struct nvme_softc *sc, uint16_t qid) 295 { 296 struct nvme_pci_softc *psc = (struct nvme_pci_softc *)sc; 297 298 if (!sc->sc_use_mq && qid > 0) 299 return 0; 300 301 KASSERT(sc->sc_ih[qid] != NULL); 302 303 pci_intr_disestablish(psc->psc_pc, sc->sc_ih[qid]); 304 sc->sc_ih[qid] = NULL; 305 306 return 0; 307 } 308 309 static int 310 nvme_pci_setup_intr(struct pci_attach_args *pa, struct nvme_pci_softc *psc) 311 { 312 struct nvme_softc *sc = &psc->psc_nvme; 313 pci_intr_handle_t *ihps; 314 int counts[PCI_INTR_TYPE_SIZE], alloced_counts[PCI_INTR_TYPE_SIZE]; 315 int max_type, intr_type; 316 int error; 317 318 if (nvme_pci_force_intx) { 319 max_type = PCI_INTR_TYPE_INTX; 320 goto force_intx; 321 } 322 323 /* MSI-X */ 324 max_type = PCI_INTR_TYPE_MSIX; 325 counts[PCI_INTR_TYPE_MSIX] = min(pci_msix_count(pa->pa_pc, pa->pa_tag), 326 ncpu + 1); 327 if (counts[PCI_INTR_TYPE_MSIX] > 0) { 328 memset(alloced_counts, 0, sizeof(alloced_counts)); 329 alloced_counts[PCI_INTR_TYPE_MSIX] = counts[PCI_INTR_TYPE_MSIX]; 330 if (pci_intr_alloc(pa, &ihps, alloced_counts, 331 PCI_INTR_TYPE_MSIX)) { 332 counts[PCI_INTR_TYPE_MSIX] = 0; 333 } else { 334 counts[PCI_INTR_TYPE_MSIX] = 335 alloced_counts[PCI_INTR_TYPE_MSIX]; 336 pci_intr_release(pa->pa_pc, ihps, 337 alloced_counts[PCI_INTR_TYPE_MSIX]); 338 } 339 } 340 if (counts[PCI_INTR_TYPE_MSIX] < 2) { 341 counts[PCI_INTR_TYPE_MSIX] = 0; 342 max_type = PCI_INTR_TYPE_MSI; 343 } else if (!nvme_pci_mq || !nvme_pci_mpsafe) { 344 counts[PCI_INTR_TYPE_MSIX] = 2; /* adminq + 1 ioq */ 345 } 346 347 retry_msi: 348 /* MSI */ 349 counts[PCI_INTR_TYPE_MSI] = pci_msi_count(pa->pa_pc, pa->pa_tag); 350 if (counts[PCI_INTR_TYPE_MSI] > 0) { 351 while (counts[PCI_INTR_TYPE_MSI] > ncpu + 1) { 352 if (counts[PCI_INTR_TYPE_MSI] / 2 <= ncpu + 1) 353 break; 354 counts[PCI_INTR_TYPE_MSI] /= 2; 355 } 356 memset(alloced_counts, 0, sizeof(alloced_counts)); 357 alloced_counts[PCI_INTR_TYPE_MSI] = counts[PCI_INTR_TYPE_MSI]; 358 if (pci_intr_alloc(pa, &ihps, alloced_counts, 359 PCI_INTR_TYPE_MSI)) { 360 counts[PCI_INTR_TYPE_MSI] = 0; 361 } else { 362 counts[PCI_INTR_TYPE_MSI] = 363 alloced_counts[PCI_INTR_TYPE_MSI]; 364 pci_intr_release(pa->pa_pc, ihps, 365 alloced_counts[PCI_INTR_TYPE_MSI]); 366 } 367 } 368 if (counts[PCI_INTR_TYPE_MSI] < 1) { 369 counts[PCI_INTR_TYPE_MSI] = 0; 370 if (max_type == PCI_INTR_TYPE_MSI) 371 max_type = PCI_INTR_TYPE_INTX; 372 } else if (!nvme_pci_mq || !nvme_pci_mpsafe) { 373 if (counts[PCI_INTR_TYPE_MSI] > 2) 374 counts[PCI_INTR_TYPE_MSI] = 2; /* adminq + 1 ioq */ 375 } 376 377 force_intx: 378 /* INTx */ 379 counts[PCI_INTR_TYPE_INTX] = 1; 380 381 memcpy(alloced_counts, counts, sizeof(counts)); 382 error = pci_intr_alloc(pa, &ihps, alloced_counts, max_type); 383 if (error) { 384 if (max_type != PCI_INTR_TYPE_INTX) { 385 retry: 386 memset(counts, 0, sizeof(counts)); 387 if (max_type == PCI_INTR_TYPE_MSIX) { 388 max_type = PCI_INTR_TYPE_MSI; 389 goto retry_msi; 390 } else { 391 max_type = PCI_INTR_TYPE_INTX; 392 goto force_intx; 393 } 394 } 395 return error; 396 } 397 398 intr_type = pci_intr_type(pa->pa_pc, ihps[0]); 399 if (alloced_counts[intr_type] < counts[intr_type]) { 400 if (intr_type != PCI_INTR_TYPE_INTX) { 401 pci_intr_release(pa->pa_pc, ihps, 402 alloced_counts[intr_type]); 403 max_type = intr_type; 404 goto retry; 405 } 406 return EBUSY; 407 } 408 409 psc->psc_intrs = ihps; 410 psc->psc_nintrs = alloced_counts[intr_type]; 411 if (intr_type == PCI_INTR_TYPE_MSI) { 412 if (alloced_counts[intr_type] > ncpu + 1) 413 alloced_counts[intr_type] = ncpu + 1; 414 } 415 sc->sc_use_mq = alloced_counts[intr_type] > 1; 416 sc->sc_nq = sc->sc_use_mq ? alloced_counts[intr_type] - 1 : 1; 417 return 0; 418 } 419 420 MODULE(MODULE_CLASS_DRIVER, nvme, "pci"); 421 422 #ifdef _MODULE 423 #include "ioconf.c" 424 425 extern const struct bdevsw ld_bdevsw; 426 extern const struct cdevsw ld_cdevsw; 427 #endif 428 429 static int 430 nvme_modcmd(modcmd_t cmd, void *opaque) 431 { 432 #ifdef _MODULE 433 devmajor_t cmajor, bmajor; 434 #endif 435 int error = 0; 436 437 switch (cmd) { 438 case MODULE_CMD_INIT: 439 #ifdef _MODULE 440 /* devsw must be done before configuring the pci device, 441 * otherwise ldattach() fails 442 */ 443 bmajor = cmajor = NODEVMAJOR; 444 error = devsw_attach(ld_cd.cd_name, &ld_bdevsw, &bmajor, 445 &ld_cdevsw, &cmajor); 446 if (error && error != EEXIST) { 447 aprint_error("%s: unable to register devsw\n", 448 ld_cd.cd_name); 449 return error; 450 } 451 452 error = config_init_component(cfdriver_ioconf_nvme_pci, 453 cfattach_ioconf_nvme_pci, cfdata_ioconf_nvme_pci); 454 if (error) 455 return error; 456 457 #endif 458 return error; 459 case MODULE_CMD_FINI: 460 #ifdef _MODULE 461 error = config_fini_component(cfdriver_ioconf_nvme_pci, 462 cfattach_ioconf_nvme_pci, cfdata_ioconf_nvme_pci); 463 if (error) 464 return error; 465 466 /* devsw not detached, it's static data and fine to stay */ 467 #endif 468 return error; 469 default: 470 return ENOTTY; 471 } 472 } 473
Indexes created Fri Oct 03 02:09:57 GMT 2025