ohci_pci.c revision 1.47
1/* $NetBSD: ohci_pci.c,v 1.47 2011/04/04 22:48:15 dyoung Exp $ */ 2 3/* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart@augustsson.net) at 9 * Carlstedt Research & Technology. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__KERNEL_RCSID(0, "$NetBSD: ohci_pci.c,v 1.47 2011/04/04 22:48:15 dyoung Exp $"); 35 36#include "ehci.h" 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/kernel.h> 41#include <sys/device.h> 42#include <sys/proc.h> 43#include <sys/queue.h> 44 45#include <sys/bus.h> 46 47#include <dev/pci/pcivar.h> 48#include <dev/pci/usb_pci.h> 49 50#include <dev/usb/usb.h> 51#include <dev/usb/usbdi.h> 52#include <dev/usb/usbdivar.h> 53#include <dev/usb/usb_mem.h> 54 55#include <dev/usb/ohcireg.h> 56#include <dev/usb/ohcivar.h> 57 58struct ohci_pci_softc { 59 ohci_softc_t sc; 60#if NEHCI > 0 61 struct usb_pci sc_pci; 62#endif 63 pci_chipset_tag_t sc_pc; 64 pcitag_t sc_tag; 65 void *sc_ih; /* interrupt vectoring */ 66}; 67 68static int 69ohci_pci_match(device_t parent, cfdata_t match, void *aux) 70{ 71 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 72 73 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 74 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 75 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_OHCI) 76 return 1; 77 78 return 0; 79} 80 81static void 82ohci_pci_attach(device_t parent, device_t self, void *aux) 83{ 84 struct ohci_pci_softc *sc = device_private(self); 85 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 86 pci_chipset_tag_t pc = pa->pa_pc; 87 pcitag_t tag = pa->pa_tag; 88 char const *intrstr; 89 pci_intr_handle_t ih; 90 pcireg_t csr; 91 char devinfo[256]; 92 usbd_status r; 93 const char *vendor; 94 95 sc->sc.sc_dev = self; 96 sc->sc.sc_bus.hci_private = sc; 97 98 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 99 aprint_normal(": %s (rev. 0x%02x)\n", 100 devinfo, PCI_REVISION(pa->pa_class)); 101 aprint_naive(": USB Controller\n"); 102 103 /* Map I/O registers */ 104 if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, 105 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 106 sc->sc.sc_size = 0; 107 aprint_error_dev(self, "can't map mem space\n"); 108 return; 109 } 110 111 /* Disable interrupts, so we don't get any spurious ones. */ 112 bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE, 113 OHCI_ALL_INTRS); 114 115 sc->sc_pc = pc; 116 sc->sc_tag = tag; 117 sc->sc.sc_bus.dmatag = pa->pa_dmat; 118 119 /* Enable the device. */ 120 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 121 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 122 csr | PCI_COMMAND_MASTER_ENABLE); 123 124 /* Map and establish the interrupt. */ 125 if (pci_intr_map(pa, &ih)) { 126 aprint_error_dev(self, "couldn't map interrupt\n"); 127 goto fail; 128 } 129 130 /* 131 * Allocate IRQ 132 */ 133 intrstr = pci_intr_string(pc, ih); 134 sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, ohci_intr, sc); 135 if (sc->sc_ih == NULL) { 136 aprint_error_dev(self, "couldn't establish interrupt"); 137 if (intrstr != NULL) 138 aprint_error(" at %s", intrstr); 139 aprint_error("\n"); 140 goto fail; 141 } 142 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 143 144 /* Figure out vendor for root hub descriptor. */ 145 vendor = pci_findvendor(pa->pa_id); 146 sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id); 147 if (vendor) 148 strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor)); 149 else 150 snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), 151 "vendor 0x%04x", PCI_VENDOR(pa->pa_id)); 152 153 r = ohci_init(&sc->sc); 154 if (r != USBD_NORMAL_COMPLETION) { 155 aprint_error_dev(self, "init failed, error=%d\n", r); 156 goto fail; 157 } 158 159#if NEHCI > 0 160 usb_pci_add(&sc->sc_pci, pa, self); 161#endif 162 163 if (!pmf_device_register1(self, ohci_suspend, ohci_resume, 164 ohci_shutdown)) 165 aprint_error_dev(self, "couldn't establish power handler\n"); 166 167 /* Attach usb device. */ 168 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 169 return; 170 171fail: 172 if (sc->sc_ih) { 173 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 174 sc->sc_ih = NULL; 175 } 176 if (sc->sc.sc_size) { 177 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 178 sc->sc.sc_size = 0; 179 } 180 return; 181} 182 183static int 184ohci_pci_detach(device_t self, int flags) 185{ 186 struct ohci_pci_softc *sc = device_private(self); 187 int rv; 188 189 rv = ohci_detach(&sc->sc, flags); 190 if (rv) 191 return rv; 192 193 pmf_device_deregister(self); 194 195 ohci_shutdown(self, flags); 196 197 if (sc->sc.sc_size) { 198 /* Disable interrupts, so we don't get any spurious ones. */ 199 bus_space_write_4(sc->sc.iot, sc->sc.ioh, 200 OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 201 } 202 203 if (sc->sc_ih != NULL) { 204 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 205 sc->sc_ih = NULL; 206 } 207 if (sc->sc.sc_size) { 208 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 209 sc->sc.sc_size = 0; 210 } 211#if NEHCI > 0 212 usb_pci_rem(&sc->sc_pci); 213#endif 214 return 0; 215} 216 217CFATTACH_DECL3_NEW(ohci_pci, sizeof(struct ohci_pci_softc), 218 ohci_pci_match, ohci_pci_attach, ohci_pci_detach, ohci_activate, NULL, 219 ohci_childdet, DVF_DETACH_SHUTDOWN); 220