optiide.c revision 1.1 1 1.1 bouyer /* $NetBSD: optiide.c,v 1.1 2003/10/08 11:51:59 bouyer Exp $ */
2 1.1 bouyer
3 1.1 bouyer /*-
4 1.1 bouyer * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 1.1 bouyer * All rights reserved.
6 1.1 bouyer *
7 1.1 bouyer * This code is derived from software contributed to The NetBSD Foundation
8 1.1 bouyer * by Steve C. Woodford.
9 1.1 bouyer *
10 1.1 bouyer * Redistribution and use in source and binary forms, with or without
11 1.1 bouyer * modification, are permitted provided that the following conditions
12 1.1 bouyer * are met:
13 1.1 bouyer * 1. Redistributions of source code must retain the above copyright
14 1.1 bouyer * notice, this list of conditions and the following disclaimer.
15 1.1 bouyer * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 bouyer * notice, this list of conditions and the following disclaimer in the
17 1.1 bouyer * documentation and/or other materials provided with the distribution.
18 1.1 bouyer * 3. All advertising materials mentioning features or use of this software
19 1.1 bouyer * must display the following acknowledgement:
20 1.1 bouyer * This product includes software developed by the NetBSD
21 1.1 bouyer * Foundation, Inc. and its contributors.
22 1.1 bouyer * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 bouyer * contributors may be used to endorse or promote products derived
24 1.1 bouyer * from this software without specific prior written permission.
25 1.1 bouyer *
26 1.1 bouyer * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 bouyer * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 bouyer * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 bouyer * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 bouyer * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 bouyer * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 bouyer * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 bouyer * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 bouyer * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 bouyer * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 bouyer * POSSIBILITY OF SUCH DAMAGE.
37 1.1 bouyer */
38 1.1 bouyer
39 1.1 bouyer #include <sys/param.h>
40 1.1 bouyer #include <sys/systm.h>
41 1.1 bouyer
42 1.1 bouyer #include <dev/pci/pcivar.h>
43 1.1 bouyer #include <dev/pci/pcidevs.h>
44 1.1 bouyer #include <dev/pci/pciidereg.h>
45 1.1 bouyer #include <dev/pci/pciidevar.h>
46 1.1 bouyer #include <dev/pci/pciide_opti_reg.h>
47 1.1 bouyer
48 1.1 bouyer void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
49 1.1 bouyer void opti_setup_channel __P((struct channel_softc*));
50 1.1 bouyer
51 1.1 bouyer int optiide_match __P((struct device *, struct cfdata *, void *));
52 1.1 bouyer void optiide_attach __P((struct device *, struct device *, void *));
53 1.1 bouyer
54 1.1 bouyer CFATTACH_DECL(optiide, sizeof(struct pciide_softc),
55 1.1 bouyer optiide_match, optiide_attach, NULL, NULL);
56 1.1 bouyer
57 1.1 bouyer const struct pciide_product_desc pciide_opti_products[] = {
58 1.1 bouyer { PCI_PRODUCT_OPTI_82C621,
59 1.1 bouyer 0,
60 1.1 bouyer "OPTi 82c621 PCI IDE controller",
61 1.1 bouyer opti_chip_map,
62 1.1 bouyer },
63 1.1 bouyer { PCI_PRODUCT_OPTI_82C568,
64 1.1 bouyer 0,
65 1.1 bouyer "OPTi 82c568 (82c621 compatible) PCI IDE controller",
66 1.1 bouyer opti_chip_map,
67 1.1 bouyer },
68 1.1 bouyer { PCI_PRODUCT_OPTI_82D568,
69 1.1 bouyer 0,
70 1.1 bouyer "OPTi 82d568 (82c621 compatible) PCI IDE controller",
71 1.1 bouyer opti_chip_map,
72 1.1 bouyer },
73 1.1 bouyer { 0,
74 1.1 bouyer 0,
75 1.1 bouyer NULL,
76 1.1 bouyer NULL
77 1.1 bouyer }
78 1.1 bouyer };
79 1.1 bouyer
80 1.1 bouyer int
81 1.1 bouyer optiide_match(parent, match, aux)
82 1.1 bouyer struct device *parent;
83 1.1 bouyer struct cfdata *match;
84 1.1 bouyer void *aux;
85 1.1 bouyer {
86 1.1 bouyer struct pci_attach_args *pa = aux;
87 1.1 bouyer
88 1.1 bouyer if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_OPTI) {
89 1.1 bouyer if (pciide_lookup_product(pa->pa_id, pciide_opti_products))
90 1.1 bouyer return (2);
91 1.1 bouyer }
92 1.1 bouyer return (0);
93 1.1 bouyer }
94 1.1 bouyer
95 1.1 bouyer void
96 1.1 bouyer optiide_attach(parent, self, aux)
97 1.1 bouyer struct device *parent, *self;
98 1.1 bouyer void *aux;
99 1.1 bouyer {
100 1.1 bouyer struct pci_attach_args *pa = aux;
101 1.1 bouyer struct pciide_softc *sc = (struct pciide_softc *)self;
102 1.1 bouyer
103 1.1 bouyer pciide_common_attach(sc, pa,
104 1.1 bouyer pciide_lookup_product(pa->pa_id, pciide_opti_products));
105 1.1 bouyer
106 1.1 bouyer }
107 1.1 bouyer
108 1.1 bouyer void
109 1.1 bouyer opti_chip_map(sc, pa)
110 1.1 bouyer struct pciide_softc *sc;
111 1.1 bouyer struct pci_attach_args *pa;
112 1.1 bouyer {
113 1.1 bouyer struct pciide_channel *cp;
114 1.1 bouyer bus_size_t cmdsize, ctlsize;
115 1.1 bouyer pcireg_t interface;
116 1.1 bouyer u_int8_t init_ctrl;
117 1.1 bouyer int channel;
118 1.1 bouyer
119 1.1 bouyer if (pciide_chipen(sc, pa) == 0)
120 1.1 bouyer return;
121 1.1 bouyer
122 1.1 bouyer aprint_normal("%s: bus-master DMA support present",
123 1.1 bouyer sc->sc_wdcdev.sc_dev.dv_xname);
124 1.1 bouyer
125 1.1 bouyer /*
126 1.1 bouyer * XXXSCW:
127 1.1 bouyer * There seem to be a couple of buggy revisions/implementations
128 1.1 bouyer * of the OPTi pciide chipset. This kludge seems to fix one of
129 1.1 bouyer * the reported problems (PR/11644) but still fails for the
130 1.1 bouyer * other (PR/13151), although the latter may be due to other
131 1.1 bouyer * issues too...
132 1.1 bouyer */
133 1.1 bouyer if (PCI_REVISION(pa->pa_class) <= 0x12) {
134 1.1 bouyer aprint_normal(" but disabled due to chip rev. <= 0x12");
135 1.1 bouyer sc->sc_dma_ok = 0;
136 1.1 bouyer } else
137 1.1 bouyer pciide_mapreg_dma(sc, pa);
138 1.1 bouyer
139 1.1 bouyer aprint_normal("\n");
140 1.1 bouyer
141 1.1 bouyer sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 |
142 1.1 bouyer WDC_CAPABILITY_MODE;
143 1.1 bouyer sc->sc_wdcdev.PIO_cap = 4;
144 1.1 bouyer if (sc->sc_dma_ok) {
145 1.1 bouyer sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
146 1.1 bouyer sc->sc_wdcdev.irqack = pciide_irqack;
147 1.1 bouyer sc->sc_wdcdev.DMA_cap = 2;
148 1.1 bouyer }
149 1.1 bouyer sc->sc_wdcdev.set_modes = opti_setup_channel;
150 1.1 bouyer
151 1.1 bouyer sc->sc_wdcdev.channels = sc->wdc_chanarray;
152 1.1 bouyer sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
153 1.1 bouyer
154 1.1 bouyer init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag,
155 1.1 bouyer OPTI_REG_INIT_CONTROL);
156 1.1 bouyer
157 1.1 bouyer interface = PCI_INTERFACE(pa->pa_class);
158 1.1 bouyer
159 1.1 bouyer for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
160 1.1 bouyer cp = &sc->pciide_channels[channel];
161 1.1 bouyer if (pciide_chansetup(sc, channel, interface) == 0)
162 1.1 bouyer continue;
163 1.1 bouyer if (channel == 1 &&
164 1.1 bouyer (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) {
165 1.1 bouyer aprint_normal("%s: %s channel ignored (disabled)\n",
166 1.1 bouyer sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
167 1.1 bouyer cp->wdc_channel.ch_flags |= WDCF_DISABLED;
168 1.1 bouyer continue;
169 1.1 bouyer }
170 1.1 bouyer pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
171 1.1 bouyer pciide_pci_intr);
172 1.1 bouyer }
173 1.1 bouyer }
174 1.1 bouyer
175 1.1 bouyer void
176 1.1 bouyer opti_setup_channel(chp)
177 1.1 bouyer struct channel_softc *chp;
178 1.1 bouyer {
179 1.1 bouyer struct ata_drive_datas *drvp;
180 1.1 bouyer struct pciide_channel *cp = (struct pciide_channel*)chp;
181 1.1 bouyer struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
182 1.1 bouyer int drive, spd;
183 1.1 bouyer int mode[2];
184 1.1 bouyer u_int8_t rv, mr;
185 1.1 bouyer
186 1.1 bouyer /*
187 1.1 bouyer * The `Delay' and `Address Setup Time' fields of the
188 1.1 bouyer * Miscellaneous Register are always zero initially.
189 1.1 bouyer */
190 1.1 bouyer mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK;
191 1.1 bouyer mr &= ~(OPTI_MISC_DELAY_MASK |
192 1.1 bouyer OPTI_MISC_ADDR_SETUP_MASK |
193 1.1 bouyer OPTI_MISC_INDEX_MASK);
194 1.1 bouyer
195 1.1 bouyer /* Prime the control register before setting timing values */
196 1.1 bouyer opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE);
197 1.1 bouyer
198 1.1 bouyer /* Determine the clockrate of the PCIbus the chip is attached to */
199 1.1 bouyer spd = (int) opti_read_config(chp, OPTI_REG_STRAP);
200 1.1 bouyer spd &= OPTI_STRAP_PCI_SPEED_MASK;
201 1.1 bouyer
202 1.1 bouyer /* setup DMA if needed */
203 1.1 bouyer pciide_channel_dma_setup(cp);
204 1.1 bouyer
205 1.1 bouyer for (drive = 0; drive < 2; drive++) {
206 1.1 bouyer drvp = &chp->ch_drive[drive];
207 1.1 bouyer /* If no drive, skip */
208 1.1 bouyer if ((drvp->drive_flags & DRIVE) == 0) {
209 1.1 bouyer mode[drive] = -1;
210 1.1 bouyer continue;
211 1.1 bouyer }
212 1.1 bouyer
213 1.1 bouyer if ((drvp->drive_flags & DRIVE_DMA)) {
214 1.1 bouyer /*
215 1.1 bouyer * Timings will be used for both PIO and DMA,
216 1.1 bouyer * so adjust DMA mode if needed
217 1.1 bouyer */
218 1.1 bouyer if (drvp->PIO_mode > (drvp->DMA_mode + 2))
219 1.1 bouyer drvp->PIO_mode = drvp->DMA_mode + 2;
220 1.1 bouyer if (drvp->DMA_mode + 2 > (drvp->PIO_mode))
221 1.1 bouyer drvp->DMA_mode = (drvp->PIO_mode > 2) ?
222 1.1 bouyer drvp->PIO_mode - 2 : 0;
223 1.1 bouyer if (drvp->DMA_mode == 0)
224 1.1 bouyer drvp->PIO_mode = 0;
225 1.1 bouyer
226 1.1 bouyer mode[drive] = drvp->DMA_mode + 5;
227 1.1 bouyer } else
228 1.1 bouyer mode[drive] = drvp->PIO_mode;
229 1.1 bouyer
230 1.1 bouyer if (drive && mode[0] >= 0 &&
231 1.1 bouyer (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) {
232 1.1 bouyer /*
233 1.1 bouyer * Can't have two drives using different values
234 1.1 bouyer * for `Address Setup Time'.
235 1.1 bouyer * Slow down the faster drive to compensate.
236 1.1 bouyer */
237 1.1 bouyer int d = (opti_tim_as[spd][mode[0]] >
238 1.1 bouyer opti_tim_as[spd][mode[1]]) ? 0 : 1;
239 1.1 bouyer
240 1.1 bouyer mode[d] = mode[1-d];
241 1.1 bouyer chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode;
242 1.1 bouyer chp->ch_drive[d].DMA_mode = 0;
243 1.1 bouyer chp->ch_drive[d].drive_flags &= ~DRIVE_DMA;
244 1.1 bouyer }
245 1.1 bouyer }
246 1.1 bouyer
247 1.1 bouyer for (drive = 0; drive < 2; drive++) {
248 1.1 bouyer int m;
249 1.1 bouyer if ((m = mode[drive]) < 0)
250 1.1 bouyer continue;
251 1.1 bouyer
252 1.1 bouyer /* Set the Address Setup Time and select appropriate index */
253 1.1 bouyer rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT;
254 1.1 bouyer rv |= OPTI_MISC_INDEX(drive);
255 1.1 bouyer opti_write_config(chp, OPTI_REG_MISC, mr | rv);
256 1.1 bouyer
257 1.1 bouyer /* Set the pulse width and recovery timing parameters */
258 1.1 bouyer rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT;
259 1.1 bouyer rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT;
260 1.1 bouyer opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv);
261 1.1 bouyer opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv);
262 1.1 bouyer
263 1.1 bouyer /* Set the Enhanced Mode register appropriately */
264 1.1 bouyer rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE);
265 1.1 bouyer rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive);
266 1.1 bouyer rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]);
267 1.1 bouyer pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv);
268 1.1 bouyer }
269 1.1 bouyer
270 1.1 bouyer /* Finally, enable the timings */
271 1.1 bouyer opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE);
272 1.1 bouyer }
273