optiide.c revision 1.11
1 /* $NetBSD: optiide.c,v 1.11 2005/05/24 05:25:15 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: optiide.c,v 1.11 2005/05/24 05:25:15 lukem Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/pciidereg.h> 48 #include <dev/pci/pciidevar.h> 49 #include <dev/pci/pciide_opti_reg.h> 50 51 static void opti_chip_map(struct pciide_softc*, struct pci_attach_args*); 52 static void opti_setup_channel(struct ata_channel*); 53 54 static int optiide_match(struct device *, struct cfdata *, void *); 55 static void optiide_attach(struct device *, struct device *, void *); 56 57 CFATTACH_DECL(optiide, sizeof(struct pciide_softc), 58 optiide_match, optiide_attach, NULL, NULL); 59 60 static const struct pciide_product_desc pciide_opti_products[] = { 61 { PCI_PRODUCT_OPTI_82C621, 62 0, 63 "OPTi 82c621 PCI IDE controller", 64 opti_chip_map, 65 }, 66 { PCI_PRODUCT_OPTI_82C568, 67 0, 68 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 69 opti_chip_map, 70 }, 71 { PCI_PRODUCT_OPTI_82D568, 72 0, 73 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 74 opti_chip_map, 75 }, 76 { 0, 77 0, 78 NULL, 79 NULL 80 } 81 }; 82 83 static int 84 optiide_match(struct device *parent, struct cfdata *match, void *aux) 85 { 86 struct pci_attach_args *pa = aux; 87 88 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_OPTI && 89 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 90 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 91 if (pciide_lookup_product(pa->pa_id, pciide_opti_products)) 92 return (2); 93 } 94 return (0); 95 } 96 97 static void 98 optiide_attach(struct device *parent, struct device *self, void *aux) 99 { 100 struct pci_attach_args *pa = aux; 101 struct pciide_softc *sc = (struct pciide_softc *)self; 102 103 pciide_common_attach(sc, pa, 104 pciide_lookup_product(pa->pa_id, pciide_opti_products)); 105 106 } 107 108 static void 109 opti_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 110 { 111 struct pciide_channel *cp; 112 bus_size_t cmdsize, ctlsize; 113 pcireg_t interface; 114 u_int8_t init_ctrl; 115 int channel; 116 117 if (pciide_chipen(sc, pa) == 0) 118 return; 119 120 aprint_normal("%s: bus-master DMA support present", 121 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 122 123 /* 124 * XXXSCW: 125 * There seem to be a couple of buggy revisions/implementations 126 * of the OPTi pciide chipset. This kludge seems to fix one of 127 * the reported problems (PR/11644) but still fails for the 128 * other (PR/13151), although the latter may be due to other 129 * issues too... 130 */ 131 if (PCI_REVISION(pa->pa_class) <= 0x12) { 132 aprint_normal(" but disabled due to chip rev. <= 0x12"); 133 sc->sc_dma_ok = 0; 134 } else 135 pciide_mapreg_dma(sc, pa); 136 137 aprint_normal("\n"); 138 139 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA32 | ATAC_CAP_DATA16; 140 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 141 if (sc->sc_dma_ok) { 142 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 143 sc->sc_wdcdev.irqack = pciide_irqack; 144 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 145 } 146 sc->sc_wdcdev.sc_atac.atac_set_modes = opti_setup_channel; 147 148 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 149 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 150 151 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 152 OPTI_REG_INIT_CONTROL); 153 154 interface = PCI_INTERFACE(pa->pa_class); 155 156 wdc_allocate_regs(&sc->sc_wdcdev); 157 158 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 159 channel++) { 160 cp = &sc->pciide_channels[channel]; 161 if (pciide_chansetup(sc, channel, interface) == 0) 162 continue; 163 if (channel == 1 && 164 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 165 aprint_normal("%s: %s channel ignored (disabled)\n", 166 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 167 cp->ata_channel.ch_flags |= ATACH_DISABLED; 168 continue; 169 } 170 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 171 pciide_pci_intr); 172 } 173 } 174 175 static void 176 opti_setup_channel(struct ata_channel *chp) 177 { 178 struct ata_drive_datas *drvp; 179 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 180 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 181 int drive, spd, s; 182 int mode[2]; 183 u_int8_t rv, mr; 184 185 /* 186 * The `Delay' and `Address Setup Time' fields of the 187 * Miscellaneous Register are always zero initially. 188 */ 189 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 190 mr &= ~(OPTI_MISC_DELAY_MASK | 191 OPTI_MISC_ADDR_SETUP_MASK | 192 OPTI_MISC_INDEX_MASK); 193 194 /* Prime the control register before setting timing values */ 195 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 196 197 /* Determine the clockrate of the PCIbus the chip is attached to */ 198 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 199 spd &= OPTI_STRAP_PCI_SPEED_MASK; 200 201 /* setup DMA if needed */ 202 pciide_channel_dma_setup(cp); 203 204 for (drive = 0; drive < 2; drive++) { 205 drvp = &chp->ch_drive[drive]; 206 /* If no drive, skip */ 207 if ((drvp->drive_flags & DRIVE) == 0) { 208 mode[drive] = -1; 209 continue; 210 } 211 212 if ((drvp->drive_flags & DRIVE_DMA)) { 213 /* 214 * Timings will be used for both PIO and DMA, 215 * so adjust DMA mode if needed 216 */ 217 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 218 drvp->PIO_mode = drvp->DMA_mode + 2; 219 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 220 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 221 drvp->PIO_mode - 2 : 0; 222 if (drvp->DMA_mode == 0) 223 drvp->PIO_mode = 0; 224 225 mode[drive] = drvp->DMA_mode + 5; 226 } else 227 mode[drive] = drvp->PIO_mode; 228 229 if (drive && mode[0] >= 0 && 230 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 231 /* 232 * Can't have two drives using different values 233 * for `Address Setup Time'. 234 * Slow down the faster drive to compensate. 235 */ 236 int d = (opti_tim_as[spd][mode[0]] > 237 opti_tim_as[spd][mode[1]]) ? 0 : 1; 238 239 mode[d] = mode[1-d]; 240 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 241 chp->ch_drive[d].DMA_mode = 0; 242 s = splbio(); 243 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 244 splx(s); 245 } 246 } 247 248 for (drive = 0; drive < 2; drive++) { 249 int m; 250 if ((m = mode[drive]) < 0) 251 continue; 252 253 /* Set the Address Setup Time and select appropriate index */ 254 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 255 rv |= OPTI_MISC_INDEX(drive); 256 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 257 258 /* Set the pulse width and recovery timing parameters */ 259 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 260 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 261 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 262 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 263 264 /* Set the Enhanced Mode register appropriately */ 265 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 266 rv &= ~OPTI_ENH_MODE_MASK(chp->ch_channel, drive); 267 rv |= OPTI_ENH_MODE(chp->ch_channel, drive, opti_tim_em[m]); 268 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 269 } 270 271 /* Finally, enable the timings */ 272 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 273 } 274
Indexes created Thu Sep 25 16:09:42 GMT 2025