optiide.c revision 1.15
1 /* $NetBSD: optiide.c,v 1.15 2007/02/09 21:55:27 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: optiide.c,v 1.15 2007/02/09 21:55:27 ad Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/pciidereg.h> 48 #include <dev/pci/pciidevar.h> 49 #include <dev/pci/pciide_opti_reg.h> 50 51 static void opti_chip_map(struct pciide_softc*, struct pci_attach_args*); 52 static void opti_setup_channel(struct ata_channel*); 53 54 static int optiide_match(struct device *, struct cfdata *, void *); 55 static void optiide_attach(struct device *, struct device *, void *); 56 57 CFATTACH_DECL(optiide, sizeof(struct pciide_softc), 58 optiide_match, optiide_attach, NULL, NULL); 59 60 static const struct pciide_product_desc pciide_opti_products[] = { 61 { PCI_PRODUCT_OPTI_82C621, 62 0, 63 "OPTi 82c621 PCI IDE controller", 64 opti_chip_map, 65 }, 66 { PCI_PRODUCT_OPTI_82C568, 67 0, 68 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 69 opti_chip_map, 70 }, 71 { PCI_PRODUCT_OPTI_82D568, 72 0, 73 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 74 opti_chip_map, 75 }, 76 { 0, 77 0, 78 NULL, 79 NULL 80 } 81 }; 82 83 static int 84 optiide_match(struct device *parent, struct cfdata *match, 85 void *aux) 86 { 87 struct pci_attach_args *pa = aux; 88 89 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_OPTI && 90 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 91 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 92 if (pciide_lookup_product(pa->pa_id, pciide_opti_products)) 93 return (2); 94 } 95 return (0); 96 } 97 98 static void 99 optiide_attach(struct device *parent, struct device *self, void *aux) 100 { 101 struct pci_attach_args *pa = aux; 102 struct pciide_softc *sc = (struct pciide_softc *)self; 103 104 pciide_common_attach(sc, pa, 105 pciide_lookup_product(pa->pa_id, pciide_opti_products)); 106 107 } 108 109 static void 110 opti_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 111 { 112 struct pciide_channel *cp; 113 bus_size_t cmdsize, ctlsize; 114 pcireg_t interface; 115 u_int8_t init_ctrl; 116 int channel; 117 118 if (pciide_chipen(sc, pa) == 0) 119 return; 120 121 aprint_verbose("%s: bus-master DMA support present", 122 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 123 124 /* 125 * XXXSCW: 126 * There seem to be a couple of buggy revisions/implementations 127 * of the OPTi pciide chipset. This kludge seems to fix one of 128 * the reported problems (PR/11644) but still fails for the 129 * other (PR/13151), although the latter may be due to other 130 * issues too... 131 */ 132 if (PCI_REVISION(pa->pa_class) <= 0x12) { 133 aprint_verbose(" but disabled due to chip rev. <= 0x12"); 134 sc->sc_dma_ok = 0; 135 } else 136 pciide_mapreg_dma(sc, pa); 137 138 aprint_verbose("\n"); 139 140 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA32 | ATAC_CAP_DATA16; 141 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 142 if (sc->sc_dma_ok) { 143 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 144 sc->sc_wdcdev.irqack = pciide_irqack; 145 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 146 } 147 sc->sc_wdcdev.sc_atac.atac_set_modes = opti_setup_channel; 148 149 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 150 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 151 152 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 153 OPTI_REG_INIT_CONTROL); 154 155 interface = PCI_INTERFACE(pa->pa_class); 156 157 wdc_allocate_regs(&sc->sc_wdcdev); 158 159 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 160 channel++) { 161 cp = &sc->pciide_channels[channel]; 162 if (pciide_chansetup(sc, channel, interface) == 0) 163 continue; 164 if (channel == 1 && 165 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 166 aprint_normal("%s: %s channel ignored (disabled)\n", 167 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 168 cp->ata_channel.ch_flags |= ATACH_DISABLED; 169 continue; 170 } 171 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 172 pciide_pci_intr); 173 } 174 } 175 176 static void 177 opti_setup_channel(struct ata_channel *chp) 178 { 179 struct ata_drive_datas *drvp; 180 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 181 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 182 int drive, spd, s; 183 int mode[2]; 184 u_int8_t rv, mr; 185 186 /* 187 * The `Delay' and `Address Setup Time' fields of the 188 * Miscellaneous Register are always zero initially. 189 */ 190 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 191 mr &= ~(OPTI_MISC_DELAY_MASK | 192 OPTI_MISC_ADDR_SETUP_MASK | 193 OPTI_MISC_INDEX_MASK); 194 195 /* Prime the control register before setting timing values */ 196 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 197 198 /* Determine the clockrate of the PCIbus the chip is attached to */ 199 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 200 spd &= OPTI_STRAP_PCI_SPEED_MASK; 201 202 /* setup DMA if needed */ 203 pciide_channel_dma_setup(cp); 204 205 for (drive = 0; drive < 2; drive++) { 206 drvp = &chp->ch_drive[drive]; 207 /* If no drive, skip */ 208 if ((drvp->drive_flags & DRIVE) == 0) { 209 mode[drive] = -1; 210 continue; 211 } 212 213 if ((drvp->drive_flags & DRIVE_DMA)) { 214 /* 215 * Timings will be used for both PIO and DMA, 216 * so adjust DMA mode if needed 217 */ 218 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 219 drvp->PIO_mode = drvp->DMA_mode + 2; 220 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 221 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 222 drvp->PIO_mode - 2 : 0; 223 if (drvp->DMA_mode == 0) 224 drvp->PIO_mode = 0; 225 226 mode[drive] = drvp->DMA_mode + 5; 227 } else 228 mode[drive] = drvp->PIO_mode; 229 230 if (drive && mode[0] >= 0 && 231 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 232 /* 233 * Can't have two drives using different values 234 * for `Address Setup Time'. 235 * Slow down the faster drive to compensate. 236 */ 237 int d = (opti_tim_as[spd][mode[0]] > 238 opti_tim_as[spd][mode[1]]) ? 0 : 1; 239 240 mode[d] = mode[1-d]; 241 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 242 chp->ch_drive[d].DMA_mode = 0; 243 s = splbio(); 244 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 245 splx(s); 246 } 247 } 248 249 for (drive = 0; drive < 2; drive++) { 250 int m; 251 if ((m = mode[drive]) < 0) 252 continue; 253 254 /* Set the Address Setup Time and select appropriate index */ 255 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 256 rv |= OPTI_MISC_INDEX(drive); 257 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 258 259 /* Set the pulse width and recovery timing parameters */ 260 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 261 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 262 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 263 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 264 265 /* Set the Enhanced Mode register appropriately */ 266 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 267 rv &= ~OPTI_ENH_MODE_MASK(chp->ch_channel, drive); 268 rv |= OPTI_ENH_MODE(chp->ch_channel, drive, opti_tim_em[m]); 269 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 270 } 271 272 /* Finally, enable the timings */ 273 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 274 } 275
Indexes created Wed Sep 24 14:09:57 GMT 2025