optiide.c revision 1.15.20.1
1 /* optiide.c,v 1.15 2007/02/09 21:55:27 ad Exp */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "optiide.c,v 1.15 2007/02/09 21:55:27 ad Exp"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/pciidereg.h> 48 #include <dev/pci/pciidevar.h> 49 #include <dev/pci/pciide_opti_reg.h> 50 51 static void opti_chip_map(struct pciide_softc*, struct pci_attach_args*); 52 static void opti_setup_channel(struct ata_channel*); 53 54 static int optiide_match(device_t, cfdata_t, void *); 55 static void optiide_attach(device_t, device_t, void *); 56 57 CFATTACH_DECL_NEW(optiide, sizeof(struct pciide_softc), 58 optiide_match, optiide_attach, NULL, NULL); 59 60 static const struct pciide_product_desc pciide_opti_products[] = { 61 { PCI_PRODUCT_OPTI_82C621, 62 0, 63 "OPTi 82c621 PCI IDE controller", 64 opti_chip_map, 65 }, 66 { PCI_PRODUCT_OPTI_82C568, 67 0, 68 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 69 opti_chip_map, 70 }, 71 { PCI_PRODUCT_OPTI_82D568, 72 0, 73 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 74 opti_chip_map, 75 }, 76 { 0, 77 0, 78 NULL, 79 NULL 80 } 81 }; 82 83 static int 84 optiide_match(device_t parent, cfdata_t match, void *aux) 85 { 86 struct pci_attach_args *pa = aux; 87 88 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_OPTI && 89 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 90 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 91 if (pciide_lookup_product(pa->pa_id, pciide_opti_products)) 92 return (2); 93 } 94 return (0); 95 } 96 97 static void 98 optiide_attach(device_t parent, device_t self, void *aux) 99 { 100 struct pci_attach_args *pa = aux; 101 struct pciide_softc *sc = device_private(self); 102 103 sc->sc_wdcdev.sc_atac.atac_dev = self; 104 105 pciide_common_attach(sc, pa, 106 pciide_lookup_product(pa->pa_id, pciide_opti_products)); 107 108 } 109 110 static void 111 opti_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 112 { 113 struct pciide_channel *cp; 114 bus_size_t cmdsize, ctlsize; 115 pcireg_t interface; 116 u_int8_t init_ctrl; 117 int channel; 118 119 if (pciide_chipen(sc, pa) == 0) 120 return; 121 122 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 123 "bus-master DMA support present"); 124 125 /* 126 * XXXSCW: 127 * There seem to be a couple of buggy revisions/implementations 128 * of the OPTi pciide chipset. This kludge seems to fix one of 129 * the reported problems (PR/11644) but still fails for the 130 * other (PR/13151), although the latter may be due to other 131 * issues too... 132 */ 133 if (PCI_REVISION(pa->pa_class) <= 0x12) { 134 aprint_verbose(" but disabled due to chip rev. <= 0x12"); 135 sc->sc_dma_ok = 0; 136 } else 137 pciide_mapreg_dma(sc, pa); 138 139 aprint_verbose("\n"); 140 141 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA32 | ATAC_CAP_DATA16; 142 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 143 if (sc->sc_dma_ok) { 144 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 145 sc->sc_wdcdev.irqack = pciide_irqack; 146 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 147 } 148 sc->sc_wdcdev.sc_atac.atac_set_modes = opti_setup_channel; 149 150 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 151 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 152 153 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 154 OPTI_REG_INIT_CONTROL); 155 156 interface = PCI_INTERFACE(pa->pa_class); 157 158 wdc_allocate_regs(&sc->sc_wdcdev); 159 160 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 161 channel++) { 162 cp = &sc->pciide_channels[channel]; 163 if (pciide_chansetup(sc, channel, interface) == 0) 164 continue; 165 if (channel == 1 && 166 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 167 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 168 "%s channel ignored (disabled)\n", cp->name); 169 cp->ata_channel.ch_flags |= ATACH_DISABLED; 170 continue; 171 } 172 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 173 pciide_pci_intr); 174 } 175 } 176 177 static void 178 opti_setup_channel(struct ata_channel *chp) 179 { 180 struct ata_drive_datas *drvp; 181 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 182 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 183 int drive, spd, s; 184 int mode[2]; 185 u_int8_t rv, mr; 186 187 /* 188 * The `Delay' and `Address Setup Time' fields of the 189 * Miscellaneous Register are always zero initially. 190 */ 191 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 192 mr &= ~(OPTI_MISC_DELAY_MASK | 193 OPTI_MISC_ADDR_SETUP_MASK | 194 OPTI_MISC_INDEX_MASK); 195 196 /* Prime the control register before setting timing values */ 197 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 198 199 /* Determine the clockrate of the PCIbus the chip is attached to */ 200 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 201 spd &= OPTI_STRAP_PCI_SPEED_MASK; 202 203 /* setup DMA if needed */ 204 pciide_channel_dma_setup(cp); 205 206 for (drive = 0; drive < 2; drive++) { 207 drvp = &chp->ch_drive[drive]; 208 /* If no drive, skip */ 209 if ((drvp->drive_flags & DRIVE) == 0) { 210 mode[drive] = -1; 211 continue; 212 } 213 214 if ((drvp->drive_flags & DRIVE_DMA)) { 215 /* 216 * Timings will be used for both PIO and DMA, 217 * so adjust DMA mode if needed 218 */ 219 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 220 drvp->PIO_mode = drvp->DMA_mode + 2; 221 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 222 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 223 drvp->PIO_mode - 2 : 0; 224 if (drvp->DMA_mode == 0) 225 drvp->PIO_mode = 0; 226 227 mode[drive] = drvp->DMA_mode + 5; 228 } else 229 mode[drive] = drvp->PIO_mode; 230 231 if (drive && mode[0] >= 0 && 232 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 233 /* 234 * Can't have two drives using different values 235 * for `Address Setup Time'. 236 * Slow down the faster drive to compensate. 237 */ 238 int d = (opti_tim_as[spd][mode[0]] > 239 opti_tim_as[spd][mode[1]]) ? 0 : 1; 240 241 mode[d] = mode[1-d]; 242 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 243 chp->ch_drive[d].DMA_mode = 0; 244 s = splbio(); 245 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 246 splx(s); 247 } 248 } 249 250 for (drive = 0; drive < 2; drive++) { 251 int m; 252 if ((m = mode[drive]) < 0) 253 continue; 254 255 /* Set the Address Setup Time and select appropriate index */ 256 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 257 rv |= OPTI_MISC_INDEX(drive); 258 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 259 260 /* Set the pulse width and recovery timing parameters */ 261 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 262 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 263 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 264 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 265 266 /* Set the Enhanced Mode register appropriately */ 267 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 268 rv &= ~OPTI_ENH_MODE_MASK(chp->ch_channel, drive); 269 rv |= OPTI_ENH_MODE(chp->ch_channel, drive, opti_tim_em[m]); 270 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 271 } 272 273 /* Finally, enable the timings */ 274 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 275 } 276
Indexes created Sun Oct 12 02:09:55 GMT 2025