pccbb.c revision 1.112.2.2
1 1.112.2.2 kent /* $NetBSD: pccbb.c,v 1.112.2.2 2005/04/29 11:29:07 kent Exp $ */ 2 1.112.2.2 kent 3 1.112.2.2 kent /* 4 1.112.2.2 kent * Copyright (c) 1998, 1999 and 2000 5 1.112.2.2 kent * HAYAKAWA Koichi. All rights reserved. 6 1.112.2.2 kent * 7 1.112.2.2 kent * Redistribution and use in source and binary forms, with or without 8 1.112.2.2 kent * modification, are permitted provided that the following conditions 9 1.112.2.2 kent * are met: 10 1.112.2.2 kent * 1. Redistributions of source code must retain the above copyright 11 1.112.2.2 kent * notice, this list of conditions and the following disclaimer. 12 1.112.2.2 kent * 2. Redistributions in binary form must reproduce the above copyright 13 1.112.2.2 kent * notice, this list of conditions and the following disclaimer in the 14 1.112.2.2 kent * documentation and/or other materials provided with the distribution. 15 1.112.2.2 kent * 3. All advertising materials mentioning features or use of this software 16 1.112.2.2 kent * must display the following acknowledgement: 17 1.112.2.2 kent * This product includes software developed by HAYAKAWA Koichi. 18 1.112.2.2 kent * 4. The name of the author may not be used to endorse or promote products 19 1.112.2.2 kent * derived from this software without specific prior written permission. 20 1.112.2.2 kent * 21 1.112.2.2 kent * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 1.112.2.2 kent * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 1.112.2.2 kent * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 1.112.2.2 kent * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 1.112.2.2 kent * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 1.112.2.2 kent * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 1.112.2.2 kent * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 1.112.2.2 kent * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 1.112.2.2 kent * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 1.112.2.2 kent * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 1.112.2.2 kent */ 32 1.112.2.2 kent 33 1.112.2.2 kent #include <sys/cdefs.h> 34 1.112.2.2 kent __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.112.2.2 2005/04/29 11:29:07 kent Exp $"); 35 1.112.2.2 kent 36 1.112.2.2 kent /* 37 1.112.2.2 kent #define CBB_DEBUG 38 1.112.2.2 kent #define SHOW_REGS 39 1.112.2.2 kent #define PCCBB_PCMCIA_POLL 40 1.112.2.2 kent */ 41 1.112.2.2 kent /* #define CBB_DEBUG */ 42 1.112.2.2 kent 43 1.112.2.2 kent /* 44 1.112.2.2 kent #define CB_PCMCIA_POLL 45 1.112.2.2 kent #define CB_PCMCIA_POLL_ONLY 46 1.112.2.2 kent #define LEVEL2 47 1.112.2.2 kent */ 48 1.112.2.2 kent 49 1.112.2.2 kent #include <sys/param.h> 50 1.112.2.2 kent #include <sys/systm.h> 51 1.112.2.2 kent #include <sys/kernel.h> 52 1.112.2.2 kent #include <sys/errno.h> 53 1.112.2.2 kent #include <sys/ioctl.h> 54 1.112.2.2 kent #include <sys/reboot.h> /* for bootverbose */ 55 1.112.2.2 kent #include <sys/syslog.h> 56 1.112.2.2 kent #include <sys/device.h> 57 1.112.2.2 kent #include <sys/malloc.h> 58 1.112.2.2 kent #include <sys/proc.h> 59 1.112.2.2 kent 60 1.112.2.2 kent #include <machine/intr.h> 61 1.112.2.2 kent #include <machine/bus.h> 62 1.112.2.2 kent 63 1.112.2.2 kent #include <dev/pci/pcivar.h> 64 1.112.2.2 kent #include <dev/pci/pcireg.h> 65 1.112.2.2 kent #include <dev/pci/pcidevs.h> 66 1.112.2.2 kent 67 1.112.2.2 kent #include <dev/pci/pccbbreg.h> 68 1.112.2.2 kent 69 1.112.2.2 kent #include <dev/cardbus/cardslotvar.h> 70 1.112.2.2 kent 71 1.112.2.2 kent #include <dev/cardbus/cardbusvar.h> 72 1.112.2.2 kent 73 1.112.2.2 kent #include <dev/pcmcia/pcmciareg.h> 74 1.112.2.2 kent #include <dev/pcmcia/pcmciavar.h> 75 1.112.2.2 kent 76 1.112.2.2 kent #include <dev/ic/i82365reg.h> 77 1.112.2.2 kent #include <dev/ic/i82365var.h> 78 1.112.2.2 kent #include <dev/pci/pccbbvar.h> 79 1.112.2.2 kent 80 1.112.2.2 kent #include "locators.h" 81 1.112.2.2 kent 82 1.112.2.2 kent #ifndef __NetBSD_Version__ 83 1.112.2.2 kent struct cfdriver cbb_cd = { 84 1.112.2.2 kent NULL, "cbb", DV_DULL 85 1.112.2.2 kent }; 86 1.112.2.2 kent #endif 87 1.112.2.2 kent 88 1.112.2.2 kent #ifdef CBB_DEBUG 89 1.112.2.2 kent #define DPRINTF(x) printf x 90 1.112.2.2 kent #define STATIC 91 1.112.2.2 kent #else 92 1.112.2.2 kent #define DPRINTF(x) 93 1.112.2.2 kent #define STATIC static 94 1.112.2.2 kent #endif 95 1.112.2.2 kent 96 1.112.2.2 kent /* 97 1.112.2.2 kent * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 1.112.2.2 kent * if you want to wait more than 1 ms. 99 1.112.2.2 kent */ 100 1.112.2.2 kent #define DELAY_MS(time, param) \ 101 1.112.2.2 kent do { \ 102 1.112.2.2 kent if (cold == 0) { \ 103 1.112.2.2 kent int tick = (hz*(time))/1000; \ 104 1.112.2.2 kent \ 105 1.112.2.2 kent if (tick <= 1) { \ 106 1.112.2.2 kent tick = 2; \ 107 1.112.2.2 kent } \ 108 1.112.2.2 kent tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 1.112.2.2 kent } else { \ 110 1.112.2.2 kent delay((time)*1000); \ 111 1.112.2.2 kent } \ 112 1.112.2.2 kent } while (0) 113 1.112.2.2 kent 114 1.112.2.2 kent int pcicbbmatch(struct device *, struct cfdata *, void *); 115 1.112.2.2 kent void pccbbattach(struct device *, struct device *, void *); 116 1.112.2.2 kent int pccbbintr(void *); 117 1.112.2.2 kent static void pci113x_insert(void *); 118 1.112.2.2 kent static int pccbbintr_function(struct pccbb_softc *); 119 1.112.2.2 kent 120 1.112.2.2 kent static int pccbb_detect_card(struct pccbb_softc *); 121 1.112.2.2 kent 122 1.112.2.2 kent static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 123 1.112.2.2 kent static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 124 1.112.2.2 kent #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 1.112.2.2 kent #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 1.112.2.2 kent 127 1.112.2.2 kent STATIC int cb_reset(struct pccbb_softc *); 128 1.112.2.2 kent STATIC int cb_detect_voltage(struct pccbb_softc *); 129 1.112.2.2 kent STATIC int cbbprint(void *, const char *); 130 1.112.2.2 kent 131 1.112.2.2 kent static int cb_chipset(u_int32_t, int *); 132 1.112.2.2 kent STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 133 1.112.2.2 kent struct pcmciabus_attach_args *); 134 1.112.2.2 kent #if 0 135 1.112.2.2 kent STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 136 1.112.2.2 kent STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 137 1.112.2.2 kent STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 138 1.112.2.2 kent #endif 139 1.112.2.2 kent 140 1.112.2.2 kent STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 141 1.112.2.2 kent STATIC int pccbb_power(cardbus_chipset_tag_t, int); 142 1.112.2.2 kent STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 143 1.112.2.2 kent #if !rbus 144 1.112.2.2 kent static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 145 1.112.2.2 kent static int pccbb_io_close(cardbus_chipset_tag_t, int); 146 1.112.2.2 kent static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 147 1.112.2.2 kent static int pccbb_mem_close(cardbus_chipset_tag_t, int); 148 1.112.2.2 kent #endif /* !rbus */ 149 1.112.2.2 kent static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 150 1.112.2.2 kent int level, int (*ih) (void *), void *sc); 151 1.112.2.2 kent static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 152 1.112.2.2 kent 153 1.112.2.2 kent static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 154 1.112.2.2 kent int level, int (*ih) (void *), void *sc); 155 1.112.2.2 kent static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 156 1.112.2.2 kent 157 1.112.2.2 kent static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int, int); 158 1.112.2.2 kent static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 159 1.112.2.2 kent static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 160 1.112.2.2 kent static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 161 1.112.2.2 kent cardbusreg_t); 162 1.112.2.2 kent static void pccbb_chipinit(struct pccbb_softc *); 163 1.112.2.2 kent 164 1.112.2.2 kent STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 165 1.112.2.2 kent struct pcmcia_mem_handle *); 166 1.112.2.2 kent STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 167 1.112.2.2 kent struct pcmcia_mem_handle *); 168 1.112.2.2 kent STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 1.112.2.2 kent bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 170 1.112.2.2 kent STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 171 1.112.2.2 kent STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 172 1.112.2.2 kent bus_size_t, bus_size_t, struct pcmcia_io_handle *); 173 1.112.2.2 kent STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 174 1.112.2.2 kent struct pcmcia_io_handle *); 175 1.112.2.2 kent STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 176 1.112.2.2 kent bus_size_t, struct pcmcia_io_handle *, int *); 177 1.112.2.2 kent STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 178 1.112.2.2 kent STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 179 1.112.2.2 kent struct pcmcia_function *, int, int (*)(void *), void *); 180 1.112.2.2 kent STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 181 1.112.2.2 kent STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 182 1.112.2.2 kent STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 183 1.112.2.2 kent STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 184 1.112.2.2 kent STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 185 1.112.2.2 kent 186 1.112.2.2 kent static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 187 1.112.2.2 kent static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 188 1.112.2.2 kent 189 1.112.2.2 kent static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 190 1.112.2.2 kent static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 191 1.112.2.2 kent static void pccbb_powerhook(int, void *); 192 1.112.2.2 kent 193 1.112.2.2 kent /* bus-space allocation and deallocation functions */ 194 1.112.2.2 kent #if rbus 195 1.112.2.2 kent 196 1.112.2.2 kent static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 197 1.112.2.2 kent bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 198 1.112.2.2 kent int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 199 1.112.2.2 kent static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 200 1.112.2.2 kent bus_space_handle_t, bus_size_t); 201 1.112.2.2 kent 202 1.112.2.2 kent #endif /* rbus */ 203 1.112.2.2 kent 204 1.112.2.2 kent #if rbus 205 1.112.2.2 kent 206 1.112.2.2 kent static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 207 1.112.2.2 kent bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 208 1.112.2.2 kent static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 209 1.112.2.2 kent bus_space_handle_t, bus_size_t); 210 1.112.2.2 kent static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 211 1.112.2.2 kent bus_size_t, bus_space_handle_t, int); 212 1.112.2.2 kent static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 213 1.112.2.2 kent bus_space_handle_t, bus_size_t); 214 1.112.2.2 kent static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 215 1.112.2.2 kent bus_space_tag_t); 216 1.112.2.2 kent void pccbb_winlist_show(struct pccbb_win_chain *); 217 1.112.2.2 kent 218 1.112.2.2 kent #endif /* rbus */ 219 1.112.2.2 kent 220 1.112.2.2 kent /* for config_defer */ 221 1.112.2.2 kent static void pccbb_pci_callback(struct device *); 222 1.112.2.2 kent 223 1.112.2.2 kent #if defined SHOW_REGS 224 1.112.2.2 kent static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 225 1.112.2.2 kent bus_space_tag_t memt, bus_space_handle_t memh); 226 1.112.2.2 kent #endif 227 1.112.2.2 kent 228 1.112.2.2 kent CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 229 1.112.2.2 kent pcicbbmatch, pccbbattach, NULL, NULL); 230 1.112.2.2 kent 231 1.112.2.2 kent static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 1.112.2.2 kent pccbb_pcmcia_mem_alloc, 233 1.112.2.2 kent pccbb_pcmcia_mem_free, 234 1.112.2.2 kent pccbb_pcmcia_mem_map, 235 1.112.2.2 kent pccbb_pcmcia_mem_unmap, 236 1.112.2.2 kent pccbb_pcmcia_io_alloc, 237 1.112.2.2 kent pccbb_pcmcia_io_free, 238 1.112.2.2 kent pccbb_pcmcia_io_map, 239 1.112.2.2 kent pccbb_pcmcia_io_unmap, 240 1.112.2.2 kent pccbb_pcmcia_intr_establish, 241 1.112.2.2 kent pccbb_pcmcia_intr_disestablish, 242 1.112.2.2 kent pccbb_pcmcia_socket_enable, 243 1.112.2.2 kent pccbb_pcmcia_socket_disable, 244 1.112.2.2 kent pccbb_pcmcia_socket_settype, 245 1.112.2.2 kent pccbb_pcmcia_card_detect 246 1.112.2.2 kent }; 247 1.112.2.2 kent 248 1.112.2.2 kent #if rbus 249 1.112.2.2 kent static struct cardbus_functions pccbb_funcs = { 250 1.112.2.2 kent pccbb_rbus_cb_space_alloc, 251 1.112.2.2 kent pccbb_rbus_cb_space_free, 252 1.112.2.2 kent pccbb_cb_intr_establish, 253 1.112.2.2 kent pccbb_cb_intr_disestablish, 254 1.112.2.2 kent pccbb_ctrl, 255 1.112.2.2 kent pccbb_power, 256 1.112.2.2 kent pccbb_make_tag, 257 1.112.2.2 kent pccbb_free_tag, 258 1.112.2.2 kent pccbb_conf_read, 259 1.112.2.2 kent pccbb_conf_write, 260 1.112.2.2 kent }; 261 1.112.2.2 kent #else 262 1.112.2.2 kent static struct cardbus_functions pccbb_funcs = { 263 1.112.2.2 kent pccbb_ctrl, 264 1.112.2.2 kent pccbb_power, 265 1.112.2.2 kent pccbb_mem_open, 266 1.112.2.2 kent pccbb_mem_close, 267 1.112.2.2 kent pccbb_io_open, 268 1.112.2.2 kent pccbb_io_close, 269 1.112.2.2 kent pccbb_cb_intr_establish, 270 1.112.2.2 kent pccbb_cb_intr_disestablish, 271 1.112.2.2 kent pccbb_make_tag, 272 1.112.2.2 kent pccbb_conf_read, 273 1.112.2.2 kent pccbb_conf_write, 274 1.112.2.2 kent }; 275 1.112.2.2 kent #endif 276 1.112.2.2 kent 277 1.112.2.2 kent int 278 1.112.2.2 kent pcicbbmatch(parent, match, aux) 279 1.112.2.2 kent struct device *parent; 280 1.112.2.2 kent struct cfdata *match; 281 1.112.2.2 kent void *aux; 282 1.112.2.2 kent { 283 1.112.2.2 kent struct pci_attach_args *pa = (struct pci_attach_args *)aux; 284 1.112.2.2 kent 285 1.112.2.2 kent if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 286 1.112.2.2 kent PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 287 1.112.2.2 kent PCI_INTERFACE(pa->pa_class) == 0) { 288 1.112.2.2 kent return 1; 289 1.112.2.2 kent } 290 1.112.2.2 kent 291 1.112.2.2 kent return 0; 292 1.112.2.2 kent } 293 1.112.2.2 kent 294 1.112.2.2 kent #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 295 1.112.2.2 kent | ((prod) << PCI_PRODUCT_SHIFT)) 296 1.112.2.2 kent 297 1.112.2.2 kent const struct yenta_chipinfo { 298 1.112.2.2 kent pcireg_t yc_id; /* vendor tag | product tag */ 299 1.112.2.2 kent int yc_chiptype; 300 1.112.2.2 kent int yc_flags; 301 1.112.2.2 kent } yc_chipsets[] = { 302 1.112.2.2 kent /* Texas Instruments chips */ 303 1.112.2.2 kent { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 304 1.112.2.2 kent PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 1.112.2.2 kent { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 306 1.112.2.2 kent PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 1.112.2.2 kent { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 308 1.112.2.2 kent PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 1.112.2.2 kent { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 310 1.112.2.2 kent PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 1.112.2.2 kent { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 312 1.112.2.2 kent PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 1.112.2.2 kent { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 314 1.112.2.2 kent PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 1.112.2.2 kent { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 316 1.112.2.2 kent PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 1.112.2.2 kent { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 318 1.112.2.2 kent PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 1.112.2.2 kent { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 320 1.112.2.2 kent PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 1.112.2.2 kent { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 322 1.112.2.2 kent PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 1.112.2.2 kent { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 324 1.112.2.2 kent PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 1.112.2.2 kent { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 326 1.112.2.2 kent PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 1.112.2.2 kent { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 328 1.112.2.2 kent PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 1.112.2.2 kent { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 330 1.112.2.2 kent PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 1.112.2.2 kent { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 332 1.112.2.2 kent PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 333 1.112.2.2 kent { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 334 1.112.2.2 kent PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 335 1.112.2.2 kent 336 1.112.2.2 kent /* Ricoh chips */ 337 1.112.2.2 kent { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 338 1.112.2.2 kent PCCBB_PCMCIA_MEM_32}, 339 1.112.2.2 kent { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 340 1.112.2.2 kent PCCBB_PCMCIA_MEM_32}, 341 1.112.2.2 kent { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 342 1.112.2.2 kent PCCBB_PCMCIA_MEM_32}, 343 1.112.2.2 kent { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 344 1.112.2.2 kent PCCBB_PCMCIA_MEM_32}, 345 1.112.2.2 kent { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 346 1.112.2.2 kent PCCBB_PCMCIA_MEM_32}, 347 1.112.2.2 kent { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 348 1.112.2.2 kent PCCBB_PCMCIA_MEM_32}, 349 1.112.2.2 kent 350 1.112.2.2 kent /* Toshiba products */ 351 1.112.2.2 kent { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 352 1.112.2.2 kent CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 353 1.112.2.2 kent { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 354 1.112.2.2 kent CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 355 1.112.2.2 kent { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 356 1.112.2.2 kent CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 357 1.112.2.2 kent { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 358 1.112.2.2 kent CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 359 1.112.2.2 kent 360 1.112.2.2 kent /* Cirrus Logic products */ 361 1.112.2.2 kent { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 362 1.112.2.2 kent CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 363 1.112.2.2 kent { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 364 1.112.2.2 kent CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 365 1.112.2.2 kent 366 1.112.2.2 kent /* sentinel, or Generic chip */ 367 1.112.2.2 kent { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 368 1.112.2.2 kent }; 369 1.112.2.2 kent 370 1.112.2.2 kent static int 371 1.112.2.2 kent cb_chipset(pci_id, flagp) 372 1.112.2.2 kent u_int32_t pci_id; 373 1.112.2.2 kent int *flagp; 374 1.112.2.2 kent { 375 1.112.2.2 kent const struct yenta_chipinfo *yc; 376 1.112.2.2 kent 377 1.112.2.2 kent /* Loop over except the last default entry. */ 378 1.112.2.2 kent for (yc = yc_chipsets; yc < yc_chipsets + 379 1.112.2.2 kent sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 380 1.112.2.2 kent if (pci_id == yc->yc_id) 381 1.112.2.2 kent break; 382 1.112.2.2 kent 383 1.112.2.2 kent if (flagp != NULL) 384 1.112.2.2 kent *flagp = yc->yc_flags; 385 1.112.2.2 kent 386 1.112.2.2 kent return (yc->yc_chiptype); 387 1.112.2.2 kent } 388 1.112.2.2 kent 389 1.112.2.2 kent static void 390 1.112.2.2 kent pccbb_shutdown(void *arg) 391 1.112.2.2 kent { 392 1.112.2.2 kent struct pccbb_softc *sc = arg; 393 1.112.2.2 kent pcireg_t command; 394 1.112.2.2 kent 395 1.112.2.2 kent DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 396 1.112.2.2 kent 397 1.112.2.2 kent /* 398 1.112.2.2 kent * turn off power 399 1.112.2.2 kent * 400 1.112.2.2 kent * XXX - do not turn off power if chipset is TI 113X because 401 1.112.2.2 kent * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 402 1.112.2.2 kent */ 403 1.112.2.2 kent if (sc->sc_chipset != CB_TI113X) { 404 1.112.2.2 kent pccbb_power((cardbus_chipset_tag_t)sc, 405 1.112.2.2 kent CARDBUS_VCC_0V | CARDBUS_VPP_0V); 406 1.112.2.2 kent } 407 1.112.2.2 kent 408 1.112.2.2 kent bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 409 1.112.2.2 kent 0); 410 1.112.2.2 kent 411 1.112.2.2 kent command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 412 1.112.2.2 kent 413 1.112.2.2 kent command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 414 1.112.2.2 kent PCI_COMMAND_MASTER_ENABLE); 415 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 416 1.112.2.2 kent 417 1.112.2.2 kent } 418 1.112.2.2 kent 419 1.112.2.2 kent void 420 1.112.2.2 kent pccbbattach(parent, self, aux) 421 1.112.2.2 kent struct device *parent; 422 1.112.2.2 kent struct device *self; 423 1.112.2.2 kent void *aux; 424 1.112.2.2 kent { 425 1.112.2.2 kent struct pccbb_softc *sc = (void *)self; 426 1.112.2.2 kent struct pci_attach_args *pa = aux; 427 1.112.2.2 kent pci_chipset_tag_t pc = pa->pa_pc; 428 1.112.2.2 kent pcireg_t busreg, reg, sock_base; 429 1.112.2.2 kent bus_addr_t sockbase; 430 1.112.2.2 kent char devinfo[256]; 431 1.112.2.2 kent int flags; 432 1.112.2.2 kent int pwrmgt_offs; 433 1.112.2.2 kent 434 1.112.2.2 kent #ifdef __HAVE_PCCBB_ATTACH_HOOK 435 1.112.2.2 kent pccbb_attach_hook(parent, self, pa); 436 1.112.2.2 kent #endif 437 1.112.2.2 kent 438 1.112.2.2 kent sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 439 1.112.2.2 kent 440 1.112.2.2 kent pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 441 1.112.2.2 kent printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 442 1.112.2.2 kent #ifdef CBB_DEBUG 443 1.112.2.2 kent printf(" (chipflags %x)", flags); 444 1.112.2.2 kent #endif 445 1.112.2.2 kent printf("\n"); 446 1.112.2.2 kent 447 1.112.2.2 kent TAILQ_INIT(&sc->sc_memwindow); 448 1.112.2.2 kent TAILQ_INIT(&sc->sc_iowindow); 449 1.112.2.2 kent 450 1.112.2.2 kent #if rbus 451 1.112.2.2 kent sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 452 1.112.2.2 kent sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 453 1.112.2.2 kent 454 1.112.2.2 kent #if 0 455 1.112.2.2 kent printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 456 1.112.2.2 kent pa->pa_memt, sc->sc_rbus_memt->rb_bt); 457 1.112.2.2 kent #endif 458 1.112.2.2 kent #endif /* rbus */ 459 1.112.2.2 kent 460 1.112.2.2 kent sc->sc_flags &= ~CBB_MEMHMAPPED; 461 1.112.2.2 kent 462 1.112.2.2 kent /* power management: set D0 state */ 463 1.112.2.2 kent sc->sc_pwrmgt_offs = 0; 464 1.112.2.2 kent if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 465 1.112.2.2 kent &pwrmgt_offs, 0)) { 466 1.112.2.2 kent reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 467 1.112.2.2 kent if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 468 1.112.2.2 kent reg & 0x100 /* PCI_PMCSR_PME_EN */) { 469 1.112.2.2 kent reg &= ~PCI_PMCSR_STATE_MASK; 470 1.112.2.2 kent reg |= PCI_PMCSR_STATE_D0; 471 1.112.2.2 kent reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 472 1.112.2.2 kent pci_conf_write(pc, pa->pa_tag, 473 1.112.2.2 kent pwrmgt_offs + PCI_PMCSR, reg); 474 1.112.2.2 kent } 475 1.112.2.2 kent 476 1.112.2.2 kent sc->sc_pwrmgt_offs = pwrmgt_offs; 477 1.112.2.2 kent } 478 1.112.2.2 kent 479 1.112.2.2 kent /* 480 1.112.2.2 kent * MAP socket registers and ExCA registers on memory-space 481 1.112.2.2 kent * When no valid address is set on socket base registers (on pci 482 1.112.2.2 kent * config space), get it not polite way. 483 1.112.2.2 kent */ 484 1.112.2.2 kent sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 485 1.112.2.2 kent 486 1.112.2.2 kent if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 487 1.112.2.2 kent PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 488 1.112.2.2 kent /* The address must be valid. */ 489 1.112.2.2 kent if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 490 1.112.2.2 kent &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 491 1.112.2.2 kent printf("%s: can't map socket base address 0x%lx\n", 492 1.112.2.2 kent sc->sc_dev.dv_xname, (unsigned long)sock_base); 493 1.112.2.2 kent /* 494 1.112.2.2 kent * I think it's funny: socket base registers must be 495 1.112.2.2 kent * mapped on memory space, but ... 496 1.112.2.2 kent */ 497 1.112.2.2 kent if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 498 1.112.2.2 kent 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 499 1.112.2.2 kent NULL)) { 500 1.112.2.2 kent printf("%s: can't map socket base address" 501 1.112.2.2 kent " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 502 1.112.2.2 kent (unsigned long)sockbase); 503 1.112.2.2 kent /* give up... allocate reg space via rbus. */ 504 1.112.2.2 kent pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 505 1.112.2.2 kent } else 506 1.112.2.2 kent sc->sc_flags |= CBB_MEMHMAPPED; 507 1.112.2.2 kent } else { 508 1.112.2.2 kent DPRINTF(("%s: socket base address 0x%lx\n", 509 1.112.2.2 kent sc->sc_dev.dv_xname, (unsigned long)sockbase)); 510 1.112.2.2 kent sc->sc_flags |= CBB_MEMHMAPPED; 511 1.112.2.2 kent } 512 1.112.2.2 kent } 513 1.112.2.2 kent 514 1.112.2.2 kent sc->sc_mem_start = 0; /* XXX */ 515 1.112.2.2 kent sc->sc_mem_end = 0xffffffff; /* XXX */ 516 1.112.2.2 kent 517 1.112.2.2 kent /* 518 1.112.2.2 kent * When interrupt isn't routed correctly, give up probing cbb and do 519 1.112.2.2 kent * not kill pcic-compatible port. 520 1.112.2.2 kent */ 521 1.112.2.2 kent if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 522 1.112.2.2 kent printf("%s: NOT USED because of unconfigured interrupt\n", 523 1.112.2.2 kent sc->sc_dev.dv_xname); 524 1.112.2.2 kent return; 525 1.112.2.2 kent } 526 1.112.2.2 kent 527 1.112.2.2 kent busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 528 1.112.2.2 kent 529 1.112.2.2 kent /* pccbb_machdep.c end */ 530 1.112.2.2 kent 531 1.112.2.2 kent #if defined CBB_DEBUG 532 1.112.2.2 kent { 533 1.112.2.2 kent static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 534 1.112.2.2 kent printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 535 1.112.2.2 kent intrname[pa->pa_intrpin], pa->pa_intrline); 536 1.112.2.2 kent } 537 1.112.2.2 kent #endif 538 1.112.2.2 kent 539 1.112.2.2 kent /* setup softc */ 540 1.112.2.2 kent sc->sc_pc = pc; 541 1.112.2.2 kent sc->sc_iot = pa->pa_iot; 542 1.112.2.2 kent sc->sc_memt = pa->pa_memt; 543 1.112.2.2 kent sc->sc_dmat = pa->pa_dmat; 544 1.112.2.2 kent sc->sc_tag = pa->pa_tag; 545 1.112.2.2 kent sc->sc_function = pa->pa_function; 546 1.112.2.2 kent sc->sc_sockbase = sock_base; 547 1.112.2.2 kent sc->sc_busnum = busreg; 548 1.112.2.2 kent 549 1.112.2.2 kent memcpy(&sc->sc_pa, pa, sizeof(*pa)); 550 1.112.2.2 kent 551 1.112.2.2 kent sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 552 1.112.2.2 kent 553 1.112.2.2 kent shutdownhook_establish(pccbb_shutdown, sc); 554 1.112.2.2 kent 555 1.112.2.2 kent /* Disable legacy register mapping. */ 556 1.112.2.2 kent switch (sc->sc_chipset) { 557 1.112.2.2 kent case CB_RX5C46X: /* fallthrough */ 558 1.112.2.2 kent #if 0 559 1.112.2.2 kent /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 560 1.112.2.2 kent case CB_RX5C47X: 561 1.112.2.2 kent #endif 562 1.112.2.2 kent /* 563 1.112.2.2 kent * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 564 1.112.2.2 kent * cannot be disabled by substituting 0 into PCI_LEGACY 565 1.112.2.2 kent * register. Ricoh CardBus bridges have special bits on Bridge 566 1.112.2.2 kent * control reg (addr 0x3e on PCI config space). 567 1.112.2.2 kent */ 568 1.112.2.2 kent reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 569 1.112.2.2 kent reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 570 1.112.2.2 kent pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 571 1.112.2.2 kent break; 572 1.112.2.2 kent 573 1.112.2.2 kent default: 574 1.112.2.2 kent /* XXX I don't know proper way to kill legacy I/O. */ 575 1.112.2.2 kent pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 576 1.112.2.2 kent break; 577 1.112.2.2 kent } 578 1.112.2.2 kent 579 1.112.2.2 kent config_defer(self, pccbb_pci_callback); 580 1.112.2.2 kent } 581 1.112.2.2 kent 582 1.112.2.2 kent 583 1.112.2.2 kent 584 1.112.2.2 kent 585 1.112.2.2 kent /* 586 1.112.2.2 kent * static void pccbb_pci_callback(struct device *self) 587 1.112.2.2 kent * 588 1.112.2.2 kent * The actual attach routine: get memory space for YENTA register 589 1.112.2.2 kent * space, setup YENTA register and route interrupt. 590 1.112.2.2 kent * 591 1.112.2.2 kent * This function should be deferred because this device may obtain 592 1.112.2.2 kent * memory space dynamically. This function must avoid obtaining 593 1.112.2.2 kent * memory area which has already kept for another device. 594 1.112.2.2 kent */ 595 1.112.2.2 kent static void 596 1.112.2.2 kent pccbb_pci_callback(self) 597 1.112.2.2 kent struct device *self; 598 1.112.2.2 kent { 599 1.112.2.2 kent struct pccbb_softc *sc = (void *)self; 600 1.112.2.2 kent pci_chipset_tag_t pc = sc->sc_pc; 601 1.112.2.2 kent pci_intr_handle_t ih; 602 1.112.2.2 kent const char *intrstr = NULL; 603 1.112.2.2 kent bus_addr_t sockbase; 604 1.112.2.2 kent struct cbslot_attach_args cba; 605 1.112.2.2 kent struct pcmciabus_attach_args paa; 606 1.112.2.2 kent struct cardslot_attach_args caa; 607 1.112.2.2 kent struct cardslot_softc *csc; 608 1.112.2.2 kent 609 1.112.2.2 kent if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 610 1.112.2.2 kent /* The socket registers aren't mapped correctly. */ 611 1.112.2.2 kent #if rbus 612 1.112.2.2 kent if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 613 1.112.2.2 kent (sc->sc_chipset == CB_RX5C47X 614 1.112.2.2 kent || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 615 1.112.2.2 kent 0, &sockbase, &sc->sc_base_memh)) { 616 1.112.2.2 kent return; 617 1.112.2.2 kent } 618 1.112.2.2 kent sc->sc_base_memt = sc->sc_memt; 619 1.112.2.2 kent pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 620 1.112.2.2 kent DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 621 1.112.2.2 kent sc->sc_dev.dv_xname, (unsigned long)sockbase, 622 1.112.2.2 kent (unsigned long)pci_conf_read(pc, sc->sc_tag, 623 1.112.2.2 kent PCI_SOCKBASE))); 624 1.112.2.2 kent #else 625 1.112.2.2 kent sc->sc_base_memt = sc->sc_memt; 626 1.112.2.2 kent #if !defined CBB_PCI_BASE 627 1.112.2.2 kent #define CBB_PCI_BASE 0x20000000 628 1.112.2.2 kent #endif 629 1.112.2.2 kent if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 630 1.112.2.2 kent 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 631 1.112.2.2 kent /* cannot allocate memory space */ 632 1.112.2.2 kent return; 633 1.112.2.2 kent } 634 1.112.2.2 kent pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 635 1.112.2.2 kent DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 636 1.112.2.2 kent sc->sc_dev.dv_xname, (unsigned long)sock_base, 637 1.112.2.2 kent (unsigned long)pci_conf_read(pc, 638 1.112.2.2 kent sc->sc_tag, PCI_SOCKBASE))); 639 1.112.2.2 kent sc->sc_sockbase = sockbase; 640 1.112.2.2 kent #endif 641 1.112.2.2 kent sc->sc_flags |= CBB_MEMHMAPPED; 642 1.112.2.2 kent } 643 1.112.2.2 kent 644 1.112.2.2 kent /* bus bridge initialization */ 645 1.112.2.2 kent pccbb_chipinit(sc); 646 1.112.2.2 kent 647 1.112.2.2 kent /* clear data structure for child device interrupt handlers */ 648 1.112.2.2 kent LIST_INIT(&sc->sc_pil); 649 1.112.2.2 kent sc->sc_pil_intr_enable = 1; 650 1.112.2.2 kent 651 1.112.2.2 kent /* Map and establish the interrupt. */ 652 1.112.2.2 kent if (pci_intr_map(&sc->sc_pa, &ih)) { 653 1.112.2.2 kent printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 654 1.112.2.2 kent return; 655 1.112.2.2 kent } 656 1.112.2.2 kent intrstr = pci_intr_string(pc, ih); 657 1.112.2.2 kent 658 1.112.2.2 kent /* 659 1.112.2.2 kent * XXX pccbbintr should be called under the priority lower 660 1.112.2.2 kent * than any other hard interupts. 661 1.112.2.2 kent */ 662 1.112.2.2 kent sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 663 1.112.2.2 kent 664 1.112.2.2 kent if (sc->sc_ih == NULL) { 665 1.112.2.2 kent printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 666 1.112.2.2 kent if (intrstr != NULL) { 667 1.112.2.2 kent printf(" at %s", intrstr); 668 1.112.2.2 kent } 669 1.112.2.2 kent printf("\n"); 670 1.112.2.2 kent return; 671 1.112.2.2 kent } 672 1.112.2.2 kent 673 1.112.2.2 kent printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 674 1.112.2.2 kent powerhook_establish(pccbb_powerhook, sc); 675 1.112.2.2 kent 676 1.112.2.2 kent { 677 1.112.2.2 kent u_int32_t sockstat; 678 1.112.2.2 kent 679 1.112.2.2 kent sockstat = bus_space_read_4(sc->sc_base_memt, 680 1.112.2.2 kent sc->sc_base_memh, CB_SOCKET_STAT); 681 1.112.2.2 kent if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 682 1.112.2.2 kent sc->sc_flags |= CBB_CARDEXIST; 683 1.112.2.2 kent } 684 1.112.2.2 kent } 685 1.112.2.2 kent 686 1.112.2.2 kent /* 687 1.112.2.2 kent * attach cardbus 688 1.112.2.2 kent */ 689 1.112.2.2 kent { 690 1.112.2.2 kent pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 691 1.112.2.2 kent pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 692 1.112.2.2 kent 693 1.112.2.2 kent /* initialize cbslot_attach */ 694 1.112.2.2 kent cba.cba_busname = "cardbus"; 695 1.112.2.2 kent cba.cba_iot = sc->sc_iot; 696 1.112.2.2 kent cba.cba_memt = sc->sc_memt; 697 1.112.2.2 kent cba.cba_dmat = sc->sc_dmat; 698 1.112.2.2 kent cba.cba_bus = (busreg >> 8) & 0x0ff; 699 1.112.2.2 kent cba.cba_cc = (void *)sc; 700 1.112.2.2 kent cba.cba_cf = &pccbb_funcs; 701 1.112.2.2 kent cba.cba_intrline = sc->sc_pa.pa_intrline; 702 1.112.2.2 kent 703 1.112.2.2 kent #if rbus 704 1.112.2.2 kent cba.cba_rbus_iot = sc->sc_rbus_iot; 705 1.112.2.2 kent cba.cba_rbus_memt = sc->sc_rbus_memt; 706 1.112.2.2 kent #endif 707 1.112.2.2 kent 708 1.112.2.2 kent cba.cba_cacheline = PCI_CACHELINE(bhlc); 709 1.112.2.2 kent cba.cba_lattimer = PCI_CB_LATENCY(busreg); 710 1.112.2.2 kent 711 1.112.2.2 kent if (bootverbose) { 712 1.112.2.2 kent printf("%s: cacheline 0x%x lattimer 0x%x\n", 713 1.112.2.2 kent sc->sc_dev.dv_xname, cba.cba_cacheline, 714 1.112.2.2 kent cba.cba_lattimer); 715 1.112.2.2 kent printf("%s: bhlc 0x%x lscp 0x%x\n", 716 1.112.2.2 kent sc->sc_dev.dv_xname, bhlc, busreg); 717 1.112.2.2 kent } 718 1.112.2.2 kent #if defined SHOW_REGS 719 1.112.2.2 kent cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 720 1.112.2.2 kent sc->sc_base_memh); 721 1.112.2.2 kent #endif 722 1.112.2.2 kent } 723 1.112.2.2 kent 724 1.112.2.2 kent pccbb_pcmcia_attach_setup(sc, &paa); 725 1.112.2.2 kent caa.caa_cb_attach = NULL; 726 1.112.2.2 kent if (cba.cba_bus == 0) 727 1.112.2.2 kent printf("%s: secondary bus number uninitialized; try PCIBIOS_BUS_FIXUP\n", sc->sc_dev.dv_xname); 728 1.112.2.2 kent else 729 1.112.2.2 kent caa.caa_cb_attach = &cba; 730 1.112.2.2 kent caa.caa_16_attach = &paa; 731 1.112.2.2 kent caa.caa_ph = &sc->sc_pcmcia_h; 732 1.112.2.2 kent 733 1.112.2.2 kent if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 734 1.112.2.2 kent DPRINTF(("pccbbattach: found cardslot\n")); 735 1.112.2.2 kent sc->sc_csc = csc; 736 1.112.2.2 kent } 737 1.112.2.2 kent 738 1.112.2.2 kent return; 739 1.112.2.2 kent } 740 1.112.2.2 kent 741 1.112.2.2 kent 742 1.112.2.2 kent 743 1.112.2.2 kent 744 1.112.2.2 kent 745 1.112.2.2 kent /* 746 1.112.2.2 kent * static void pccbb_chipinit(struct pccbb_softc *sc) 747 1.112.2.2 kent * 748 1.112.2.2 kent * This function initialize YENTA chip registers listed below: 749 1.112.2.2 kent * 1) PCI command reg, 750 1.112.2.2 kent * 2) PCI and CardBus latency timer, 751 1.112.2.2 kent * 3) route PCI interrupt, 752 1.112.2.2 kent * 4) close all memory and io windows. 753 1.112.2.2 kent * 5) turn off bus power. 754 1.112.2.2 kent * 6) card detect and power cycle interrupts on. 755 1.112.2.2 kent * 7) clear interrupt 756 1.112.2.2 kent */ 757 1.112.2.2 kent static void 758 1.112.2.2 kent pccbb_chipinit(sc) 759 1.112.2.2 kent struct pccbb_softc *sc; 760 1.112.2.2 kent { 761 1.112.2.2 kent pci_chipset_tag_t pc = sc->sc_pc; 762 1.112.2.2 kent pcitag_t tag = sc->sc_tag; 763 1.112.2.2 kent bus_space_tag_t bmt = sc->sc_base_memt; 764 1.112.2.2 kent bus_space_handle_t bmh = sc->sc_base_memh; 765 1.112.2.2 kent pcireg_t reg; 766 1.112.2.2 kent 767 1.112.2.2 kent /* 768 1.112.2.2 kent * Set PCI command reg. 769 1.112.2.2 kent * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 770 1.112.2.2 kent */ 771 1.112.2.2 kent reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 772 1.112.2.2 kent /* I believe it is harmless. */ 773 1.112.2.2 kent reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 774 1.112.2.2 kent PCI_COMMAND_MASTER_ENABLE); 775 1.112.2.2 kent pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 776 1.112.2.2 kent 777 1.112.2.2 kent /* 778 1.112.2.2 kent * Set CardBus latency timer. 779 1.112.2.2 kent */ 780 1.112.2.2 kent reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 781 1.112.2.2 kent if (PCI_CB_LATENCY(reg) < 0x20) { 782 1.112.2.2 kent reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 783 1.112.2.2 kent reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 784 1.112.2.2 kent pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 785 1.112.2.2 kent } 786 1.112.2.2 kent DPRINTF(("CardBus latency timer 0x%x (%x)\n", 787 1.112.2.2 kent PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 788 1.112.2.2 kent 789 1.112.2.2 kent /* 790 1.112.2.2 kent * Set PCI latency timer. 791 1.112.2.2 kent */ 792 1.112.2.2 kent reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 793 1.112.2.2 kent if (PCI_LATTIMER(reg) < 0x10) { 794 1.112.2.2 kent reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 795 1.112.2.2 kent reg |= (0x10 << PCI_LATTIMER_SHIFT); 796 1.112.2.2 kent pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 797 1.112.2.2 kent } 798 1.112.2.2 kent DPRINTF(("PCI latency timer 0x%x (%x)\n", 799 1.112.2.2 kent PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 800 1.112.2.2 kent 801 1.112.2.2 kent 802 1.112.2.2 kent /* Route functional interrupts to PCI. */ 803 1.112.2.2 kent reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 804 1.112.2.2 kent reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 805 1.112.2.2 kent reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 806 1.112.2.2 kent reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 807 1.112.2.2 kent pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 808 1.112.2.2 kent 809 1.112.2.2 kent switch (sc->sc_chipset) { 810 1.112.2.2 kent case CB_TI113X: 811 1.112.2.2 kent reg = pci_conf_read(pc, tag, PCI_CBCTRL); 812 1.112.2.2 kent /* This bit is shared, but may read as 0 on some chips, so set 813 1.112.2.2 kent it explicitly on both functions. */ 814 1.112.2.2 kent reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 815 1.112.2.2 kent /* CSC intr enable */ 816 1.112.2.2 kent reg |= PCI113X_CBCTRL_PCI_CSC; 817 1.112.2.2 kent /* functional intr prohibit | prohibit ISA routing */ 818 1.112.2.2 kent reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 819 1.112.2.2 kent pci_conf_write(pc, tag, PCI_CBCTRL, reg); 820 1.112.2.2 kent break; 821 1.112.2.2 kent 822 1.112.2.2 kent case CB_TI12XX: 823 1.112.2.2 kent /* 824 1.112.2.2 kent * Some TI 12xx (and [14][45]xx) based pci cards 825 1.112.2.2 kent * sometimes have issues with the MFUNC register not 826 1.112.2.2 kent * being initialized due to a bad EEPROM on board. 827 1.112.2.2 kent * Laptops that this matters on have this register 828 1.112.2.2 kent * properly initialized. 829 1.112.2.2 kent * 830 1.112.2.2 kent * The TI125X parts have a different register. 831 1.112.2.2 kent */ 832 1.112.2.2 kent reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 833 1.112.2.2 kent if (reg == 0) { 834 1.112.2.2 kent reg &= ~PCI12XX_MFUNC_PIN0; 835 1.112.2.2 kent reg |= PCI12XX_MFUNC_PIN0_INTA; 836 1.112.2.2 kent if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 837 1.112.2.2 kent PCI12XX_SYSCTRL_INTRTIE) == 0) { 838 1.112.2.2 kent reg &= ~PCI12XX_MFUNC_PIN1; 839 1.112.2.2 kent reg |= PCI12XX_MFUNC_PIN1_INTB; 840 1.112.2.2 kent } 841 1.112.2.2 kent pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 842 1.112.2.2 kent } 843 1.112.2.2 kent /* fallthrough */ 844 1.112.2.2 kent 845 1.112.2.2 kent case CB_TI125X: 846 1.112.2.2 kent /* 847 1.112.2.2 kent * Disable zoom video. Some machines initialize this 848 1.112.2.2 kent * improperly and experience has shown that this helps 849 1.112.2.2 kent * prevent strange behavior. 850 1.112.2.2 kent */ 851 1.112.2.2 kent pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 852 1.112.2.2 kent 853 1.112.2.2 kent reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 854 1.112.2.2 kent reg |= PCI12XX_SYSCTRL_VCCPROT; 855 1.112.2.2 kent pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 856 1.112.2.2 kent reg = pci_conf_read(pc, tag, PCI_CBCTRL); 857 1.112.2.2 kent reg |= PCI12XX_CBCTRL_CSC; 858 1.112.2.2 kent pci_conf_write(pc, tag, PCI_CBCTRL, reg); 859 1.112.2.2 kent break; 860 1.112.2.2 kent 861 1.112.2.2 kent case CB_TOPIC95B: 862 1.112.2.2 kent reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 863 1.112.2.2 kent reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 864 1.112.2.2 kent pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 865 1.112.2.2 kent reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 866 1.112.2.2 kent DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 867 1.112.2.2 kent sc->sc_dev.dv_xname, reg)); 868 1.112.2.2 kent reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 869 1.112.2.2 kent TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 870 1.112.2.2 kent reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 871 1.112.2.2 kent DPRINTF(("0x%x\n", reg)); 872 1.112.2.2 kent pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 873 1.112.2.2 kent break; 874 1.112.2.2 kent 875 1.112.2.2 kent case CB_TOPIC97: 876 1.112.2.2 kent reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 877 1.112.2.2 kent DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 878 1.112.2.2 kent sc->sc_dev.dv_xname, reg)); 879 1.112.2.2 kent reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 880 1.112.2.2 kent TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 881 1.112.2.2 kent reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 882 1.112.2.2 kent reg |= TOPIC97_SLOT_CTRL_PCIINT; 883 1.112.2.2 kent reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 884 1.112.2.2 kent DPRINTF(("0x%x\n", reg)); 885 1.112.2.2 kent pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 886 1.112.2.2 kent /* make sure to assert LV card support bits */ 887 1.112.2.2 kent bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 888 1.112.2.2 kent 0x800 + 0x3e, 889 1.112.2.2 kent bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 890 1.112.2.2 kent 0x800 + 0x3e) | 0x03); 891 1.112.2.2 kent break; 892 1.112.2.2 kent } 893 1.112.2.2 kent 894 1.112.2.2 kent /* Close all memory and I/O windows. */ 895 1.112.2.2 kent pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 896 1.112.2.2 kent pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 897 1.112.2.2 kent pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 898 1.112.2.2 kent pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 899 1.112.2.2 kent pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 900 1.112.2.2 kent pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 901 1.112.2.2 kent pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 902 1.112.2.2 kent pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 903 1.112.2.2 kent 904 1.112.2.2 kent /* reset 16-bit pcmcia bus */ 905 1.112.2.2 kent bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 906 1.112.2.2 kent bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 907 1.112.2.2 kent 908 1.112.2.2 kent /* turn off power */ 909 1.112.2.2 kent pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 910 1.112.2.2 kent 911 1.112.2.2 kent /* CSC Interrupt: Card detect and power cycle interrupts on */ 912 1.112.2.2 kent reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 913 1.112.2.2 kent reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 914 1.112.2.2 kent bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 915 1.112.2.2 kent /* reset interrupt */ 916 1.112.2.2 kent bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 917 1.112.2.2 kent bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 918 1.112.2.2 kent } 919 1.112.2.2 kent 920 1.112.2.2 kent 921 1.112.2.2 kent 922 1.112.2.2 kent 923 1.112.2.2 kent /* 924 1.112.2.2 kent * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 925 1.112.2.2 kent * struct pcmciabus_attach_args *paa) 926 1.112.2.2 kent * 927 1.112.2.2 kent * This function attaches 16-bit PCcard bus. 928 1.112.2.2 kent */ 929 1.112.2.2 kent STATIC void 930 1.112.2.2 kent pccbb_pcmcia_attach_setup(sc, paa) 931 1.112.2.2 kent struct pccbb_softc *sc; 932 1.112.2.2 kent struct pcmciabus_attach_args *paa; 933 1.112.2.2 kent { 934 1.112.2.2 kent struct pcic_handle *ph = &sc->sc_pcmcia_h; 935 1.112.2.2 kent #if rbus 936 1.112.2.2 kent rbus_tag_t rb; 937 1.112.2.2 kent #endif 938 1.112.2.2 kent 939 1.112.2.2 kent /* initialize pcmcia part in pccbb_softc */ 940 1.112.2.2 kent ph->ph_parent = (struct device *)sc; 941 1.112.2.2 kent ph->sock = sc->sc_function; 942 1.112.2.2 kent ph->flags = 0; 943 1.112.2.2 kent ph->shutdown = 0; 944 1.112.2.2 kent ph->ih_irq = sc->sc_pa.pa_intrline; 945 1.112.2.2 kent ph->ph_bus_t = sc->sc_base_memt; 946 1.112.2.2 kent ph->ph_bus_h = sc->sc_base_memh; 947 1.112.2.2 kent ph->ph_read = pccbb_pcmcia_read; 948 1.112.2.2 kent ph->ph_write = pccbb_pcmcia_write; 949 1.112.2.2 kent sc->sc_pct = &pccbb_pcmcia_funcs; 950 1.112.2.2 kent 951 1.112.2.2 kent /* 952 1.112.2.2 kent * We need to do a few things here: 953 1.112.2.2 kent * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 954 1.112.2.2 kent * setting the IRQ numbers to 0. 955 1.112.2.2 kent * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 956 1.112.2.2 kent * routing of CSC interrupts (e.g. card removal) to PCI while in 957 1.112.2.2 kent * PCMCIA mode. We just leave this set all the time. 958 1.112.2.2 kent * 3) Enable card insertion/removal interrupts in case the chip also 959 1.112.2.2 kent * needs that while in PCMCIA mode. 960 1.112.2.2 kent * 4) Clear any pending CSC interrupt. 961 1.112.2.2 kent */ 962 1.112.2.2 kent Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 963 1.112.2.2 kent if (sc->sc_chipset == CB_TI113X) { 964 1.112.2.2 kent Pcic_write(ph, PCIC_CSC_INTR, 0); 965 1.112.2.2 kent } else { 966 1.112.2.2 kent Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 967 1.112.2.2 kent Pcic_read(ph, PCIC_CSC); 968 1.112.2.2 kent } 969 1.112.2.2 kent 970 1.112.2.2 kent /* initialize pcmcia bus attachment */ 971 1.112.2.2 kent paa->paa_busname = "pcmcia"; 972 1.112.2.2 kent paa->pct = sc->sc_pct; 973 1.112.2.2 kent paa->pch = ph; 974 1.112.2.2 kent paa->iobase = 0; /* I don't use them */ 975 1.112.2.2 kent paa->iosize = 0; 976 1.112.2.2 kent #if rbus 977 1.112.2.2 kent rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 978 1.112.2.2 kent paa->iobase = rb->rb_start + rb->rb_offset; 979 1.112.2.2 kent paa->iosize = rb->rb_end - rb->rb_start; 980 1.112.2.2 kent #endif 981 1.112.2.2 kent 982 1.112.2.2 kent return; 983 1.112.2.2 kent } 984 1.112.2.2 kent 985 1.112.2.2 kent #if 0 986 1.112.2.2 kent STATIC void 987 1.112.2.2 kent pccbb_pcmcia_attach_card(ph) 988 1.112.2.2 kent struct pcic_handle *ph; 989 1.112.2.2 kent { 990 1.112.2.2 kent if (ph->flags & PCIC_FLAG_CARDP) { 991 1.112.2.2 kent panic("pccbb_pcmcia_attach_card: already attached"); 992 1.112.2.2 kent } 993 1.112.2.2 kent 994 1.112.2.2 kent /* call the MI attach function */ 995 1.112.2.2 kent pcmcia_card_attach(ph->pcmcia); 996 1.112.2.2 kent 997 1.112.2.2 kent ph->flags |= PCIC_FLAG_CARDP; 998 1.112.2.2 kent } 999 1.112.2.2 kent 1000 1.112.2.2 kent STATIC void 1001 1.112.2.2 kent pccbb_pcmcia_detach_card(ph, flags) 1002 1.112.2.2 kent struct pcic_handle *ph; 1003 1.112.2.2 kent int flags; 1004 1.112.2.2 kent { 1005 1.112.2.2 kent if (!(ph->flags & PCIC_FLAG_CARDP)) { 1006 1.112.2.2 kent panic("pccbb_pcmcia_detach_card: already detached"); 1007 1.112.2.2 kent } 1008 1.112.2.2 kent 1009 1.112.2.2 kent ph->flags &= ~PCIC_FLAG_CARDP; 1010 1.112.2.2 kent 1011 1.112.2.2 kent /* call the MI detach function */ 1012 1.112.2.2 kent pcmcia_card_detach(ph->pcmcia, flags); 1013 1.112.2.2 kent } 1014 1.112.2.2 kent #endif 1015 1.112.2.2 kent 1016 1.112.2.2 kent /* 1017 1.112.2.2 kent * int pccbbintr(arg) 1018 1.112.2.2 kent * void *arg; 1019 1.112.2.2 kent * This routine handles the interrupt from Yenta PCI-CardBus bridge 1020 1.112.2.2 kent * itself. 1021 1.112.2.2 kent */ 1022 1.112.2.2 kent int 1023 1.112.2.2 kent pccbbintr(arg) 1024 1.112.2.2 kent void *arg; 1025 1.112.2.2 kent { 1026 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1027 1.112.2.2 kent u_int32_t sockevent, sockstate; 1028 1.112.2.2 kent bus_space_tag_t memt = sc->sc_base_memt; 1029 1.112.2.2 kent bus_space_handle_t memh = sc->sc_base_memh; 1030 1.112.2.2 kent struct pcic_handle *ph = &sc->sc_pcmcia_h; 1031 1.112.2.2 kent 1032 1.112.2.2 kent sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1033 1.112.2.2 kent bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1034 1.112.2.2 kent Pcic_read(ph, PCIC_CSC); 1035 1.112.2.2 kent 1036 1.112.2.2 kent if (sockevent == 0) { 1037 1.112.2.2 kent /* This intr is not for me: it may be for my child devices. */ 1038 1.112.2.2 kent if (sc->sc_pil_intr_enable) { 1039 1.112.2.2 kent return pccbbintr_function(sc); 1040 1.112.2.2 kent } else { 1041 1.112.2.2 kent return 0; 1042 1.112.2.2 kent } 1043 1.112.2.2 kent } 1044 1.112.2.2 kent 1045 1.112.2.2 kent if (sockevent & CB_SOCKET_EVENT_CD) { 1046 1.112.2.2 kent sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1047 1.112.2.2 kent if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1048 1.112.2.2 kent /* A card should be removed. */ 1049 1.112.2.2 kent if (sc->sc_flags & CBB_CARDEXIST) { 1050 1.112.2.2 kent DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1051 1.112.2.2 kent sockevent)); 1052 1.112.2.2 kent DPRINTF((" card removed, 0x%08x\n", sockstate)); 1053 1.112.2.2 kent sc->sc_flags &= ~CBB_CARDEXIST; 1054 1.112.2.2 kent if (sc->sc_csc->sc_status & 1055 1.112.2.2 kent CARDSLOT_STATUS_CARD_16) { 1056 1.112.2.2 kent #if 0 1057 1.112.2.2 kent struct pcic_handle *ph = 1058 1.112.2.2 kent &sc->sc_pcmcia_h; 1059 1.112.2.2 kent 1060 1.112.2.2 kent pcmcia_card_deactivate(ph->pcmcia); 1061 1.112.2.2 kent pccbb_pcmcia_socket_disable(ph); 1062 1.112.2.2 kent pccbb_pcmcia_detach_card(ph, 1063 1.112.2.2 kent DETACH_FORCE); 1064 1.112.2.2 kent #endif 1065 1.112.2.2 kent cardslot_event_throw(sc->sc_csc, 1066 1.112.2.2 kent CARDSLOT_EVENT_REMOVAL_16); 1067 1.112.2.2 kent } else if (sc->sc_csc->sc_status & 1068 1.112.2.2 kent CARDSLOT_STATUS_CARD_CB) { 1069 1.112.2.2 kent /* Cardbus intr removed */ 1070 1.112.2.2 kent cardslot_event_throw(sc->sc_csc, 1071 1.112.2.2 kent CARDSLOT_EVENT_REMOVAL_CB); 1072 1.112.2.2 kent } 1073 1.112.2.2 kent } else if (sc->sc_flags & CBB_INSERTING) { 1074 1.112.2.2 kent sc->sc_flags &= ~CBB_INSERTING; 1075 1.112.2.2 kent callout_stop(&sc->sc_insert_ch); 1076 1.112.2.2 kent } 1077 1.112.2.2 kent } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1078 1.112.2.2 kent /* 1079 1.112.2.2 kent * The pccbbintr may called from powerdown hook when 1080 1.112.2.2 kent * the system resumed, to detect the card 1081 1.112.2.2 kent * insertion/removal during suspension. 1082 1.112.2.2 kent */ 1083 1.112.2.2 kent (sc->sc_flags & CBB_CARDEXIST) == 0) { 1084 1.112.2.2 kent if (sc->sc_flags & CBB_INSERTING) { 1085 1.112.2.2 kent callout_stop(&sc->sc_insert_ch); 1086 1.112.2.2 kent } 1087 1.112.2.2 kent callout_reset(&sc->sc_insert_ch, hz / 5, 1088 1.112.2.2 kent pci113x_insert, sc); 1089 1.112.2.2 kent sc->sc_flags |= CBB_INSERTING; 1090 1.112.2.2 kent } 1091 1.112.2.2 kent } 1092 1.112.2.2 kent 1093 1.112.2.2 kent if (sockevent & CB_SOCKET_EVENT_POWER) { 1094 1.112.2.2 kent /* XXX: Does not happen when attaching a 16-bit card */ 1095 1.112.2.2 kent sc->sc_pwrcycle++; 1096 1.112.2.2 kent wakeup(&sc->sc_pwrcycle); 1097 1.112.2.2 kent } 1098 1.112.2.2 kent 1099 1.112.2.2 kent return (1); 1100 1.112.2.2 kent } 1101 1.112.2.2 kent 1102 1.112.2.2 kent /* 1103 1.112.2.2 kent * static int pccbbintr_function(struct pccbb_softc *sc) 1104 1.112.2.2 kent * 1105 1.112.2.2 kent * This function calls each interrupt handler registered at the 1106 1.112.2.2 kent * bridge. The interrupt handlers are called in registered order. 1107 1.112.2.2 kent */ 1108 1.112.2.2 kent static int 1109 1.112.2.2 kent pccbbintr_function(sc) 1110 1.112.2.2 kent struct pccbb_softc *sc; 1111 1.112.2.2 kent { 1112 1.112.2.2 kent int retval = 0, val; 1113 1.112.2.2 kent struct pccbb_intrhand_list *pil; 1114 1.112.2.2 kent int s, splchanged; 1115 1.112.2.2 kent 1116 1.112.2.2 kent for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1117 1.112.2.2 kent pil = LIST_NEXT(pil, pil_next)) { 1118 1.112.2.2 kent /* 1119 1.112.2.2 kent * XXX priority change. gross. I use if-else 1120 1.112.2.2 kent * sentense instead of switch-case sentense because of 1121 1.112.2.2 kent * avoiding duplicate case value error. More than one 1122 1.112.2.2 kent * IPL_XXX use same value. It depends on 1123 1.112.2.2 kent * implimentation. 1124 1.112.2.2 kent */ 1125 1.112.2.2 kent splchanged = 1; 1126 1.112.2.2 kent if (pil->pil_level == IPL_SERIAL) { 1127 1.112.2.2 kent s = splserial(); 1128 1.112.2.2 kent } else if (pil->pil_level == IPL_HIGH) { 1129 1.112.2.2 kent s = splhigh(); 1130 1.112.2.2 kent } else if (pil->pil_level == IPL_CLOCK) { 1131 1.112.2.2 kent s = splclock(); 1132 1.112.2.2 kent } else if (pil->pil_level == IPL_AUDIO) { 1133 1.112.2.2 kent s = splaudio(); 1134 1.112.2.2 kent } else if (pil->pil_level == IPL_VM) { 1135 1.112.2.2 kent s = splvm(); 1136 1.112.2.2 kent } else if (pil->pil_level == IPL_TTY) { 1137 1.112.2.2 kent s = spltty(); 1138 1.112.2.2 kent } else if (pil->pil_level == IPL_SOFTSERIAL) { 1139 1.112.2.2 kent s = splsoftserial(); 1140 1.112.2.2 kent } else if (pil->pil_level == IPL_NET) { 1141 1.112.2.2 kent s = splnet(); 1142 1.112.2.2 kent } else { 1143 1.112.2.2 kent s = 0; /* XXX: gcc */ 1144 1.112.2.2 kent splchanged = 0; 1145 1.112.2.2 kent /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1146 1.112.2.2 kent } 1147 1.112.2.2 kent 1148 1.112.2.2 kent val = (*pil->pil_func)(pil->pil_arg); 1149 1.112.2.2 kent 1150 1.112.2.2 kent if (splchanged != 0) { 1151 1.112.2.2 kent splx(s); 1152 1.112.2.2 kent } 1153 1.112.2.2 kent 1154 1.112.2.2 kent retval = retval == 1 ? 1 : 1155 1.112.2.2 kent retval == 0 ? val : val != 0 ? val : retval; 1156 1.112.2.2 kent } 1157 1.112.2.2 kent 1158 1.112.2.2 kent return retval; 1159 1.112.2.2 kent } 1160 1.112.2.2 kent 1161 1.112.2.2 kent static void 1162 1.112.2.2 kent pci113x_insert(arg) 1163 1.112.2.2 kent void *arg; 1164 1.112.2.2 kent { 1165 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1166 1.112.2.2 kent u_int32_t sockevent, sockstate; 1167 1.112.2.2 kent 1168 1.112.2.2 kent if (!(sc->sc_flags & CBB_INSERTING)) { 1169 1.112.2.2 kent /* We add a card only under inserting state. */ 1170 1.112.2.2 kent return; 1171 1.112.2.2 kent } 1172 1.112.2.2 kent sc->sc_flags &= ~CBB_INSERTING; 1173 1.112.2.2 kent 1174 1.112.2.2 kent sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1175 1.112.2.2 kent CB_SOCKET_EVENT); 1176 1.112.2.2 kent sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1177 1.112.2.2 kent CB_SOCKET_STAT); 1178 1.112.2.2 kent 1179 1.112.2.2 kent if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1180 1.112.2.2 kent DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1181 1.112.2.2 kent DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1182 1.112.2.2 kent sc->sc_flags |= CBB_CARDEXIST; 1183 1.112.2.2 kent /* call pccard interrupt handler here */ 1184 1.112.2.2 kent if (sockstate & CB_SOCKET_STAT_16BIT) { 1185 1.112.2.2 kent /* 16-bit card found */ 1186 1.112.2.2 kent /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1187 1.112.2.2 kent cardslot_event_throw(sc->sc_csc, 1188 1.112.2.2 kent CARDSLOT_EVENT_INSERTION_16); 1189 1.112.2.2 kent } else if (sockstate & CB_SOCKET_STAT_CB) { 1190 1.112.2.2 kent /* cardbus card found */ 1191 1.112.2.2 kent /* cardbus_attach_card(sc->sc_csc); */ 1192 1.112.2.2 kent cardslot_event_throw(sc->sc_csc, 1193 1.112.2.2 kent CARDSLOT_EVENT_INSERTION_CB); 1194 1.112.2.2 kent } else { 1195 1.112.2.2 kent /* who are you? */ 1196 1.112.2.2 kent } 1197 1.112.2.2 kent } else { 1198 1.112.2.2 kent callout_reset(&sc->sc_insert_ch, hz / 10, 1199 1.112.2.2 kent pci113x_insert, sc); 1200 1.112.2.2 kent } 1201 1.112.2.2 kent } 1202 1.112.2.2 kent 1203 1.112.2.2 kent #define PCCBB_PCMCIA_OFFSET 0x800 1204 1.112.2.2 kent static u_int8_t 1205 1.112.2.2 kent pccbb_pcmcia_read(ph, reg) 1206 1.112.2.2 kent struct pcic_handle *ph; 1207 1.112.2.2 kent int reg; 1208 1.112.2.2 kent { 1209 1.112.2.2 kent bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1210 1.112.2.2 kent PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1211 1.112.2.2 kent 1212 1.112.2.2 kent return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1213 1.112.2.2 kent PCCBB_PCMCIA_OFFSET + reg); 1214 1.112.2.2 kent } 1215 1.112.2.2 kent 1216 1.112.2.2 kent static void 1217 1.112.2.2 kent pccbb_pcmcia_write(ph, reg, val) 1218 1.112.2.2 kent struct pcic_handle *ph; 1219 1.112.2.2 kent int reg; 1220 1.112.2.2 kent u_int8_t val; 1221 1.112.2.2 kent { 1222 1.112.2.2 kent bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1223 1.112.2.2 kent val); 1224 1.112.2.2 kent 1225 1.112.2.2 kent bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1226 1.112.2.2 kent PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1227 1.112.2.2 kent } 1228 1.112.2.2 kent 1229 1.112.2.2 kent /* 1230 1.112.2.2 kent * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1231 1.112.2.2 kent */ 1232 1.112.2.2 kent STATIC int 1233 1.112.2.2 kent pccbb_ctrl(ct, command) 1234 1.112.2.2 kent cardbus_chipset_tag_t ct; 1235 1.112.2.2 kent int command; 1236 1.112.2.2 kent { 1237 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1238 1.112.2.2 kent 1239 1.112.2.2 kent switch (command) { 1240 1.112.2.2 kent case CARDBUS_CD: 1241 1.112.2.2 kent if (2 == pccbb_detect_card(sc)) { 1242 1.112.2.2 kent int retval = 0; 1243 1.112.2.2 kent int status = cb_detect_voltage(sc); 1244 1.112.2.2 kent if (PCCARD_VCC_5V & status) { 1245 1.112.2.2 kent retval |= CARDBUS_5V_CARD; 1246 1.112.2.2 kent } 1247 1.112.2.2 kent if (PCCARD_VCC_3V & status) { 1248 1.112.2.2 kent retval |= CARDBUS_3V_CARD; 1249 1.112.2.2 kent } 1250 1.112.2.2 kent if (PCCARD_VCC_XV & status) { 1251 1.112.2.2 kent retval |= CARDBUS_XV_CARD; 1252 1.112.2.2 kent } 1253 1.112.2.2 kent if (PCCARD_VCC_YV & status) { 1254 1.112.2.2 kent retval |= CARDBUS_YV_CARD; 1255 1.112.2.2 kent } 1256 1.112.2.2 kent return retval; 1257 1.112.2.2 kent } else { 1258 1.112.2.2 kent return 0; 1259 1.112.2.2 kent } 1260 1.112.2.2 kent case CARDBUS_RESET: 1261 1.112.2.2 kent return cb_reset(sc); 1262 1.112.2.2 kent case CARDBUS_IO_ENABLE: /* fallthrough */ 1263 1.112.2.2 kent case CARDBUS_IO_DISABLE: /* fallthrough */ 1264 1.112.2.2 kent case CARDBUS_MEM_ENABLE: /* fallthrough */ 1265 1.112.2.2 kent case CARDBUS_MEM_DISABLE: /* fallthrough */ 1266 1.112.2.2 kent case CARDBUS_BM_ENABLE: /* fallthrough */ 1267 1.112.2.2 kent case CARDBUS_BM_DISABLE: /* fallthrough */ 1268 1.112.2.2 kent /* XXX: I think we don't need to call this function below. */ 1269 1.112.2.2 kent return pccbb_cardenable(sc, command); 1270 1.112.2.2 kent } 1271 1.112.2.2 kent 1272 1.112.2.2 kent return 0; 1273 1.112.2.2 kent } 1274 1.112.2.2 kent 1275 1.112.2.2 kent /* 1276 1.112.2.2 kent * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1277 1.112.2.2 kent * This function returns true when it succeeds and returns false when 1278 1.112.2.2 kent * it fails. 1279 1.112.2.2 kent */ 1280 1.112.2.2 kent STATIC int 1281 1.112.2.2 kent pccbb_power(ct, command) 1282 1.112.2.2 kent cardbus_chipset_tag_t ct; 1283 1.112.2.2 kent int command; 1284 1.112.2.2 kent { 1285 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1286 1.112.2.2 kent u_int32_t status, sock_ctrl, reg_ctrl; 1287 1.112.2.2 kent bus_space_tag_t memt = sc->sc_base_memt; 1288 1.112.2.2 kent bus_space_handle_t memh = sc->sc_base_memh; 1289 1.112.2.2 kent int on = 0, pwrcycle; 1290 1.112.2.2 kent 1291 1.112.2.2 kent DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1292 1.112.2.2 kent (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1293 1.112.2.2 kent (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1294 1.112.2.2 kent (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1295 1.112.2.2 kent (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1296 1.112.2.2 kent (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1297 1.112.2.2 kent (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1298 1.112.2.2 kent "UNKNOWN", 1299 1.112.2.2 kent (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1300 1.112.2.2 kent (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1301 1.112.2.2 kent (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1302 1.112.2.2 kent (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1303 1.112.2.2 kent "UNKNOWN", command)); 1304 1.112.2.2 kent 1305 1.112.2.2 kent status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1306 1.112.2.2 kent sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1307 1.112.2.2 kent 1308 1.112.2.2 kent switch (command & CARDBUS_VCCMASK) { 1309 1.112.2.2 kent case CARDBUS_VCC_UC: 1310 1.112.2.2 kent break; 1311 1.112.2.2 kent case CARDBUS_VCC_5V: 1312 1.112.2.2 kent on++; 1313 1.112.2.2 kent if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1314 1.112.2.2 kent sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1315 1.112.2.2 kent sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1316 1.112.2.2 kent } else { 1317 1.112.2.2 kent printf("%s: BAD voltage request: no 5 V card\n", 1318 1.112.2.2 kent sc->sc_dev.dv_xname); 1319 1.112.2.2 kent return 0; 1320 1.112.2.2 kent } 1321 1.112.2.2 kent break; 1322 1.112.2.2 kent case CARDBUS_VCC_3V: 1323 1.112.2.2 kent on++; 1324 1.112.2.2 kent if (CB_SOCKET_STAT_3VCARD & status) { 1325 1.112.2.2 kent sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1326 1.112.2.2 kent sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1327 1.112.2.2 kent } else { 1328 1.112.2.2 kent printf("%s: BAD voltage request: no 3.3 V card\n", 1329 1.112.2.2 kent sc->sc_dev.dv_xname); 1330 1.112.2.2 kent return 0; 1331 1.112.2.2 kent } 1332 1.112.2.2 kent break; 1333 1.112.2.2 kent case CARDBUS_VCC_0V: 1334 1.112.2.2 kent sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1335 1.112.2.2 kent break; 1336 1.112.2.2 kent default: 1337 1.112.2.2 kent return 0; /* power NEVER changed */ 1338 1.112.2.2 kent } 1339 1.112.2.2 kent 1340 1.112.2.2 kent switch (command & CARDBUS_VPPMASK) { 1341 1.112.2.2 kent case CARDBUS_VPP_UC: 1342 1.112.2.2 kent break; 1343 1.112.2.2 kent case CARDBUS_VPP_0V: 1344 1.112.2.2 kent sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1345 1.112.2.2 kent break; 1346 1.112.2.2 kent case CARDBUS_VPP_VCC: 1347 1.112.2.2 kent sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1348 1.112.2.2 kent sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1349 1.112.2.2 kent break; 1350 1.112.2.2 kent case CARDBUS_VPP_12V: 1351 1.112.2.2 kent sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1352 1.112.2.2 kent sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1353 1.112.2.2 kent break; 1354 1.112.2.2 kent } 1355 1.112.2.2 kent 1356 1.112.2.2 kent pwrcycle = sc->sc_pwrcycle; 1357 1.112.2.2 kent 1358 1.112.2.2 kent #if 0 1359 1.112.2.2 kent DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1360 1.112.2.2 kent #endif 1361 1.112.2.2 kent bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1362 1.112.2.2 kent 1363 1.112.2.2 kent if (on) { 1364 1.112.2.2 kent int s, error = 0; 1365 1.112.2.2 kent struct timeval before, after, diff; 1366 1.112.2.2 kent 1367 1.112.2.2 kent microtime(&before); 1368 1.112.2.2 kent s = splbio(); 1369 1.112.2.2 kent while (pwrcycle == sc->sc_pwrcycle) { 1370 1.112.2.2 kent /* 1371 1.112.2.2 kent * XXX: Set timeout to 200ms because power cycle event 1372 1.112.2.2 kent * will be never happen when attaching a 16-bit card. 1373 1.112.2.2 kent */ 1374 1.112.2.2 kent if ((error = tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1375 1.112.2.2 kent hz / 5)) == EWOULDBLOCK) 1376 1.112.2.2 kent break; 1377 1.112.2.2 kent } 1378 1.112.2.2 kent splx(s); 1379 1.112.2.2 kent microtime(&after); 1380 1.112.2.2 kent timersub(&after, &before, &diff); 1381 1.112.2.2 kent printf("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1382 1.112.2.2 kent error == EWOULDBLOCK ? " too long" : "", 1383 1.112.2.2 kent diff.tv_sec, diff.tv_usec); 1384 1.112.2.2 kent } 1385 1.112.2.2 kent 1386 1.112.2.2 kent status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1387 1.112.2.2 kent 1388 1.112.2.2 kent if (on) { 1389 1.112.2.2 kent if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1390 1.112.2.2 kent printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1391 1.112.2.2 kent } 1392 1.112.2.2 kent 1393 1.112.2.2 kent if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1394 1.112.2.2 kent printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1395 1.112.2.2 kent sc->sc_dev.dv_xname, sock_ctrl, status); 1396 1.112.2.2 kent printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1397 1.112.2.2 kent sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1398 1.112.2.2 kent sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1399 1.112.2.2 kent bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1400 1.112.2.2 kent status &= ~CB_SOCKET_STAT_BADVCC; 1401 1.112.2.2 kent bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1402 1.112.2.2 kent printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1403 1.112.2.2 kent CB_SOCKET_STAT)); 1404 1.112.2.2 kent return 0; 1405 1.112.2.2 kent } 1406 1.112.2.2 kent 1407 1.112.2.2 kent if (sc->sc_chipset == CB_TOPIC97) { 1408 1.112.2.2 kent reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1409 1.112.2.2 kent reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1410 1.112.2.2 kent if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1411 1.112.2.2 kent reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1412 1.112.2.2 kent else 1413 1.112.2.2 kent reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1414 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1415 1.112.2.2 kent } 1416 1.112.2.2 kent 1417 1.112.2.2 kent return 1; /* power changed correctly */ 1418 1.112.2.2 kent } 1419 1.112.2.2 kent 1420 1.112.2.2 kent #if defined CB_PCMCIA_POLL 1421 1.112.2.2 kent struct cb_poll_str { 1422 1.112.2.2 kent void *arg; 1423 1.112.2.2 kent int (*func)(void *); 1424 1.112.2.2 kent int level; 1425 1.112.2.2 kent pccard_chipset_tag_t ct; 1426 1.112.2.2 kent int count; 1427 1.112.2.2 kent struct callout poll_ch; 1428 1.112.2.2 kent }; 1429 1.112.2.2 kent 1430 1.112.2.2 kent static struct cb_poll_str cb_poll[10]; 1431 1.112.2.2 kent static int cb_poll_n = 0; 1432 1.112.2.2 kent 1433 1.112.2.2 kent static void cb_pcmcia_poll(void *arg); 1434 1.112.2.2 kent 1435 1.112.2.2 kent static void 1436 1.112.2.2 kent cb_pcmcia_poll(arg) 1437 1.112.2.2 kent void *arg; 1438 1.112.2.2 kent { 1439 1.112.2.2 kent struct cb_poll_str *poll = arg; 1440 1.112.2.2 kent struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1441 1.112.2.2 kent struct pccbb_softc *sc = psc->cpc_parent; 1442 1.112.2.2 kent int s; 1443 1.112.2.2 kent u_int32_t spsr; /* socket present-state reg */ 1444 1.112.2.2 kent 1445 1.112.2.2 kent callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1446 1.112.2.2 kent switch (poll->level) { 1447 1.112.2.2 kent case IPL_NET: 1448 1.112.2.2 kent s = splnet(); 1449 1.112.2.2 kent break; 1450 1.112.2.2 kent case IPL_BIO: 1451 1.112.2.2 kent s = splbio(); 1452 1.112.2.2 kent break; 1453 1.112.2.2 kent case IPL_TTY: /* fallthrough */ 1454 1.112.2.2 kent default: 1455 1.112.2.2 kent s = spltty(); 1456 1.112.2.2 kent break; 1457 1.112.2.2 kent } 1458 1.112.2.2 kent 1459 1.112.2.2 kent spsr = 1460 1.112.2.2 kent bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1461 1.112.2.2 kent CB_SOCKET_STAT); 1462 1.112.2.2 kent 1463 1.112.2.2 kent #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1464 1.112.2.2 kent if (!(spsr & 0x40)) { /* CINT low */ 1465 1.112.2.2 kent #else 1466 1.112.2.2 kent if (1) { 1467 1.112.2.2 kent #endif 1468 1.112.2.2 kent if ((*poll->func) (poll->arg) == 1) { 1469 1.112.2.2 kent ++poll->count; 1470 1.112.2.2 kent printf("intr: reported from poller, 0x%x\n", spsr); 1471 1.112.2.2 kent #if defined LEVEL2 1472 1.112.2.2 kent } else { 1473 1.112.2.2 kent printf("intr: miss! 0x%x\n", spsr); 1474 1.112.2.2 kent #endif 1475 1.112.2.2 kent } 1476 1.112.2.2 kent } 1477 1.112.2.2 kent splx(s); 1478 1.112.2.2 kent } 1479 1.112.2.2 kent #endif /* defined CB_PCMCIA_POLL */ 1480 1.112.2.2 kent 1481 1.112.2.2 kent /* 1482 1.112.2.2 kent * static int pccbb_detect_card(struct pccbb_softc *sc) 1483 1.112.2.2 kent * return value: 0 if no card exists. 1484 1.112.2.2 kent * 1 if 16-bit card exists. 1485 1.112.2.2 kent * 2 if cardbus card exists. 1486 1.112.2.2 kent */ 1487 1.112.2.2 kent static int 1488 1.112.2.2 kent pccbb_detect_card(sc) 1489 1.112.2.2 kent struct pccbb_softc *sc; 1490 1.112.2.2 kent { 1491 1.112.2.2 kent bus_space_handle_t base_memh = sc->sc_base_memh; 1492 1.112.2.2 kent bus_space_tag_t base_memt = sc->sc_base_memt; 1493 1.112.2.2 kent u_int32_t sockstat = 1494 1.112.2.2 kent bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1495 1.112.2.2 kent int retval = 0; 1496 1.112.2.2 kent 1497 1.112.2.2 kent /* CD1 and CD2 asserted */ 1498 1.112.2.2 kent if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1499 1.112.2.2 kent /* card must be present */ 1500 1.112.2.2 kent if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1501 1.112.2.2 kent /* NOTACARD DEASSERTED */ 1502 1.112.2.2 kent if (CB_SOCKET_STAT_CB & sockstat) { 1503 1.112.2.2 kent /* CardBus mode */ 1504 1.112.2.2 kent retval = 2; 1505 1.112.2.2 kent } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1506 1.112.2.2 kent /* 16-bit mode */ 1507 1.112.2.2 kent retval = 1; 1508 1.112.2.2 kent } 1509 1.112.2.2 kent } 1510 1.112.2.2 kent } 1511 1.112.2.2 kent return retval; 1512 1.112.2.2 kent } 1513 1.112.2.2 kent 1514 1.112.2.2 kent /* 1515 1.112.2.2 kent * STATIC int cb_reset(struct pccbb_softc *sc) 1516 1.112.2.2 kent * This function resets CardBus card. 1517 1.112.2.2 kent */ 1518 1.112.2.2 kent STATIC int 1519 1.112.2.2 kent cb_reset(sc) 1520 1.112.2.2 kent struct pccbb_softc *sc; 1521 1.112.2.2 kent { 1522 1.112.2.2 kent /* 1523 1.112.2.2 kent * Reset Assert at least 20 ms 1524 1.112.2.2 kent * Some machines request longer duration. 1525 1.112.2.2 kent */ 1526 1.112.2.2 kent int reset_duration = 1527 1.112.2.2 kent (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1528 1.112.2.2 kent u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1529 1.112.2.2 kent 1530 1.112.2.2 kent /* Reset bit Assert (bit 6 at 0x3E) */ 1531 1.112.2.2 kent bcr |= CB_BCR_RESET_ENABLE; 1532 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1533 1.112.2.2 kent DELAY_MS(reset_duration, sc); 1534 1.112.2.2 kent 1535 1.112.2.2 kent if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1536 1.112.2.2 kent /* Reset bit Deassert (bit 6 at 0x3E) */ 1537 1.112.2.2 kent bcr &= ~CB_BCR_RESET_ENABLE; 1538 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1539 1.112.2.2 kent DELAY_MS(reset_duration, sc); 1540 1.112.2.2 kent } 1541 1.112.2.2 kent /* No card found on the slot. Keep Reset. */ 1542 1.112.2.2 kent return 1; 1543 1.112.2.2 kent } 1544 1.112.2.2 kent 1545 1.112.2.2 kent /* 1546 1.112.2.2 kent * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1547 1.112.2.2 kent * This function detect card Voltage. 1548 1.112.2.2 kent */ 1549 1.112.2.2 kent STATIC int 1550 1.112.2.2 kent cb_detect_voltage(sc) 1551 1.112.2.2 kent struct pccbb_softc *sc; 1552 1.112.2.2 kent { 1553 1.112.2.2 kent u_int32_t psr; /* socket present-state reg */ 1554 1.112.2.2 kent bus_space_tag_t iot = sc->sc_base_memt; 1555 1.112.2.2 kent bus_space_handle_t ioh = sc->sc_base_memh; 1556 1.112.2.2 kent int vol = PCCARD_VCC_UKN; /* set 0 */ 1557 1.112.2.2 kent 1558 1.112.2.2 kent psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1559 1.112.2.2 kent 1560 1.112.2.2 kent if (0x400u & psr) { 1561 1.112.2.2 kent vol |= PCCARD_VCC_5V; 1562 1.112.2.2 kent } 1563 1.112.2.2 kent if (0x800u & psr) { 1564 1.112.2.2 kent vol |= PCCARD_VCC_3V; 1565 1.112.2.2 kent } 1566 1.112.2.2 kent 1567 1.112.2.2 kent return vol; 1568 1.112.2.2 kent } 1569 1.112.2.2 kent 1570 1.112.2.2 kent STATIC int 1571 1.112.2.2 kent cbbprint(aux, pcic) 1572 1.112.2.2 kent void *aux; 1573 1.112.2.2 kent const char *pcic; 1574 1.112.2.2 kent { 1575 1.112.2.2 kent /* 1576 1.112.2.2 kent struct cbslot_attach_args *cba = aux; 1577 1.112.2.2 kent 1578 1.112.2.2 kent if (cba->cba_slot >= 0) { 1579 1.112.2.2 kent aprint_normal(" slot %d", cba->cba_slot); 1580 1.112.2.2 kent } 1581 1.112.2.2 kent */ 1582 1.112.2.2 kent return UNCONF; 1583 1.112.2.2 kent } 1584 1.112.2.2 kent 1585 1.112.2.2 kent /* 1586 1.112.2.2 kent * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1587 1.112.2.2 kent * This function enables and disables the card 1588 1.112.2.2 kent */ 1589 1.112.2.2 kent STATIC int 1590 1.112.2.2 kent pccbb_cardenable(sc, function) 1591 1.112.2.2 kent struct pccbb_softc *sc; 1592 1.112.2.2 kent int function; 1593 1.112.2.2 kent { 1594 1.112.2.2 kent u_int32_t command = 1595 1.112.2.2 kent pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1596 1.112.2.2 kent 1597 1.112.2.2 kent DPRINTF(("pccbb_cardenable:")); 1598 1.112.2.2 kent switch (function) { 1599 1.112.2.2 kent case CARDBUS_IO_ENABLE: 1600 1.112.2.2 kent command |= PCI_COMMAND_IO_ENABLE; 1601 1.112.2.2 kent break; 1602 1.112.2.2 kent case CARDBUS_IO_DISABLE: 1603 1.112.2.2 kent command &= ~PCI_COMMAND_IO_ENABLE; 1604 1.112.2.2 kent break; 1605 1.112.2.2 kent case CARDBUS_MEM_ENABLE: 1606 1.112.2.2 kent command |= PCI_COMMAND_MEM_ENABLE; 1607 1.112.2.2 kent break; 1608 1.112.2.2 kent case CARDBUS_MEM_DISABLE: 1609 1.112.2.2 kent command &= ~PCI_COMMAND_MEM_ENABLE; 1610 1.112.2.2 kent break; 1611 1.112.2.2 kent case CARDBUS_BM_ENABLE: 1612 1.112.2.2 kent command |= PCI_COMMAND_MASTER_ENABLE; 1613 1.112.2.2 kent break; 1614 1.112.2.2 kent case CARDBUS_BM_DISABLE: 1615 1.112.2.2 kent command &= ~PCI_COMMAND_MASTER_ENABLE; 1616 1.112.2.2 kent break; 1617 1.112.2.2 kent default: 1618 1.112.2.2 kent return 0; 1619 1.112.2.2 kent } 1620 1.112.2.2 kent 1621 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1622 1.112.2.2 kent DPRINTF((" command reg 0x%x\n", command)); 1623 1.112.2.2 kent return 1; 1624 1.112.2.2 kent } 1625 1.112.2.2 kent 1626 1.112.2.2 kent #if !rbus 1627 1.112.2.2 kent /* 1628 1.112.2.2 kent * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1629 1.112.2.2 kent */ 1630 1.112.2.2 kent static int 1631 1.112.2.2 kent pccbb_io_open(ct, win, start, end) 1632 1.112.2.2 kent cardbus_chipset_tag_t ct; 1633 1.112.2.2 kent int win; 1634 1.112.2.2 kent u_int32_t start, end; 1635 1.112.2.2 kent { 1636 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1637 1.112.2.2 kent int basereg; 1638 1.112.2.2 kent int limitreg; 1639 1.112.2.2 kent 1640 1.112.2.2 kent if ((win < 0) || (win > 2)) { 1641 1.112.2.2 kent #if defined DIAGNOSTIC 1642 1.112.2.2 kent printf("cardbus_io_open: window out of range %d\n", win); 1643 1.112.2.2 kent #endif 1644 1.112.2.2 kent return 0; 1645 1.112.2.2 kent } 1646 1.112.2.2 kent 1647 1.112.2.2 kent basereg = win * 8 + 0x2c; 1648 1.112.2.2 kent limitreg = win * 8 + 0x30; 1649 1.112.2.2 kent 1650 1.112.2.2 kent DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1651 1.112.2.2 kent start, basereg, end, limitreg)); 1652 1.112.2.2 kent 1653 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1654 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1655 1.112.2.2 kent return 1; 1656 1.112.2.2 kent } 1657 1.112.2.2 kent 1658 1.112.2.2 kent /* 1659 1.112.2.2 kent * int pccbb_io_close(cardbus_chipset_tag_t, int) 1660 1.112.2.2 kent */ 1661 1.112.2.2 kent static int 1662 1.112.2.2 kent pccbb_io_close(ct, win) 1663 1.112.2.2 kent cardbus_chipset_tag_t ct; 1664 1.112.2.2 kent int win; 1665 1.112.2.2 kent { 1666 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1667 1.112.2.2 kent int basereg; 1668 1.112.2.2 kent int limitreg; 1669 1.112.2.2 kent 1670 1.112.2.2 kent if ((win < 0) || (win > 2)) { 1671 1.112.2.2 kent #if defined DIAGNOSTIC 1672 1.112.2.2 kent printf("cardbus_io_close: window out of range %d\n", win); 1673 1.112.2.2 kent #endif 1674 1.112.2.2 kent return 0; 1675 1.112.2.2 kent } 1676 1.112.2.2 kent 1677 1.112.2.2 kent basereg = win * 8 + 0x2c; 1678 1.112.2.2 kent limitreg = win * 8 + 0x30; 1679 1.112.2.2 kent 1680 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1681 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1682 1.112.2.2 kent return 1; 1683 1.112.2.2 kent } 1684 1.112.2.2 kent 1685 1.112.2.2 kent /* 1686 1.112.2.2 kent * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1687 1.112.2.2 kent */ 1688 1.112.2.2 kent static int 1689 1.112.2.2 kent pccbb_mem_open(ct, win, start, end) 1690 1.112.2.2 kent cardbus_chipset_tag_t ct; 1691 1.112.2.2 kent int win; 1692 1.112.2.2 kent u_int32_t start, end; 1693 1.112.2.2 kent { 1694 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1695 1.112.2.2 kent int basereg; 1696 1.112.2.2 kent int limitreg; 1697 1.112.2.2 kent 1698 1.112.2.2 kent if ((win < 0) || (win > 2)) { 1699 1.112.2.2 kent #if defined DIAGNOSTIC 1700 1.112.2.2 kent printf("cardbus_mem_open: window out of range %d\n", win); 1701 1.112.2.2 kent #endif 1702 1.112.2.2 kent return 0; 1703 1.112.2.2 kent } 1704 1.112.2.2 kent 1705 1.112.2.2 kent basereg = win * 8 + 0x1c; 1706 1.112.2.2 kent limitreg = win * 8 + 0x20; 1707 1.112.2.2 kent 1708 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1709 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1710 1.112.2.2 kent return 1; 1711 1.112.2.2 kent } 1712 1.112.2.2 kent 1713 1.112.2.2 kent /* 1714 1.112.2.2 kent * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1715 1.112.2.2 kent */ 1716 1.112.2.2 kent static int 1717 1.112.2.2 kent pccbb_mem_close(ct, win) 1718 1.112.2.2 kent cardbus_chipset_tag_t ct; 1719 1.112.2.2 kent int win; 1720 1.112.2.2 kent { 1721 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1722 1.112.2.2 kent int basereg; 1723 1.112.2.2 kent int limitreg; 1724 1.112.2.2 kent 1725 1.112.2.2 kent if ((win < 0) || (win > 2)) { 1726 1.112.2.2 kent #if defined DIAGNOSTIC 1727 1.112.2.2 kent printf("cardbus_mem_close: window out of range %d\n", win); 1728 1.112.2.2 kent #endif 1729 1.112.2.2 kent return 0; 1730 1.112.2.2 kent } 1731 1.112.2.2 kent 1732 1.112.2.2 kent basereg = win * 8 + 0x1c; 1733 1.112.2.2 kent limitreg = win * 8 + 0x20; 1734 1.112.2.2 kent 1735 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1736 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1737 1.112.2.2 kent return 1; 1738 1.112.2.2 kent } 1739 1.112.2.2 kent #endif 1740 1.112.2.2 kent 1741 1.112.2.2 kent /* 1742 1.112.2.2 kent * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1743 1.112.2.2 kent * int irq, 1744 1.112.2.2 kent * int level, 1745 1.112.2.2 kent * int (* func)(void *), 1746 1.112.2.2 kent * void *arg) 1747 1.112.2.2 kent * 1748 1.112.2.2 kent * This function registers an interrupt handler at the bridge, in 1749 1.112.2.2 kent * order not to call the interrupt handlers of child devices when 1750 1.112.2.2 kent * a card-deletion interrupt occurs. 1751 1.112.2.2 kent * 1752 1.112.2.2 kent * The arguments irq and level are not used. 1753 1.112.2.2 kent */ 1754 1.112.2.2 kent static void * 1755 1.112.2.2 kent pccbb_cb_intr_establish(ct, irq, level, func, arg) 1756 1.112.2.2 kent cardbus_chipset_tag_t ct; 1757 1.112.2.2 kent int irq, level; 1758 1.112.2.2 kent int (*func)(void *); 1759 1.112.2.2 kent void *arg; 1760 1.112.2.2 kent { 1761 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1762 1.112.2.2 kent 1763 1.112.2.2 kent return pccbb_intr_establish(sc, irq, level, func, arg); 1764 1.112.2.2 kent } 1765 1.112.2.2 kent 1766 1.112.2.2 kent 1767 1.112.2.2 kent /* 1768 1.112.2.2 kent * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1769 1.112.2.2 kent * void *ih) 1770 1.112.2.2 kent * 1771 1.112.2.2 kent * This function removes an interrupt handler pointed by ih. 1772 1.112.2.2 kent */ 1773 1.112.2.2 kent static void 1774 1.112.2.2 kent pccbb_cb_intr_disestablish(ct, ih) 1775 1.112.2.2 kent cardbus_chipset_tag_t ct; 1776 1.112.2.2 kent void *ih; 1777 1.112.2.2 kent { 1778 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1779 1.112.2.2 kent 1780 1.112.2.2 kent pccbb_intr_disestablish(sc, ih); 1781 1.112.2.2 kent } 1782 1.112.2.2 kent 1783 1.112.2.2 kent 1784 1.112.2.2 kent void 1785 1.112.2.2 kent pccbb_intr_route(sc) 1786 1.112.2.2 kent struct pccbb_softc *sc; 1787 1.112.2.2 kent { 1788 1.112.2.2 kent pcireg_t reg; 1789 1.112.2.2 kent 1790 1.112.2.2 kent /* initialize bridge intr routing */ 1791 1.112.2.2 kent reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1792 1.112.2.2 kent reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1793 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1794 1.112.2.2 kent 1795 1.112.2.2 kent switch (sc->sc_chipset) { 1796 1.112.2.2 kent case CB_TI113X: 1797 1.112.2.2 kent reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1798 1.112.2.2 kent /* functional intr enabled */ 1799 1.112.2.2 kent reg |= PCI113X_CBCTRL_PCI_INTR; 1800 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1801 1.112.2.2 kent break; 1802 1.112.2.2 kent default: 1803 1.112.2.2 kent break; 1804 1.112.2.2 kent } 1805 1.112.2.2 kent } 1806 1.112.2.2 kent 1807 1.112.2.2 kent /* 1808 1.112.2.2 kent * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1809 1.112.2.2 kent * int irq, 1810 1.112.2.2 kent * int level, 1811 1.112.2.2 kent * int (* func)(void *), 1812 1.112.2.2 kent * void *arg) 1813 1.112.2.2 kent * 1814 1.112.2.2 kent * This function registers an interrupt handler at the bridge, in 1815 1.112.2.2 kent * order not to call the interrupt handlers of child devices when 1816 1.112.2.2 kent * a card-deletion interrupt occurs. 1817 1.112.2.2 kent * 1818 1.112.2.2 kent * The arguments irq is not used because pccbb selects intr vector. 1819 1.112.2.2 kent */ 1820 1.112.2.2 kent static void * 1821 1.112.2.2 kent pccbb_intr_establish(sc, irq, level, func, arg) 1822 1.112.2.2 kent struct pccbb_softc *sc; 1823 1.112.2.2 kent int irq, level; 1824 1.112.2.2 kent int (*func)(void *); 1825 1.112.2.2 kent void *arg; 1826 1.112.2.2 kent { 1827 1.112.2.2 kent struct pccbb_intrhand_list *pil, *newpil; 1828 1.112.2.2 kent 1829 1.112.2.2 kent DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1830 1.112.2.2 kent 1831 1.112.2.2 kent if (LIST_EMPTY(&sc->sc_pil)) { 1832 1.112.2.2 kent pccbb_intr_route(sc); 1833 1.112.2.2 kent } 1834 1.112.2.2 kent 1835 1.112.2.2 kent /* 1836 1.112.2.2 kent * Allocate a room for interrupt handler structure. 1837 1.112.2.2 kent */ 1838 1.112.2.2 kent if (NULL == (newpil = 1839 1.112.2.2 kent (struct pccbb_intrhand_list *)malloc(sizeof(struct 1840 1.112.2.2 kent pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1841 1.112.2.2 kent return NULL; 1842 1.112.2.2 kent } 1843 1.112.2.2 kent 1844 1.112.2.2 kent newpil->pil_func = func; 1845 1.112.2.2 kent newpil->pil_arg = arg; 1846 1.112.2.2 kent newpil->pil_level = level; 1847 1.112.2.2 kent 1848 1.112.2.2 kent if (LIST_EMPTY(&sc->sc_pil)) { 1849 1.112.2.2 kent LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1850 1.112.2.2 kent } else { 1851 1.112.2.2 kent for (pil = LIST_FIRST(&sc->sc_pil); 1852 1.112.2.2 kent LIST_NEXT(pil, pil_next) != NULL; 1853 1.112.2.2 kent pil = LIST_NEXT(pil, pil_next)); 1854 1.112.2.2 kent LIST_INSERT_AFTER(pil, newpil, pil_next); 1855 1.112.2.2 kent } 1856 1.112.2.2 kent 1857 1.112.2.2 kent DPRINTF(("pccbb_intr_establish add pil. %p\n", 1858 1.112.2.2 kent LIST_FIRST(&sc->sc_pil))); 1859 1.112.2.2 kent 1860 1.112.2.2 kent return newpil; 1861 1.112.2.2 kent } 1862 1.112.2.2 kent 1863 1.112.2.2 kent /* 1864 1.112.2.2 kent * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1865 1.112.2.2 kent * void *ih) 1866 1.112.2.2 kent * 1867 1.112.2.2 kent * This function removes an interrupt handler pointed by ih. ih 1868 1.112.2.2 kent * should be the value returned by cardbus_intr_establish() or 1869 1.112.2.2 kent * NULL. 1870 1.112.2.2 kent * 1871 1.112.2.2 kent * When ih is NULL, this function will do nothing. 1872 1.112.2.2 kent */ 1873 1.112.2.2 kent static void 1874 1.112.2.2 kent pccbb_intr_disestablish(sc, ih) 1875 1.112.2.2 kent struct pccbb_softc *sc; 1876 1.112.2.2 kent void *ih; 1877 1.112.2.2 kent { 1878 1.112.2.2 kent struct pccbb_intrhand_list *pil; 1879 1.112.2.2 kent pcireg_t reg; 1880 1.112.2.2 kent 1881 1.112.2.2 kent DPRINTF(("pccbb_intr_disestablish start. %p\n", 1882 1.112.2.2 kent LIST_FIRST(&sc->sc_pil))); 1883 1.112.2.2 kent 1884 1.112.2.2 kent if (ih == NULL) { 1885 1.112.2.2 kent /* intr handler is not set */ 1886 1.112.2.2 kent DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1887 1.112.2.2 kent return; 1888 1.112.2.2 kent } 1889 1.112.2.2 kent 1890 1.112.2.2 kent #ifdef DIAGNOSTIC 1891 1.112.2.2 kent for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1892 1.112.2.2 kent pil = LIST_NEXT(pil, pil_next)) { 1893 1.112.2.2 kent DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1894 1.112.2.2 kent if (pil == ih) { 1895 1.112.2.2 kent DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1896 1.112.2.2 kent break; 1897 1.112.2.2 kent } 1898 1.112.2.2 kent } 1899 1.112.2.2 kent if (pil == NULL) { 1900 1.112.2.2 kent panic("pccbb_intr_disestablish: %s cannot find pil %p", 1901 1.112.2.2 kent sc->sc_dev.dv_xname, ih); 1902 1.112.2.2 kent } 1903 1.112.2.2 kent #endif 1904 1.112.2.2 kent 1905 1.112.2.2 kent pil = (struct pccbb_intrhand_list *)ih; 1906 1.112.2.2 kent LIST_REMOVE(pil, pil_next); 1907 1.112.2.2 kent free(pil, M_DEVBUF); 1908 1.112.2.2 kent DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1909 1.112.2.2 kent 1910 1.112.2.2 kent if (LIST_EMPTY(&sc->sc_pil)) { 1911 1.112.2.2 kent /* No interrupt handlers */ 1912 1.112.2.2 kent 1913 1.112.2.2 kent DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1914 1.112.2.2 kent 1915 1.112.2.2 kent /* stop routing PCI intr */ 1916 1.112.2.2 kent reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1917 1.112.2.2 kent reg |= CB_BCR_INTR_IREQ_ENABLE; 1918 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1919 1.112.2.2 kent 1920 1.112.2.2 kent switch (sc->sc_chipset) { 1921 1.112.2.2 kent case CB_TI113X: 1922 1.112.2.2 kent reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1923 1.112.2.2 kent /* functional intr disabled */ 1924 1.112.2.2 kent reg &= ~PCI113X_CBCTRL_PCI_INTR; 1925 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1926 1.112.2.2 kent break; 1927 1.112.2.2 kent default: 1928 1.112.2.2 kent break; 1929 1.112.2.2 kent } 1930 1.112.2.2 kent } 1931 1.112.2.2 kent } 1932 1.112.2.2 kent 1933 1.112.2.2 kent #if defined SHOW_REGS 1934 1.112.2.2 kent static void 1935 1.112.2.2 kent cb_show_regs(pc, tag, memt, memh) 1936 1.112.2.2 kent pci_chipset_tag_t pc; 1937 1.112.2.2 kent pcitag_t tag; 1938 1.112.2.2 kent bus_space_tag_t memt; 1939 1.112.2.2 kent bus_space_handle_t memh; 1940 1.112.2.2 kent { 1941 1.112.2.2 kent int i; 1942 1.112.2.2 kent printf("PCI config regs:"); 1943 1.112.2.2 kent for (i = 0; i < 0x50; i += 4) { 1944 1.112.2.2 kent if (i % 16 == 0) { 1945 1.112.2.2 kent printf("\n 0x%02x:", i); 1946 1.112.2.2 kent } 1947 1.112.2.2 kent printf(" %08x", pci_conf_read(pc, tag, i)); 1948 1.112.2.2 kent } 1949 1.112.2.2 kent for (i = 0x80; i < 0xb0; i += 4) { 1950 1.112.2.2 kent if (i % 16 == 0) { 1951 1.112.2.2 kent printf("\n 0x%02x:", i); 1952 1.112.2.2 kent } 1953 1.112.2.2 kent printf(" %08x", pci_conf_read(pc, tag, i)); 1954 1.112.2.2 kent } 1955 1.112.2.2 kent 1956 1.112.2.2 kent if (memh == 0) { 1957 1.112.2.2 kent printf("\n"); 1958 1.112.2.2 kent return; 1959 1.112.2.2 kent } 1960 1.112.2.2 kent 1961 1.112.2.2 kent printf("\nsocket regs:"); 1962 1.112.2.2 kent for (i = 0; i <= 0x10; i += 0x04) { 1963 1.112.2.2 kent printf(" %08x", bus_space_read_4(memt, memh, i)); 1964 1.112.2.2 kent } 1965 1.112.2.2 kent printf("\nExCA regs:"); 1966 1.112.2.2 kent for (i = 0; i < 0x08; ++i) { 1967 1.112.2.2 kent printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1968 1.112.2.2 kent } 1969 1.112.2.2 kent printf("\n"); 1970 1.112.2.2 kent return; 1971 1.112.2.2 kent } 1972 1.112.2.2 kent #endif 1973 1.112.2.2 kent 1974 1.112.2.2 kent /* 1975 1.112.2.2 kent * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1976 1.112.2.2 kent * int busno, int devno, int function) 1977 1.112.2.2 kent * This is the function to make a tag to access config space of 1978 1.112.2.2 kent * a CardBus Card. It works same as pci_conf_read. 1979 1.112.2.2 kent */ 1980 1.112.2.2 kent static cardbustag_t 1981 1.112.2.2 kent pccbb_make_tag(cc, busno, devno, function) 1982 1.112.2.2 kent cardbus_chipset_tag_t cc; 1983 1.112.2.2 kent int busno, devno, function; 1984 1.112.2.2 kent { 1985 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1986 1.112.2.2 kent 1987 1.112.2.2 kent return pci_make_tag(sc->sc_pc, busno, devno, function); 1988 1.112.2.2 kent } 1989 1.112.2.2 kent 1990 1.112.2.2 kent static void 1991 1.112.2.2 kent pccbb_free_tag(cc, tag) 1992 1.112.2.2 kent cardbus_chipset_tag_t cc; 1993 1.112.2.2 kent cardbustag_t tag; 1994 1.112.2.2 kent { 1995 1.112.2.2 kent } 1996 1.112.2.2 kent 1997 1.112.2.2 kent /* 1998 1.112.2.2 kent * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1999 1.112.2.2 kent * cardbustag_t tag, int offset) 2000 1.112.2.2 kent * This is the function to read the config space of a CardBus Card. 2001 1.112.2.2 kent * It works same as pci_conf_read. 2002 1.112.2.2 kent */ 2003 1.112.2.2 kent static cardbusreg_t 2004 1.112.2.2 kent pccbb_conf_read(cc, tag, offset) 2005 1.112.2.2 kent cardbus_chipset_tag_t cc; 2006 1.112.2.2 kent cardbustag_t tag; 2007 1.112.2.2 kent int offset; /* register offset */ 2008 1.112.2.2 kent { 2009 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2010 1.112.2.2 kent 2011 1.112.2.2 kent return pci_conf_read(sc->sc_pc, tag, offset); 2012 1.112.2.2 kent } 2013 1.112.2.2 kent 2014 1.112.2.2 kent /* 2015 1.112.2.2 kent * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 2016 1.112.2.2 kent * int offs, cardbusreg_t val) 2017 1.112.2.2 kent * This is the function to write the config space of a CardBus Card. 2018 1.112.2.2 kent * It works same as pci_conf_write. 2019 1.112.2.2 kent */ 2020 1.112.2.2 kent static void 2021 1.112.2.2 kent pccbb_conf_write(cc, tag, reg, val) 2022 1.112.2.2 kent cardbus_chipset_tag_t cc; 2023 1.112.2.2 kent cardbustag_t tag; 2024 1.112.2.2 kent int reg; /* register offset */ 2025 1.112.2.2 kent cardbusreg_t val; 2026 1.112.2.2 kent { 2027 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2028 1.112.2.2 kent 2029 1.112.2.2 kent pci_conf_write(sc->sc_pc, tag, reg, val); 2030 1.112.2.2 kent } 2031 1.112.2.2 kent 2032 1.112.2.2 kent #if 0 2033 1.112.2.2 kent STATIC int 2034 1.112.2.2 kent pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2035 1.112.2.2 kent bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2036 1.112.2.2 kent int speed, int flags, 2037 1.112.2.2 kent bus_space_handle_t * iohp) 2038 1.112.2.2 kent #endif 2039 1.112.2.2 kent /* 2040 1.112.2.2 kent * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2041 1.112.2.2 kent * bus_addr_t start, bus_size_t size, 2042 1.112.2.2 kent * bus_size_t align, 2043 1.112.2.2 kent * struct pcmcia_io_handle *pcihp 2044 1.112.2.2 kent * 2045 1.112.2.2 kent * This function only allocates I/O region for pccard. This function 2046 1.112.2.2 kent * never maps the allocated region to pccard I/O area. 2047 1.112.2.2 kent * 2048 1.112.2.2 kent * XXX: The interface of this function is not very good, I believe. 2049 1.112.2.2 kent */ 2050 1.112.2.2 kent STATIC int 2051 1.112.2.2 kent pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2052 1.112.2.2 kent pcmcia_chipset_handle_t pch; 2053 1.112.2.2 kent bus_addr_t start; /* start address */ 2054 1.112.2.2 kent bus_size_t size; 2055 1.112.2.2 kent bus_size_t align; 2056 1.112.2.2 kent struct pcmcia_io_handle *pcihp; 2057 1.112.2.2 kent { 2058 1.112.2.2 kent struct pcic_handle *ph = (struct pcic_handle *)pch; 2059 1.112.2.2 kent bus_addr_t ioaddr; 2060 1.112.2.2 kent int flags = 0; 2061 1.112.2.2 kent bus_space_tag_t iot; 2062 1.112.2.2 kent bus_space_handle_t ioh; 2063 1.112.2.2 kent bus_addr_t mask; 2064 1.112.2.2 kent #if rbus 2065 1.112.2.2 kent rbus_tag_t rb; 2066 1.112.2.2 kent #endif 2067 1.112.2.2 kent if (align == 0) { 2068 1.112.2.2 kent align = size; /* XXX: funny??? */ 2069 1.112.2.2 kent } 2070 1.112.2.2 kent 2071 1.112.2.2 kent if (start != 0) { 2072 1.112.2.2 kent /* XXX: assume all card decode lower 10 bits by its hardware */ 2073 1.112.2.2 kent mask = 0x3ff; 2074 1.112.2.2 kent /* enforce to use only masked address */ 2075 1.112.2.2 kent start &= mask; 2076 1.112.2.2 kent } else { 2077 1.112.2.2 kent /* 2078 1.112.2.2 kent * calculate mask: 2079 1.112.2.2 kent * 1. get the most significant bit of size (call it msb). 2080 1.112.2.2 kent * 2. compare msb with the value of size. 2081 1.112.2.2 kent * 3. if size is larger, shift msb left once. 2082 1.112.2.2 kent * 4. obtain mask value to decrement msb. 2083 1.112.2.2 kent */ 2084 1.112.2.2 kent bus_size_t size_tmp = size; 2085 1.112.2.2 kent int shifts = 0; 2086 1.112.2.2 kent 2087 1.112.2.2 kent mask = 1; 2088 1.112.2.2 kent while (size_tmp) { 2089 1.112.2.2 kent ++shifts; 2090 1.112.2.2 kent size_tmp >>= 1; 2091 1.112.2.2 kent } 2092 1.112.2.2 kent mask = (1 << shifts); 2093 1.112.2.2 kent if (mask < size) { 2094 1.112.2.2 kent mask <<= 1; 2095 1.112.2.2 kent } 2096 1.112.2.2 kent --mask; 2097 1.112.2.2 kent } 2098 1.112.2.2 kent 2099 1.112.2.2 kent /* 2100 1.112.2.2 kent * Allocate some arbitrary I/O space. 2101 1.112.2.2 kent */ 2102 1.112.2.2 kent 2103 1.112.2.2 kent iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2104 1.112.2.2 kent 2105 1.112.2.2 kent #if rbus 2106 1.112.2.2 kent rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2107 1.112.2.2 kent if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2108 1.112.2.2 kent return 1; 2109 1.112.2.2 kent } 2110 1.112.2.2 kent DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2111 1.112.2.2 kent (u_long) ioaddr, (u_long) size)); 2112 1.112.2.2 kent #else 2113 1.112.2.2 kent if (start) { 2114 1.112.2.2 kent ioaddr = start; 2115 1.112.2.2 kent if (bus_space_map(iot, start, size, 0, &ioh)) { 2116 1.112.2.2 kent return 1; 2117 1.112.2.2 kent } 2118 1.112.2.2 kent DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2119 1.112.2.2 kent (u_long) ioaddr, (u_long) size)); 2120 1.112.2.2 kent } else { 2121 1.112.2.2 kent flags |= PCMCIA_IO_ALLOCATED; 2122 1.112.2.2 kent if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2123 1.112.2.2 kent 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2124 1.112.2.2 kent size, align, 0, 0, &ioaddr, &ioh)) { 2125 1.112.2.2 kent /* No room be able to be get. */ 2126 1.112.2.2 kent return 1; 2127 1.112.2.2 kent } 2128 1.112.2.2 kent DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2129 1.112.2.2 kent (u_long) ioaddr, (u_long) size)); 2130 1.112.2.2 kent } 2131 1.112.2.2 kent #endif 2132 1.112.2.2 kent 2133 1.112.2.2 kent pcihp->iot = iot; 2134 1.112.2.2 kent pcihp->ioh = ioh; 2135 1.112.2.2 kent pcihp->addr = ioaddr; 2136 1.112.2.2 kent pcihp->size = size; 2137 1.112.2.2 kent pcihp->flags = flags; 2138 1.112.2.2 kent 2139 1.112.2.2 kent return 0; 2140 1.112.2.2 kent } 2141 1.112.2.2 kent 2142 1.112.2.2 kent /* 2143 1.112.2.2 kent * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2144 1.112.2.2 kent * struct pcmcia_io_handle *pcihp) 2145 1.112.2.2 kent * 2146 1.112.2.2 kent * This function only frees I/O region for pccard. 2147 1.112.2.2 kent * 2148 1.112.2.2 kent * XXX: The interface of this function is not very good, I believe. 2149 1.112.2.2 kent */ 2150 1.112.2.2 kent void 2151 1.112.2.2 kent pccbb_pcmcia_io_free(pch, pcihp) 2152 1.112.2.2 kent pcmcia_chipset_handle_t pch; 2153 1.112.2.2 kent struct pcmcia_io_handle *pcihp; 2154 1.112.2.2 kent { 2155 1.112.2.2 kent #if !rbus 2156 1.112.2.2 kent bus_space_tag_t iot = pcihp->iot; 2157 1.112.2.2 kent #endif 2158 1.112.2.2 kent bus_space_handle_t ioh = pcihp->ioh; 2159 1.112.2.2 kent bus_size_t size = pcihp->size; 2160 1.112.2.2 kent 2161 1.112.2.2 kent #if rbus 2162 1.112.2.2 kent struct pccbb_softc *sc = 2163 1.112.2.2 kent (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2164 1.112.2.2 kent rbus_tag_t rb = sc->sc_rbus_iot; 2165 1.112.2.2 kent 2166 1.112.2.2 kent rbus_space_free(rb, ioh, size, NULL); 2167 1.112.2.2 kent #else 2168 1.112.2.2 kent if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2169 1.112.2.2 kent bus_space_free(iot, ioh, size); 2170 1.112.2.2 kent else 2171 1.112.2.2 kent bus_space_unmap(iot, ioh, size); 2172 1.112.2.2 kent #endif 2173 1.112.2.2 kent } 2174 1.112.2.2 kent 2175 1.112.2.2 kent /* 2176 1.112.2.2 kent * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2177 1.112.2.2 kent * bus_addr_t offset, bus_size_t size, 2178 1.112.2.2 kent * struct pcmcia_io_handle *pcihp, 2179 1.112.2.2 kent * int *windowp) 2180 1.112.2.2 kent * 2181 1.112.2.2 kent * This function maps the allocated I/O region to pccard. This function 2182 1.112.2.2 kent * never allocates any I/O region for pccard I/O area. I don't 2183 1.112.2.2 kent * understand why the original authors of pcmciabus separated alloc and 2184 1.112.2.2 kent * map. I believe the two must be unite. 2185 1.112.2.2 kent * 2186 1.112.2.2 kent * XXX: no wait timing control? 2187 1.112.2.2 kent */ 2188 1.112.2.2 kent int 2189 1.112.2.2 kent pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2190 1.112.2.2 kent pcmcia_chipset_handle_t pch; 2191 1.112.2.2 kent int width; 2192 1.112.2.2 kent bus_addr_t offset; 2193 1.112.2.2 kent bus_size_t size; 2194 1.112.2.2 kent struct pcmcia_io_handle *pcihp; 2195 1.112.2.2 kent int *windowp; 2196 1.112.2.2 kent { 2197 1.112.2.2 kent struct pcic_handle *ph = (struct pcic_handle *)pch; 2198 1.112.2.2 kent bus_addr_t ioaddr = pcihp->addr + offset; 2199 1.112.2.2 kent int i, win; 2200 1.112.2.2 kent #if defined CBB_DEBUG 2201 1.112.2.2 kent static char *width_names[] = { "dynamic", "io8", "io16" }; 2202 1.112.2.2 kent #endif 2203 1.112.2.2 kent 2204 1.112.2.2 kent /* Sanity check I/O handle. */ 2205 1.112.2.2 kent 2206 1.112.2.2 kent if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2207 1.112.2.2 kent panic("pccbb_pcmcia_io_map iot is bogus"); 2208 1.112.2.2 kent } 2209 1.112.2.2 kent 2210 1.112.2.2 kent /* XXX Sanity check offset/size. */ 2211 1.112.2.2 kent 2212 1.112.2.2 kent win = -1; 2213 1.112.2.2 kent for (i = 0; i < PCIC_IO_WINS; i++) { 2214 1.112.2.2 kent if ((ph->ioalloc & (1 << i)) == 0) { 2215 1.112.2.2 kent win = i; 2216 1.112.2.2 kent ph->ioalloc |= (1 << i); 2217 1.112.2.2 kent break; 2218 1.112.2.2 kent } 2219 1.112.2.2 kent } 2220 1.112.2.2 kent 2221 1.112.2.2 kent if (win == -1) { 2222 1.112.2.2 kent return 1; 2223 1.112.2.2 kent } 2224 1.112.2.2 kent 2225 1.112.2.2 kent *windowp = win; 2226 1.112.2.2 kent 2227 1.112.2.2 kent /* XXX this is pretty gross */ 2228 1.112.2.2 kent 2229 1.112.2.2 kent DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2230 1.112.2.2 kent win, width_names[width], (u_long) ioaddr, (u_long) size)); 2231 1.112.2.2 kent 2232 1.112.2.2 kent /* XXX wtf is this doing here? */ 2233 1.112.2.2 kent 2234 1.112.2.2 kent #if 0 2235 1.112.2.2 kent printf(" port 0x%lx", (u_long) ioaddr); 2236 1.112.2.2 kent if (size > 1) { 2237 1.112.2.2 kent printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2238 1.112.2.2 kent } 2239 1.112.2.2 kent #endif 2240 1.112.2.2 kent 2241 1.112.2.2 kent ph->io[win].addr = ioaddr; 2242 1.112.2.2 kent ph->io[win].size = size; 2243 1.112.2.2 kent ph->io[win].width = width; 2244 1.112.2.2 kent 2245 1.112.2.2 kent /* actual dirty register-value changing in the function below. */ 2246 1.112.2.2 kent pccbb_pcmcia_do_io_map(ph, win); 2247 1.112.2.2 kent 2248 1.112.2.2 kent return 0; 2249 1.112.2.2 kent } 2250 1.112.2.2 kent 2251 1.112.2.2 kent /* 2252 1.112.2.2 kent * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2253 1.112.2.2 kent * 2254 1.112.2.2 kent * This function changes register-value to map I/O region for pccard. 2255 1.112.2.2 kent */ 2256 1.112.2.2 kent static void 2257 1.112.2.2 kent pccbb_pcmcia_do_io_map(ph, win) 2258 1.112.2.2 kent struct pcic_handle *ph; 2259 1.112.2.2 kent int win; 2260 1.112.2.2 kent { 2261 1.112.2.2 kent static u_int8_t pcic_iowidth[3] = { 2262 1.112.2.2 kent PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2263 1.112.2.2 kent PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2264 1.112.2.2 kent PCIC_IOCTL_IO0_DATASIZE_8BIT, 2265 1.112.2.2 kent PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2266 1.112.2.2 kent PCIC_IOCTL_IO0_DATASIZE_16BIT, 2267 1.112.2.2 kent }; 2268 1.112.2.2 kent 2269 1.112.2.2 kent #define PCIC_SIA_START_LOW 0 2270 1.112.2.2 kent #define PCIC_SIA_START_HIGH 1 2271 1.112.2.2 kent #define PCIC_SIA_STOP_LOW 2 2272 1.112.2.2 kent #define PCIC_SIA_STOP_HIGH 3 2273 1.112.2.2 kent 2274 1.112.2.2 kent int regbase_win = 0x8 + win * 0x04; 2275 1.112.2.2 kent u_int8_t ioctl, enable; 2276 1.112.2.2 kent 2277 1.112.2.2 kent DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2278 1.112.2.2 kent "width %d\n", win, (unsigned long)ph->io[win].addr, 2279 1.112.2.2 kent (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2280 1.112.2.2 kent 2281 1.112.2.2 kent Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2282 1.112.2.2 kent ph->io[win].addr & 0xff); 2283 1.112.2.2 kent Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2284 1.112.2.2 kent (ph->io[win].addr >> 8) & 0xff); 2285 1.112.2.2 kent 2286 1.112.2.2 kent Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2287 1.112.2.2 kent (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2288 1.112.2.2 kent Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2289 1.112.2.2 kent ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2290 1.112.2.2 kent 2291 1.112.2.2 kent ioctl = Pcic_read(ph, PCIC_IOCTL); 2292 1.112.2.2 kent enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2293 1.112.2.2 kent switch (win) { 2294 1.112.2.2 kent case 0: 2295 1.112.2.2 kent ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2296 1.112.2.2 kent PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2297 1.112.2.2 kent PCIC_IOCTL_IO0_DATASIZE_MASK); 2298 1.112.2.2 kent ioctl |= pcic_iowidth[ph->io[win].width]; 2299 1.112.2.2 kent enable |= PCIC_ADDRWIN_ENABLE_IO0; 2300 1.112.2.2 kent break; 2301 1.112.2.2 kent case 1: 2302 1.112.2.2 kent ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2303 1.112.2.2 kent PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2304 1.112.2.2 kent PCIC_IOCTL_IO1_DATASIZE_MASK); 2305 1.112.2.2 kent ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2306 1.112.2.2 kent enable |= PCIC_ADDRWIN_ENABLE_IO1; 2307 1.112.2.2 kent break; 2308 1.112.2.2 kent } 2309 1.112.2.2 kent Pcic_write(ph, PCIC_IOCTL, ioctl); 2310 1.112.2.2 kent Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2311 1.112.2.2 kent #if defined CBB_DEBUG 2312 1.112.2.2 kent { 2313 1.112.2.2 kent u_int8_t start_low = 2314 1.112.2.2 kent Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2315 1.112.2.2 kent u_int8_t start_high = 2316 1.112.2.2 kent Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2317 1.112.2.2 kent u_int8_t stop_low = 2318 1.112.2.2 kent Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2319 1.112.2.2 kent u_int8_t stop_high = 2320 1.112.2.2 kent Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2321 1.112.2.2 kent printf 2322 1.112.2.2 kent (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2323 1.112.2.2 kent start_low, start_high, stop_low, stop_high, ioctl, enable); 2324 1.112.2.2 kent } 2325 1.112.2.2 kent #endif 2326 1.112.2.2 kent } 2327 1.112.2.2 kent 2328 1.112.2.2 kent /* 2329 1.112.2.2 kent * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2330 1.112.2.2 kent * 2331 1.112.2.2 kent * This function unmaps I/O region. No return value. 2332 1.112.2.2 kent */ 2333 1.112.2.2 kent STATIC void 2334 1.112.2.2 kent pccbb_pcmcia_io_unmap(pch, win) 2335 1.112.2.2 kent pcmcia_chipset_handle_t pch; 2336 1.112.2.2 kent int win; 2337 1.112.2.2 kent { 2338 1.112.2.2 kent struct pcic_handle *ph = (struct pcic_handle *)pch; 2339 1.112.2.2 kent int reg; 2340 1.112.2.2 kent 2341 1.112.2.2 kent if (win >= PCIC_IO_WINS || win < 0) { 2342 1.112.2.2 kent panic("pccbb_pcmcia_io_unmap: window out of range"); 2343 1.112.2.2 kent } 2344 1.112.2.2 kent 2345 1.112.2.2 kent reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2346 1.112.2.2 kent switch (win) { 2347 1.112.2.2 kent case 0: 2348 1.112.2.2 kent reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2349 1.112.2.2 kent break; 2350 1.112.2.2 kent case 1: 2351 1.112.2.2 kent reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2352 1.112.2.2 kent break; 2353 1.112.2.2 kent } 2354 1.112.2.2 kent Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2355 1.112.2.2 kent 2356 1.112.2.2 kent ph->ioalloc &= ~(1 << win); 2357 1.112.2.2 kent } 2358 1.112.2.2 kent 2359 1.112.2.2 kent static int 2360 1.112.2.2 kent pccbb_pcmcia_wait_ready(ph) 2361 1.112.2.2 kent struct pcic_handle *ph; 2362 1.112.2.2 kent { 2363 1.112.2.2 kent u_int8_t stat; 2364 1.112.2.2 kent int i; 2365 1.112.2.2 kent 2366 1.112.2.2 kent /* wait an initial 10ms for quick cards */ 2367 1.112.2.2 kent stat = Pcic_read(ph, PCIC_IF_STATUS); 2368 1.112.2.2 kent if (stat & PCIC_IF_STATUS_READY) 2369 1.112.2.2 kent return (0); 2370 1.112.2.2 kent pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2371 1.112.2.2 kent for (i = 0; i < 50; i++) { 2372 1.112.2.2 kent stat = Pcic_read(ph, PCIC_IF_STATUS); 2373 1.112.2.2 kent if (stat & PCIC_IF_STATUS_READY) 2374 1.112.2.2 kent return (0); 2375 1.112.2.2 kent if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2376 1.112.2.2 kent PCIC_IF_STATUS_CARDDETECT_PRESENT) 2377 1.112.2.2 kent return (ENXIO); 2378 1.112.2.2 kent /* wait .1s (100ms) each iteration now */ 2379 1.112.2.2 kent pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2380 1.112.2.2 kent } 2381 1.112.2.2 kent 2382 1.112.2.2 kent printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2383 1.112.2.2 kent return (EWOULDBLOCK); 2384 1.112.2.2 kent } 2385 1.112.2.2 kent 2386 1.112.2.2 kent /* 2387 1.112.2.2 kent * Perform long (msec order) delay. 2388 1.112.2.2 kent */ 2389 1.112.2.2 kent static void 2390 1.112.2.2 kent pccbb_pcmcia_delay(ph, timo, wmesg) 2391 1.112.2.2 kent struct pcic_handle *ph; 2392 1.112.2.2 kent int timo; /* in ms. must not be zero */ 2393 1.112.2.2 kent const char *wmesg; 2394 1.112.2.2 kent { 2395 1.112.2.2 kent 2396 1.112.2.2 kent #ifdef DIAGNOSTIC 2397 1.112.2.2 kent if (timo <= 0) 2398 1.112.2.2 kent panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2399 1.112.2.2 kent if (!curlwp) 2400 1.112.2.2 kent panic("pccbb_pcmcia_delay: called in interrupt context"); 2401 1.112.2.2 kent #if 0 2402 1.112.2.2 kent if (!ph->event_thread) 2403 1.112.2.2 kent panic("pccbb_pcmcia_delay: no event thread"); 2404 1.112.2.2 kent #endif 2405 1.112.2.2 kent #endif 2406 1.112.2.2 kent DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2407 1.112.2.2 kent wmesg, ph->event_thread, timo)); 2408 1.112.2.2 kent tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2409 1.112.2.2 kent } 2410 1.112.2.2 kent 2411 1.112.2.2 kent /* 2412 1.112.2.2 kent * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2413 1.112.2.2 kent * 2414 1.112.2.2 kent * This function enables the card. All information is stored in 2415 1.112.2.2 kent * the first argument, pcmcia_chipset_handle_t. 2416 1.112.2.2 kent */ 2417 1.112.2.2 kent STATIC void 2418 1.112.2.2 kent pccbb_pcmcia_socket_enable(pch) 2419 1.112.2.2 kent pcmcia_chipset_handle_t pch; 2420 1.112.2.2 kent { 2421 1.112.2.2 kent struct pcic_handle *ph = (struct pcic_handle *)pch; 2422 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2423 1.112.2.2 kent pcireg_t spsr; 2424 1.112.2.2 kent int voltage; 2425 1.112.2.2 kent int win; 2426 1.112.2.2 kent u_int8_t power, intr; 2427 1.112.2.2 kent #ifdef DIAGNOSTIC 2428 1.112.2.2 kent int reg; 2429 1.112.2.2 kent #endif 2430 1.112.2.2 kent 2431 1.112.2.2 kent /* this bit is mostly stolen from pcic_attach_card */ 2432 1.112.2.2 kent 2433 1.112.2.2 kent DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2434 1.112.2.2 kent 2435 1.112.2.2 kent /* get card Vcc info */ 2436 1.112.2.2 kent spsr = 2437 1.112.2.2 kent bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2438 1.112.2.2 kent CB_SOCKET_STAT); 2439 1.112.2.2 kent if (spsr & CB_SOCKET_STAT_5VCARD) { 2440 1.112.2.2 kent DPRINTF(("5V card\n")); 2441 1.112.2.2 kent voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2442 1.112.2.2 kent } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2443 1.112.2.2 kent DPRINTF(("3V card\n")); 2444 1.112.2.2 kent voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2445 1.112.2.2 kent } else { 2446 1.112.2.2 kent printf("?V card, 0x%x\n", spsr); /* XXX */ 2447 1.112.2.2 kent return; 2448 1.112.2.2 kent } 2449 1.112.2.2 kent 2450 1.112.2.2 kent /* disable interrupts; assert RESET */ 2451 1.112.2.2 kent intr = Pcic_read(ph, PCIC_INTR); 2452 1.112.2.2 kent intr &= PCIC_INTR_ENABLE; 2453 1.112.2.2 kent Pcic_write(ph, PCIC_INTR, intr); 2454 1.112.2.2 kent 2455 1.112.2.2 kent /* zero out the address windows */ 2456 1.112.2.2 kent Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2457 1.112.2.2 kent 2458 1.112.2.2 kent /* power down the socket to reset it, clear the card reset pin */ 2459 1.112.2.2 kent pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2460 1.112.2.2 kent 2461 1.112.2.2 kent /* power off; assert output enable bit */ 2462 1.112.2.2 kent power = PCIC_PWRCTL_OE; 2463 1.112.2.2 kent Pcic_write(ph, PCIC_PWRCTL, power); 2464 1.112.2.2 kent 2465 1.112.2.2 kent /* power up the socket */ 2466 1.112.2.2 kent if (pccbb_power(sc, voltage) == 0) 2467 1.112.2.2 kent return; 2468 1.112.2.2 kent 2469 1.112.2.2 kent /* 2470 1.112.2.2 kent * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2471 1.112.2.2 kent * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2472 1.112.2.2 kent * RESET Width (Th (Hi-z RESET)) = 1ms 2473 1.112.2.2 kent * RESET Width (Tw (RESET)) = 10us 2474 1.112.2.2 kent */ 2475 1.112.2.2 kent pccbb_pcmcia_delay(ph, 1, "pccen1"); 2476 1.112.2.2 kent 2477 1.112.2.2 kent /* negate RESET */ 2478 1.112.2.2 kent intr |= PCIC_INTR_RESET; 2479 1.112.2.2 kent Pcic_write(ph, PCIC_INTR, intr); 2480 1.112.2.2 kent 2481 1.112.2.2 kent /* 2482 1.112.2.2 kent * RESET Setup Time (Tsu (RESET)) = 20ms 2483 1.112.2.2 kent */ 2484 1.112.2.2 kent pccbb_pcmcia_delay(ph, 20, "pccen2"); 2485 1.112.2.2 kent 2486 1.112.2.2 kent #ifdef DIAGNOSTIC 2487 1.112.2.2 kent reg = Pcic_read(ph, PCIC_IF_STATUS); 2488 1.112.2.2 kent if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2489 1.112.2.2 kent printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2490 1.112.2.2 kent #endif 2491 1.112.2.2 kent 2492 1.112.2.2 kent /* wait for the chip to finish initializing */ 2493 1.112.2.2 kent if (pccbb_pcmcia_wait_ready(ph)) { 2494 1.112.2.2 kent /* XXX return a failure status?? */ 2495 1.112.2.2 kent pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2496 1.112.2.2 kent Pcic_write(ph, PCIC_PWRCTL, 0); 2497 1.112.2.2 kent return; 2498 1.112.2.2 kent } 2499 1.112.2.2 kent 2500 1.112.2.2 kent /* reinstall all the memory and io mappings */ 2501 1.112.2.2 kent for (win = 0; win < PCIC_MEM_WINS; ++win) 2502 1.112.2.2 kent if (ph->memalloc & (1 << win)) 2503 1.112.2.2 kent pccbb_pcmcia_do_mem_map(ph, win); 2504 1.112.2.2 kent for (win = 0; win < PCIC_IO_WINS; ++win) 2505 1.112.2.2 kent if (ph->ioalloc & (1 << win)) 2506 1.112.2.2 kent pccbb_pcmcia_do_io_map(ph, win); 2507 1.112.2.2 kent } 2508 1.112.2.2 kent 2509 1.112.2.2 kent /* 2510 1.112.2.2 kent * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2511 1.112.2.2 kent * 2512 1.112.2.2 kent * This function disables the card. All information is stored in 2513 1.112.2.2 kent * the first argument, pcmcia_chipset_handle_t. 2514 1.112.2.2 kent */ 2515 1.112.2.2 kent STATIC void 2516 1.112.2.2 kent pccbb_pcmcia_socket_disable(pch) 2517 1.112.2.2 kent pcmcia_chipset_handle_t pch; 2518 1.112.2.2 kent { 2519 1.112.2.2 kent struct pcic_handle *ph = (struct pcic_handle *)pch; 2520 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2521 1.112.2.2 kent u_int8_t intr; 2522 1.112.2.2 kent 2523 1.112.2.2 kent DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2524 1.112.2.2 kent 2525 1.112.2.2 kent /* disable interrupts; assert RESET */ 2526 1.112.2.2 kent intr = Pcic_read(ph, PCIC_INTR); 2527 1.112.2.2 kent intr &= PCIC_INTR_ENABLE; 2528 1.112.2.2 kent Pcic_write(ph, PCIC_INTR, intr); 2529 1.112.2.2 kent 2530 1.112.2.2 kent /* zero out the address windows */ 2531 1.112.2.2 kent Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2532 1.112.2.2 kent 2533 1.112.2.2 kent /* power down the socket to reset it, clear the card reset pin */ 2534 1.112.2.2 kent pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2535 1.112.2.2 kent 2536 1.112.2.2 kent /* disable socket: negate output enable bit and power off */ 2537 1.112.2.2 kent Pcic_write(ph, PCIC_PWRCTL, 0); 2538 1.112.2.2 kent 2539 1.112.2.2 kent /* 2540 1.112.2.2 kent * Vcc Falling Time (Tpf) = 300ms 2541 1.112.2.2 kent */ 2542 1.112.2.2 kent pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2543 1.112.2.2 kent } 2544 1.112.2.2 kent 2545 1.112.2.2 kent STATIC void 2546 1.112.2.2 kent pccbb_pcmcia_socket_settype(pch, type) 2547 1.112.2.2 kent pcmcia_chipset_handle_t pch; 2548 1.112.2.2 kent int type; 2549 1.112.2.2 kent { 2550 1.112.2.2 kent struct pcic_handle *ph = (struct pcic_handle *)pch; 2551 1.112.2.2 kent u_int8_t intr; 2552 1.112.2.2 kent 2553 1.112.2.2 kent /* set the card type */ 2554 1.112.2.2 kent 2555 1.112.2.2 kent intr = Pcic_read(ph, PCIC_INTR); 2556 1.112.2.2 kent intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2557 1.112.2.2 kent if (type == PCMCIA_IFTYPE_IO) 2558 1.112.2.2 kent intr |= PCIC_INTR_CARDTYPE_IO; 2559 1.112.2.2 kent else 2560 1.112.2.2 kent intr |= PCIC_INTR_CARDTYPE_MEM; 2561 1.112.2.2 kent Pcic_write(ph, PCIC_INTR, intr); 2562 1.112.2.2 kent 2563 1.112.2.2 kent DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2564 1.112.2.2 kent ph->ph_parent->dv_xname, ph->sock, 2565 1.112.2.2 kent ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2566 1.112.2.2 kent } 2567 1.112.2.2 kent 2568 1.112.2.2 kent /* 2569 1.112.2.2 kent * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2570 1.112.2.2 kent * 2571 1.112.2.2 kent * This function detects whether a card is in the slot or not. 2572 1.112.2.2 kent * If a card is inserted, return 1. Otherwise, return 0. 2573 1.112.2.2 kent */ 2574 1.112.2.2 kent STATIC int 2575 1.112.2.2 kent pccbb_pcmcia_card_detect(pch) 2576 1.112.2.2 kent pcmcia_chipset_handle_t pch; 2577 1.112.2.2 kent { 2578 1.112.2.2 kent struct pcic_handle *ph = (struct pcic_handle *)pch; 2579 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2580 1.112.2.2 kent 2581 1.112.2.2 kent DPRINTF(("pccbb_pcmcia_card_detect\n")); 2582 1.112.2.2 kent return pccbb_detect_card(sc) == 1 ? 1 : 0; 2583 1.112.2.2 kent } 2584 1.112.2.2 kent 2585 1.112.2.2 kent #if 0 2586 1.112.2.2 kent STATIC int 2587 1.112.2.2 kent pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2588 1.112.2.2 kent bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2589 1.112.2.2 kent bus_space_tag_t * memtp bus_space_handle_t * memhp) 2590 1.112.2.2 kent #endif 2591 1.112.2.2 kent /* 2592 1.112.2.2 kent * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2593 1.112.2.2 kent * bus_size_t size, 2594 1.112.2.2 kent * struct pcmcia_mem_handle *pcmhp) 2595 1.112.2.2 kent * 2596 1.112.2.2 kent * This function only allocates memory region for pccard. This 2597 1.112.2.2 kent * function never maps the allocated region to pccard memory area. 2598 1.112.2.2 kent * 2599 1.112.2.2 kent * XXX: Why the argument of start address is not in? 2600 1.112.2.2 kent */ 2601 1.112.2.2 kent STATIC int 2602 1.112.2.2 kent pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2603 1.112.2.2 kent pcmcia_chipset_handle_t pch; 2604 1.112.2.2 kent bus_size_t size; 2605 1.112.2.2 kent struct pcmcia_mem_handle *pcmhp; 2606 1.112.2.2 kent { 2607 1.112.2.2 kent struct pcic_handle *ph = (struct pcic_handle *)pch; 2608 1.112.2.2 kent bus_space_handle_t memh; 2609 1.112.2.2 kent bus_addr_t addr; 2610 1.112.2.2 kent bus_size_t sizepg; 2611 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2612 1.112.2.2 kent #if rbus 2613 1.112.2.2 kent rbus_tag_t rb; 2614 1.112.2.2 kent #endif 2615 1.112.2.2 kent 2616 1.112.2.2 kent /* Check that the card is still there. */ 2617 1.112.2.2 kent if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2618 1.112.2.2 kent PCIC_IF_STATUS_CARDDETECT_PRESENT) 2619 1.112.2.2 kent return 1; 2620 1.112.2.2 kent 2621 1.112.2.2 kent /* out of sc->memh, allocate as many pages as necessary */ 2622 1.112.2.2 kent 2623 1.112.2.2 kent /* convert size to PCIC pages */ 2624 1.112.2.2 kent /* 2625 1.112.2.2 kent * This is not enough; when the requested region is on the page 2626 1.112.2.2 kent * boundaries, this may calculate wrong result. 2627 1.112.2.2 kent */ 2628 1.112.2.2 kent sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2629 1.112.2.2 kent #if 0 2630 1.112.2.2 kent if (sizepg > PCIC_MAX_MEM_PAGES) { 2631 1.112.2.2 kent return 1; 2632 1.112.2.2 kent } 2633 1.112.2.2 kent #endif 2634 1.112.2.2 kent 2635 1.112.2.2 kent if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2636 1.112.2.2 kent return 1; 2637 1.112.2.2 kent } 2638 1.112.2.2 kent 2639 1.112.2.2 kent addr = 0; /* XXX gcc -Wuninitialized */ 2640 1.112.2.2 kent 2641 1.112.2.2 kent #if rbus 2642 1.112.2.2 kent rb = sc->sc_rbus_memt; 2643 1.112.2.2 kent if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2644 1.112.2.2 kent sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2645 1.112.2.2 kent &addr, &memh)) { 2646 1.112.2.2 kent return 1; 2647 1.112.2.2 kent } 2648 1.112.2.2 kent #else 2649 1.112.2.2 kent if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2650 1.112.2.2 kent sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2651 1.112.2.2 kent 0, /* boundary */ 2652 1.112.2.2 kent 0, /* flags */ 2653 1.112.2.2 kent &addr, &memh)) { 2654 1.112.2.2 kent return 1; 2655 1.112.2.2 kent } 2656 1.112.2.2 kent #endif 2657 1.112.2.2 kent 2658 1.112.2.2 kent DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2659 1.112.2.2 kent "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2660 1.112.2.2 kent (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2661 1.112.2.2 kent 2662 1.112.2.2 kent pcmhp->memt = sc->sc_memt; 2663 1.112.2.2 kent pcmhp->memh = memh; 2664 1.112.2.2 kent pcmhp->addr = addr; 2665 1.112.2.2 kent pcmhp->size = size; 2666 1.112.2.2 kent pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2667 1.112.2.2 kent /* What is mhandle? I feel it is very dirty and it must go trush. */ 2668 1.112.2.2 kent pcmhp->mhandle = 0; 2669 1.112.2.2 kent /* No offset??? Funny. */ 2670 1.112.2.2 kent 2671 1.112.2.2 kent return 0; 2672 1.112.2.2 kent } 2673 1.112.2.2 kent 2674 1.112.2.2 kent /* 2675 1.112.2.2 kent * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2676 1.112.2.2 kent * struct pcmcia_mem_handle *pcmhp) 2677 1.112.2.2 kent * 2678 1.112.2.2 kent * This function release the memory space allocated by the function 2679 1.112.2.2 kent * pccbb_pcmcia_mem_alloc(). 2680 1.112.2.2 kent */ 2681 1.112.2.2 kent STATIC void 2682 1.112.2.2 kent pccbb_pcmcia_mem_free(pch, pcmhp) 2683 1.112.2.2 kent pcmcia_chipset_handle_t pch; 2684 1.112.2.2 kent struct pcmcia_mem_handle *pcmhp; 2685 1.112.2.2 kent { 2686 1.112.2.2 kent #if rbus 2687 1.112.2.2 kent struct pcic_handle *ph = (struct pcic_handle *)pch; 2688 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2689 1.112.2.2 kent 2690 1.112.2.2 kent rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2691 1.112.2.2 kent #else 2692 1.112.2.2 kent bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2693 1.112.2.2 kent #endif 2694 1.112.2.2 kent } 2695 1.112.2.2 kent 2696 1.112.2.2 kent /* 2697 1.112.2.2 kent * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2698 1.112.2.2 kent * 2699 1.112.2.2 kent * This function release the memory space allocated by the function 2700 1.112.2.2 kent * pccbb_pcmcia_mem_alloc(). 2701 1.112.2.2 kent */ 2702 1.112.2.2 kent STATIC void 2703 1.112.2.2 kent pccbb_pcmcia_do_mem_map(ph, win) 2704 1.112.2.2 kent struct pcic_handle *ph; 2705 1.112.2.2 kent int win; 2706 1.112.2.2 kent { 2707 1.112.2.2 kent int regbase_win; 2708 1.112.2.2 kent bus_addr_t phys_addr; 2709 1.112.2.2 kent bus_addr_t phys_end; 2710 1.112.2.2 kent 2711 1.112.2.2 kent #define PCIC_SMM_START_LOW 0 2712 1.112.2.2 kent #define PCIC_SMM_START_HIGH 1 2713 1.112.2.2 kent #define PCIC_SMM_STOP_LOW 2 2714 1.112.2.2 kent #define PCIC_SMM_STOP_HIGH 3 2715 1.112.2.2 kent #define PCIC_CMA_LOW 4 2716 1.112.2.2 kent #define PCIC_CMA_HIGH 5 2717 1.112.2.2 kent 2718 1.112.2.2 kent u_int8_t start_low, start_high = 0; 2719 1.112.2.2 kent u_int8_t stop_low, stop_high; 2720 1.112.2.2 kent u_int8_t off_low, off_high; 2721 1.112.2.2 kent u_int8_t mem_window; 2722 1.112.2.2 kent int reg; 2723 1.112.2.2 kent 2724 1.112.2.2 kent int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2725 1.112.2.2 kent int mem8 = 2726 1.112.2.2 kent (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2727 1.112.2.2 kent || (kind == PCMCIA_MEM_ATTR); 2728 1.112.2.2 kent 2729 1.112.2.2 kent regbase_win = 0x10 + win * 0x08; 2730 1.112.2.2 kent 2731 1.112.2.2 kent phys_addr = ph->mem[win].addr; 2732 1.112.2.2 kent phys_end = phys_addr + ph->mem[win].size; 2733 1.112.2.2 kent 2734 1.112.2.2 kent DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2735 1.112.2.2 kent (unsigned long)phys_addr, (unsigned long)phys_end, 2736 1.112.2.2 kent (unsigned long)ph->mem[win].offset)); 2737 1.112.2.2 kent 2738 1.112.2.2 kent #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2739 1.112.2.2 kent #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2740 1.112.2.2 kent #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2741 1.112.2.2 kent 2742 1.112.2.2 kent /* bit 19:12 */ 2743 1.112.2.2 kent start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2744 1.112.2.2 kent /* bit 23:20 and bit 7 on */ 2745 1.112.2.2 kent start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2746 1.112.2.2 kent |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2747 1.112.2.2 kent /* bit 31:24, for 32-bit address */ 2748 1.112.2.2 kent mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2749 1.112.2.2 kent 2750 1.112.2.2 kent Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2751 1.112.2.2 kent Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2752 1.112.2.2 kent 2753 1.112.2.2 kent if (((struct pccbb_softc *)ph-> 2754 1.112.2.2 kent ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2755 1.112.2.2 kent Pcic_write(ph, 0x40 + win, mem_window); 2756 1.112.2.2 kent } 2757 1.112.2.2 kent 2758 1.112.2.2 kent stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2759 1.112.2.2 kent stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2760 1.112.2.2 kent | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2761 1.112.2.2 kent /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2762 1.112.2.2 kent 2763 1.112.2.2 kent Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2764 1.112.2.2 kent Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2765 1.112.2.2 kent 2766 1.112.2.2 kent off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2767 1.112.2.2 kent off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2768 1.112.2.2 kent & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2769 1.112.2.2 kent | ((kind == PCMCIA_MEM_ATTR) ? 2770 1.112.2.2 kent PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2771 1.112.2.2 kent 2772 1.112.2.2 kent Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2773 1.112.2.2 kent Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2774 1.112.2.2 kent 2775 1.112.2.2 kent reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2776 1.112.2.2 kent reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2777 1.112.2.2 kent Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2778 1.112.2.2 kent 2779 1.112.2.2 kent #if defined CBB_DEBUG 2780 1.112.2.2 kent { 2781 1.112.2.2 kent int r1, r2, r3, r4, r5, r6, r7 = 0; 2782 1.112.2.2 kent 2783 1.112.2.2 kent r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2784 1.112.2.2 kent r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2785 1.112.2.2 kent r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2786 1.112.2.2 kent r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2787 1.112.2.2 kent r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2788 1.112.2.2 kent r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2789 1.112.2.2 kent if (((struct pccbb_softc *)(ph-> 2790 1.112.2.2 kent ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2791 1.112.2.2 kent r7 = Pcic_read(ph, 0x40 + win); 2792 1.112.2.2 kent } 2793 1.112.2.2 kent 2794 1.112.2.2 kent DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2795 1.112.2.2 kent "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2796 1.112.2.2 kent if (((struct pccbb_softc *)(ph-> 2797 1.112.2.2 kent ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2798 1.112.2.2 kent DPRINTF((" %02x", r7)); 2799 1.112.2.2 kent } 2800 1.112.2.2 kent DPRINTF(("\n")); 2801 1.112.2.2 kent } 2802 1.112.2.2 kent #endif 2803 1.112.2.2 kent } 2804 1.112.2.2 kent 2805 1.112.2.2 kent /* 2806 1.112.2.2 kent * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2807 1.112.2.2 kent * bus_addr_t card_addr, bus_size_t size, 2808 1.112.2.2 kent * struct pcmcia_mem_handle *pcmhp, 2809 1.112.2.2 kent * bus_addr_t *offsetp, int *windowp) 2810 1.112.2.2 kent * 2811 1.112.2.2 kent * This function maps memory space allocated by the function 2812 1.112.2.2 kent * pccbb_pcmcia_mem_alloc(). 2813 1.112.2.2 kent */ 2814 1.112.2.2 kent STATIC int 2815 1.112.2.2 kent pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2816 1.112.2.2 kent pcmcia_chipset_handle_t pch; 2817 1.112.2.2 kent int kind; 2818 1.112.2.2 kent bus_addr_t card_addr; 2819 1.112.2.2 kent bus_size_t size; 2820 1.112.2.2 kent struct pcmcia_mem_handle *pcmhp; 2821 1.112.2.2 kent bus_addr_t *offsetp; 2822 1.112.2.2 kent int *windowp; 2823 1.112.2.2 kent { 2824 1.112.2.2 kent struct pcic_handle *ph = (struct pcic_handle *)pch; 2825 1.112.2.2 kent bus_addr_t busaddr; 2826 1.112.2.2 kent long card_offset; 2827 1.112.2.2 kent int win; 2828 1.112.2.2 kent 2829 1.112.2.2 kent /* Check that the card is still there. */ 2830 1.112.2.2 kent if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2831 1.112.2.2 kent PCIC_IF_STATUS_CARDDETECT_PRESENT) 2832 1.112.2.2 kent return 1; 2833 1.112.2.2 kent 2834 1.112.2.2 kent for (win = 0; win < PCIC_MEM_WINS; ++win) { 2835 1.112.2.2 kent if ((ph->memalloc & (1 << win)) == 0) { 2836 1.112.2.2 kent ph->memalloc |= (1 << win); 2837 1.112.2.2 kent break; 2838 1.112.2.2 kent } 2839 1.112.2.2 kent } 2840 1.112.2.2 kent 2841 1.112.2.2 kent if (win == PCIC_MEM_WINS) { 2842 1.112.2.2 kent return 1; 2843 1.112.2.2 kent } 2844 1.112.2.2 kent 2845 1.112.2.2 kent *windowp = win; 2846 1.112.2.2 kent 2847 1.112.2.2 kent /* XXX this is pretty gross */ 2848 1.112.2.2 kent 2849 1.112.2.2 kent if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2850 1.112.2.2 kent panic("pccbb_pcmcia_mem_map memt is bogus"); 2851 1.112.2.2 kent } 2852 1.112.2.2 kent 2853 1.112.2.2 kent busaddr = pcmhp->addr; 2854 1.112.2.2 kent 2855 1.112.2.2 kent /* 2856 1.112.2.2 kent * compute the address offset to the pcmcia address space for the 2857 1.112.2.2 kent * pcic. this is intentionally signed. The masks and shifts below 2858 1.112.2.2 kent * will cause TRT to happen in the pcic registers. Deal with making 2859 1.112.2.2 kent * sure the address is aligned, and return the alignment offset. 2860 1.112.2.2 kent */ 2861 1.112.2.2 kent 2862 1.112.2.2 kent *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2863 1.112.2.2 kent card_addr -= *offsetp; 2864 1.112.2.2 kent 2865 1.112.2.2 kent DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2866 1.112.2.2 kent "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2867 1.112.2.2 kent (u_long) card_addr)); 2868 1.112.2.2 kent 2869 1.112.2.2 kent /* 2870 1.112.2.2 kent * include the offset in the size, and decrement size by one, since 2871 1.112.2.2 kent * the hw wants start/stop 2872 1.112.2.2 kent */ 2873 1.112.2.2 kent size += *offsetp - 1; 2874 1.112.2.2 kent 2875 1.112.2.2 kent card_offset = (((long)card_addr) - ((long)busaddr)); 2876 1.112.2.2 kent 2877 1.112.2.2 kent ph->mem[win].addr = busaddr; 2878 1.112.2.2 kent ph->mem[win].size = size; 2879 1.112.2.2 kent ph->mem[win].offset = card_offset; 2880 1.112.2.2 kent ph->mem[win].kind = kind; 2881 1.112.2.2 kent 2882 1.112.2.2 kent pccbb_pcmcia_do_mem_map(ph, win); 2883 1.112.2.2 kent 2884 1.112.2.2 kent return 0; 2885 1.112.2.2 kent } 2886 1.112.2.2 kent 2887 1.112.2.2 kent /* 2888 1.112.2.2 kent * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2889 1.112.2.2 kent * int window) 2890 1.112.2.2 kent * 2891 1.112.2.2 kent * This function unmaps memory space which mapped by the function 2892 1.112.2.2 kent * pccbb_pcmcia_mem_map(). 2893 1.112.2.2 kent */ 2894 1.112.2.2 kent STATIC void 2895 1.112.2.2 kent pccbb_pcmcia_mem_unmap(pch, window) 2896 1.112.2.2 kent pcmcia_chipset_handle_t pch; 2897 1.112.2.2 kent int window; 2898 1.112.2.2 kent { 2899 1.112.2.2 kent struct pcic_handle *ph = (struct pcic_handle *)pch; 2900 1.112.2.2 kent int reg; 2901 1.112.2.2 kent 2902 1.112.2.2 kent if (window >= PCIC_MEM_WINS) { 2903 1.112.2.2 kent panic("pccbb_pcmcia_mem_unmap: window out of range"); 2904 1.112.2.2 kent } 2905 1.112.2.2 kent 2906 1.112.2.2 kent reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2907 1.112.2.2 kent reg &= ~(1 << window); 2908 1.112.2.2 kent Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2909 1.112.2.2 kent 2910 1.112.2.2 kent ph->memalloc &= ~(1 << window); 2911 1.112.2.2 kent } 2912 1.112.2.2 kent 2913 1.112.2.2 kent #if defined PCCBB_PCMCIA_POLL 2914 1.112.2.2 kent struct pccbb_poll_str { 2915 1.112.2.2 kent void *arg; 2916 1.112.2.2 kent int (*func)(void *); 2917 1.112.2.2 kent int level; 2918 1.112.2.2 kent struct pcic_handle *ph; 2919 1.112.2.2 kent int count; 2920 1.112.2.2 kent int num; 2921 1.112.2.2 kent struct callout poll_ch; 2922 1.112.2.2 kent }; 2923 1.112.2.2 kent 2924 1.112.2.2 kent static struct pccbb_poll_str pccbb_poll[10]; 2925 1.112.2.2 kent static int pccbb_poll_n = 0; 2926 1.112.2.2 kent 2927 1.112.2.2 kent static void pccbb_pcmcia_poll(void *arg); 2928 1.112.2.2 kent 2929 1.112.2.2 kent static void 2930 1.112.2.2 kent pccbb_pcmcia_poll(arg) 2931 1.112.2.2 kent void *arg; 2932 1.112.2.2 kent { 2933 1.112.2.2 kent struct pccbb_poll_str *poll = arg; 2934 1.112.2.2 kent struct pcic_handle *ph = poll->ph; 2935 1.112.2.2 kent struct pccbb_softc *sc = ph->sc; 2936 1.112.2.2 kent int s; 2937 1.112.2.2 kent u_int32_t spsr; /* socket present-state reg */ 2938 1.112.2.2 kent 2939 1.112.2.2 kent callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2940 1.112.2.2 kent switch (poll->level) { 2941 1.112.2.2 kent case IPL_NET: 2942 1.112.2.2 kent s = splnet(); 2943 1.112.2.2 kent break; 2944 1.112.2.2 kent case IPL_BIO: 2945 1.112.2.2 kent s = splbio(); 2946 1.112.2.2 kent break; 2947 1.112.2.2 kent case IPL_TTY: /* fallthrough */ 2948 1.112.2.2 kent default: 2949 1.112.2.2 kent s = spltty(); 2950 1.112.2.2 kent break; 2951 1.112.2.2 kent } 2952 1.112.2.2 kent 2953 1.112.2.2 kent spsr = 2954 1.112.2.2 kent bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2955 1.112.2.2 kent CB_SOCKET_STAT); 2956 1.112.2.2 kent 2957 1.112.2.2 kent #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2958 1.112.2.2 kent if (!(spsr & 0x40)) /* CINT low */ 2959 1.112.2.2 kent #else 2960 1.112.2.2 kent if (1) 2961 1.112.2.2 kent #endif 2962 1.112.2.2 kent { 2963 1.112.2.2 kent if ((*poll->func) (poll->arg) > 0) { 2964 1.112.2.2 kent ++poll->count; 2965 1.112.2.2 kent /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2966 1.112.2.2 kent #if defined LEVEL2 2967 1.112.2.2 kent } else { 2968 1.112.2.2 kent printf("intr: miss! 0x%x\n", spsr); 2969 1.112.2.2 kent #endif 2970 1.112.2.2 kent } 2971 1.112.2.2 kent } 2972 1.112.2.2 kent splx(s); 2973 1.112.2.2 kent } 2974 1.112.2.2 kent #endif /* defined CB_PCMCIA_POLL */ 2975 1.112.2.2 kent 2976 1.112.2.2 kent /* 2977 1.112.2.2 kent * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2978 1.112.2.2 kent * struct pcmcia_function *pf, 2979 1.112.2.2 kent * int ipl, 2980 1.112.2.2 kent * int (*func)(void *), 2981 1.112.2.2 kent * void *arg); 2982 1.112.2.2 kent * 2983 1.112.2.2 kent * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2984 1.112.2.2 kent */ 2985 1.112.2.2 kent STATIC void * 2986 1.112.2.2 kent pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2987 1.112.2.2 kent pcmcia_chipset_handle_t pch; 2988 1.112.2.2 kent struct pcmcia_function *pf; 2989 1.112.2.2 kent int ipl; 2990 1.112.2.2 kent int (*func)(void *); 2991 1.112.2.2 kent void *arg; 2992 1.112.2.2 kent { 2993 1.112.2.2 kent struct pcic_handle *ph = (struct pcic_handle *)pch; 2994 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2995 1.112.2.2 kent 2996 1.112.2.2 kent if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2997 1.112.2.2 kent /* what should I do? */ 2998 1.112.2.2 kent if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2999 1.112.2.2 kent DPRINTF(("%s does not provide edge nor pulse " 3000 1.112.2.2 kent "interrupt\n", sc->sc_dev.dv_xname)); 3001 1.112.2.2 kent return NULL; 3002 1.112.2.2 kent } 3003 1.112.2.2 kent /* 3004 1.112.2.2 kent * XXX Noooooo! The interrupt flag must set properly!! 3005 1.112.2.2 kent * dumb pcmcia driver!! 3006 1.112.2.2 kent */ 3007 1.112.2.2 kent } 3008 1.112.2.2 kent 3009 1.112.2.2 kent return pccbb_intr_establish(sc, 0, ipl, func, arg); 3010 1.112.2.2 kent } 3011 1.112.2.2 kent 3012 1.112.2.2 kent /* 3013 1.112.2.2 kent * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 3014 1.112.2.2 kent * void *ih) 3015 1.112.2.2 kent * 3016 1.112.2.2 kent * This function disables PC-Card interrupt. 3017 1.112.2.2 kent */ 3018 1.112.2.2 kent STATIC void 3019 1.112.2.2 kent pccbb_pcmcia_intr_disestablish(pch, ih) 3020 1.112.2.2 kent pcmcia_chipset_handle_t pch; 3021 1.112.2.2 kent void *ih; 3022 1.112.2.2 kent { 3023 1.112.2.2 kent struct pcic_handle *ph = (struct pcic_handle *)pch; 3024 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3025 1.112.2.2 kent 3026 1.112.2.2 kent pccbb_intr_disestablish(sc, ih); 3027 1.112.2.2 kent } 3028 1.112.2.2 kent 3029 1.112.2.2 kent #if rbus 3030 1.112.2.2 kent /* 3031 1.112.2.2 kent * static int 3032 1.112.2.2 kent * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3033 1.112.2.2 kent * bus_addr_t addr, bus_size_t size, 3034 1.112.2.2 kent * bus_addr_t mask, bus_size_t align, 3035 1.112.2.2 kent * int flags, bus_addr_t *addrp; 3036 1.112.2.2 kent * bus_space_handle_t *bshp) 3037 1.112.2.2 kent * 3038 1.112.2.2 kent * This function allocates a portion of memory or io space for 3039 1.112.2.2 kent * clients. This function is called from CardBus card drivers. 3040 1.112.2.2 kent */ 3041 1.112.2.2 kent static int 3042 1.112.2.2 kent pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3043 1.112.2.2 kent cardbus_chipset_tag_t ct; 3044 1.112.2.2 kent rbus_tag_t rb; 3045 1.112.2.2 kent bus_addr_t addr; 3046 1.112.2.2 kent bus_size_t size; 3047 1.112.2.2 kent bus_addr_t mask; 3048 1.112.2.2 kent bus_size_t align; 3049 1.112.2.2 kent int flags; 3050 1.112.2.2 kent bus_addr_t *addrp; 3051 1.112.2.2 kent bus_space_handle_t *bshp; 3052 1.112.2.2 kent { 3053 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3054 1.112.2.2 kent 3055 1.112.2.2 kent DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3056 1.112.2.2 kent "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3057 1.112.2.2 kent (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3058 1.112.2.2 kent 3059 1.112.2.2 kent if (align == 0) { 3060 1.112.2.2 kent align = size; 3061 1.112.2.2 kent } 3062 1.112.2.2 kent 3063 1.112.2.2 kent if (rb->rb_bt == sc->sc_memt) { 3064 1.112.2.2 kent if (align < 16) { 3065 1.112.2.2 kent return 1; 3066 1.112.2.2 kent } 3067 1.112.2.2 kent /* 3068 1.112.2.2 kent * XXX: align more than 0x1000 to avoid overwrapping 3069 1.112.2.2 kent * memory windows for two or more devices. 0x1000 3070 1.112.2.2 kent * means memory window's granularity. 3071 1.112.2.2 kent * 3072 1.112.2.2 kent * Two or more devices should be able to share same 3073 1.112.2.2 kent * memory window region. However, overrapping memory 3074 1.112.2.2 kent * window is not good because some devices, such as 3075 1.112.2.2 kent * 3Com 3C575[BC], have a broken address decoder and 3076 1.112.2.2 kent * intrude other's memory region. 3077 1.112.2.2 kent */ 3078 1.112.2.2 kent if (align < 0x1000) { 3079 1.112.2.2 kent align = 0x1000; 3080 1.112.2.2 kent } 3081 1.112.2.2 kent } else if (rb->rb_bt == sc->sc_iot) { 3082 1.112.2.2 kent if (align < 4) { 3083 1.112.2.2 kent return 1; 3084 1.112.2.2 kent } 3085 1.112.2.2 kent /* XXX: hack for avoiding ISA image */ 3086 1.112.2.2 kent if (mask < 0x0100) { 3087 1.112.2.2 kent mask = 0x3ff; 3088 1.112.2.2 kent addr = 0x300; 3089 1.112.2.2 kent } 3090 1.112.2.2 kent 3091 1.112.2.2 kent } else { 3092 1.112.2.2 kent DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3093 1.112.2.2 kent "NOT used. io: 0x%lx, mem: 0x%lx\n", 3094 1.112.2.2 kent (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3095 1.112.2.2 kent (unsigned long)sc->sc_memt)); 3096 1.112.2.2 kent return 1; 3097 1.112.2.2 kent /* XXX: panic here? */ 3098 1.112.2.2 kent } 3099 1.112.2.2 kent 3100 1.112.2.2 kent if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3101 1.112.2.2 kent printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3102 1.112.2.2 kent return 1; 3103 1.112.2.2 kent } 3104 1.112.2.2 kent 3105 1.112.2.2 kent pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3106 1.112.2.2 kent 3107 1.112.2.2 kent return 0; 3108 1.112.2.2 kent } 3109 1.112.2.2 kent 3110 1.112.2.2 kent /* 3111 1.112.2.2 kent * static int 3112 1.112.2.2 kent * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3113 1.112.2.2 kent * bus_space_handle_t *bshp, bus_size_t size); 3114 1.112.2.2 kent * 3115 1.112.2.2 kent * This function is called from CardBus card drivers. 3116 1.112.2.2 kent */ 3117 1.112.2.2 kent static int 3118 1.112.2.2 kent pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3119 1.112.2.2 kent cardbus_chipset_tag_t ct; 3120 1.112.2.2 kent rbus_tag_t rb; 3121 1.112.2.2 kent bus_space_handle_t bsh; 3122 1.112.2.2 kent bus_size_t size; 3123 1.112.2.2 kent { 3124 1.112.2.2 kent struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3125 1.112.2.2 kent bus_space_tag_t bt = rb->rb_bt; 3126 1.112.2.2 kent 3127 1.112.2.2 kent pccbb_close_win(sc, bt, bsh, size); 3128 1.112.2.2 kent 3129 1.112.2.2 kent if (bt == sc->sc_memt) { 3130 1.112.2.2 kent } else if (bt == sc->sc_iot) { 3131 1.112.2.2 kent } else { 3132 1.112.2.2 kent return 1; 3133 1.112.2.2 kent /* XXX: panic here? */ 3134 1.112.2.2 kent } 3135 1.112.2.2 kent 3136 1.112.2.2 kent return rbus_space_free(rb, bsh, size, NULL); 3137 1.112.2.2 kent } 3138 1.112.2.2 kent #endif /* rbus */ 3139 1.112.2.2 kent 3140 1.112.2.2 kent #if rbus 3141 1.112.2.2 kent 3142 1.112.2.2 kent static int 3143 1.112.2.2 kent pccbb_open_win(sc, bst, addr, size, bsh, flags) 3144 1.112.2.2 kent struct pccbb_softc *sc; 3145 1.112.2.2 kent bus_space_tag_t bst; 3146 1.112.2.2 kent bus_addr_t addr; 3147 1.112.2.2 kent bus_size_t size; 3148 1.112.2.2 kent bus_space_handle_t bsh; 3149 1.112.2.2 kent int flags; 3150 1.112.2.2 kent { 3151 1.112.2.2 kent struct pccbb_win_chain_head *head; 3152 1.112.2.2 kent bus_addr_t align; 3153 1.112.2.2 kent 3154 1.112.2.2 kent head = &sc->sc_iowindow; 3155 1.112.2.2 kent align = 0x04; 3156 1.112.2.2 kent if (sc->sc_memt == bst) { 3157 1.112.2.2 kent head = &sc->sc_memwindow; 3158 1.112.2.2 kent align = 0x1000; 3159 1.112.2.2 kent DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3160 1.112.2.2 kent (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3161 1.112.2.2 kent (unsigned long)bst)); 3162 1.112.2.2 kent } 3163 1.112.2.2 kent 3164 1.112.2.2 kent if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3165 1.112.2.2 kent printf("%s: pccbb_open_win: %s winlist insert failed\n", 3166 1.112.2.2 kent sc->sc_dev.dv_xname, 3167 1.112.2.2 kent (head == &sc->sc_memwindow) ? "mem" : "io"); 3168 1.112.2.2 kent } 3169 1.112.2.2 kent pccbb_winset(align, sc, bst); 3170 1.112.2.2 kent 3171 1.112.2.2 kent return 0; 3172 1.112.2.2 kent } 3173 1.112.2.2 kent 3174 1.112.2.2 kent static int 3175 1.112.2.2 kent pccbb_close_win(sc, bst, bsh, size) 3176 1.112.2.2 kent struct pccbb_softc *sc; 3177 1.112.2.2 kent bus_space_tag_t bst; 3178 1.112.2.2 kent bus_space_handle_t bsh; 3179 1.112.2.2 kent bus_size_t size; 3180 1.112.2.2 kent { 3181 1.112.2.2 kent struct pccbb_win_chain_head *head; 3182 1.112.2.2 kent bus_addr_t align; 3183 1.112.2.2 kent 3184 1.112.2.2 kent head = &sc->sc_iowindow; 3185 1.112.2.2 kent align = 0x04; 3186 1.112.2.2 kent if (sc->sc_memt == bst) { 3187 1.112.2.2 kent head = &sc->sc_memwindow; 3188 1.112.2.2 kent align = 0x1000; 3189 1.112.2.2 kent } 3190 1.112.2.2 kent 3191 1.112.2.2 kent if (pccbb_winlist_delete(head, bsh, size)) { 3192 1.112.2.2 kent printf("%s: pccbb_close_win: %s winlist delete failed\n", 3193 1.112.2.2 kent sc->sc_dev.dv_xname, 3194 1.112.2.2 kent (head == &sc->sc_memwindow) ? "mem" : "io"); 3195 1.112.2.2 kent } 3196 1.112.2.2 kent pccbb_winset(align, sc, bst); 3197 1.112.2.2 kent 3198 1.112.2.2 kent return 0; 3199 1.112.2.2 kent } 3200 1.112.2.2 kent 3201 1.112.2.2 kent static int 3202 1.112.2.2 kent pccbb_winlist_insert(head, start, size, bsh, flags) 3203 1.112.2.2 kent struct pccbb_win_chain_head *head; 3204 1.112.2.2 kent bus_addr_t start; 3205 1.112.2.2 kent bus_size_t size; 3206 1.112.2.2 kent bus_space_handle_t bsh; 3207 1.112.2.2 kent int flags; 3208 1.112.2.2 kent { 3209 1.112.2.2 kent struct pccbb_win_chain *chainp, *elem; 3210 1.112.2.2 kent 3211 1.112.2.2 kent if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3212 1.112.2.2 kent M_NOWAIT)) == NULL) 3213 1.112.2.2 kent return (1); /* fail */ 3214 1.112.2.2 kent 3215 1.112.2.2 kent elem->wc_start = start; 3216 1.112.2.2 kent elem->wc_end = start + (size - 1); 3217 1.112.2.2 kent elem->wc_handle = bsh; 3218 1.112.2.2 kent elem->wc_flags = flags; 3219 1.112.2.2 kent 3220 1.112.2.2 kent for (chainp = TAILQ_FIRST(head); chainp != NULL; 3221 1.112.2.2 kent chainp = TAILQ_NEXT(chainp, wc_list)) { 3222 1.112.2.2 kent if (chainp->wc_end < start) 3223 1.112.2.2 kent continue; 3224 1.112.2.2 kent TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3225 1.112.2.2 kent return (0); 3226 1.112.2.2 kent } 3227 1.112.2.2 kent 3228 1.112.2.2 kent TAILQ_INSERT_TAIL(head, elem, wc_list); 3229 1.112.2.2 kent return (0); 3230 1.112.2.2 kent } 3231 1.112.2.2 kent 3232 1.112.2.2 kent static int 3233 1.112.2.2 kent pccbb_winlist_delete(head, bsh, size) 3234 1.112.2.2 kent struct pccbb_win_chain_head *head; 3235 1.112.2.2 kent bus_space_handle_t bsh; 3236 1.112.2.2 kent bus_size_t size; 3237 1.112.2.2 kent { 3238 1.112.2.2 kent struct pccbb_win_chain *chainp; 3239 1.112.2.2 kent 3240 1.112.2.2 kent for (chainp = TAILQ_FIRST(head); chainp != NULL; 3241 1.112.2.2 kent chainp = TAILQ_NEXT(chainp, wc_list)) { 3242 1.112.2.2 kent if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3243 1.112.2.2 kent continue; 3244 1.112.2.2 kent if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3245 1.112.2.2 kent printf("pccbb_winlist_delete: window 0x%lx size " 3246 1.112.2.2 kent "inconsistent: 0x%lx, 0x%lx\n", 3247 1.112.2.2 kent (unsigned long)chainp->wc_start, 3248 1.112.2.2 kent (unsigned long)(chainp->wc_end - chainp->wc_start), 3249 1.112.2.2 kent (unsigned long)(size - 1)); 3250 1.112.2.2 kent return 1; 3251 1.112.2.2 kent } 3252 1.112.2.2 kent 3253 1.112.2.2 kent TAILQ_REMOVE(head, chainp, wc_list); 3254 1.112.2.2 kent free(chainp, M_DEVBUF); 3255 1.112.2.2 kent 3256 1.112.2.2 kent return 0; 3257 1.112.2.2 kent } 3258 1.112.2.2 kent 3259 1.112.2.2 kent return 1; /* fail: no candidate to remove */ 3260 1.112.2.2 kent } 3261 1.112.2.2 kent 3262 1.112.2.2 kent static void 3263 1.112.2.2 kent pccbb_winset(align, sc, bst) 3264 1.112.2.2 kent bus_addr_t align; 3265 1.112.2.2 kent struct pccbb_softc *sc; 3266 1.112.2.2 kent bus_space_tag_t bst; 3267 1.112.2.2 kent { 3268 1.112.2.2 kent pci_chipset_tag_t pc; 3269 1.112.2.2 kent pcitag_t tag; 3270 1.112.2.2 kent bus_addr_t mask = ~(align - 1); 3271 1.112.2.2 kent struct { 3272 1.112.2.2 kent cardbusreg_t win_start; 3273 1.112.2.2 kent cardbusreg_t win_limit; 3274 1.112.2.2 kent int win_flags; 3275 1.112.2.2 kent } win[2]; 3276 1.112.2.2 kent struct pccbb_win_chain *chainp; 3277 1.112.2.2 kent int offs; 3278 1.112.2.2 kent 3279 1.112.2.2 kent win[0].win_start = win[1].win_start = 0xffffffff; 3280 1.112.2.2 kent win[0].win_limit = win[1].win_limit = 0; 3281 1.112.2.2 kent win[0].win_flags = win[1].win_flags = 0; 3282 1.112.2.2 kent 3283 1.112.2.2 kent chainp = TAILQ_FIRST(&sc->sc_iowindow); 3284 1.112.2.2 kent offs = 0x2c; 3285 1.112.2.2 kent if (sc->sc_memt == bst) { 3286 1.112.2.2 kent chainp = TAILQ_FIRST(&sc->sc_memwindow); 3287 1.112.2.2 kent offs = 0x1c; 3288 1.112.2.2 kent } 3289 1.112.2.2 kent 3290 1.112.2.2 kent if (chainp != NULL) { 3291 1.112.2.2 kent win[0].win_start = chainp->wc_start & mask; 3292 1.112.2.2 kent win[0].win_limit = chainp->wc_end & mask; 3293 1.112.2.2 kent win[0].win_flags = chainp->wc_flags; 3294 1.112.2.2 kent chainp = TAILQ_NEXT(chainp, wc_list); 3295 1.112.2.2 kent } 3296 1.112.2.2 kent 3297 1.112.2.2 kent for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3298 1.112.2.2 kent if (win[1].win_start == 0xffffffff) { 3299 1.112.2.2 kent /* window 1 is not used */ 3300 1.112.2.2 kent if ((win[0].win_flags == chainp->wc_flags) && 3301 1.112.2.2 kent (win[0].win_limit + align >= 3302 1.112.2.2 kent (chainp->wc_start & mask))) { 3303 1.112.2.2 kent /* concatenate */ 3304 1.112.2.2 kent win[0].win_limit = chainp->wc_end & mask; 3305 1.112.2.2 kent } else { 3306 1.112.2.2 kent /* make new window */ 3307 1.112.2.2 kent win[1].win_start = chainp->wc_start & mask; 3308 1.112.2.2 kent win[1].win_limit = chainp->wc_end & mask; 3309 1.112.2.2 kent win[1].win_flags = chainp->wc_flags; 3310 1.112.2.2 kent } 3311 1.112.2.2 kent continue; 3312 1.112.2.2 kent } 3313 1.112.2.2 kent 3314 1.112.2.2 kent /* Both windows are engaged. */ 3315 1.112.2.2 kent if (win[0].win_flags == win[1].win_flags) { 3316 1.112.2.2 kent /* same flags */ 3317 1.112.2.2 kent if (win[0].win_flags == chainp->wc_flags) { 3318 1.112.2.2 kent if (win[1].win_start - (win[0].win_limit + 3319 1.112.2.2 kent align) < 3320 1.112.2.2 kent (chainp->wc_start & mask) - 3321 1.112.2.2 kent ((chainp->wc_end & mask) + align)) { 3322 1.112.2.2 kent /* 3323 1.112.2.2 kent * merge window 0 and 1, and set win1 3324 1.112.2.2 kent * to chainp 3325 1.112.2.2 kent */ 3326 1.112.2.2 kent win[0].win_limit = win[1].win_limit; 3327 1.112.2.2 kent win[1].win_start = 3328 1.112.2.2 kent chainp->wc_start & mask; 3329 1.112.2.2 kent win[1].win_limit = 3330 1.112.2.2 kent chainp->wc_end & mask; 3331 1.112.2.2 kent } else { 3332 1.112.2.2 kent win[1].win_limit = 3333 1.112.2.2 kent chainp->wc_end & mask; 3334 1.112.2.2 kent } 3335 1.112.2.2 kent } else { 3336 1.112.2.2 kent /* different flags */ 3337 1.112.2.2 kent 3338 1.112.2.2 kent /* concatenate win0 and win1 */ 3339 1.112.2.2 kent win[0].win_limit = win[1].win_limit; 3340 1.112.2.2 kent /* allocate win[1] to new space */ 3341 1.112.2.2 kent win[1].win_start = chainp->wc_start & mask; 3342 1.112.2.2 kent win[1].win_limit = chainp->wc_end & mask; 3343 1.112.2.2 kent win[1].win_flags = chainp->wc_flags; 3344 1.112.2.2 kent } 3345 1.112.2.2 kent } else { 3346 1.112.2.2 kent /* the flags of win[0] and win[1] is different */ 3347 1.112.2.2 kent if (win[0].win_flags == chainp->wc_flags) { 3348 1.112.2.2 kent win[0].win_limit = chainp->wc_end & mask; 3349 1.112.2.2 kent /* 3350 1.112.2.2 kent * XXX this creates overlapping windows, so 3351 1.112.2.2 kent * what should the poor bridge do if one is 3352 1.112.2.2 kent * cachable, and the other is not? 3353 1.112.2.2 kent */ 3354 1.112.2.2 kent printf("%s: overlapping windows\n", 3355 1.112.2.2 kent sc->sc_dev.dv_xname); 3356 1.112.2.2 kent } else { 3357 1.112.2.2 kent win[1].win_limit = chainp->wc_end & mask; 3358 1.112.2.2 kent } 3359 1.112.2.2 kent } 3360 1.112.2.2 kent } 3361 1.112.2.2 kent 3362 1.112.2.2 kent pc = sc->sc_pc; 3363 1.112.2.2 kent tag = sc->sc_tag; 3364 1.112.2.2 kent pci_conf_write(pc, tag, offs, win[0].win_start); 3365 1.112.2.2 kent pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3366 1.112.2.2 kent pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3367 1.112.2.2 kent pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3368 1.112.2.2 kent DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3369 1.112.2.2 kent (unsigned long)pci_conf_read(pc, tag, offs), 3370 1.112.2.2 kent (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3371 1.112.2.2 kent (unsigned long)pci_conf_read(pc, tag, offs + 8), 3372 1.112.2.2 kent (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3373 1.112.2.2 kent 3374 1.112.2.2 kent if (bst == sc->sc_memt) { 3375 1.112.2.2 kent pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3376 1.112.2.2 kent 3377 1.112.2.2 kent bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3378 1.112.2.2 kent if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3379 1.112.2.2 kent bcr |= CB_BCR_PREFETCH_MEMWIN0; 3380 1.112.2.2 kent if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3381 1.112.2.2 kent bcr |= CB_BCR_PREFETCH_MEMWIN1; 3382 1.112.2.2 kent pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3383 1.112.2.2 kent } 3384 1.112.2.2 kent } 3385 1.112.2.2 kent 3386 1.112.2.2 kent #endif /* rbus */ 3387 1.112.2.2 kent 3388 1.112.2.2 kent static void 3389 1.112.2.2 kent pccbb_powerhook(why, arg) 3390 1.112.2.2 kent int why; 3391 1.112.2.2 kent void *arg; 3392 1.112.2.2 kent { 3393 1.112.2.2 kent struct pccbb_softc *sc = arg; 3394 1.112.2.2 kent pcireg_t reg; 3395 1.112.2.2 kent bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3396 1.112.2.2 kent bus_space_handle_t base_memh = sc->sc_base_memh; 3397 1.112.2.2 kent 3398 1.112.2.2 kent DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3399 1.112.2.2 kent 3400 1.112.2.2 kent if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3401 1.112.2.2 kent DPRINTF(("%s: power: why %d stopping intr\n", 3402 1.112.2.2 kent sc->sc_dev.dv_xname, why)); 3403 1.112.2.2 kent if (sc->sc_pil_intr_enable) { 3404 1.112.2.2 kent (void)pccbbintr_function(sc); 3405 1.112.2.2 kent } 3406 1.112.2.2 kent sc->sc_pil_intr_enable = 0; 3407 1.112.2.2 kent 3408 1.112.2.2 kent pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3409 1.112.2.2 kent 3410 1.112.2.2 kent /* ToDo: deactivate or suspend child devices */ 3411 1.112.2.2 kent 3412 1.112.2.2 kent } 3413 1.112.2.2 kent 3414 1.112.2.2 kent if (why == PWR_RESUME) { 3415 1.112.2.2 kent if (sc->sc_pwrmgt_offs != 0) { 3416 1.112.2.2 kent reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3417 1.112.2.2 kent sc->sc_pwrmgt_offs + 4); 3418 1.112.2.2 kent if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3419 1.112.2.2 kent reg & 0x100) { 3420 1.112.2.2 kent /* powrstate != D0 */ 3421 1.112.2.2 kent 3422 1.112.2.2 kent printf("%s going back to D0 mode\n", 3423 1.112.2.2 kent sc->sc_dev.dv_xname); 3424 1.112.2.2 kent reg &= ~PCI_PMCSR_STATE_MASK; 3425 1.112.2.2 kent reg |= PCI_PMCSR_STATE_D0; 3426 1.112.2.2 kent reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3427 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, 3428 1.112.2.2 kent sc->sc_pwrmgt_offs + 4, reg); 3429 1.112.2.2 kent 3430 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, 3431 1.112.2.2 kent PCI_SOCKBASE, sc->sc_sockbase); 3432 1.112.2.2 kent pci_conf_write(sc->sc_pc, sc->sc_tag, 3433 1.112.2.2 kent PCI_BUSNUM, sc->sc_busnum); 3434 1.112.2.2 kent pccbb_chipinit(sc); 3435 1.112.2.2 kent /* setup memory and io space window for CB */ 3436 1.112.2.2 kent pccbb_winset(0x1000, sc, sc->sc_memt); 3437 1.112.2.2 kent pccbb_winset(0x04, sc, sc->sc_iot); 3438 1.112.2.2 kent goto norestore; 3439 1.112.2.2 kent } 3440 1.112.2.2 kent } 3441 1.112.2.2 kent pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3442 1.112.2.2 kent norestore: 3443 1.112.2.2 kent 3444 1.112.2.2 kent if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3445 1.112.2.2 kent /* BIOS did not recover this register */ 3446 1.112.2.2 kent pci_conf_write (sc->sc_pc, sc->sc_tag, 3447 1.112.2.2 kent PCI_SOCKBASE, sc->sc_sockbase); 3448 1.112.2.2 kent if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3449 1.112.2.2 kent /* BIOS did not recover this register */ 3450 1.112.2.2 kent pci_conf_write (sc->sc_pc, sc->sc_tag, 3451 1.112.2.2 kent PCI_BUSNUM, sc->sc_busnum); 3452 1.112.2.2 kent /* CSC Interrupt: Card detect interrupt on */ 3453 1.112.2.2 kent reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3454 1.112.2.2 kent /* Card detect intr is turned on. */ 3455 1.112.2.2 kent reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3456 1.112.2.2 kent bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3457 1.112.2.2 kent /* reset interrupt */ 3458 1.112.2.2 kent reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3459 1.112.2.2 kent bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3460 1.112.2.2 kent 3461 1.112.2.2 kent /* 3462 1.112.2.2 kent * check for card insertion or removal during suspend period. 3463 1.112.2.2 kent * XXX: the code can't cope with card swap (remove then 3464 1.112.2.2 kent * insert). how can we detect such situation? 3465 1.112.2.2 kent */ 3466 1.112.2.2 kent (void)pccbbintr(sc); 3467 1.112.2.2 kent 3468 1.112.2.2 kent sc->sc_pil_intr_enable = 1; 3469 1.112.2.2 kent DPRINTF(("%s: power: RESUME enabling intr\n", 3470 1.112.2.2 kent sc->sc_dev.dv_xname)); 3471 1.112.2.2 kent 3472 1.112.2.2 kent /* ToDo: activate or wakeup child devices */ 3473 1.112.2.2 kent } 3474 1.112.2.2 kent } 3475
Indexes created Tue Oct 21 19:09:51 GMT 2025