pccbb.c revision 1.3.2.9 1 1.3.2.9 bouyer /* $NetBSD: pccbb.c,v 1.3.2.9 2001/03/12 13:31:09 bouyer Exp $ */
2 1.2 haya
3 1.1 haya /*
4 1.3.2.2 bouyer * Copyright (c) 1998, 1999 and 2000
5 1.3.2.2 bouyer * HAYAKAWA Koichi. All rights reserved.
6 1.1 haya *
7 1.1 haya * Redistribution and use in source and binary forms, with or without
8 1.1 haya * modification, are permitted provided that the following conditions
9 1.1 haya * are met:
10 1.1 haya * 1. Redistributions of source code must retain the above copyright
11 1.1 haya * notice, this list of conditions and the following disclaimer.
12 1.1 haya * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 haya * notice, this list of conditions and the following disclaimer in the
14 1.1 haya * documentation and/or other materials provided with the distribution.
15 1.1 haya * 3. All advertising materials mentioning features or use of this software
16 1.1 haya * must display the following acknowledgement:
17 1.1 haya * This product includes software developed by HAYAKAWA Koichi.
18 1.1 haya * 4. The name of the author may not be used to endorse or promote products
19 1.1 haya * derived from this software without specific prior written permission.
20 1.1 haya *
21 1.1 haya * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 1.1 haya * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 1.1 haya * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 1.1 haya * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 1.1 haya * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 1.1 haya * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 1.1 haya * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 1.1 haya * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 1.1 haya * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 1.1 haya * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 1.1 haya */
32 1.1 haya
33 1.1 haya /*
34 1.1 haya #define CBB_DEBUG
35 1.1 haya #define SHOW_REGS
36 1.1 haya #define PCCBB_PCMCIA_POLL
37 1.1 haya */
38 1.1 haya /* #define CBB_DEBUG */
39 1.1 haya
40 1.1 haya /*
41 1.1 haya #define CB_PCMCIA_POLL
42 1.1 haya #define CB_PCMCIA_POLL_ONLY
43 1.1 haya #define LEVEL2
44 1.1 haya */
45 1.1 haya
46 1.1 haya #include <sys/types.h>
47 1.1 haya #include <sys/param.h>
48 1.1 haya #include <sys/systm.h>
49 1.1 haya #include <sys/kernel.h>
50 1.1 haya #include <sys/errno.h>
51 1.1 haya #include <sys/ioctl.h>
52 1.3.2.8 bouyer #include <sys/reboot.h> /* for bootverbose */
53 1.1 haya #include <sys/syslog.h>
54 1.1 haya #include <sys/device.h>
55 1.1 haya #include <sys/malloc.h>
56 1.3.2.8 bouyer #include <sys/proc.h>
57 1.1 haya
58 1.1 haya #include <machine/intr.h>
59 1.1 haya #include <machine/bus.h>
60 1.1 haya
61 1.1 haya #include <dev/pci/pcivar.h>
62 1.1 haya #include <dev/pci/pcireg.h>
63 1.1 haya #include <dev/pci/pcidevs.h>
64 1.1 haya
65 1.1 haya #include <dev/pci/pccbbreg.h>
66 1.1 haya
67 1.1 haya #include <dev/cardbus/cardslotvar.h>
68 1.1 haya
69 1.1 haya #include <dev/cardbus/cardbusvar.h>
70 1.1 haya
71 1.1 haya #include <dev/pcmcia/pcmciareg.h>
72 1.1 haya #include <dev/pcmcia/pcmciavar.h>
73 1.1 haya
74 1.1 haya #include <dev/ic/i82365reg.h>
75 1.1 haya #include <dev/ic/i82365var.h>
76 1.1 haya #include <dev/pci/pccbbvar.h>
77 1.1 haya
78 1.1 haya #include "locators.h"
79 1.1 haya
80 1.1 haya #ifndef __NetBSD_Version__
81 1.1 haya struct cfdriver cbb_cd = {
82 1.3.2.2 bouyer NULL, "cbb", DV_DULL
83 1.1 haya };
84 1.1 haya #endif
85 1.1 haya
86 1.1 haya #if defined CBB_DEBUG
87 1.1 haya #define DPRINTF(x) printf x
88 1.1 haya #define STATIC
89 1.1 haya #else
90 1.1 haya #define DPRINTF(x)
91 1.1 haya #define STATIC static
92 1.1 haya #endif
93 1.1 haya
94 1.3.2.8 bouyer /*
95 1.3.2.8 bouyer * DELAY_MS() is a wait millisecond. It shall use instead of delay()
96 1.3.2.8 bouyer * if you want to wait more than 1 ms.
97 1.3.2.8 bouyer */
98 1.3.2.8 bouyer #define DELAY_MS(time, param) \
99 1.3.2.8 bouyer do { \
100 1.3.2.8 bouyer if (cold == 0) { \
101 1.3.2.8 bouyer int tick = (hz*(time))/1000; \
102 1.3.2.8 bouyer \
103 1.3.2.8 bouyer if (tick <= 1) { \
104 1.3.2.8 bouyer tick = 2; \
105 1.3.2.8 bouyer } \
106 1.3.2.8 bouyer tsleep((void *)(param), PCATCH, "pccbb", tick); \
107 1.3.2.8 bouyer } else { \
108 1.3.2.8 bouyer delay((time)*1000); \
109 1.3.2.8 bouyer } \
110 1.3.2.8 bouyer } while (0)
111 1.3.2.8 bouyer
112 1.1 haya int pcicbbmatch __P((struct device *, struct cfdata *, void *));
113 1.1 haya void pccbbattach __P((struct device *, struct device *, void *));
114 1.1 haya int pccbbintr __P((void *));
115 1.1 haya static void pci113x_insert __P((void *));
116 1.3.2.2 bouyer static int pccbbintr_function __P((struct pccbb_softc *));
117 1.1 haya
118 1.1 haya static int pccbb_detect_card __P((struct pccbb_softc *));
119 1.1 haya
120 1.1 haya static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t));
121 1.1 haya static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int));
122 1.1 haya #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg)))
123 1.1 haya #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val)))
124 1.1 haya
125 1.1 haya STATIC int cb_reset __P((struct pccbb_softc *));
126 1.1 haya STATIC int cb_detect_voltage __P((struct pccbb_softc *));
127 1.1 haya STATIC int cbbprint __P((void *, const char *));
128 1.1 haya
129 1.3.2.2 bouyer static int cb_chipset __P((u_int32_t, int *));
130 1.3.2.2 bouyer STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *,
131 1.3.2.2 bouyer struct pcmciabus_attach_args *));
132 1.1 haya #if 0
133 1.1 haya STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *));
134 1.1 haya STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int));
135 1.1 haya STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *));
136 1.1 haya #endif
137 1.1 haya
138 1.1 haya STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int));
139 1.1 haya STATIC int pccbb_power __P((cardbus_chipset_tag_t, int));
140 1.3.2.2 bouyer STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function));
141 1.1 haya #if !rbus
142 1.3.2.2 bouyer static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t,
143 1.3.2.2 bouyer u_int32_t));
144 1.1 haya static int pccbb_io_close __P((cardbus_chipset_tag_t, int));
145 1.3.2.2 bouyer static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t,
146 1.3.2.2 bouyer u_int32_t));
147 1.1 haya static int pccbb_mem_close __P((cardbus_chipset_tag_t, int));
148 1.1 haya #endif /* !rbus */
149 1.3.2.2 bouyer static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq,
150 1.3.2.2 bouyer int level, int (*ih) (void *), void *sc));
151 1.3.2.2 bouyer static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih));
152 1.3.2.2 bouyer
153 1.3.2.2 bouyer static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq,
154 1.3.2.2 bouyer int level, int (*ih) (void *), void *sc));
155 1.3.2.2 bouyer static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih));
156 1.1 haya
157 1.1 haya static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int));
158 1.1 haya static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t));
159 1.3.2.2 bouyer static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t,
160 1.3.2.2 bouyer int));
161 1.3.2.2 bouyer static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int,
162 1.3.2.2 bouyer cardbusreg_t));
163 1.1 haya static void pccbb_chipinit __P((struct pccbb_softc *));
164 1.1 haya
165 1.1 haya STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t,
166 1.3.2.2 bouyer struct pcmcia_mem_handle *));
167 1.1 haya STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t,
168 1.3.2.2 bouyer struct pcmcia_mem_handle *));
169 1.1 haya STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t,
170 1.3.2.2 bouyer bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *));
171 1.1 haya STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int));
172 1.1 haya STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t,
173 1.3.2.2 bouyer bus_size_t, bus_size_t, struct pcmcia_io_handle *));
174 1.1 haya STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t,
175 1.3.2.2 bouyer struct pcmcia_io_handle *));
176 1.1 haya STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t,
177 1.3.2.2 bouyer bus_size_t, struct pcmcia_io_handle *, int *));
178 1.1 haya STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int));
179 1.1 haya STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t,
180 1.3.2.2 bouyer struct pcmcia_function *, int, int (*)(void *), void *));
181 1.3.2.2 bouyer STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t,
182 1.3.2.2 bouyer void *));
183 1.1 haya STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t));
184 1.1 haya STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t));
185 1.1 haya STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch));
186 1.1 haya
187 1.1 haya static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int));
188 1.1 haya static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *));
189 1.1 haya static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int));
190 1.3.2.2 bouyer static void pccbb_powerhook __P((int, void *));
191 1.1 haya
192 1.3.2.2 bouyer /* bus-space allocation and deallocation functions */
193 1.1 haya #if rbus
194 1.1 haya
195 1.1 haya static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t,
196 1.3.2.2 bouyer bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align,
197 1.3.2.2 bouyer int flags, bus_addr_t * addrp, bus_space_handle_t * bshp));
198 1.1 haya static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t,
199 1.3.2.2 bouyer bus_space_handle_t, bus_size_t));
200 1.1 haya
201 1.1 haya #endif /* rbus */
202 1.1 haya
203 1.1 haya #if rbus
204 1.1 haya
205 1.3.2.2 bouyer static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t,
206 1.3.2.2 bouyer bus_addr_t, bus_size_t, bus_space_handle_t, int flags));
207 1.3.2.2 bouyer static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t,
208 1.3.2.2 bouyer bus_space_handle_t, bus_size_t));
209 1.3.2.2 bouyer static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t,
210 1.3.2.2 bouyer bus_size_t, bus_space_handle_t, int));
211 1.3.2.2 bouyer static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *,
212 1.3.2.2 bouyer bus_space_handle_t, bus_size_t));
213 1.1 haya static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *,
214 1.3.2.2 bouyer bus_space_tag_t));
215 1.1 haya void pccbb_winlist_show(struct pccbb_win_chain *);
216 1.1 haya
217 1.1 haya #endif /* rbus */
218 1.1 haya
219 1.1 haya /* for config_defer */
220 1.1 haya static void pccbb_pci_callback __P((struct device *));
221 1.1 haya
222 1.1 haya #if defined SHOW_REGS
223 1.3.2.2 bouyer static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag,
224 1.3.2.2 bouyer bus_space_tag_t memt, bus_space_handle_t memh));
225 1.1 haya #endif
226 1.1 haya
227 1.1 haya struct cfattach cbb_pci_ca = {
228 1.1 haya sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach
229 1.1 haya };
230 1.1 haya
231 1.1 haya static struct pcmcia_chip_functions pccbb_pcmcia_funcs = {
232 1.3.2.2 bouyer pccbb_pcmcia_mem_alloc,
233 1.3.2.2 bouyer pccbb_pcmcia_mem_free,
234 1.3.2.2 bouyer pccbb_pcmcia_mem_map,
235 1.3.2.2 bouyer pccbb_pcmcia_mem_unmap,
236 1.3.2.2 bouyer pccbb_pcmcia_io_alloc,
237 1.3.2.2 bouyer pccbb_pcmcia_io_free,
238 1.3.2.2 bouyer pccbb_pcmcia_io_map,
239 1.3.2.2 bouyer pccbb_pcmcia_io_unmap,
240 1.3.2.2 bouyer pccbb_pcmcia_intr_establish,
241 1.3.2.2 bouyer pccbb_pcmcia_intr_disestablish,
242 1.3.2.2 bouyer pccbb_pcmcia_socket_enable,
243 1.3.2.2 bouyer pccbb_pcmcia_socket_disable,
244 1.3.2.2 bouyer pccbb_pcmcia_card_detect
245 1.1 haya };
246 1.1 haya
247 1.1 haya #if rbus
248 1.1 haya static struct cardbus_functions pccbb_funcs = {
249 1.3.2.2 bouyer pccbb_rbus_cb_space_alloc,
250 1.3.2.2 bouyer pccbb_rbus_cb_space_free,
251 1.3.2.2 bouyer pccbb_cb_intr_establish,
252 1.3.2.2 bouyer pccbb_cb_intr_disestablish,
253 1.3.2.2 bouyer pccbb_ctrl,
254 1.3.2.2 bouyer pccbb_power,
255 1.3.2.2 bouyer pccbb_make_tag,
256 1.3.2.2 bouyer pccbb_free_tag,
257 1.3.2.2 bouyer pccbb_conf_read,
258 1.3.2.2 bouyer pccbb_conf_write,
259 1.1 haya };
260 1.1 haya #else
261 1.1 haya static struct cardbus_functions pccbb_funcs = {
262 1.3.2.2 bouyer pccbb_ctrl,
263 1.3.2.2 bouyer pccbb_power,
264 1.3.2.2 bouyer pccbb_mem_open,
265 1.3.2.2 bouyer pccbb_mem_close,
266 1.3.2.2 bouyer pccbb_io_open,
267 1.3.2.2 bouyer pccbb_io_close,
268 1.3.2.2 bouyer pccbb_cb_intr_establish,
269 1.3.2.2 bouyer pccbb_cb_intr_disestablish,
270 1.3.2.2 bouyer pccbb_make_tag,
271 1.3.2.2 bouyer pccbb_conf_read,
272 1.3.2.2 bouyer pccbb_conf_write,
273 1.1 haya };
274 1.1 haya #endif
275 1.1 haya
276 1.1 haya int
277 1.1 haya pcicbbmatch(parent, match, aux)
278 1.3.2.2 bouyer struct device *parent;
279 1.3.2.2 bouyer struct cfdata *match;
280 1.3.2.2 bouyer void *aux;
281 1.3.2.2 bouyer {
282 1.3.2.2 bouyer struct pci_attach_args *pa = (struct pci_attach_args *)aux;
283 1.3.2.2 bouyer
284 1.3.2.2 bouyer if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
285 1.3.2.2 bouyer PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS &&
286 1.3.2.2 bouyer PCI_INTERFACE(pa->pa_class) == 0) {
287 1.3.2.2 bouyer return 1;
288 1.3.2.2 bouyer }
289 1.1 haya
290 1.3.2.2 bouyer return 0;
291 1.1 haya }
292 1.1 haya
293 1.1 haya #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \
294 1.1 haya | ((prod) << PCI_PRODUCT_SHIFT))
295 1.1 haya
296 1.3.2.9 bouyer const struct yenta_chipinfo {
297 1.3.2.2 bouyer pcireg_t yc_id; /* vendor tag | product tag */
298 1.3.2.2 bouyer int yc_chiptype;
299 1.3.2.2 bouyer int yc_flags;
300 1.1 haya } yc_chipsets[] = {
301 1.3.2.2 bouyer /* Texas Instruments chips */
302 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X,
303 1.3.2.2 bouyer PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
304 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X,
305 1.3.2.2 bouyer PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
306 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX,
307 1.3.2.2 bouyer PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
308 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX,
309 1.3.2.2 bouyer PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
310 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX,
311 1.3.2.2 bouyer PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
312 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX,
313 1.3.2.2 bouyer PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
314 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX,
315 1.3.2.2 bouyer PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
316 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX,
317 1.3.2.2 bouyer PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
318 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX,
319 1.3.2.2 bouyer PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
320 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX,
321 1.3.2.2 bouyer PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
322 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX,
323 1.3.2.2 bouyer PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
324 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX,
325 1.3.2.2 bouyer PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
326 1.3.2.2 bouyer
327 1.3.2.2 bouyer /* Ricoh chips */
328 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X,
329 1.3.2.2 bouyer PCCBB_PCMCIA_MEM_32},
330 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X,
331 1.3.2.2 bouyer PCCBB_PCMCIA_MEM_32},
332 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X,
333 1.3.2.2 bouyer PCCBB_PCMCIA_MEM_32},
334 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X,
335 1.3.2.2 bouyer PCCBB_PCMCIA_MEM_32},
336 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X,
337 1.3.2.2 bouyer PCCBB_PCMCIA_MEM_32},
338 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X,
339 1.3.2.2 bouyer PCCBB_PCMCIA_MEM_32},
340 1.3.2.2 bouyer
341 1.3.2.2 bouyer /* Toshiba products */
342 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95),
343 1.3.2.2 bouyer CB_TOPIC95, PCCBB_PCMCIA_MEM_32},
344 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B),
345 1.3.2.2 bouyer CB_TOPIC95B, PCCBB_PCMCIA_MEM_32},
346 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97),
347 1.3.2.2 bouyer CB_TOPIC97, PCCBB_PCMCIA_MEM_32},
348 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100),
349 1.3.2.2 bouyer CB_TOPIC97, PCCBB_PCMCIA_MEM_32},
350 1.3.2.2 bouyer
351 1.3.2.2 bouyer /* Cirrus Logic products */
352 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832),
353 1.3.2.2 bouyer CB_CIRRUS, PCCBB_PCMCIA_MEM_32},
354 1.3.2.2 bouyer { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833),
355 1.3.2.2 bouyer CB_CIRRUS, PCCBB_PCMCIA_MEM_32},
356 1.1 haya
357 1.3.2.2 bouyer /* sentinel, or Generic chip */
358 1.3.2.2 bouyer { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32},
359 1.1 haya };
360 1.1 haya
361 1.1 haya static int
362 1.3.2.2 bouyer cb_chipset(pci_id, flagp)
363 1.3.2.2 bouyer u_int32_t pci_id;
364 1.3.2.2 bouyer int *flagp;
365 1.3.2.2 bouyer {
366 1.3.2.9 bouyer const struct yenta_chipinfo *yc;
367 1.3.2.2 bouyer
368 1.3.2.2 bouyer /* Loop over except the last default entry. */
369 1.3.2.2 bouyer for (yc = yc_chipsets; yc < yc_chipsets +
370 1.3.2.2 bouyer sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++)
371 1.3.2.2 bouyer if (pci_id == yc->yc_id)
372 1.3.2.2 bouyer break;
373 1.1 haya
374 1.3.2.2 bouyer if (flagp != NULL)
375 1.3.2.2 bouyer *flagp = yc->yc_flags;
376 1.1 haya
377 1.3.2.2 bouyer return (yc->yc_chiptype);
378 1.1 haya }
379 1.1 haya
380 1.3.2.2 bouyer static void
381 1.3.2.2 bouyer pccbb_shutdown(void *arg)
382 1.3.2.2 bouyer {
383 1.3.2.2 bouyer struct pccbb_softc *sc = arg;
384 1.3.2.2 bouyer pcireg_t command;
385 1.1 haya
386 1.3.2.2 bouyer DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname));
387 1.3.2.4 bouyer
388 1.3.2.5 bouyer /*
389 1.3.2.5 bouyer * turn off power
390 1.3.2.5 bouyer *
391 1.3.2.5 bouyer * XXX - do not turn off power if chipset is TI 113X because
392 1.3.2.5 bouyer * only TI 1130 with PowerMac 2400 hangs in pccbb_power().
393 1.3.2.5 bouyer */
394 1.3.2.5 bouyer if (sc->sc_chipset != CB_TI113X) {
395 1.3.2.5 bouyer pccbb_power((cardbus_chipset_tag_t)sc,
396 1.3.2.5 bouyer CARDBUS_VCC_0V | CARDBUS_VPP_0V);
397 1.3.2.5 bouyer }
398 1.3.2.4 bouyer
399 1.3.2.2 bouyer bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK,
400 1.3.2.2 bouyer 0);
401 1.1 haya
402 1.3.2.2 bouyer command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
403 1.1 haya
404 1.3.2.2 bouyer command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
405 1.3.2.2 bouyer PCI_COMMAND_MASTER_ENABLE);
406 1.3.2.2 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command);
407 1.3.2.2 bouyer
408 1.3.2.2 bouyer }
409 1.1 haya
410 1.1 haya void
411 1.1 haya pccbbattach(parent, self, aux)
412 1.3.2.2 bouyer struct device *parent;
413 1.3.2.2 bouyer struct device *self;
414 1.3.2.2 bouyer void *aux;
415 1.3.2.2 bouyer {
416 1.3.2.2 bouyer struct pccbb_softc *sc = (void *)self;
417 1.3.2.2 bouyer struct pci_attach_args *pa = aux;
418 1.3.2.2 bouyer pci_chipset_tag_t pc = pa->pa_pc;
419 1.3.2.2 bouyer pcireg_t busreg, reg, sock_base;
420 1.3.2.2 bouyer bus_addr_t sockbase;
421 1.3.2.2 bouyer char devinfo[256];
422 1.3.2.2 bouyer int flags;
423 1.3.2.2 bouyer
424 1.3.2.2 bouyer sc->sc_chipset = cb_chipset(pa->pa_id, &flags);
425 1.1 haya
426 1.3.2.2 bouyer pci_devinfo(pa->pa_id, 0, 0, devinfo);
427 1.3.2.2 bouyer printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class));
428 1.3.2.2 bouyer #ifdef CBB_DEBUG
429 1.3.2.2 bouyer printf(" (chipflags %x)", flags);
430 1.3.2.2 bouyer #endif
431 1.3.2.2 bouyer printf("\n");
432 1.3.2.2 bouyer
433 1.3.2.2 bouyer TAILQ_INIT(&sc->sc_memwindow);
434 1.3.2.2 bouyer TAILQ_INIT(&sc->sc_iowindow);
435 1.1 haya
436 1.1 haya #if rbus
437 1.3.2.2 bouyer sc->sc_rbus_iot = rbus_pccbb_parent_io(pa);
438 1.3.2.2 bouyer sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa);
439 1.1 haya #endif /* rbus */
440 1.1 haya
441 1.3.2.2 bouyer sc->sc_base_memh = 0;
442 1.1 haya
443 1.3.2.2 bouyer /*
444 1.3.2.2 bouyer * MAP socket registers and ExCA registers on memory-space
445 1.3.2.2 bouyer * When no valid address is set on socket base registers (on pci
446 1.3.2.2 bouyer * config space), get it not polite way.
447 1.3.2.2 bouyer */
448 1.3.2.2 bouyer sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE);
449 1.3.2.2 bouyer
450 1.3.2.2 bouyer if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 &&
451 1.3.2.2 bouyer PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) {
452 1.3.2.2 bouyer /* The address must be valid. */
453 1.3.2.2 bouyer if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0,
454 1.3.2.2 bouyer &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) {
455 1.3.2.2 bouyer printf("%s: can't map socket base address 0x%x\n",
456 1.3.2.2 bouyer sc->sc_dev.dv_xname, sock_base);
457 1.3.2.2 bouyer /*
458 1.3.2.2 bouyer * I think it's funny: socket base registers must be
459 1.3.2.2 bouyer * mapped on memory space, but ...
460 1.3.2.2 bouyer */
461 1.3.2.2 bouyer if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO,
462 1.3.2.2 bouyer 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase,
463 1.3.2.2 bouyer NULL)) {
464 1.3.2.2 bouyer printf("%s: can't map socket base address"
465 1.3.2.2 bouyer " 0x%lx: io mode\n", sc->sc_dev.dv_xname,
466 1.3.2.2 bouyer sockbase);
467 1.3.2.2 bouyer /* give up... allocate reg space via rbus. */
468 1.3.2.2 bouyer sc->sc_base_memh = 0;
469 1.3.2.2 bouyer pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0);
470 1.3.2.2 bouyer }
471 1.3.2.2 bouyer } else {
472 1.3.2.2 bouyer DPRINTF(("%s: socket base address 0x%lx\n",
473 1.3.2.2 bouyer sc->sc_dev.dv_xname, sockbase));
474 1.3.2.2 bouyer }
475 1.3.2.2 bouyer }
476 1.1 haya
477 1.3.2.2 bouyer sc->sc_mem_start = 0; /* XXX */
478 1.3.2.2 bouyer sc->sc_mem_end = 0xffffffff; /* XXX */
479 1.1 haya
480 1.3.2.2 bouyer /*
481 1.3.2.2 bouyer * When interrupt isn't routed correctly, give up probing cbb and do
482 1.3.2.2 bouyer * not kill pcic-compatible port.
483 1.3.2.2 bouyer */
484 1.3.2.2 bouyer if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) {
485 1.3.2.2 bouyer printf("%s: NOT USED because of unconfigured interrupt\n",
486 1.3.2.2 bouyer sc->sc_dev.dv_xname);
487 1.3.2.2 bouyer return;
488 1.3.2.2 bouyer }
489 1.1 haya
490 1.3.2.2 bouyer /*
491 1.3.2.2 bouyer * When bus number isn't set correctly, give up using 32-bit CardBus
492 1.3.2.2 bouyer * mode.
493 1.3.2.2 bouyer */
494 1.3.2.2 bouyer busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM);
495 1.3.2.1 thorpej #if notyet
496 1.3.2.2 bouyer if (((busreg >> 8) & 0xff) == 0) {
497 1.3.2.2 bouyer printf("%s: CardBus support disabled because of unconfigured bus number\n",
498 1.3.2.2 bouyer sc->sc_dev.dv_xname);
499 1.3.2.2 bouyer flags |= PCCBB_PCMCIA_16BITONLY;
500 1.3.2.2 bouyer }
501 1.3.2.1 thorpej #endif
502 1.3.2.1 thorpej
503 1.3.2.2 bouyer /* pccbb_machdep.c end */
504 1.1 haya
505 1.1 haya #if defined CBB_DEBUG
506 1.3.2.2 bouyer {
507 1.3.2.2 bouyer static char *intrname[5] = { "NON", "A", "B", "C", "D" };
508 1.3.2.2 bouyer printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname,
509 1.3.2.2 bouyer intrname[pa->pa_intrpin], pa->pa_intrline);
510 1.3.2.2 bouyer }
511 1.1 haya #endif
512 1.1 haya
513 1.3.2.2 bouyer /* setup softc */
514 1.3.2.2 bouyer sc->sc_pc = pc;
515 1.3.2.2 bouyer sc->sc_iot = pa->pa_iot;
516 1.3.2.2 bouyer sc->sc_memt = pa->pa_memt;
517 1.3.2.2 bouyer sc->sc_dmat = pa->pa_dmat;
518 1.3.2.2 bouyer sc->sc_tag = pa->pa_tag;
519 1.3.2.2 bouyer sc->sc_function = pa->pa_function;
520 1.3.2.9 bouyer sc->sc_sockbase = sock_base;
521 1.3.2.9 bouyer sc->sc_busnum = busreg;
522 1.3.2.2 bouyer
523 1.3.2.6 bouyer memcpy(&sc->sc_pa, pa, sizeof(*pa));
524 1.3.2.2 bouyer
525 1.3.2.2 bouyer sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */
526 1.3.2.2 bouyer
527 1.3.2.2 bouyer shutdownhook_establish(pccbb_shutdown, sc);
528 1.3.2.2 bouyer
529 1.3.2.2 bouyer /* Disable legacy register mapping. */
530 1.3.2.2 bouyer switch (sc->sc_chipset) {
531 1.3.2.2 bouyer case CB_RX5C46X: /* fallthrough */
532 1.3.2.2 bouyer #if 0
533 1.3.2.2 bouyer /* The RX5C47X-series requires writes to the PCI_LEGACY register. */
534 1.3.2.2 bouyer case CB_RX5C47X:
535 1.1 haya #endif
536 1.3.2.2 bouyer /*
537 1.3.2.2 bouyer * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges
538 1.3.2.2 bouyer * cannot be disabled by substituting 0 into PCI_LEGACY
539 1.3.2.2 bouyer * register. Ricoh CardBus bridges have special bits on Bridge
540 1.3.2.2 bouyer * control reg (addr 0x3e on PCI config space).
541 1.3.2.2 bouyer */
542 1.3.2.2 bouyer reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR);
543 1.3.2.2 bouyer reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA);
544 1.3.2.2 bouyer pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg);
545 1.3.2.2 bouyer break;
546 1.3.2.2 bouyer
547 1.3.2.2 bouyer default:
548 1.3.2.2 bouyer /* XXX I don't know proper way to kill legacy I/O. */
549 1.3.2.2 bouyer pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0);
550 1.3.2.2 bouyer break;
551 1.3.2.2 bouyer }
552 1.3.2.2 bouyer
553 1.3.2.2 bouyer config_defer(self, pccbb_pci_callback);
554 1.1 haya }
555 1.1 haya
556 1.1 haya
557 1.1 haya
558 1.1 haya
559 1.3.2.2 bouyer /*
560 1.3.2.2 bouyer * static void pccbb_pci_callback(struct device *self)
561 1.3.2.2 bouyer *
562 1.3.2.2 bouyer * The actual attach routine: get memory space for YENTA register
563 1.3.2.2 bouyer * space, setup YENTA register and route interrupt.
564 1.3.2.2 bouyer *
565 1.3.2.2 bouyer * This function should be deferred because this device may obtain
566 1.3.2.2 bouyer * memory space dynamically. This function must avoid obtaining
567 1.3.2.2 bouyer * memory area which has already kept for another device.
568 1.3.2.2 bouyer */
569 1.1 haya static void
570 1.1 haya pccbb_pci_callback(self)
571 1.3.2.2 bouyer struct device *self;
572 1.1 haya {
573 1.3.2.2 bouyer struct pccbb_softc *sc = (void *)self;
574 1.3.2.2 bouyer pci_chipset_tag_t pc = sc->sc_pc;
575 1.3.2.2 bouyer bus_space_tag_t base_memt;
576 1.3.2.2 bouyer bus_space_handle_t base_memh;
577 1.3.2.2 bouyer u_int32_t maskreg;
578 1.3.2.2 bouyer pci_intr_handle_t ih;
579 1.3.2.2 bouyer const char *intrstr = NULL;
580 1.3.2.2 bouyer bus_addr_t sockbase;
581 1.3.2.2 bouyer struct cbslot_attach_args cba;
582 1.3.2.2 bouyer struct pcmciabus_attach_args paa;
583 1.3.2.2 bouyer struct cardslot_attach_args caa;
584 1.3.2.2 bouyer struct cardslot_softc *csc;
585 1.1 haya
586 1.3.2.2 bouyer if (0 == sc->sc_base_memh) {
587 1.3.2.2 bouyer /* The socket registers aren't mapped correctly. */
588 1.1 haya #if rbus
589 1.3.2.2 bouyer if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff,
590 1.3.2.2 bouyer (sc->sc_chipset == CB_RX5C47X
591 1.3.2.2 bouyer || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000,
592 1.3.2.2 bouyer 0, &sockbase, &sc->sc_base_memh)) {
593 1.3.2.2 bouyer return;
594 1.3.2.2 bouyer }
595 1.3.2.2 bouyer sc->sc_base_memt = sc->sc_memt;
596 1.3.2.2 bouyer pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase);
597 1.3.2.2 bouyer DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n",
598 1.3.2.2 bouyer sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag,
599 1.3.2.2 bouyer PCI_SOCKBASE)));
600 1.1 haya #else
601 1.3.2.2 bouyer sc->sc_base_memt = sc->sc_memt;
602 1.1 haya #if !defined CBB_PCI_BASE
603 1.1 haya #define CBB_PCI_BASE 0x20000000
604 1.1 haya #endif
605 1.3.2.2 bouyer if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff,
606 1.3.2.2 bouyer 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) {
607 1.3.2.2 bouyer /* cannot allocate memory space */
608 1.3.2.2 bouyer return;
609 1.3.2.2 bouyer }
610 1.3.2.2 bouyer pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase);
611 1.3.2.2 bouyer DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n",
612 1.3.2.2 bouyer sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc,
613 1.3.2.2 bouyer sc->sc_tag, PCI_SOCKBASE)));
614 1.1 haya #endif
615 1.3.2.2 bouyer }
616 1.1 haya
617 1.3.2.2 bouyer /* bus bridge initialization */
618 1.3.2.2 bouyer pccbb_chipinit(sc);
619 1.1 haya
620 1.3.2.2 bouyer base_memt = sc->sc_base_memt; /* socket regs memory tag */
621 1.3.2.2 bouyer base_memh = sc->sc_base_memh; /* socket regs memory handle */
622 1.1 haya
623 1.3.2.2 bouyer /* CSC Interrupt: Card detect interrupt on */
624 1.3.2.2 bouyer maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK);
625 1.3.2.2 bouyer maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */
626 1.3.2.2 bouyer bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg);
627 1.3.2.2 bouyer /* reset interrupt */
628 1.3.2.2 bouyer bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT,
629 1.3.2.2 bouyer bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT));
630 1.3.2.2 bouyer
631 1.3.2.2 bouyer /* clear data structure for child device interrupt handlers */
632 1.3.2.2 bouyer sc->sc_pil = NULL;
633 1.3.2.2 bouyer sc->sc_pil_intr_enable = 1;
634 1.3.2.2 bouyer
635 1.3.2.2 bouyer /* Map and establish the interrupt. */
636 1.3.2.6 bouyer if (pci_intr_map(&sc->sc_pa, &ih)) {
637 1.3.2.2 bouyer printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
638 1.3.2.2 bouyer return;
639 1.3.2.2 bouyer }
640 1.3.2.2 bouyer intrstr = pci_intr_string(pc, ih);
641 1.1 haya
642 1.3.2.2 bouyer /*
643 1.3.2.2 bouyer * XXX pccbbintr should be called under the priority lower
644 1.3.2.2 bouyer * than any other hard interrputs.
645 1.3.2.2 bouyer */
646 1.3.2.2 bouyer sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc);
647 1.3.2.2 bouyer
648 1.3.2.2 bouyer if (sc->sc_ih == NULL) {
649 1.3.2.2 bouyer printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname);
650 1.3.2.2 bouyer if (intrstr != NULL) {
651 1.3.2.2 bouyer printf(" at %s", intrstr);
652 1.3.2.2 bouyer }
653 1.3.2.2 bouyer printf("\n");
654 1.3.2.2 bouyer return;
655 1.3.2.2 bouyer }
656 1.1 haya
657 1.3.2.2 bouyer printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
658 1.3.2.2 bouyer powerhook_establish(pccbb_powerhook, sc);
659 1.1 haya
660 1.3.2.2 bouyer {
661 1.3.2.2 bouyer u_int32_t sockstat =
662 1.3.2.2 bouyer bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT);
663 1.3.2.2 bouyer if (0 == (sockstat & CB_SOCKET_STAT_CD)) {
664 1.3.2.2 bouyer sc->sc_flags |= CBB_CARDEXIST;
665 1.3.2.2 bouyer }
666 1.3.2.2 bouyer }
667 1.1 haya
668 1.3.2.2 bouyer /*
669 1.3.2.2 bouyer * attach cardbus
670 1.3.2.2 bouyer */
671 1.3.2.2 bouyer if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) {
672 1.3.2.2 bouyer pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM);
673 1.3.2.2 bouyer pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG);
674 1.3.2.2 bouyer
675 1.3.2.2 bouyer /* initialize cbslot_attach */
676 1.3.2.2 bouyer cba.cba_busname = "cardbus";
677 1.3.2.2 bouyer cba.cba_iot = sc->sc_iot;
678 1.3.2.2 bouyer cba.cba_memt = sc->sc_memt;
679 1.3.2.2 bouyer cba.cba_dmat = sc->sc_dmat;
680 1.3.2.2 bouyer cba.cba_bus = (busreg >> 8) & 0x0ff;
681 1.3.2.2 bouyer cba.cba_cc = (void *)sc;
682 1.3.2.2 bouyer cba.cba_cf = &pccbb_funcs;
683 1.3.2.6 bouyer cba.cba_intrline = sc->sc_pa.pa_intrline;
684 1.1 haya
685 1.1 haya #if rbus
686 1.3.2.2 bouyer cba.cba_rbus_iot = sc->sc_rbus_iot;
687 1.3.2.2 bouyer cba.cba_rbus_memt = sc->sc_rbus_memt;
688 1.1 haya #endif
689 1.1 haya
690 1.3.2.2 bouyer cba.cba_cacheline = PCI_CACHELINE(bhlc);
691 1.3.2.2 bouyer cba.cba_lattimer = PCI_CB_LATENCY(busreg);
692 1.1 haya
693 1.3.2.6 bouyer if (bootverbose) {
694 1.3.2.6 bouyer printf("%s: cacheline 0x%x lattimer 0x%x\n",
695 1.3.2.6 bouyer sc->sc_dev.dv_xname, cba.cba_cacheline,
696 1.3.2.6 bouyer cba.cba_lattimer);
697 1.3.2.6 bouyer printf("%s: bhlc 0x%x lscp 0x%x\n",
698 1.3.2.6 bouyer sc->sc_dev.dv_xname, bhlc, busreg);
699 1.3.2.6 bouyer }
700 1.1 haya #if defined SHOW_REGS
701 1.3.2.2 bouyer cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt,
702 1.3.2.2 bouyer sc->sc_base_memh);
703 1.1 haya #endif
704 1.3.2.2 bouyer }
705 1.1 haya
706 1.3.2.2 bouyer pccbb_pcmcia_attach_setup(sc, &paa);
707 1.3.2.2 bouyer caa.caa_cb_attach = NULL;
708 1.3.2.2 bouyer if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) {
709 1.3.2.2 bouyer caa.caa_cb_attach = &cba;
710 1.3.2.2 bouyer }
711 1.3.2.2 bouyer caa.caa_16_attach = &paa;
712 1.3.2.2 bouyer caa.caa_ph = &sc->sc_pcmcia_h;
713 1.1 haya
714 1.3.2.2 bouyer if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) {
715 1.3.2.2 bouyer DPRINTF(("pccbbattach: found cardslot\n"));
716 1.3.2.2 bouyer sc->sc_csc = csc;
717 1.3.2.2 bouyer }
718 1.1 haya
719 1.3.2.2 bouyer return;
720 1.1 haya }
721 1.1 haya
722 1.1 haya
723 1.1 haya
724 1.3.2.2 bouyer
725 1.3.2.2 bouyer
726 1.3.2.2 bouyer /*
727 1.3.2.2 bouyer * static void pccbb_chipinit(struct pccbb_softc *sc)
728 1.3.2.2 bouyer *
729 1.3.2.2 bouyer * This function initialize YENTA chip registers listed below:
730 1.3.2.2 bouyer * 1) PCI command reg,
731 1.3.2.2 bouyer * 2) PCI and CardBus latency timer,
732 1.3.2.2 bouyer * 3) route PCI interrupt,
733 1.3.2.2 bouyer * 4) close all memory and io windows.
734 1.3.2.2 bouyer */
735 1.1 haya static void
736 1.1 haya pccbb_chipinit(sc)
737 1.3.2.2 bouyer struct pccbb_softc *sc;
738 1.1 haya {
739 1.3.2.2 bouyer pci_chipset_tag_t pc = sc->sc_pc;
740 1.3.2.2 bouyer pcitag_t tag = sc->sc_tag;
741 1.3.2.2 bouyer pcireg_t reg;
742 1.3.2.2 bouyer
743 1.3.2.2 bouyer /*
744 1.3.2.2 bouyer * Set PCI command reg.
745 1.3.2.2 bouyer * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip.
746 1.3.2.2 bouyer */
747 1.3.2.2 bouyer reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
748 1.3.2.2 bouyer /* I believe it is harmless. */
749 1.3.2.2 bouyer reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
750 1.3.2.2 bouyer PCI_COMMAND_MASTER_ENABLE);
751 1.3.2.2 bouyer pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);
752 1.3.2.2 bouyer
753 1.3.2.2 bouyer /*
754 1.3.2.2 bouyer * Set CardBus latency timer.
755 1.3.2.2 bouyer */
756 1.3.2.2 bouyer reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG);
757 1.3.2.2 bouyer if (PCI_CB_LATENCY(reg) < 0x20) {
758 1.3.2.2 bouyer reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT);
759 1.3.2.2 bouyer reg |= (0x20 << PCI_CB_LATENCY_SHIFT);
760 1.3.2.2 bouyer pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg);
761 1.3.2.2 bouyer }
762 1.3.2.2 bouyer DPRINTF(("CardBus latency timer 0x%x (%x)\n",
763 1.3.2.2 bouyer PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG)));
764 1.1 haya
765 1.3.2.2 bouyer /*
766 1.3.2.2 bouyer * Set PCI latency timer.
767 1.3.2.2 bouyer */
768 1.3.2.2 bouyer reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
769 1.3.2.2 bouyer if (PCI_LATTIMER(reg) < 0x10) {
770 1.3.2.2 bouyer reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
771 1.3.2.2 bouyer reg |= (0x10 << PCI_LATTIMER_SHIFT);
772 1.3.2.2 bouyer pci_conf_write(pc, tag, PCI_BHLC_REG, reg);
773 1.3.2.2 bouyer }
774 1.3.2.2 bouyer DPRINTF(("PCI latency timer 0x%x (%x)\n",
775 1.3.2.2 bouyer PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG)));
776 1.1 haya
777 1.1 haya
778 1.3.2.2 bouyer /* Route functional interrupts to PCI. */
779 1.3.2.2 bouyer reg = pci_conf_read(pc, tag, PCI_BCR_INTR);
780 1.3.2.4 bouyer reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */
781 1.3.2.2 bouyer reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */
782 1.3.2.3 bouyer reg |= CB_BCR_RESET_ENABLE; /* assert reset */
783 1.3.2.2 bouyer pci_conf_write(pc, tag, PCI_BCR_INTR, reg);
784 1.3.2.2 bouyer
785 1.3.2.2 bouyer switch (sc->sc_chipset) {
786 1.3.2.2 bouyer case CB_TI113X:
787 1.3.2.2 bouyer reg = pci_conf_read(pc, tag, PCI_CBCTRL);
788 1.3.2.2 bouyer /* This bit is shared, but may read as 0 on some chips, so set
789 1.3.2.2 bouyer it explicitly on both functions. */
790 1.3.2.2 bouyer reg |= PCI113X_CBCTRL_PCI_IRQ_ENA;
791 1.3.2.2 bouyer /* CSC intr enable */
792 1.3.2.2 bouyer reg |= PCI113X_CBCTRL_PCI_CSC;
793 1.3.2.2 bouyer /* functional intr prohibit | prohibit ISA routing */
794 1.3.2.2 bouyer reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK);
795 1.3.2.2 bouyer pci_conf_write(pc, tag, PCI_CBCTRL, reg);
796 1.3.2.5 bouyer break;
797 1.3.2.5 bouyer
798 1.3.2.5 bouyer case CB_TI12XX:
799 1.3.2.5 bouyer reg = pci_conf_read(pc, tag, PCI_SYSCTRL);
800 1.3.2.5 bouyer reg |= PCI12XX_SYSCTRL_VCCPROT;
801 1.3.2.5 bouyer pci_conf_write(pc, tag, PCI_SYSCTRL, reg);
802 1.3.2.2 bouyer break;
803 1.3.2.2 bouyer
804 1.3.2.2 bouyer case CB_TOPIC95B:
805 1.3.2.2 bouyer reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL);
806 1.3.2.2 bouyer reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL;
807 1.3.2.2 bouyer pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg);
808 1.3.2.2 bouyer
809 1.3.2.2 bouyer reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL);
810 1.3.2.2 bouyer DPRINTF(("%s: topic slot ctrl reg 0x%x -> ",
811 1.3.2.2 bouyer sc->sc_dev.dv_xname, reg));
812 1.3.2.2 bouyer reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
813 1.3.2.2 bouyer TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);
814 1.3.2.2 bouyer reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
815 1.3.2.2 bouyer DPRINTF(("0x%x\n", reg));
816 1.3.2.2 bouyer pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg);
817 1.3.2.2 bouyer break;
818 1.3.2.2 bouyer }
819 1.1 haya
820 1.3.2.2 bouyer /* Close all memory and I/O windows. */
821 1.3.2.2 bouyer pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff);
822 1.3.2.2 bouyer pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0);
823 1.3.2.2 bouyer pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff);
824 1.3.2.2 bouyer pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0);
825 1.3.2.2 bouyer pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff);
826 1.3.2.2 bouyer pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0);
827 1.3.2.2 bouyer pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff);
828 1.3.2.2 bouyer pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0);
829 1.3.2.3 bouyer
830 1.3.2.3 bouyer /* reset 16-bit pcmcia bus */
831 1.3.2.3 bouyer bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh,
832 1.3.2.3 bouyer 0x800 + PCIC_INTR,
833 1.3.2.3 bouyer bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh,
834 1.3.2.3 bouyer 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET);
835 1.3.2.3 bouyer
836 1.3.2.3 bouyer /* turn of power */
837 1.3.2.3 bouyer pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
838 1.1 haya }
839 1.1 haya
840 1.1 haya
841 1.1 haya
842 1.3.2.2 bouyer
843 1.3.2.1 thorpej /*
844 1.3.2.2 bouyer * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc,
845 1.3.2.2 bouyer * struct pcmciabus_attach_args *paa)
846 1.3.2.2 bouyer *
847 1.3.2.2 bouyer * This function attaches 16-bit PCcard bus.
848 1.3.2.1 thorpej */
849 1.1 haya STATIC void
850 1.1 haya pccbb_pcmcia_attach_setup(sc, paa)
851 1.3.2.2 bouyer struct pccbb_softc *sc;
852 1.3.2.2 bouyer struct pcmciabus_attach_args *paa;
853 1.1 haya {
854 1.3.2.2 bouyer struct pcic_handle *ph = &sc->sc_pcmcia_h;
855 1.3.2.2 bouyer #if rbus
856 1.3.2.2 bouyer rbus_tag_t rb;
857 1.3.2.2 bouyer #endif
858 1.1 haya
859 1.3.2.2 bouyer /* initialize pcmcia part in pccbb_softc */
860 1.3.2.2 bouyer ph->ph_parent = (struct device *)sc;
861 1.3.2.2 bouyer ph->sock = sc->sc_function;
862 1.3.2.2 bouyer ph->flags = 0;
863 1.3.2.2 bouyer ph->shutdown = 0;
864 1.3.2.6 bouyer ph->ih_irq = sc->sc_pa.pa_intrline;
865 1.3.2.2 bouyer ph->ph_bus_t = sc->sc_base_memt;
866 1.3.2.2 bouyer ph->ph_bus_h = sc->sc_base_memh;
867 1.3.2.2 bouyer ph->ph_read = pccbb_pcmcia_read;
868 1.3.2.2 bouyer ph->ph_write = pccbb_pcmcia_write;
869 1.3.2.2 bouyer sc->sc_pct = &pccbb_pcmcia_funcs;
870 1.3.2.2 bouyer
871 1.3.2.2 bouyer /*
872 1.3.2.2 bouyer * We need to do a few things here:
873 1.3.2.2 bouyer * 1) Disable routing of CSC and functional interrupts to ISA IRQs by
874 1.3.2.2 bouyer * setting the IRQ numbers to 0.
875 1.3.2.2 bouyer * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable
876 1.3.2.2 bouyer * routing of CSC interrupts (e.g. card removal) to PCI while in
877 1.3.2.2 bouyer * PCMCIA mode. We just leave this set all the time.
878 1.3.2.2 bouyer * 3) Enable card insertion/removal interrupts in case the chip also
879 1.3.2.2 bouyer * needs that while in PCMCIA mode.
880 1.3.2.2 bouyer * 4) Clear any pending CSC interrupt.
881 1.3.2.2 bouyer */
882 1.3.2.3 bouyer Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE);
883 1.3.2.2 bouyer if (sc->sc_chipset == CB_TI113X) {
884 1.3.2.2 bouyer Pcic_write(ph, PCIC_CSC_INTR, 0);
885 1.3.2.2 bouyer } else {
886 1.3.2.2 bouyer Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE);
887 1.3.2.2 bouyer Pcic_read(ph, PCIC_CSC);
888 1.3.2.2 bouyer }
889 1.1 haya
890 1.3.2.2 bouyer /* initialize pcmcia bus attachment */
891 1.3.2.2 bouyer paa->paa_busname = "pcmcia";
892 1.3.2.2 bouyer paa->pct = sc->sc_pct;
893 1.3.2.2 bouyer paa->pch = ph;
894 1.3.2.2 bouyer paa->iobase = 0; /* I don't use them */
895 1.3.2.2 bouyer paa->iosize = 0;
896 1.3.2.2 bouyer #if rbus
897 1.3.2.2 bouyer rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot;
898 1.3.2.2 bouyer paa->iobase = rb->rb_start + rb->rb_offset;
899 1.3.2.2 bouyer paa->iosize = rb->rb_end - rb->rb_start;
900 1.3.2.2 bouyer #endif
901 1.1 haya
902 1.3.2.2 bouyer return;
903 1.3.2.2 bouyer }
904 1.1 haya
905 1.1 haya #if 0
906 1.1 haya STATIC void
907 1.1 haya pccbb_pcmcia_attach_card(ph)
908 1.3.2.2 bouyer struct pcic_handle *ph;
909 1.1 haya {
910 1.3.2.2 bouyer if (ph->flags & PCIC_FLAG_CARDP) {
911 1.3.2.2 bouyer panic("pccbb_pcmcia_attach_card: already attached");
912 1.3.2.2 bouyer }
913 1.1 haya
914 1.3.2.2 bouyer /* call the MI attach function */
915 1.3.2.2 bouyer pcmcia_card_attach(ph->pcmcia);
916 1.1 haya
917 1.3.2.2 bouyer ph->flags |= PCIC_FLAG_CARDP;
918 1.1 haya }
919 1.1 haya
920 1.1 haya STATIC void
921 1.1 haya pccbb_pcmcia_detach_card(ph, flags)
922 1.3.2.2 bouyer struct pcic_handle *ph;
923 1.3.2.2 bouyer int flags;
924 1.1 haya {
925 1.3.2.2 bouyer if (!(ph->flags & PCIC_FLAG_CARDP)) {
926 1.3.2.2 bouyer panic("pccbb_pcmcia_detach_card: already detached");
927 1.3.2.2 bouyer }
928 1.1 haya
929 1.3.2.2 bouyer ph->flags &= ~PCIC_FLAG_CARDP;
930 1.1 haya
931 1.3.2.2 bouyer /* call the MI detach function */
932 1.3.2.2 bouyer pcmcia_card_detach(ph->pcmcia, flags);
933 1.1 haya }
934 1.1 haya #endif
935 1.1 haya
936 1.3.2.1 thorpej /*
937 1.3.2.1 thorpej * int pccbbintr(arg)
938 1.3.2.1 thorpej * void *arg;
939 1.3.2.1 thorpej * This routine handles the interrupt from Yenta PCI-CardBus bridge
940 1.3.2.1 thorpej * itself.
941 1.3.2.1 thorpej */
942 1.1 haya int
943 1.1 haya pccbbintr(arg)
944 1.3.2.2 bouyer void *arg;
945 1.1 haya {
946 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)arg;
947 1.3.2.2 bouyer u_int32_t sockevent, sockstate;
948 1.3.2.2 bouyer bus_space_tag_t memt = sc->sc_base_memt;
949 1.3.2.2 bouyer bus_space_handle_t memh = sc->sc_base_memh;
950 1.3.2.2 bouyer struct pcic_handle *ph = &sc->sc_pcmcia_h;
951 1.3.2.2 bouyer
952 1.3.2.2 bouyer sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT);
953 1.3.2.2 bouyer bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent);
954 1.3.2.2 bouyer Pcic_read(ph, PCIC_CSC);
955 1.3.2.2 bouyer
956 1.3.2.2 bouyer if (sockevent == 0) {
957 1.3.2.2 bouyer /* This intr is not for me: it may be for my child devices. */
958 1.3.2.2 bouyer if (sc->sc_pil_intr_enable) {
959 1.3.2.2 bouyer return pccbbintr_function(sc);
960 1.3.2.2 bouyer } else {
961 1.3.2.2 bouyer return 0;
962 1.3.2.2 bouyer }
963 1.3.2.2 bouyer }
964 1.1 haya
965 1.3.2.2 bouyer if (sockevent & CB_SOCKET_EVENT_CD) {
966 1.3.2.2 bouyer sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
967 1.3.2.2 bouyer if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) {
968 1.3.2.2 bouyer /* A card should be removed. */
969 1.3.2.2 bouyer if (sc->sc_flags & CBB_CARDEXIST) {
970 1.3.2.2 bouyer DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname,
971 1.3.2.2 bouyer sockevent));
972 1.3.2.2 bouyer DPRINTF((" card removed, 0x%08x\n", sockstate));
973 1.3.2.2 bouyer sc->sc_flags &= ~CBB_CARDEXIST;
974 1.3.2.2 bouyer if (sc->sc_csc->sc_status &
975 1.3.2.2 bouyer CARDSLOT_STATUS_CARD_16) {
976 1.1 haya #if 0
977 1.3.2.2 bouyer struct pcic_handle *ph =
978 1.3.2.2 bouyer &sc->sc_pcmcia_h;
979 1.1 haya
980 1.3.2.2 bouyer pcmcia_card_deactivate(ph->pcmcia);
981 1.3.2.2 bouyer pccbb_pcmcia_socket_disable(ph);
982 1.3.2.2 bouyer pccbb_pcmcia_detach_card(ph,
983 1.3.2.2 bouyer DETACH_FORCE);
984 1.3.2.2 bouyer #endif
985 1.3.2.2 bouyer cardslot_event_throw(sc->sc_csc,
986 1.3.2.2 bouyer CARDSLOT_EVENT_REMOVAL_16);
987 1.3.2.2 bouyer } else if (sc->sc_csc->sc_status &
988 1.3.2.2 bouyer CARDSLOT_STATUS_CARD_CB) {
989 1.3.2.2 bouyer /* Cardbus intr removed */
990 1.3.2.2 bouyer cardslot_event_throw(sc->sc_csc,
991 1.3.2.2 bouyer CARDSLOT_EVENT_REMOVAL_CB);
992 1.3.2.2 bouyer }
993 1.3.2.2 bouyer }
994 1.3.2.2 bouyer } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) &&
995 1.3.2.2 bouyer /*
996 1.3.2.2 bouyer * The pccbbintr may called from powerdown hook when
997 1.3.2.2 bouyer * the system resumed, to detect the card
998 1.3.2.2 bouyer * insertion/removal during suspension.
999 1.3.2.2 bouyer */
1000 1.3.2.2 bouyer (sc->sc_flags & CBB_CARDEXIST) == 0) {
1001 1.3.2.2 bouyer if (sc->sc_flags & CBB_INSERTING) {
1002 1.3.2.2 bouyer callout_stop(&sc->sc_insert_ch);
1003 1.3.2.2 bouyer }
1004 1.3.2.2 bouyer callout_reset(&sc->sc_insert_ch, hz / 10,
1005 1.3.2.2 bouyer pci113x_insert, sc);
1006 1.3.2.2 bouyer sc->sc_flags |= CBB_INSERTING;
1007 1.3.2.2 bouyer }
1008 1.3.2.2 bouyer }
1009 1.1 haya
1010 1.3.2.2 bouyer return (1);
1011 1.1 haya }
1012 1.1 haya
1013 1.3.2.2 bouyer /*
1014 1.3.2.2 bouyer * static int pccbbintr_function(struct pccbb_softc *sc)
1015 1.3.2.2 bouyer *
1016 1.3.2.2 bouyer * This function calls each interrupt handler registered at the
1017 1.3.2.2 bouyer * bridge. The interrupt handlers are called in registered order.
1018 1.3.2.2 bouyer */
1019 1.3.2.2 bouyer static int
1020 1.3.2.2 bouyer pccbbintr_function(sc)
1021 1.3.2.2 bouyer struct pccbb_softc *sc;
1022 1.3.2.2 bouyer {
1023 1.3.2.2 bouyer int retval = 0, val;
1024 1.3.2.2 bouyer struct pccbb_intrhand_list *pil;
1025 1.3.2.2 bouyer int s, splchanged;
1026 1.3.2.2 bouyer
1027 1.3.2.2 bouyer for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) {
1028 1.3.2.2 bouyer /*
1029 1.3.2.2 bouyer * XXX priority change. gross. I use if-else
1030 1.3.2.2 bouyer * sentense instead of switch-case sentense because of
1031 1.3.2.2 bouyer * avoiding duplicate case value error. More than one
1032 1.3.2.2 bouyer * IPL_XXX use same value. It depends on
1033 1.3.2.2 bouyer * implimentation.
1034 1.3.2.2 bouyer */
1035 1.3.2.2 bouyer splchanged = 1;
1036 1.3.2.2 bouyer if (pil->pil_level == IPL_SERIAL) {
1037 1.3.2.2 bouyer s = splserial();
1038 1.3.2.2 bouyer } else if (pil->pil_level == IPL_HIGH) {
1039 1.3.2.2 bouyer s = splhigh();
1040 1.3.2.2 bouyer } else if (pil->pil_level == IPL_CLOCK) {
1041 1.3.2.2 bouyer s = splclock();
1042 1.3.2.2 bouyer } else if (pil->pil_level == IPL_AUDIO) {
1043 1.3.2.2 bouyer s = splaudio();
1044 1.3.2.2 bouyer } else if (pil->pil_level == IPL_IMP) {
1045 1.3.2.2 bouyer s = splimp();
1046 1.3.2.2 bouyer } else if (pil->pil_level == IPL_TTY) {
1047 1.3.2.2 bouyer s = spltty();
1048 1.3.2.2 bouyer } else if (pil->pil_level == IPL_SOFTSERIAL) {
1049 1.3.2.2 bouyer s = splsoftserial();
1050 1.3.2.2 bouyer } else if (pil->pil_level == IPL_NET) {
1051 1.3.2.2 bouyer s = splnet();
1052 1.3.2.2 bouyer } else {
1053 1.3.2.2 bouyer splchanged = 0;
1054 1.3.2.2 bouyer /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */
1055 1.3.2.2 bouyer }
1056 1.3.2.2 bouyer
1057 1.3.2.2 bouyer val = (*pil->pil_func)(pil->pil_arg);
1058 1.3.2.2 bouyer
1059 1.3.2.2 bouyer if (splchanged != 0) {
1060 1.3.2.2 bouyer splx(s);
1061 1.3.2.2 bouyer }
1062 1.3.2.2 bouyer
1063 1.3.2.2 bouyer retval = retval == 1 ? 1 :
1064 1.3.2.2 bouyer retval == 0 ? val : val != 0 ? val : retval;
1065 1.3.2.2 bouyer }
1066 1.1 haya
1067 1.3.2.2 bouyer return retval;
1068 1.3.2.2 bouyer }
1069 1.1 haya
1070 1.1 haya static void
1071 1.1 haya pci113x_insert(arg)
1072 1.3.2.2 bouyer void *arg;
1073 1.1 haya {
1074 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)arg;
1075 1.3.2.2 bouyer u_int32_t sockevent, sockstate;
1076 1.1 haya
1077 1.3.2.2 bouyer sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
1078 1.3.2.2 bouyer CB_SOCKET_EVENT);
1079 1.3.2.2 bouyer sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
1080 1.3.2.2 bouyer CB_SOCKET_STAT);
1081 1.3.2.2 bouyer
1082 1.3.2.2 bouyer if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */
1083 1.3.2.2 bouyer DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent));
1084 1.3.2.2 bouyer DPRINTF((" card inserted, 0x%08x\n", sockstate));
1085 1.3.2.2 bouyer sc->sc_flags |= CBB_CARDEXIST;
1086 1.3.2.2 bouyer /* call pccard interrupt handler here */
1087 1.3.2.2 bouyer if (sockstate & CB_SOCKET_STAT_16BIT) {
1088 1.3.2.2 bouyer /* 16-bit card found */
1089 1.1 haya /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */
1090 1.3.2.2 bouyer cardslot_event_throw(sc->sc_csc,
1091 1.3.2.2 bouyer CARDSLOT_EVENT_INSERTION_16);
1092 1.3.2.2 bouyer } else if (sockstate & CB_SOCKET_STAT_CB) {
1093 1.3.2.2 bouyer /* cardbus card found */
1094 1.1 haya /* cardbus_attach_card(sc->sc_csc); */
1095 1.3.2.2 bouyer cardslot_event_throw(sc->sc_csc,
1096 1.3.2.2 bouyer CARDSLOT_EVENT_INSERTION_CB);
1097 1.3.2.2 bouyer } else {
1098 1.3.2.2 bouyer /* who are you? */
1099 1.3.2.2 bouyer }
1100 1.3.2.2 bouyer } else {
1101 1.3.2.2 bouyer callout_reset(&sc->sc_insert_ch, hz / 10,
1102 1.3.2.2 bouyer pci113x_insert, sc);
1103 1.3.2.2 bouyer }
1104 1.1 haya }
1105 1.1 haya
1106 1.1 haya #define PCCBB_PCMCIA_OFFSET 0x800
1107 1.1 haya static u_int8_t
1108 1.1 haya pccbb_pcmcia_read(ph, reg)
1109 1.3.2.2 bouyer struct pcic_handle *ph;
1110 1.3.2.2 bouyer int reg;
1111 1.1 haya {
1112 1.3.2.4 bouyer bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h,
1113 1.3.2.4 bouyer PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ);
1114 1.3.2.4 bouyer
1115 1.3.2.2 bouyer return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h,
1116 1.3.2.2 bouyer PCCBB_PCMCIA_OFFSET + reg);
1117 1.1 haya }
1118 1.1 haya
1119 1.1 haya static void
1120 1.1 haya pccbb_pcmcia_write(ph, reg, val)
1121 1.3.2.2 bouyer struct pcic_handle *ph;
1122 1.3.2.2 bouyer int reg;
1123 1.3.2.2 bouyer u_int8_t val;
1124 1.1 haya {
1125 1.3.2.2 bouyer bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg,
1126 1.3.2.2 bouyer val);
1127 1.3.2.4 bouyer
1128 1.3.2.4 bouyer bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h,
1129 1.3.2.4 bouyer PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE);
1130 1.1 haya }
1131 1.1 haya
1132 1.3.2.1 thorpej /*
1133 1.3.2.1 thorpej * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int)
1134 1.3.2.1 thorpej */
1135 1.1 haya STATIC int
1136 1.1 haya pccbb_ctrl(ct, command)
1137 1.3.2.2 bouyer cardbus_chipset_tag_t ct;
1138 1.3.2.2 bouyer int command;
1139 1.1 haya {
1140 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1141 1.1 haya
1142 1.3.2.2 bouyer switch (command) {
1143 1.3.2.2 bouyer case CARDBUS_CD:
1144 1.3.2.2 bouyer if (2 == pccbb_detect_card(sc)) {
1145 1.3.2.2 bouyer int retval = 0;
1146 1.3.2.2 bouyer int status = cb_detect_voltage(sc);
1147 1.3.2.2 bouyer if (PCCARD_VCC_5V & status) {
1148 1.3.2.2 bouyer retval |= CARDBUS_5V_CARD;
1149 1.3.2.2 bouyer }
1150 1.3.2.2 bouyer if (PCCARD_VCC_3V & status) {
1151 1.3.2.2 bouyer retval |= CARDBUS_3V_CARD;
1152 1.3.2.2 bouyer }
1153 1.3.2.2 bouyer if (PCCARD_VCC_XV & status) {
1154 1.3.2.2 bouyer retval |= CARDBUS_XV_CARD;
1155 1.3.2.2 bouyer }
1156 1.3.2.2 bouyer if (PCCARD_VCC_YV & status) {
1157 1.3.2.2 bouyer retval |= CARDBUS_YV_CARD;
1158 1.3.2.2 bouyer }
1159 1.3.2.2 bouyer return retval;
1160 1.3.2.2 bouyer } else {
1161 1.3.2.2 bouyer return 0;
1162 1.3.2.2 bouyer }
1163 1.3.2.2 bouyer break;
1164 1.3.2.2 bouyer case CARDBUS_RESET:
1165 1.3.2.2 bouyer return cb_reset(sc);
1166 1.3.2.2 bouyer break;
1167 1.3.2.2 bouyer case CARDBUS_IO_ENABLE: /* fallthrough */
1168 1.3.2.2 bouyer case CARDBUS_IO_DISABLE: /* fallthrough */
1169 1.3.2.2 bouyer case CARDBUS_MEM_ENABLE: /* fallthrough */
1170 1.3.2.2 bouyer case CARDBUS_MEM_DISABLE: /* fallthrough */
1171 1.3.2.2 bouyer case CARDBUS_BM_ENABLE: /* fallthrough */
1172 1.3.2.2 bouyer case CARDBUS_BM_DISABLE: /* fallthrough */
1173 1.3.2.2 bouyer return pccbb_cardenable(sc, command);
1174 1.3.2.2 bouyer break;
1175 1.3.2.2 bouyer }
1176 1.1 haya
1177 1.3.2.2 bouyer return 0;
1178 1.1 haya }
1179 1.1 haya
1180 1.3.2.1 thorpej /*
1181 1.3.2.1 thorpej * STATIC int pccbb_power(cardbus_chipset_tag_t, int)
1182 1.3.2.1 thorpej * This function returns true when it succeeds and returns false when
1183 1.3.2.1 thorpej * it fails.
1184 1.3.2.1 thorpej */
1185 1.1 haya STATIC int
1186 1.1 haya pccbb_power(ct, command)
1187 1.3.2.2 bouyer cardbus_chipset_tag_t ct;
1188 1.3.2.2 bouyer int command;
1189 1.1 haya {
1190 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1191 1.1 haya
1192 1.3.2.2 bouyer u_int32_t status, sock_ctrl;
1193 1.3.2.2 bouyer bus_space_tag_t memt = sc->sc_base_memt;
1194 1.3.2.2 bouyer bus_space_handle_t memh = sc->sc_base_memh;
1195 1.3.2.2 bouyer
1196 1.3.2.2 bouyer DPRINTF(("pccbb_power: %s and %s [%x]\n",
1197 1.3.2.2 bouyer (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" :
1198 1.3.2.2 bouyer (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" :
1199 1.3.2.2 bouyer (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" :
1200 1.3.2.2 bouyer (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" :
1201 1.3.2.2 bouyer (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" :
1202 1.3.2.2 bouyer (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" :
1203 1.3.2.2 bouyer "UNKNOWN",
1204 1.3.2.2 bouyer (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" :
1205 1.3.2.2 bouyer (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" :
1206 1.3.2.2 bouyer (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" :
1207 1.3.2.2 bouyer (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" :
1208 1.3.2.2 bouyer "UNKNOWN", command));
1209 1.3.2.2 bouyer
1210 1.3.2.2 bouyer status = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
1211 1.3.2.2 bouyer sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL);
1212 1.3.2.2 bouyer
1213 1.3.2.2 bouyer switch (command & CARDBUS_VCCMASK) {
1214 1.3.2.2 bouyer case CARDBUS_VCC_UC:
1215 1.3.2.2 bouyer break;
1216 1.3.2.2 bouyer case CARDBUS_VCC_5V:
1217 1.3.2.2 bouyer if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */
1218 1.3.2.2 bouyer sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK;
1219 1.3.2.2 bouyer sock_ctrl |= CB_SOCKET_CTRL_VCC_5V;
1220 1.3.2.2 bouyer } else {
1221 1.3.2.2 bouyer printf("%s: BAD voltage request: no 5 V card\n",
1222 1.3.2.2 bouyer sc->sc_dev.dv_xname);
1223 1.3.2.2 bouyer }
1224 1.3.2.2 bouyer break;
1225 1.3.2.2 bouyer case CARDBUS_VCC_3V:
1226 1.3.2.2 bouyer if (CB_SOCKET_STAT_3VCARD & status) {
1227 1.3.2.2 bouyer sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK;
1228 1.3.2.2 bouyer sock_ctrl |= CB_SOCKET_CTRL_VCC_3V;
1229 1.3.2.2 bouyer } else {
1230 1.3.2.2 bouyer printf("%s: BAD voltage request: no 3.3 V card\n",
1231 1.3.2.2 bouyer sc->sc_dev.dv_xname);
1232 1.3.2.2 bouyer }
1233 1.3.2.2 bouyer break;
1234 1.3.2.2 bouyer case CARDBUS_VCC_0V:
1235 1.3.2.2 bouyer sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK;
1236 1.3.2.2 bouyer break;
1237 1.3.2.2 bouyer default:
1238 1.3.2.2 bouyer return 0; /* power NEVER changed */
1239 1.3.2.2 bouyer break;
1240 1.3.2.2 bouyer }
1241 1.1 haya
1242 1.3.2.2 bouyer switch (command & CARDBUS_VPPMASK) {
1243 1.3.2.2 bouyer case CARDBUS_VPP_UC:
1244 1.3.2.2 bouyer break;
1245 1.3.2.2 bouyer case CARDBUS_VPP_0V:
1246 1.3.2.2 bouyer sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK;
1247 1.3.2.2 bouyer break;
1248 1.3.2.2 bouyer case CARDBUS_VPP_VCC:
1249 1.3.2.2 bouyer sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK;
1250 1.3.2.2 bouyer sock_ctrl |= ((sock_ctrl >> 4) & 0x07);
1251 1.3.2.2 bouyer break;
1252 1.3.2.2 bouyer case CARDBUS_VPP_12V:
1253 1.3.2.2 bouyer sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK;
1254 1.3.2.2 bouyer sock_ctrl |= CB_SOCKET_CTRL_VPP_12V;
1255 1.3.2.2 bouyer break;
1256 1.3.2.2 bouyer }
1257 1.1 haya
1258 1.1 haya #if 0
1259 1.3.2.2 bouyer DPRINTF(("sock_ctrl: %x\n", sock_ctrl));
1260 1.1 haya #endif
1261 1.3.2.2 bouyer bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl);
1262 1.3.2.2 bouyer status = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
1263 1.1 haya
1264 1.3.2.2 bouyer if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */
1265 1.3.2.2 bouyer printf
1266 1.3.2.2 bouyer ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n",
1267 1.3.2.2 bouyer sc->sc_dev.dv_xname, sock_ctrl, status);
1268 1.3.2.2 bouyer DPRINTF(("pccbb_power: %s and %s [%x]\n",
1269 1.3.2.2 bouyer (command & CARDBUS_VCCMASK) ==
1270 1.3.2.2 bouyer CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command &
1271 1.3.2.2 bouyer CARDBUS_VCCMASK) ==
1272 1.3.2.2 bouyer CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command &
1273 1.3.2.2 bouyer CARDBUS_VCCMASK) ==
1274 1.3.2.2 bouyer CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command &
1275 1.3.2.2 bouyer CARDBUS_VCCMASK) ==
1276 1.3.2.2 bouyer CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command &
1277 1.3.2.2 bouyer CARDBUS_VCCMASK) ==
1278 1.3.2.2 bouyer CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command &
1279 1.3.2.2 bouyer CARDBUS_VCCMASK) ==
1280 1.3.2.2 bouyer CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN",
1281 1.3.2.2 bouyer (command & CARDBUS_VPPMASK) ==
1282 1.3.2.2 bouyer CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command &
1283 1.3.2.2 bouyer CARDBUS_VPPMASK) ==
1284 1.3.2.2 bouyer CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command &
1285 1.3.2.2 bouyer CARDBUS_VPPMASK) ==
1286 1.3.2.2 bouyer CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command &
1287 1.3.2.2 bouyer CARDBUS_VPPMASK) ==
1288 1.3.2.2 bouyer CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command));
1289 1.1 haya #if 0
1290 1.3.2.2 bouyer if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) {
1291 1.3.2.2 bouyer u_int32_t force =
1292 1.3.2.2 bouyer bus_space_read_4(memt, memh, CB_SOCKET_FORCE);
1293 1.3.2.2 bouyer /* Reset Bad Vcc request */
1294 1.3.2.2 bouyer force &= ~CB_SOCKET_FORCE_BADVCC;
1295 1.3.2.2 bouyer bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force);
1296 1.3.2.2 bouyer printf("new status 0x%x\n", bus_space_read_4(memt, memh,
1297 1.3.2.2 bouyer CB_SOCKET_STAT));
1298 1.3.2.2 bouyer return 1;
1299 1.3.2.2 bouyer }
1300 1.1 haya #endif
1301 1.3.2.2 bouyer return 0;
1302 1.3.2.2 bouyer }
1303 1.3.2.4 bouyer
1304 1.3.2.4 bouyer /*
1305 1.3.2.4 bouyer * XXX delay 300 ms: though the standard defines that the Vcc set-up
1306 1.3.2.4 bouyer * time is 20 ms, some PC-Card bridge requires longer duration.
1307 1.3.2.4 bouyer */
1308 1.3.2.8 bouyer #if 0 /* XXX called on interrupt context */
1309 1.3.2.8 bouyer DELAY_MS(300, sc);
1310 1.3.2.8 bouyer #else
1311 1.3.2.4 bouyer delay(300 * 1000);
1312 1.3.2.8 bouyer #endif
1313 1.3.2.4 bouyer
1314 1.3.2.2 bouyer return 1; /* power changed correctly */
1315 1.1 haya }
1316 1.1 haya
1317 1.1 haya #if defined CB_PCMCIA_POLL
1318 1.1 haya struct cb_poll_str {
1319 1.3.2.2 bouyer void *arg;
1320 1.3.2.2 bouyer int (*func) __P((void *));
1321 1.3.2.2 bouyer int level;
1322 1.3.2.2 bouyer pccard_chipset_tag_t ct;
1323 1.3.2.2 bouyer int count;
1324 1.3.2.2 bouyer struct callout poll_ch;
1325 1.1 haya };
1326 1.1 haya
1327 1.1 haya static struct cb_poll_str cb_poll[10];
1328 1.1 haya static int cb_poll_n = 0;
1329 1.1 haya
1330 1.1 haya static void cb_pcmcia_poll __P((void *arg));
1331 1.1 haya
1332 1.1 haya static void
1333 1.1 haya cb_pcmcia_poll(arg)
1334 1.3.2.2 bouyer void *arg;
1335 1.1 haya {
1336 1.3.2.2 bouyer struct cb_poll_str *poll = arg;
1337 1.3.2.2 bouyer struct cbb_pcmcia_softc *psc = (void *)poll->ct->v;
1338 1.3.2.2 bouyer struct pccbb_softc *sc = psc->cpc_parent;
1339 1.3.2.2 bouyer int s;
1340 1.3.2.2 bouyer u_int32_t spsr; /* socket present-state reg */
1341 1.3.2.2 bouyer
1342 1.3.2.2 bouyer callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll);
1343 1.3.2.2 bouyer switch (poll->level) {
1344 1.3.2.2 bouyer case IPL_NET:
1345 1.3.2.2 bouyer s = splnet();
1346 1.3.2.2 bouyer break;
1347 1.3.2.2 bouyer case IPL_BIO:
1348 1.3.2.2 bouyer s = splbio();
1349 1.3.2.2 bouyer break;
1350 1.3.2.2 bouyer case IPL_TTY: /* fallthrough */
1351 1.3.2.2 bouyer default:
1352 1.3.2.2 bouyer s = spltty();
1353 1.3.2.2 bouyer break;
1354 1.3.2.2 bouyer }
1355 1.3.2.2 bouyer
1356 1.3.2.2 bouyer spsr =
1357 1.3.2.2 bouyer bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
1358 1.3.2.2 bouyer CB_SOCKET_STAT);
1359 1.1 haya
1360 1.1 haya #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2
1361 1.3.2.2 bouyer if (!(spsr & 0x40)) { /* CINT low */
1362 1.1 haya #else
1363 1.3.2.2 bouyer if (1) {
1364 1.1 haya #endif
1365 1.3.2.2 bouyer if ((*poll->func) (poll->arg) == 1) {
1366 1.3.2.2 bouyer ++poll->count;
1367 1.3.2.2 bouyer printf("intr: reported from poller, 0x%x\n", spsr);
1368 1.1 haya #if defined LEVEL2
1369 1.3.2.2 bouyer } else {
1370 1.3.2.2 bouyer printf("intr: miss! 0x%x\n", spsr);
1371 1.1 haya #endif
1372 1.3.2.2 bouyer }
1373 1.3.2.2 bouyer }
1374 1.3.2.2 bouyer splx(s);
1375 1.1 haya }
1376 1.1 haya #endif /* defined CB_PCMCIA_POLL */
1377 1.1 haya
1378 1.3.2.1 thorpej /*
1379 1.3.2.1 thorpej * static int pccbb_detect_card(struct pccbb_softc *sc)
1380 1.3.2.1 thorpej * return value: 0 if no card exists.
1381 1.3.2.1 thorpej * 1 if 16-bit card exists.
1382 1.3.2.1 thorpej * 2 if cardbus card exists.
1383 1.3.2.1 thorpej */
1384 1.1 haya static int
1385 1.1 haya pccbb_detect_card(sc)
1386 1.3.2.2 bouyer struct pccbb_softc *sc;
1387 1.1 haya {
1388 1.3.2.2 bouyer bus_space_handle_t base_memh = sc->sc_base_memh;
1389 1.3.2.2 bouyer bus_space_tag_t base_memt = sc->sc_base_memt;
1390 1.3.2.2 bouyer u_int32_t sockstat =
1391 1.3.2.2 bouyer bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT);
1392 1.3.2.2 bouyer int retval = 0;
1393 1.3.2.2 bouyer
1394 1.3.2.2 bouyer /* CD1 and CD2 asserted */
1395 1.3.2.2 bouyer if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) {
1396 1.3.2.2 bouyer /* card must be present */
1397 1.3.2.2 bouyer if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) {
1398 1.3.2.2 bouyer /* NOTACARD DEASSERTED */
1399 1.3.2.2 bouyer if (CB_SOCKET_STAT_CB & sockstat) {
1400 1.3.2.2 bouyer /* CardBus mode */
1401 1.3.2.2 bouyer retval = 2;
1402 1.3.2.2 bouyer } else if (CB_SOCKET_STAT_16BIT & sockstat) {
1403 1.3.2.2 bouyer /* 16-bit mode */
1404 1.3.2.2 bouyer retval = 1;
1405 1.3.2.2 bouyer }
1406 1.3.2.2 bouyer }
1407 1.3.2.2 bouyer }
1408 1.3.2.2 bouyer return retval;
1409 1.1 haya }
1410 1.1 haya
1411 1.3.2.1 thorpej /*
1412 1.3.2.1 thorpej * STATIC int cb_reset(struct pccbb_softc *sc)
1413 1.3.2.1 thorpej * This function resets CardBus card.
1414 1.3.2.1 thorpej */
1415 1.1 haya STATIC int
1416 1.1 haya cb_reset(sc)
1417 1.3.2.2 bouyer struct pccbb_softc *sc;
1418 1.1 haya {
1419 1.3.2.2 bouyer /*
1420 1.3.2.2 bouyer * Reset Assert at least 20 ms
1421 1.3.2.2 bouyer * Some machines request longer duration.
1422 1.3.2.2 bouyer */
1423 1.3.2.2 bouyer int reset_duration =
1424 1.3.2.8 bouyer (sc->sc_chipset == CB_RX5C47X ? 400 : 40);
1425 1.3.2.2 bouyer u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
1426 1.3.2.2 bouyer
1427 1.3.2.2 bouyer /* Reset bit Assert (bit 6 at 0x3E) */
1428 1.3.2.2 bouyer bcr |= CB_BCR_RESET_ENABLE;
1429 1.3.2.2 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr);
1430 1.3.2.8 bouyer DELAY_MS(reset_duration, sc);
1431 1.3.2.2 bouyer
1432 1.3.2.2 bouyer if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */
1433 1.3.2.2 bouyer /* Reset bit Deassert (bit 6 at 0x3E) */
1434 1.3.2.2 bouyer bcr &= ~CB_BCR_RESET_ENABLE;
1435 1.3.2.2 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr);
1436 1.3.2.8 bouyer DELAY_MS(reset_duration, sc);
1437 1.3.2.2 bouyer }
1438 1.3.2.2 bouyer /* No card found on the slot. Keep Reset. */
1439 1.3.2.2 bouyer return 1;
1440 1.1 haya }
1441 1.1 haya
1442 1.3.2.1 thorpej /*
1443 1.3.2.1 thorpej * STATIC int cb_detect_voltage(struct pccbb_softc *sc)
1444 1.3.2.1 thorpej * This function detect card Voltage.
1445 1.3.2.1 thorpej */
1446 1.1 haya STATIC int
1447 1.1 haya cb_detect_voltage(sc)
1448 1.3.2.2 bouyer struct pccbb_softc *sc;
1449 1.1 haya {
1450 1.3.2.2 bouyer u_int32_t psr; /* socket present-state reg */
1451 1.3.2.2 bouyer bus_space_tag_t iot = sc->sc_base_memt;
1452 1.3.2.2 bouyer bus_space_handle_t ioh = sc->sc_base_memh;
1453 1.3.2.2 bouyer int vol = PCCARD_VCC_UKN; /* set 0 */
1454 1.1 haya
1455 1.3.2.2 bouyer psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT);
1456 1.1 haya
1457 1.3.2.2 bouyer if (0x400u & psr) {
1458 1.3.2.2 bouyer vol |= PCCARD_VCC_5V;
1459 1.3.2.2 bouyer }
1460 1.3.2.2 bouyer if (0x800u & psr) {
1461 1.3.2.2 bouyer vol |= PCCARD_VCC_3V;
1462 1.3.2.2 bouyer }
1463 1.1 haya
1464 1.3.2.2 bouyer return vol;
1465 1.3.2.2 bouyer }
1466 1.1 haya
1467 1.1 haya STATIC int
1468 1.1 haya cbbprint(aux, pcic)
1469 1.3.2.2 bouyer void *aux;
1470 1.3.2.2 bouyer const char *pcic;
1471 1.1 haya {
1472 1.1 haya /*
1473 1.1 haya struct cbslot_attach_args *cba = aux;
1474 1.1 haya
1475 1.1 haya if (cba->cba_slot >= 0) {
1476 1.1 haya printf(" slot %d", cba->cba_slot);
1477 1.1 haya }
1478 1.1 haya */
1479 1.3.2.2 bouyer return UNCONF;
1480 1.1 haya }
1481 1.1 haya
1482 1.3.2.1 thorpej /*
1483 1.3.2.1 thorpej * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function)
1484 1.3.2.1 thorpej * This function enables and disables the card
1485 1.3.2.1 thorpej */
1486 1.1 haya STATIC int
1487 1.1 haya pccbb_cardenable(sc, function)
1488 1.3.2.2 bouyer struct pccbb_softc *sc;
1489 1.3.2.2 bouyer int function;
1490 1.1 haya {
1491 1.3.2.2 bouyer u_int32_t command =
1492 1.3.2.2 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
1493 1.1 haya
1494 1.3.2.2 bouyer DPRINTF(("pccbb_cardenable:"));
1495 1.3.2.2 bouyer switch (function) {
1496 1.3.2.2 bouyer case CARDBUS_IO_ENABLE:
1497 1.3.2.2 bouyer command |= PCI_COMMAND_IO_ENABLE;
1498 1.3.2.2 bouyer break;
1499 1.3.2.2 bouyer case CARDBUS_IO_DISABLE:
1500 1.3.2.2 bouyer command &= ~PCI_COMMAND_IO_ENABLE;
1501 1.3.2.2 bouyer break;
1502 1.3.2.2 bouyer case CARDBUS_MEM_ENABLE:
1503 1.3.2.2 bouyer command |= PCI_COMMAND_MEM_ENABLE;
1504 1.3.2.2 bouyer break;
1505 1.3.2.2 bouyer case CARDBUS_MEM_DISABLE:
1506 1.3.2.2 bouyer command &= ~PCI_COMMAND_MEM_ENABLE;
1507 1.3.2.2 bouyer break;
1508 1.3.2.2 bouyer case CARDBUS_BM_ENABLE:
1509 1.3.2.2 bouyer command |= PCI_COMMAND_MASTER_ENABLE;
1510 1.3.2.2 bouyer break;
1511 1.3.2.2 bouyer case CARDBUS_BM_DISABLE:
1512 1.3.2.2 bouyer command &= ~PCI_COMMAND_MASTER_ENABLE;
1513 1.3.2.2 bouyer break;
1514 1.3.2.2 bouyer default:
1515 1.3.2.2 bouyer return 0;
1516 1.3.2.2 bouyer }
1517 1.1 haya
1518 1.3.2.2 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command);
1519 1.3.2.2 bouyer DPRINTF((" command reg 0x%x\n", command));
1520 1.3.2.2 bouyer return 1;
1521 1.1 haya }
1522 1.1 haya
1523 1.1 haya #if !rbus
1524 1.3.2.1 thorpej /*
1525 1.3.2.1 thorpej * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)
1526 1.3.2.1 thorpej */
1527 1.1 haya static int
1528 1.1 haya pccbb_io_open(ct, win, start, end)
1529 1.3.2.2 bouyer cardbus_chipset_tag_t ct;
1530 1.3.2.2 bouyer int win;
1531 1.3.2.2 bouyer u_int32_t start, end;
1532 1.3.2.2 bouyer {
1533 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1534 1.3.2.2 bouyer int basereg;
1535 1.3.2.2 bouyer int limitreg;
1536 1.1 haya
1537 1.3.2.2 bouyer if ((win < 0) || (win > 2)) {
1538 1.1 haya #if defined DIAGNOSTIC
1539 1.3.2.2 bouyer printf("cardbus_io_open: window out of range %d\n", win);
1540 1.1 haya #endif
1541 1.3.2.2 bouyer return 0;
1542 1.3.2.2 bouyer }
1543 1.1 haya
1544 1.3.2.2 bouyer basereg = win * 8 + 0x2c;
1545 1.3.2.2 bouyer limitreg = win * 8 + 0x30;
1546 1.1 haya
1547 1.3.2.2 bouyer DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n",
1548 1.3.2.2 bouyer start, basereg, end, limitreg));
1549 1.1 haya
1550 1.3.2.2 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start);
1551 1.3.2.2 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end);
1552 1.3.2.2 bouyer return 1;
1553 1.1 haya }
1554 1.3.2.2 bouyer
1555 1.3.2.1 thorpej /*
1556 1.3.2.1 thorpej * int pccbb_io_close(cardbus_chipset_tag_t, int)
1557 1.3.2.1 thorpej */
1558 1.1 haya static int
1559 1.1 haya pccbb_io_close(ct, win)
1560 1.3.2.2 bouyer cardbus_chipset_tag_t ct;
1561 1.3.2.2 bouyer int win;
1562 1.1 haya {
1563 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1564 1.3.2.2 bouyer int basereg;
1565 1.3.2.2 bouyer int limitreg;
1566 1.1 haya
1567 1.3.2.2 bouyer if ((win < 0) || (win > 2)) {
1568 1.1 haya #if defined DIAGNOSTIC
1569 1.3.2.2 bouyer printf("cardbus_io_close: window out of range %d\n", win);
1570 1.1 haya #endif
1571 1.3.2.2 bouyer return 0;
1572 1.3.2.2 bouyer }
1573 1.1 haya
1574 1.3.2.2 bouyer basereg = win * 8 + 0x2c;
1575 1.3.2.2 bouyer limitreg = win * 8 + 0x30;
1576 1.1 haya
1577 1.3.2.2 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0);
1578 1.3.2.2 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0);
1579 1.3.2.2 bouyer return 1;
1580 1.1 haya }
1581 1.1 haya
1582 1.3.2.1 thorpej /*
1583 1.3.2.1 thorpej * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)
1584 1.3.2.1 thorpej */
1585 1.1 haya static int
1586 1.1 haya pccbb_mem_open(ct, win, start, end)
1587 1.3.2.2 bouyer cardbus_chipset_tag_t ct;
1588 1.3.2.2 bouyer int win;
1589 1.3.2.2 bouyer u_int32_t start, end;
1590 1.3.2.2 bouyer {
1591 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1592 1.3.2.2 bouyer int basereg;
1593 1.3.2.2 bouyer int limitreg;
1594 1.1 haya
1595 1.3.2.2 bouyer if ((win < 0) || (win > 2)) {
1596 1.1 haya #if defined DIAGNOSTIC
1597 1.3.2.2 bouyer printf("cardbus_mem_open: window out of range %d\n", win);
1598 1.1 haya #endif
1599 1.3.2.2 bouyer return 0;
1600 1.3.2.2 bouyer }
1601 1.1 haya
1602 1.3.2.2 bouyer basereg = win * 8 + 0x1c;
1603 1.3.2.2 bouyer limitreg = win * 8 + 0x20;
1604 1.1 haya
1605 1.3.2.2 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start);
1606 1.3.2.2 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end);
1607 1.3.2.2 bouyer return 1;
1608 1.1 haya }
1609 1.1 haya
1610 1.3.2.1 thorpej /*
1611 1.3.2.1 thorpej * int pccbb_mem_close(cardbus_chipset_tag_t, int)
1612 1.3.2.1 thorpej */
1613 1.1 haya static int
1614 1.1 haya pccbb_mem_close(ct, win)
1615 1.3.2.2 bouyer cardbus_chipset_tag_t ct;
1616 1.3.2.2 bouyer int win;
1617 1.1 haya {
1618 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1619 1.3.2.2 bouyer int basereg;
1620 1.3.2.2 bouyer int limitreg;
1621 1.1 haya
1622 1.3.2.2 bouyer if ((win < 0) || (win > 2)) {
1623 1.1 haya #if defined DIAGNOSTIC
1624 1.3.2.2 bouyer printf("cardbus_mem_close: window out of range %d\n", win);
1625 1.1 haya #endif
1626 1.3.2.2 bouyer return 0;
1627 1.3.2.2 bouyer }
1628 1.1 haya
1629 1.3.2.2 bouyer basereg = win * 8 + 0x1c;
1630 1.3.2.2 bouyer limitreg = win * 8 + 0x20;
1631 1.1 haya
1632 1.3.2.2 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0);
1633 1.3.2.2 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0);
1634 1.3.2.2 bouyer return 1;
1635 1.1 haya }
1636 1.1 haya #endif
1637 1.1 haya
1638 1.3.2.2 bouyer /*
1639 1.3.2.2 bouyer * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct,
1640 1.3.2.2 bouyer * int irq,
1641 1.3.2.2 bouyer * int level,
1642 1.3.2.2 bouyer * int (* func) __P((void *)),
1643 1.3.2.2 bouyer * void *arg)
1644 1.3.2.2 bouyer *
1645 1.3.2.2 bouyer * This function registers an interrupt handler at the bridge, in
1646 1.3.2.2 bouyer * order not to call the interrupt handlers of child devices when
1647 1.3.2.2 bouyer * a card-deletion interrupt occurs.
1648 1.3.2.2 bouyer *
1649 1.3.2.2 bouyer * The arguments irq and level are not used.
1650 1.3.2.2 bouyer */
1651 1.3.2.2 bouyer static void *
1652 1.3.2.2 bouyer pccbb_cb_intr_establish(ct, irq, level, func, arg)
1653 1.3.2.2 bouyer cardbus_chipset_tag_t ct;
1654 1.3.2.2 bouyer int irq, level;
1655 1.3.2.2 bouyer int (*func) __P((void *));
1656 1.3.2.2 bouyer void *arg;
1657 1.3.2.2 bouyer {
1658 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1659 1.1 haya
1660 1.3.2.2 bouyer return pccbb_intr_establish(sc, irq, level, func, arg);
1661 1.3.2.2 bouyer }
1662 1.1 haya
1663 1.1 haya
1664 1.3.2.2 bouyer /*
1665 1.3.2.2 bouyer * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct,
1666 1.3.2.2 bouyer * void *ih)
1667 1.3.2.2 bouyer *
1668 1.3.2.2 bouyer * This function removes an interrupt handler pointed by ih.
1669 1.3.2.2 bouyer */
1670 1.3.2.2 bouyer static void
1671 1.3.2.2 bouyer pccbb_cb_intr_disestablish(ct, ih)
1672 1.3.2.2 bouyer cardbus_chipset_tag_t ct;
1673 1.3.2.2 bouyer void *ih;
1674 1.3.2.2 bouyer {
1675 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1676 1.3.2.2 bouyer
1677 1.3.2.2 bouyer pccbb_intr_disestablish(sc, ih);
1678 1.1 haya }
1679 1.1 haya
1680 1.1 haya
1681 1.3.2.2 bouyer /*
1682 1.3.2.2 bouyer * static void *pccbb_intr_establish(struct pccbb_softc *sc,
1683 1.3.2.2 bouyer * int irq,
1684 1.3.2.2 bouyer * int level,
1685 1.3.2.2 bouyer * int (* func) __P((void *)),
1686 1.3.2.2 bouyer * void *arg)
1687 1.3.2.2 bouyer *
1688 1.3.2.2 bouyer * This function registers an interrupt handler at the bridge, in
1689 1.3.2.2 bouyer * order not to call the interrupt handlers of child devices when
1690 1.3.2.2 bouyer * a card-deletion interrupt occurs.
1691 1.3.2.2 bouyer *
1692 1.3.2.2 bouyer * The arguments irq is not used because pccbb selects intr vector.
1693 1.3.2.2 bouyer */
1694 1.3.2.2 bouyer static void *
1695 1.3.2.2 bouyer pccbb_intr_establish(sc, irq, level, func, arg)
1696 1.3.2.2 bouyer struct pccbb_softc *sc;
1697 1.3.2.2 bouyer int irq, level;
1698 1.3.2.2 bouyer int (*func) __P((void *));
1699 1.3.2.2 bouyer void *arg;
1700 1.3.2.2 bouyer {
1701 1.3.2.2 bouyer struct pccbb_intrhand_list *pil, *newpil;
1702 1.3.2.4 bouyer pcireg_t reg;
1703 1.3.2.2 bouyer
1704 1.3.2.2 bouyer DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil));
1705 1.3.2.2 bouyer
1706 1.3.2.2 bouyer if (sc->sc_pil == NULL) {
1707 1.3.2.2 bouyer /* initialize bridge intr routing */
1708 1.3.2.4 bouyer reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
1709 1.3.2.4 bouyer reg &= ~CB_BCR_INTR_IREQ_ENABLE;
1710 1.3.2.4 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg);
1711 1.3.2.2 bouyer
1712 1.3.2.2 bouyer switch (sc->sc_chipset) {
1713 1.3.2.2 bouyer case CB_TI113X:
1714 1.3.2.4 bouyer reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL);
1715 1.3.2.4 bouyer /* functional intr enabled */
1716 1.3.2.4 bouyer reg |= PCI113X_CBCTRL_PCI_INTR;
1717 1.3.2.4 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg);
1718 1.3.2.4 bouyer break;
1719 1.3.2.2 bouyer default:
1720 1.3.2.2 bouyer break;
1721 1.3.2.2 bouyer }
1722 1.3.2.2 bouyer }
1723 1.3.2.2 bouyer
1724 1.3.2.2 bouyer /*
1725 1.3.2.2 bouyer * Allocate a room for interrupt handler structure.
1726 1.3.2.2 bouyer */
1727 1.3.2.2 bouyer if (NULL == (newpil =
1728 1.3.2.2 bouyer (struct pccbb_intrhand_list *)malloc(sizeof(struct
1729 1.3.2.2 bouyer pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) {
1730 1.3.2.2 bouyer return NULL;
1731 1.3.2.2 bouyer }
1732 1.1 haya
1733 1.3.2.2 bouyer newpil->pil_func = func;
1734 1.3.2.2 bouyer newpil->pil_arg = arg;
1735 1.3.2.2 bouyer newpil->pil_level = level;
1736 1.3.2.2 bouyer newpil->pil_next = NULL;
1737 1.3.2.2 bouyer
1738 1.3.2.2 bouyer if (sc->sc_pil == NULL) {
1739 1.3.2.2 bouyer sc->sc_pil = newpil;
1740 1.3.2.2 bouyer } else {
1741 1.3.2.2 bouyer for (pil = sc->sc_pil; pil->pil_next != NULL;
1742 1.3.2.2 bouyer pil = pil->pil_next);
1743 1.3.2.2 bouyer pil->pil_next = newpil;
1744 1.3.2.2 bouyer }
1745 1.1 haya
1746 1.3.2.2 bouyer DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil));
1747 1.3.2.2 bouyer
1748 1.3.2.2 bouyer return newpil;
1749 1.1 haya }
1750 1.1 haya
1751 1.3.2.2 bouyer /*
1752 1.3.2.2 bouyer * static void *pccbb_intr_disestablish(struct pccbb_softc *sc,
1753 1.3.2.2 bouyer * void *ih)
1754 1.3.2.2 bouyer *
1755 1.3.2.2 bouyer * This function removes an interrupt handler pointed by ih.
1756 1.3.2.2 bouyer */
1757 1.3.2.2 bouyer static void
1758 1.3.2.2 bouyer pccbb_intr_disestablish(sc, ih)
1759 1.3.2.2 bouyer struct pccbb_softc *sc;
1760 1.3.2.2 bouyer void *ih;
1761 1.3.2.2 bouyer {
1762 1.3.2.2 bouyer struct pccbb_intrhand_list *pil, **pil_prev;
1763 1.3.2.4 bouyer pcireg_t reg;
1764 1.3.2.2 bouyer
1765 1.3.2.2 bouyer DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil));
1766 1.3.2.2 bouyer
1767 1.3.2.2 bouyer pil_prev = &sc->sc_pil;
1768 1.3.2.2 bouyer
1769 1.3.2.2 bouyer for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) {
1770 1.3.2.2 bouyer if (pil == ih) {
1771 1.3.2.2 bouyer *pil_prev = pil->pil_next;
1772 1.3.2.2 bouyer free(pil, M_DEVBUF);
1773 1.3.2.2 bouyer DPRINTF(("pccbb_intr_disestablish frees one pil\n"));
1774 1.3.2.2 bouyer break;
1775 1.3.2.2 bouyer }
1776 1.3.2.2 bouyer pil_prev = &pil->pil_next;
1777 1.3.2.2 bouyer }
1778 1.1 haya
1779 1.3.2.2 bouyer if (sc->sc_pil == NULL) {
1780 1.3.2.2 bouyer /* No interrupt handlers */
1781 1.1 haya
1782 1.3.2.2 bouyer DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n"));
1783 1.1 haya
1784 1.3.2.4 bouyer /* stop routing PCI intr */
1785 1.3.2.4 bouyer reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
1786 1.3.2.4 bouyer reg |= CB_BCR_INTR_IREQ_ENABLE;
1787 1.3.2.4 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg);
1788 1.3.2.4 bouyer
1789 1.3.2.2 bouyer switch (sc->sc_chipset) {
1790 1.3.2.2 bouyer case CB_TI113X:
1791 1.3.2.4 bouyer reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL);
1792 1.3.2.4 bouyer /* functional intr disabled */
1793 1.3.2.4 bouyer reg &= ~PCI113X_CBCTRL_PCI_INTR;
1794 1.3.2.4 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg);
1795 1.3.2.4 bouyer break;
1796 1.3.2.2 bouyer default:
1797 1.3.2.2 bouyer break;
1798 1.3.2.2 bouyer }
1799 1.3.2.2 bouyer }
1800 1.3.2.2 bouyer }
1801 1.1 haya
1802 1.1 haya #if defined SHOW_REGS
1803 1.1 haya static void
1804 1.1 haya cb_show_regs(pc, tag, memt, memh)
1805 1.3.2.2 bouyer pci_chipset_tag_t pc;
1806 1.3.2.2 bouyer pcitag_t tag;
1807 1.3.2.2 bouyer bus_space_tag_t memt;
1808 1.3.2.2 bouyer bus_space_handle_t memh;
1809 1.3.2.2 bouyer {
1810 1.3.2.2 bouyer int i;
1811 1.3.2.2 bouyer printf("PCI config regs:");
1812 1.3.2.2 bouyer for (i = 0; i < 0x50; i += 4) {
1813 1.3.2.2 bouyer if (i % 16 == 0) {
1814 1.3.2.2 bouyer printf("\n 0x%02x:", i);
1815 1.3.2.2 bouyer }
1816 1.3.2.2 bouyer printf(" %08x", pci_conf_read(pc, tag, i));
1817 1.3.2.2 bouyer }
1818 1.3.2.2 bouyer for (i = 0x80; i < 0xb0; i += 4) {
1819 1.3.2.2 bouyer if (i % 16 == 0) {
1820 1.3.2.2 bouyer printf("\n 0x%02x:", i);
1821 1.3.2.2 bouyer }
1822 1.3.2.2 bouyer printf(" %08x", pci_conf_read(pc, tag, i));
1823 1.3.2.2 bouyer }
1824 1.1 haya
1825 1.3.2.2 bouyer if (memh == 0) {
1826 1.3.2.2 bouyer printf("\n");
1827 1.3.2.2 bouyer return;
1828 1.3.2.2 bouyer }
1829 1.1 haya
1830 1.3.2.2 bouyer printf("\nsocket regs:");
1831 1.3.2.2 bouyer for (i = 0; i <= 0x10; i += 0x04) {
1832 1.3.2.2 bouyer printf(" %08x", bus_space_read_4(memt, memh, i));
1833 1.3.2.2 bouyer }
1834 1.3.2.2 bouyer printf("\nExCA regs:");
1835 1.3.2.2 bouyer for (i = 0; i < 0x08; ++i) {
1836 1.3.2.2 bouyer printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i));
1837 1.3.2.2 bouyer }
1838 1.3.2.2 bouyer printf("\n");
1839 1.3.2.2 bouyer return;
1840 1.1 haya }
1841 1.1 haya #endif
1842 1.1 haya
1843 1.3.2.1 thorpej /*
1844 1.3.2.1 thorpej * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc,
1845 1.3.2.1 thorpej * int busno, int devno, int function)
1846 1.3.2.1 thorpej * This is the function to make a tag to access config space of
1847 1.3.2.1 thorpej * a CardBus Card. It works same as pci_conf_read.
1848 1.3.2.1 thorpej */
1849 1.1 haya static cardbustag_t
1850 1.1 haya pccbb_make_tag(cc, busno, devno, function)
1851 1.3.2.2 bouyer cardbus_chipset_tag_t cc;
1852 1.3.2.2 bouyer int busno, devno, function;
1853 1.1 haya {
1854 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)cc;
1855 1.1 haya
1856 1.3.2.2 bouyer return pci_make_tag(sc->sc_pc, busno, devno, function);
1857 1.1 haya }
1858 1.1 haya
1859 1.1 haya static void
1860 1.1 haya pccbb_free_tag(cc, tag)
1861 1.3.2.2 bouyer cardbus_chipset_tag_t cc;
1862 1.3.2.2 bouyer cardbustag_t tag;
1863 1.1 haya {
1864 1.1 haya }
1865 1.1 haya
1866 1.3.2.1 thorpej /*
1867 1.3.2.1 thorpej * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc,
1868 1.3.2.1 thorpej * cardbustag_t tag, int offset)
1869 1.3.2.1 thorpej * This is the function to read the config space of a CardBus Card.
1870 1.3.2.1 thorpej * It works same as pci_conf_read.
1871 1.3.2.1 thorpej */
1872 1.1 haya static cardbusreg_t
1873 1.1 haya pccbb_conf_read(cc, tag, offset)
1874 1.3.2.2 bouyer cardbus_chipset_tag_t cc;
1875 1.3.2.2 bouyer cardbustag_t tag;
1876 1.3.2.2 bouyer int offset; /* register offset */
1877 1.1 haya {
1878 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)cc;
1879 1.1 haya
1880 1.3.2.2 bouyer return pci_conf_read(sc->sc_pc, tag, offset);
1881 1.1 haya }
1882 1.1 haya
1883 1.3.2.1 thorpej /*
1884 1.3.2.1 thorpej * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag,
1885 1.3.2.1 thorpej * int offs, cardbusreg_t val)
1886 1.3.2.1 thorpej * This is the function to write the config space of a CardBus Card.
1887 1.3.2.1 thorpej * It works same as pci_conf_write.
1888 1.3.2.1 thorpej */
1889 1.1 haya static void
1890 1.1 haya pccbb_conf_write(cc, tag, reg, val)
1891 1.3.2.2 bouyer cardbus_chipset_tag_t cc;
1892 1.3.2.2 bouyer cardbustag_t tag;
1893 1.3.2.2 bouyer int reg; /* register offset */
1894 1.3.2.2 bouyer cardbusreg_t val;
1895 1.1 haya {
1896 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)cc;
1897 1.1 haya
1898 1.3.2.2 bouyer pci_conf_write(sc->sc_pc, tag, reg, val);
1899 1.1 haya }
1900 1.1 haya
1901 1.1 haya #if 0
1902 1.1 haya STATIC int
1903 1.1 haya pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch,
1904 1.3.2.2 bouyer bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask,
1905 1.3.2.2 bouyer int speed, int flags,
1906 1.3.2.2 bouyer bus_space_handle_t * iohp)
1907 1.1 haya #endif
1908 1.3.2.1 thorpej /*
1909 1.3.2.1 thorpej * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch,
1910 1.3.2.1 thorpej * bus_addr_t start, bus_size_t size,
1911 1.3.2.1 thorpej * bus_size_t align,
1912 1.3.2.1 thorpej * struct pcmcia_io_handle *pcihp
1913 1.3.2.1 thorpej *
1914 1.3.2.1 thorpej * This function only allocates I/O region for pccard. This function
1915 1.3.2.2 bouyer * never maps the allocated region to pccard I/O area.
1916 1.3.2.1 thorpej *
1917 1.3.2.1 thorpej * XXX: The interface of this function is not very good, I believe.
1918 1.3.2.1 thorpej */
1919 1.3.2.2 bouyer STATIC int
1920 1.1 haya pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp)
1921 1.3.2.2 bouyer pcmcia_chipset_handle_t pch;
1922 1.3.2.2 bouyer bus_addr_t start; /* start address */
1923 1.3.2.2 bouyer bus_size_t size;
1924 1.3.2.2 bouyer bus_size_t align;
1925 1.3.2.2 bouyer struct pcmcia_io_handle *pcihp;
1926 1.3.2.2 bouyer {
1927 1.3.2.2 bouyer struct pcic_handle *ph = (struct pcic_handle *)pch;
1928 1.3.2.2 bouyer bus_addr_t ioaddr;
1929 1.3.2.2 bouyer int flags = 0;
1930 1.3.2.2 bouyer bus_space_tag_t iot;
1931 1.3.2.2 bouyer bus_space_handle_t ioh;
1932 1.3.2.8 bouyer bus_addr_t mask;
1933 1.1 haya #if rbus
1934 1.3.2.2 bouyer rbus_tag_t rb;
1935 1.1 haya #endif
1936 1.3.2.2 bouyer if (align == 0) {
1937 1.3.2.2 bouyer align = size; /* XXX: funny??? */
1938 1.3.2.2 bouyer }
1939 1.1 haya
1940 1.3.2.8 bouyer if (start != 0) {
1941 1.3.2.8 bouyer /* XXX: assume all card decode lower 10 bits by its hardware */
1942 1.3.2.8 bouyer mask = 0x3ff;
1943 1.3.2.8 bouyer } else {
1944 1.3.2.8 bouyer /*
1945 1.3.2.8 bouyer * calculate mask:
1946 1.3.2.8 bouyer * 1. get the most significant bit of size (call it msb).
1947 1.3.2.8 bouyer * 2. compare msb with the value of size.
1948 1.3.2.8 bouyer * 3. if size is larger, shift msb left once.
1949 1.3.2.8 bouyer * 4. obtain mask value to decrement msb.
1950 1.3.2.8 bouyer */
1951 1.3.2.8 bouyer bus_size_t size_tmp = size;
1952 1.3.2.8 bouyer int shifts = 0;
1953 1.3.2.8 bouyer
1954 1.3.2.8 bouyer mask = 1;
1955 1.3.2.8 bouyer while (size_tmp) {
1956 1.3.2.8 bouyer ++shifts;
1957 1.3.2.8 bouyer size_tmp >>= 1;
1958 1.3.2.8 bouyer }
1959 1.3.2.8 bouyer mask = (1 << shifts);
1960 1.3.2.8 bouyer if (mask < size) {
1961 1.3.2.8 bouyer mask <<= 1;
1962 1.3.2.8 bouyer }
1963 1.3.2.8 bouyer --mask;
1964 1.3.2.8 bouyer }
1965 1.3.2.8 bouyer
1966 1.3.2.2 bouyer /*
1967 1.3.2.2 bouyer * Allocate some arbitrary I/O space.
1968 1.3.2.2 bouyer */
1969 1.1 haya
1970 1.3.2.2 bouyer iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot;
1971 1.1 haya
1972 1.1 haya #if rbus
1973 1.3.2.2 bouyer rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot;
1974 1.3.2.8 bouyer if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) {
1975 1.3.2.2 bouyer return 1;
1976 1.3.2.2 bouyer }
1977 1.3.2.2 bouyer #else
1978 1.3.2.2 bouyer if (start) {
1979 1.3.2.2 bouyer ioaddr = start;
1980 1.3.2.2 bouyer if (bus_space_map(iot, start, size, 0, &ioh)) {
1981 1.3.2.2 bouyer return 1;
1982 1.3.2.2 bouyer }
1983 1.3.2.2 bouyer DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n",
1984 1.3.2.2 bouyer (u_long) ioaddr, (u_long) size));
1985 1.3.2.2 bouyer } else {
1986 1.3.2.2 bouyer flags |= PCMCIA_IO_ALLOCATED;
1987 1.3.2.2 bouyer if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ ,
1988 1.3.2.2 bouyer 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */
1989 1.3.2.2 bouyer size, align, 0, 0, &ioaddr, &ioh)) {
1990 1.3.2.2 bouyer /* No room be able to be get. */
1991 1.3.2.2 bouyer return 1;
1992 1.3.2.2 bouyer }
1993 1.3.2.2 bouyer DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n",
1994 1.3.2.2 bouyer (u_long) ioaddr, (u_long) size));
1995 1.3.2.2 bouyer }
1996 1.1 haya #endif
1997 1.1 haya
1998 1.3.2.2 bouyer pcihp->iot = iot;
1999 1.3.2.2 bouyer pcihp->ioh = ioh;
2000 1.3.2.2 bouyer pcihp->addr = ioaddr;
2001 1.3.2.2 bouyer pcihp->size = size;
2002 1.3.2.2 bouyer pcihp->flags = flags;
2003 1.1 haya
2004 1.3.2.2 bouyer return 0;
2005 1.1 haya }
2006 1.1 haya
2007 1.3.2.1 thorpej /*
2008 1.3.2.1 thorpej * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch,
2009 1.3.2.1 thorpej * struct pcmcia_io_handle *pcihp)
2010 1.3.2.1 thorpej *
2011 1.3.2.1 thorpej * This function only frees I/O region for pccard.
2012 1.3.2.1 thorpej *
2013 1.3.2.1 thorpej * XXX: The interface of this function is not very good, I believe.
2014 1.3.2.1 thorpej */
2015 1.3.2.2 bouyer void
2016 1.1 haya pccbb_pcmcia_io_free(pch, pcihp)
2017 1.3.2.2 bouyer pcmcia_chipset_handle_t pch;
2018 1.3.2.2 bouyer struct pcmcia_io_handle *pcihp;
2019 1.1 haya {
2020 1.1 haya #if !rbus
2021 1.3.2.2 bouyer bus_space_tag_t iot = pcihp->iot;
2022 1.1 haya #endif
2023 1.3.2.2 bouyer bus_space_handle_t ioh = pcihp->ioh;
2024 1.3.2.2 bouyer bus_size_t size = pcihp->size;
2025 1.1 haya
2026 1.1 haya #if rbus
2027 1.3.2.2 bouyer struct pccbb_softc *sc =
2028 1.3.2.2 bouyer (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent;
2029 1.3.2.2 bouyer rbus_tag_t rb = sc->sc_rbus_iot;
2030 1.1 haya
2031 1.3.2.2 bouyer rbus_space_free(rb, ioh, size, NULL);
2032 1.1 haya #else
2033 1.3.2.2 bouyer if (pcihp->flags & PCMCIA_IO_ALLOCATED)
2034 1.3.2.2 bouyer bus_space_free(iot, ioh, size);
2035 1.3.2.2 bouyer else
2036 1.3.2.2 bouyer bus_space_unmap(iot, ioh, size);
2037 1.1 haya #endif
2038 1.1 haya }
2039 1.1 haya
2040 1.3.2.1 thorpej /*
2041 1.3.2.1 thorpej * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width,
2042 1.3.2.1 thorpej * bus_addr_t offset, bus_size_t size,
2043 1.3.2.1 thorpej * struct pcmcia_io_handle *pcihp,
2044 1.3.2.1 thorpej * int *windowp)
2045 1.3.2.1 thorpej *
2046 1.3.2.1 thorpej * This function maps the allocated I/O region to pccard. This function
2047 1.3.2.1 thorpej * never allocates any I/O region for pccard I/O area. I don't
2048 1.3.2.1 thorpej * understand why the original authors of pcmciabus separated alloc and
2049 1.3.2.1 thorpej * map. I believe the two must be unite.
2050 1.3.2.1 thorpej *
2051 1.3.2.1 thorpej * XXX: no wait timing control?
2052 1.3.2.1 thorpej */
2053 1.3.2.2 bouyer int
2054 1.1 haya pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp)
2055 1.3.2.2 bouyer pcmcia_chipset_handle_t pch;
2056 1.3.2.2 bouyer int width;
2057 1.3.2.2 bouyer bus_addr_t offset;
2058 1.3.2.2 bouyer bus_size_t size;
2059 1.3.2.2 bouyer struct pcmcia_io_handle *pcihp;
2060 1.3.2.2 bouyer int *windowp;
2061 1.3.2.2 bouyer {
2062 1.3.2.2 bouyer struct pcic_handle *ph = (struct pcic_handle *)pch;
2063 1.3.2.2 bouyer bus_addr_t ioaddr = pcihp->addr + offset;
2064 1.3.2.2 bouyer int i, win;
2065 1.1 haya #if defined CBB_DEBUG
2066 1.3.2.2 bouyer static char *width_names[] = { "dynamic", "io8", "io16" };
2067 1.1 haya #endif
2068 1.1 haya
2069 1.3.2.2 bouyer /* Sanity check I/O handle. */
2070 1.1 haya
2071 1.3.2.2 bouyer if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) {
2072 1.3.2.2 bouyer panic("pccbb_pcmcia_io_map iot is bogus");
2073 1.3.2.2 bouyer }
2074 1.1 haya
2075 1.3.2.2 bouyer /* XXX Sanity check offset/size. */
2076 1.1 haya
2077 1.3.2.2 bouyer win = -1;
2078 1.3.2.2 bouyer for (i = 0; i < PCIC_IO_WINS; i++) {
2079 1.3.2.2 bouyer if ((ph->ioalloc & (1 << i)) == 0) {
2080 1.3.2.2 bouyer win = i;
2081 1.3.2.2 bouyer ph->ioalloc |= (1 << i);
2082 1.3.2.2 bouyer break;
2083 1.3.2.2 bouyer }
2084 1.3.2.2 bouyer }
2085 1.1 haya
2086 1.3.2.2 bouyer if (win == -1) {
2087 1.3.2.2 bouyer return 1;
2088 1.3.2.2 bouyer }
2089 1.1 haya
2090 1.3.2.2 bouyer *windowp = win;
2091 1.1 haya
2092 1.3.2.2 bouyer /* XXX this is pretty gross */
2093 1.1 haya
2094 1.3.2.2 bouyer DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n",
2095 1.3.2.2 bouyer win, width_names[width], (u_long) ioaddr, (u_long) size));
2096 1.1 haya
2097 1.3.2.2 bouyer /* XXX wtf is this doing here? */
2098 1.1 haya
2099 1.1 haya #if 0
2100 1.3.2.2 bouyer printf(" port 0x%lx", (u_long) ioaddr);
2101 1.3.2.2 bouyer if (size > 1) {
2102 1.3.2.2 bouyer printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1);
2103 1.3.2.2 bouyer }
2104 1.1 haya #endif
2105 1.1 haya
2106 1.3.2.2 bouyer ph->io[win].addr = ioaddr;
2107 1.3.2.2 bouyer ph->io[win].size = size;
2108 1.3.2.2 bouyer ph->io[win].width = width;
2109 1.1 haya
2110 1.3.2.2 bouyer /* actual dirty register-value changing in the function below. */
2111 1.3.2.2 bouyer pccbb_pcmcia_do_io_map(ph, win);
2112 1.1 haya
2113 1.3.2.2 bouyer return 0;
2114 1.1 haya }
2115 1.1 haya
2116 1.3.2.1 thorpej /*
2117 1.3.2.1 thorpej * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win)
2118 1.3.2.1 thorpej *
2119 1.3.2.1 thorpej * This function changes register-value to map I/O region for pccard.
2120 1.3.2.1 thorpej */
2121 1.3.2.2 bouyer static void
2122 1.1 haya pccbb_pcmcia_do_io_map(ph, win)
2123 1.3.2.2 bouyer struct pcic_handle *ph;
2124 1.3.2.2 bouyer int win;
2125 1.1 haya {
2126 1.3.2.2 bouyer static u_int8_t pcic_iowidth[3] = {
2127 1.3.2.2 bouyer PCIC_IOCTL_IO0_IOCS16SRC_CARD,
2128 1.3.2.2 bouyer PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
2129 1.3.2.2 bouyer PCIC_IOCTL_IO0_DATASIZE_8BIT,
2130 1.3.2.2 bouyer PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
2131 1.3.2.2 bouyer PCIC_IOCTL_IO0_DATASIZE_16BIT,
2132 1.3.2.2 bouyer };
2133 1.1 haya
2134 1.1 haya #define PCIC_SIA_START_LOW 0
2135 1.1 haya #define PCIC_SIA_START_HIGH 1
2136 1.1 haya #define PCIC_SIA_STOP_LOW 2
2137 1.1 haya #define PCIC_SIA_STOP_HIGH 3
2138 1.1 haya
2139 1.3.2.2 bouyer int regbase_win = 0x8 + win * 0x04;
2140 1.3.2.2 bouyer u_int8_t ioctl, enable;
2141 1.1 haya
2142 1.3.2.2 bouyer DPRINTF(
2143 1.3.2.2 bouyer ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n",
2144 1.3.2.2 bouyer win, (long)ph->io[win].addr, (long)ph->io[win].size,
2145 1.3.2.2 bouyer ph->io[win].width * 8));
2146 1.3.2.2 bouyer
2147 1.3.2.2 bouyer Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW,
2148 1.3.2.2 bouyer ph->io[win].addr & 0xff);
2149 1.3.2.2 bouyer Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH,
2150 1.3.2.2 bouyer (ph->io[win].addr >> 8) & 0xff);
2151 1.3.2.2 bouyer
2152 1.3.2.2 bouyer Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW,
2153 1.3.2.2 bouyer (ph->io[win].addr + ph->io[win].size - 1) & 0xff);
2154 1.3.2.2 bouyer Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH,
2155 1.3.2.2 bouyer ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff);
2156 1.3.2.2 bouyer
2157 1.3.2.2 bouyer ioctl = Pcic_read(ph, PCIC_IOCTL);
2158 1.3.2.2 bouyer enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
2159 1.3.2.2 bouyer switch (win) {
2160 1.3.2.2 bouyer case 0:
2161 1.3.2.2 bouyer ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT |
2162 1.3.2.2 bouyer PCIC_IOCTL_IO0_IOCS16SRC_MASK |
2163 1.3.2.2 bouyer PCIC_IOCTL_IO0_DATASIZE_MASK);
2164 1.3.2.2 bouyer ioctl |= pcic_iowidth[ph->io[win].width];
2165 1.3.2.2 bouyer enable |= PCIC_ADDRWIN_ENABLE_IO0;
2166 1.3.2.2 bouyer break;
2167 1.3.2.2 bouyer case 1:
2168 1.3.2.2 bouyer ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT |
2169 1.3.2.2 bouyer PCIC_IOCTL_IO1_IOCS16SRC_MASK |
2170 1.3.2.2 bouyer PCIC_IOCTL_IO1_DATASIZE_MASK);
2171 1.3.2.2 bouyer ioctl |= (pcic_iowidth[ph->io[win].width] << 4);
2172 1.3.2.2 bouyer enable |= PCIC_ADDRWIN_ENABLE_IO1;
2173 1.3.2.2 bouyer break;
2174 1.3.2.2 bouyer }
2175 1.3.2.2 bouyer Pcic_write(ph, PCIC_IOCTL, ioctl);
2176 1.3.2.2 bouyer Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable);
2177 1.1 haya #if defined CBB_DEBUG
2178 1.3.2.2 bouyer {
2179 1.3.2.2 bouyer u_int8_t start_low =
2180 1.3.2.2 bouyer Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW);
2181 1.3.2.2 bouyer u_int8_t start_high =
2182 1.3.2.2 bouyer Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH);
2183 1.3.2.2 bouyer u_int8_t stop_low =
2184 1.3.2.2 bouyer Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW);
2185 1.3.2.2 bouyer u_int8_t stop_high =
2186 1.3.2.2 bouyer Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH);
2187 1.3.2.2 bouyer printf
2188 1.3.2.2 bouyer (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n",
2189 1.3.2.2 bouyer start_low, start_high, stop_low, stop_high, ioctl, enable);
2190 1.3.2.2 bouyer }
2191 1.1 haya #endif
2192 1.1 haya }
2193 1.1 haya
2194 1.3.2.1 thorpej /*
2195 1.3.2.1 thorpej * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win)
2196 1.3.2.1 thorpej *
2197 1.3.2.2 bouyer * This function unmaps I/O region. No return value.
2198 1.3.2.1 thorpej */
2199 1.3.2.2 bouyer STATIC void
2200 1.1 haya pccbb_pcmcia_io_unmap(pch, win)
2201 1.3.2.2 bouyer pcmcia_chipset_handle_t pch;
2202 1.3.2.2 bouyer int win;
2203 1.1 haya {
2204 1.3.2.2 bouyer struct pcic_handle *ph = (struct pcic_handle *)pch;
2205 1.3.2.2 bouyer int reg;
2206 1.1 haya
2207 1.3.2.2 bouyer if (win >= PCIC_IO_WINS || win < 0) {
2208 1.3.2.2 bouyer panic("pccbb_pcmcia_io_unmap: window out of range");
2209 1.3.2.2 bouyer }
2210 1.1 haya
2211 1.3.2.2 bouyer reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
2212 1.3.2.2 bouyer switch (win) {
2213 1.3.2.2 bouyer case 0:
2214 1.3.2.2 bouyer reg &= ~PCIC_ADDRWIN_ENABLE_IO0;
2215 1.3.2.2 bouyer break;
2216 1.3.2.2 bouyer case 1:
2217 1.3.2.2 bouyer reg &= ~PCIC_ADDRWIN_ENABLE_IO1;
2218 1.3.2.2 bouyer break;
2219 1.3.2.2 bouyer }
2220 1.3.2.2 bouyer Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg);
2221 1.1 haya
2222 1.3.2.2 bouyer ph->ioalloc &= ~(1 << win);
2223 1.1 haya }
2224 1.1 haya
2225 1.3.2.1 thorpej /*
2226 1.3.2.1 thorpej * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph)
2227 1.3.2.1 thorpej *
2228 1.3.2.1 thorpej * This function enables the card. All information is stored in
2229 1.3.2.1 thorpej * the first argument, pcmcia_chipset_handle_t.
2230 1.3.2.1 thorpej */
2231 1.1 haya static void
2232 1.1 haya pccbb_pcmcia_wait_ready(ph)
2233 1.3.2.2 bouyer struct pcic_handle *ph;
2234 1.1 haya {
2235 1.3.2.2 bouyer int i;
2236 1.1 haya
2237 1.3.2.2 bouyer DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n",
2238 1.3.2.2 bouyer Pcic_read(ph, PCIC_IF_STATUS)));
2239 1.1 haya
2240 1.3.2.8 bouyer for (i = 0; i < 2000; i++) {
2241 1.3.2.2 bouyer if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) {
2242 1.3.2.2 bouyer return;
2243 1.3.2.2 bouyer }
2244 1.3.2.8 bouyer DELAY_MS(2, ph->ph_parent);
2245 1.1 haya #ifdef CBB_DEBUG
2246 1.3.2.8 bouyer if ((i > 1000) && (i % 25 == 24))
2247 1.3.2.2 bouyer printf(".");
2248 1.1 haya #endif
2249 1.3.2.2 bouyer }
2250 1.1 haya
2251 1.1 haya #ifdef DIAGNOSTIC
2252 1.3.2.2 bouyer printf("pcic_wait_ready: ready never happened, status = %02x\n",
2253 1.3.2.2 bouyer Pcic_read(ph, PCIC_IF_STATUS));
2254 1.1 haya #endif
2255 1.1 haya }
2256 1.1 haya
2257 1.3.2.1 thorpej /*
2258 1.3.2.1 thorpej * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch)
2259 1.3.2.1 thorpej *
2260 1.3.2.1 thorpej * This function enables the card. All information is stored in
2261 1.3.2.1 thorpej * the first argument, pcmcia_chipset_handle_t.
2262 1.3.2.1 thorpej */
2263 1.1 haya STATIC void
2264 1.1 haya pccbb_pcmcia_socket_enable(pch)
2265 1.3.2.2 bouyer pcmcia_chipset_handle_t pch;
2266 1.1 haya {
2267 1.3.2.2 bouyer struct pcic_handle *ph = (struct pcic_handle *)pch;
2268 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
2269 1.3.2.2 bouyer int cardtype, win;
2270 1.3.2.2 bouyer u_int8_t power, intr;
2271 1.3.2.2 bouyer pcireg_t spsr;
2272 1.3.2.2 bouyer int voltage;
2273 1.3.2.2 bouyer
2274 1.3.2.2 bouyer /* this bit is mostly stolen from pcic_attach_card */
2275 1.3.2.2 bouyer
2276 1.3.2.2 bouyer DPRINTF(("pccbb_pcmcia_socket_enable: "));
2277 1.3.2.2 bouyer
2278 1.3.2.2 bouyer /* get card Vcc info */
2279 1.3.2.2 bouyer
2280 1.3.2.2 bouyer spsr =
2281 1.3.2.2 bouyer bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
2282 1.3.2.2 bouyer CB_SOCKET_STAT);
2283 1.3.2.2 bouyer if (spsr & CB_SOCKET_STAT_5VCARD) {
2284 1.3.2.2 bouyer DPRINTF(("5V card\n"));
2285 1.3.2.2 bouyer voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC;
2286 1.3.2.2 bouyer } else if (spsr & CB_SOCKET_STAT_3VCARD) {
2287 1.3.2.2 bouyer DPRINTF(("3V card\n"));
2288 1.3.2.2 bouyer voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC;
2289 1.3.2.2 bouyer } else {
2290 1.3.2.2 bouyer printf("?V card, 0x%x\n", spsr); /* XXX */
2291 1.3.2.2 bouyer return;
2292 1.3.2.2 bouyer }
2293 1.1 haya
2294 1.3.2.7 bouyer /* disable socket: negate output enable bit and power off */
2295 1.1 haya
2296 1.3.2.4 bouyer power = 0;
2297 1.3.2.2 bouyer Pcic_write(ph, PCIC_PWRCTL, power);
2298 1.1 haya
2299 1.3.2.2 bouyer /* power down the socket to reset it, clear the card reset pin */
2300 1.1 haya
2301 1.3.2.2 bouyer pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
2302 1.1 haya
2303 1.3.2.2 bouyer /*
2304 1.3.2.2 bouyer * wait 200ms until power fails (Tpf). Then, wait 100ms since
2305 1.3.2.2 bouyer * we are changing Vcc (Toff).
2306 1.3.2.2 bouyer */
2307 1.3.2.2 bouyer /* delay(300*1000); too much */
2308 1.1 haya
2309 1.3.2.4 bouyer /* assert reset bit */
2310 1.3.2.4 bouyer intr = Pcic_read(ph, PCIC_INTR);
2311 1.3.2.4 bouyer intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK);
2312 1.3.2.4 bouyer Pcic_write(ph, PCIC_INTR, intr);
2313 1.1 haya
2314 1.3.2.4 bouyer /* power up the socket and output enable */
2315 1.3.2.2 bouyer power = Pcic_read(ph, PCIC_PWRCTL);
2316 1.3.2.2 bouyer power |= PCIC_PWRCTL_OE;
2317 1.3.2.2 bouyer Pcic_write(ph, PCIC_PWRCTL, power);
2318 1.3.2.4 bouyer pccbb_power(sc, voltage);
2319 1.1 haya
2320 1.3.2.2 bouyer /*
2321 1.3.2.8 bouyer * hold RESET at least 20 ms: the spec says only 10 us is
2322 1.3.2.8 bouyer * enough, but TI1130 requires at least 20 ms.
2323 1.3.2.2 bouyer */
2324 1.3.2.8 bouyer #if 0 /* XXX called on interrupt context */
2325 1.3.2.8 bouyer DELAY_MS(20, sc);
2326 1.3.2.8 bouyer #else
2327 1.3.2.8 bouyer delay(20 * 1000);
2328 1.3.2.8 bouyer #endif
2329 1.1 haya
2330 1.3.2.2 bouyer /* clear the reset flag */
2331 1.1 haya
2332 1.3.2.2 bouyer intr |= PCIC_INTR_RESET;
2333 1.3.2.2 bouyer Pcic_write(ph, PCIC_INTR, intr);
2334 1.1 haya
2335 1.3.2.2 bouyer /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */
2336 1.1 haya
2337 1.3.2.8 bouyer #if 0 /* XXX called on interrupt context */
2338 1.3.2.8 bouyer DELAY_MS(20, sc);
2339 1.3.2.8 bouyer #else
2340 1.3.2.8 bouyer delay(20 * 1000);
2341 1.3.2.8 bouyer #endif
2342 1.1 haya
2343 1.3.2.2 bouyer /* wait for the chip to finish initializing */
2344 1.1 haya
2345 1.3.2.2 bouyer pccbb_pcmcia_wait_ready(ph);
2346 1.1 haya
2347 1.3.2.2 bouyer /* zero out the address windows */
2348 1.1 haya
2349 1.3.2.2 bouyer Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0);
2350 1.1 haya
2351 1.3.2.2 bouyer /* set the card type */
2352 1.1 haya
2353 1.3.2.2 bouyer cardtype = pcmcia_card_gettype(ph->pcmcia);
2354 1.1 haya
2355 1.3.2.2 bouyer intr |= ((cardtype == PCMCIA_IFTYPE_IO) ?
2356 1.3.2.2 bouyer PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM);
2357 1.3.2.2 bouyer Pcic_write(ph, PCIC_INTR, intr);
2358 1.1 haya
2359 1.3.2.2 bouyer DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n",
2360 1.3.2.2 bouyer ph->ph_parent->dv_xname, ph->sock,
2361 1.3.2.2 bouyer ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr));
2362 1.1 haya
2363 1.3.2.2 bouyer /* reinstall all the memory and io mappings */
2364 1.1 haya
2365 1.3.2.2 bouyer for (win = 0; win < PCIC_MEM_WINS; ++win) {
2366 1.3.2.2 bouyer if (ph->memalloc & (1 << win)) {
2367 1.3.2.2 bouyer pccbb_pcmcia_do_mem_map(ph, win);
2368 1.3.2.2 bouyer }
2369 1.3.2.2 bouyer }
2370 1.1 haya
2371 1.3.2.2 bouyer for (win = 0; win < PCIC_IO_WINS; ++win) {
2372 1.3.2.2 bouyer if (ph->ioalloc & (1 << win)) {
2373 1.3.2.2 bouyer pccbb_pcmcia_do_io_map(ph, win);
2374 1.3.2.2 bouyer }
2375 1.3.2.2 bouyer }
2376 1.1 haya }
2377 1.1 haya
2378 1.3.2.1 thorpej /*
2379 1.3.2.1 thorpej * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph)
2380 1.3.2.1 thorpej *
2381 1.3.2.1 thorpej * This function disables the card. All information is stored in
2382 1.3.2.1 thorpej * the first argument, pcmcia_chipset_handle_t.
2383 1.3.2.1 thorpej */
2384 1.1 haya STATIC void
2385 1.1 haya pccbb_pcmcia_socket_disable(pch)
2386 1.3.2.2 bouyer pcmcia_chipset_handle_t pch;
2387 1.1 haya {
2388 1.3.2.2 bouyer struct pcic_handle *ph = (struct pcic_handle *)pch;
2389 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
2390 1.3.2.2 bouyer u_int8_t power, intr;
2391 1.3.2.2 bouyer
2392 1.3.2.2 bouyer DPRINTF(("pccbb_pcmcia_socket_disable\n"));
2393 1.3.2.2 bouyer
2394 1.3.2.2 bouyer /* reset signal asserting... */
2395 1.3.2.2 bouyer
2396 1.3.2.2 bouyer intr = Pcic_read(ph, PCIC_INTR);
2397 1.3.2.2 bouyer intr &= ~(PCIC_INTR_CARDTYPE_MASK);
2398 1.3.2.2 bouyer Pcic_write(ph, PCIC_INTR, intr);
2399 1.3.2.2 bouyer delay(2 * 1000);
2400 1.3.2.2 bouyer
2401 1.3.2.2 bouyer /* power down the socket */
2402 1.3.2.2 bouyer power = Pcic_read(ph, PCIC_PWRCTL);
2403 1.3.2.2 bouyer power &= ~PCIC_PWRCTL_OE;
2404 1.3.2.2 bouyer Pcic_write(ph, PCIC_PWRCTL, power);
2405 1.3.2.2 bouyer pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
2406 1.3.2.2 bouyer /*
2407 1.3.2.2 bouyer * wait 300ms until power fails (Tpf).
2408 1.3.2.2 bouyer */
2409 1.3.2.8 bouyer #if 0 /* XXX called on interrupt context */
2410 1.3.2.8 bouyer DELAY_MS(300, sc);
2411 1.3.2.8 bouyer #else
2412 1.3.2.2 bouyer delay(300 * 1000);
2413 1.3.2.8 bouyer #endif
2414 1.1 haya }
2415 1.1 haya
2416 1.3.2.1 thorpej /*
2417 1.1 haya * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph)
2418 1.1 haya *
2419 1.1 haya * This function detects whether a card is in the slot or not.
2420 1.1 haya * If a card is inserted, return 1. Otherwise, return 0.
2421 1.3.2.1 thorpej */
2422 1.1 haya STATIC int
2423 1.1 haya pccbb_pcmcia_card_detect(pch)
2424 1.3.2.2 bouyer pcmcia_chipset_handle_t pch;
2425 1.1 haya {
2426 1.3.2.2 bouyer struct pcic_handle *ph = (struct pcic_handle *)pch;
2427 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
2428 1.1 haya
2429 1.3.2.2 bouyer DPRINTF(("pccbb_pcmcia_card_detect\n"));
2430 1.3.2.2 bouyer return pccbb_detect_card(sc) == 1 ? 1 : 0;
2431 1.3.2.2 bouyer }
2432 1.1 haya
2433 1.1 haya #if 0
2434 1.1 haya STATIC int
2435 1.1 haya pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch,
2436 1.3.2.2 bouyer bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags,
2437 1.3.2.2 bouyer bus_space_tag_t * memtp bus_space_handle_t * memhp)
2438 1.1 haya #endif
2439 1.3.2.1 thorpej /*
2440 1.3.2.1 thorpej * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch,
2441 1.3.2.1 thorpej * bus_size_t size,
2442 1.3.2.1 thorpej * struct pcmcia_mem_handle *pcmhp)
2443 1.3.2.1 thorpej *
2444 1.3.2.1 thorpej * This function only allocates memory region for pccard. This
2445 1.3.2.2 bouyer * function never maps the allocated region to pccard memory area.
2446 1.3.2.1 thorpej *
2447 1.3.2.1 thorpej * XXX: Why the argument of start address is not in?
2448 1.3.2.1 thorpej */
2449 1.3.2.2 bouyer STATIC int
2450 1.1 haya pccbb_pcmcia_mem_alloc(pch, size, pcmhp)
2451 1.3.2.2 bouyer pcmcia_chipset_handle_t pch;
2452 1.3.2.2 bouyer bus_size_t size;
2453 1.3.2.2 bouyer struct pcmcia_mem_handle *pcmhp;
2454 1.3.2.2 bouyer {
2455 1.3.2.2 bouyer struct pcic_handle *ph = (struct pcic_handle *)pch;
2456 1.3.2.2 bouyer bus_space_handle_t memh;
2457 1.3.2.2 bouyer bus_addr_t addr;
2458 1.3.2.2 bouyer bus_size_t sizepg;
2459 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
2460 1.1 haya #if rbus
2461 1.3.2.2 bouyer rbus_tag_t rb;
2462 1.1 haya #endif
2463 1.1 haya
2464 1.3.2.2 bouyer /* out of sc->memh, allocate as many pages as necessary */
2465 1.1 haya
2466 1.3.2.2 bouyer /* convert size to PCIC pages */
2467 1.3.2.2 bouyer /*
2468 1.3.2.2 bouyer * This is not enough; when the requested region is on the page
2469 1.3.2.2 bouyer * boundaries, this may calculate wrong result.
2470 1.3.2.2 bouyer */
2471 1.3.2.2 bouyer sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE;
2472 1.1 haya #if 0
2473 1.3.2.2 bouyer if (sizepg > PCIC_MAX_MEM_PAGES) {
2474 1.3.2.2 bouyer return 1;
2475 1.3.2.2 bouyer }
2476 1.1 haya #endif
2477 1.1 haya
2478 1.3.2.2 bouyer if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) {
2479 1.3.2.2 bouyer return 1;
2480 1.3.2.2 bouyer }
2481 1.1 haya
2482 1.3.2.2 bouyer addr = 0; /* XXX gcc -Wuninitialized */
2483 1.1 haya
2484 1.1 haya #if rbus
2485 1.3.2.2 bouyer rb = sc->sc_rbus_memt;
2486 1.3.2.2 bouyer if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE,
2487 1.3.2.2 bouyer sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0,
2488 1.3.2.2 bouyer &addr, &memh)) {
2489 1.3.2.2 bouyer return 1;
2490 1.3.2.2 bouyer }
2491 1.1 haya #else
2492 1.3.2.2 bouyer if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end,
2493 1.3.2.2 bouyer sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE,
2494 1.3.2.2 bouyer 0, /* boundary */
2495 1.3.2.2 bouyer 0, /* flags */
2496 1.3.2.2 bouyer &addr, &memh)) {
2497 1.3.2.2 bouyer return 1;
2498 1.3.2.2 bouyer }
2499 1.1 haya #endif
2500 1.1 haya
2501 1.3.2.2 bouyer DPRINTF(
2502 1.3.2.2 bouyer ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n",
2503 1.3.2.2 bouyer addr, size, sizepg * PCIC_MEM_PAGESIZE));
2504 1.3.2.2 bouyer
2505 1.3.2.2 bouyer pcmhp->memt = sc->sc_memt;
2506 1.3.2.2 bouyer pcmhp->memh = memh;
2507 1.3.2.2 bouyer pcmhp->addr = addr;
2508 1.3.2.2 bouyer pcmhp->size = size;
2509 1.3.2.2 bouyer pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE;
2510 1.3.2.2 bouyer /* What is mhandle? I feel it is very dirty and it must go trush. */
2511 1.3.2.2 bouyer pcmhp->mhandle = 0;
2512 1.3.2.2 bouyer /* No offset??? Funny. */
2513 1.1 haya
2514 1.3.2.2 bouyer return 0;
2515 1.1 haya }
2516 1.1 haya
2517 1.3.2.1 thorpej /*
2518 1.3.2.1 thorpej * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch,
2519 1.3.2.1 thorpej * struct pcmcia_mem_handle *pcmhp)
2520 1.3.2.1 thorpej *
2521 1.3.2.2 bouyer * This function release the memory space allocated by the function
2522 1.3.2.1 thorpej * pccbb_pcmcia_mem_alloc().
2523 1.3.2.1 thorpej */
2524 1.3.2.2 bouyer STATIC void
2525 1.1 haya pccbb_pcmcia_mem_free(pch, pcmhp)
2526 1.3.2.2 bouyer pcmcia_chipset_handle_t pch;
2527 1.3.2.2 bouyer struct pcmcia_mem_handle *pcmhp;
2528 1.1 haya {
2529 1.1 haya #if rbus
2530 1.3.2.2 bouyer struct pcic_handle *ph = (struct pcic_handle *)pch;
2531 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
2532 1.1 haya
2533 1.3.2.2 bouyer rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL);
2534 1.1 haya #else
2535 1.3.2.2 bouyer bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize);
2536 1.1 haya #endif
2537 1.1 haya }
2538 1.1 haya
2539 1.3.2.1 thorpej /*
2540 1.3.2.1 thorpej * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win)
2541 1.3.2.1 thorpej *
2542 1.3.2.2 bouyer * This function release the memory space allocated by the function
2543 1.3.2.1 thorpej * pccbb_pcmcia_mem_alloc().
2544 1.3.2.1 thorpej */
2545 1.3.2.2 bouyer STATIC void
2546 1.1 haya pccbb_pcmcia_do_mem_map(ph, win)
2547 1.3.2.2 bouyer struct pcic_handle *ph;
2548 1.3.2.2 bouyer int win;
2549 1.1 haya {
2550 1.3.2.2 bouyer int regbase_win;
2551 1.3.2.2 bouyer bus_addr_t phys_addr;
2552 1.3.2.2 bouyer bus_addr_t phys_end;
2553 1.1 haya
2554 1.1 haya #define PCIC_SMM_START_LOW 0
2555 1.1 haya #define PCIC_SMM_START_HIGH 1
2556 1.1 haya #define PCIC_SMM_STOP_LOW 2
2557 1.1 haya #define PCIC_SMM_STOP_HIGH 3
2558 1.1 haya #define PCIC_CMA_LOW 4
2559 1.1 haya #define PCIC_CMA_HIGH 5
2560 1.1 haya
2561 1.3.2.2 bouyer u_int8_t start_low, start_high = 0;
2562 1.3.2.2 bouyer u_int8_t stop_low, stop_high;
2563 1.3.2.2 bouyer u_int8_t off_low, off_high;
2564 1.3.2.2 bouyer u_int8_t mem_window;
2565 1.3.2.2 bouyer int reg;
2566 1.3.2.2 bouyer
2567 1.3.2.2 bouyer int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK;
2568 1.3.2.2 bouyer int mem8 =
2569 1.3.2.2 bouyer (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8
2570 1.3.2.2 bouyer || (kind == PCMCIA_MEM_ATTR);
2571 1.1 haya
2572 1.3.2.2 bouyer regbase_win = 0x10 + win * 0x08;
2573 1.1 haya
2574 1.3.2.2 bouyer phys_addr = ph->mem[win].addr;
2575 1.3.2.2 bouyer phys_end = phys_addr + ph->mem[win].size;
2576 1.1 haya
2577 1.3.2.2 bouyer DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n",
2578 1.3.2.2 bouyer phys_addr, phys_end, ph->mem[win].offset));
2579 1.1 haya
2580 1.1 haya #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT
2581 1.1 haya #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8)
2582 1.1 haya #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12)
2583 1.1 haya
2584 1.3.2.2 bouyer /* bit 19:12 */
2585 1.3.2.2 bouyer start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff;
2586 1.3.2.2 bouyer /* bit 23:20 and bit 7 on */
2587 1.3.2.2 bouyer start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f)
2588 1.3.2.2 bouyer |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT);
2589 1.3.2.2 bouyer /* bit 31:24, for 32-bit address */
2590 1.3.2.2 bouyer mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff;
2591 1.3.2.2 bouyer
2592 1.3.2.2 bouyer Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low);
2593 1.3.2.2 bouyer Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high);
2594 1.3.2.2 bouyer
2595 1.3.2.2 bouyer if (((struct pccbb_softc *)ph->
2596 1.3.2.2 bouyer ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) {
2597 1.3.2.2 bouyer Pcic_write(ph, 0x40 + win, mem_window);
2598 1.3.2.2 bouyer }
2599 1.1 haya
2600 1.3.2.2 bouyer stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff;
2601 1.3.2.2 bouyer stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f)
2602 1.3.2.2 bouyer | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */
2603 1.3.2.2 bouyer /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */
2604 1.3.2.2 bouyer
2605 1.3.2.2 bouyer Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low);
2606 1.3.2.2 bouyer Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high);
2607 1.3.2.2 bouyer
2608 1.3.2.2 bouyer off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff;
2609 1.3.2.2 bouyer off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8))
2610 1.3.2.2 bouyer & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK)
2611 1.3.2.2 bouyer | ((kind == PCMCIA_MEM_ATTR) ?
2612 1.3.2.2 bouyer PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0);
2613 1.3.2.2 bouyer
2614 1.3.2.2 bouyer Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low);
2615 1.3.2.2 bouyer Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high);
2616 1.3.2.2 bouyer
2617 1.3.2.2 bouyer reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
2618 1.3.2.2 bouyer reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16);
2619 1.3.2.2 bouyer Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg);
2620 1.1 haya
2621 1.1 haya #if defined CBB_DEBUG
2622 1.3.2.2 bouyer {
2623 1.3.2.2 bouyer int r1, r2, r3, r4, r5, r6, r7 = 0;
2624 1.1 haya
2625 1.3.2.2 bouyer r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW);
2626 1.3.2.2 bouyer r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH);
2627 1.3.2.2 bouyer r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW);
2628 1.3.2.2 bouyer r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH);
2629 1.3.2.2 bouyer r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW);
2630 1.3.2.2 bouyer r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH);
2631 1.3.2.2 bouyer if (((struct pccbb_softc *)(ph->
2632 1.3.2.2 bouyer ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) {
2633 1.3.2.2 bouyer r7 = Pcic_read(ph, 0x40 + win);
2634 1.3.2.2 bouyer }
2635 1.3.2.2 bouyer
2636 1.3.2.2 bouyer DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x "
2637 1.3.2.2 bouyer "%02x%02x", win, r1, r2, r3, r4, r5, r6));
2638 1.3.2.2 bouyer if (((struct pccbb_softc *)(ph->
2639 1.3.2.2 bouyer ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) {
2640 1.3.2.2 bouyer DPRINTF((" %02x", r7));
2641 1.3.2.2 bouyer }
2642 1.3.2.2 bouyer DPRINTF(("\n"));
2643 1.3.2.2 bouyer }
2644 1.1 haya #endif
2645 1.1 haya }
2646 1.1 haya
2647 1.3.2.1 thorpej /*
2648 1.3.2.1 thorpej * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind,
2649 1.3.2.1 thorpej * bus_addr_t card_addr, bus_size_t size,
2650 1.3.2.1 thorpej * struct pcmcia_mem_handle *pcmhp,
2651 1.3.2.1 thorpej * bus_addr_t *offsetp, int *windowp)
2652 1.3.2.1 thorpej *
2653 1.3.2.2 bouyer * This function maps memory space allocated by the function
2654 1.3.2.1 thorpej * pccbb_pcmcia_mem_alloc().
2655 1.3.2.1 thorpej */
2656 1.3.2.2 bouyer STATIC int
2657 1.1 haya pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp)
2658 1.3.2.2 bouyer pcmcia_chipset_handle_t pch;
2659 1.3.2.2 bouyer int kind;
2660 1.3.2.2 bouyer bus_addr_t card_addr;
2661 1.3.2.2 bouyer bus_size_t size;
2662 1.3.2.2 bouyer struct pcmcia_mem_handle *pcmhp;
2663 1.3.2.2 bouyer bus_addr_t *offsetp;
2664 1.3.2.2 bouyer int *windowp;
2665 1.3.2.2 bouyer {
2666 1.3.2.2 bouyer struct pcic_handle *ph = (struct pcic_handle *)pch;
2667 1.3.2.2 bouyer bus_addr_t busaddr;
2668 1.3.2.2 bouyer long card_offset;
2669 1.3.2.2 bouyer int win;
2670 1.3.2.2 bouyer
2671 1.3.2.2 bouyer for (win = 0; win < PCIC_MEM_WINS; ++win) {
2672 1.3.2.2 bouyer if ((ph->memalloc & (1 << win)) == 0) {
2673 1.3.2.2 bouyer ph->memalloc |= (1 << win);
2674 1.3.2.2 bouyer break;
2675 1.3.2.2 bouyer }
2676 1.3.2.2 bouyer }
2677 1.1 haya
2678 1.3.2.2 bouyer if (win == PCIC_MEM_WINS) {
2679 1.3.2.2 bouyer return 1;
2680 1.3.2.2 bouyer }
2681 1.1 haya
2682 1.3.2.2 bouyer *windowp = win;
2683 1.1 haya
2684 1.3.2.2 bouyer /* XXX this is pretty gross */
2685 1.1 haya
2686 1.3.2.2 bouyer if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) {
2687 1.3.2.2 bouyer panic("pccbb_pcmcia_mem_map memt is bogus");
2688 1.3.2.2 bouyer }
2689 1.1 haya
2690 1.3.2.2 bouyer busaddr = pcmhp->addr;
2691 1.1 haya
2692 1.3.2.2 bouyer /*
2693 1.3.2.2 bouyer * compute the address offset to the pcmcia address space for the
2694 1.3.2.2 bouyer * pcic. this is intentionally signed. The masks and shifts below
2695 1.3.2.2 bouyer * will cause TRT to happen in the pcic registers. Deal with making
2696 1.3.2.2 bouyer * sure the address is aligned, and return the alignment offset.
2697 1.3.2.2 bouyer */
2698 1.3.2.2 bouyer
2699 1.3.2.2 bouyer *offsetp = card_addr % PCIC_MEM_PAGESIZE;
2700 1.3.2.2 bouyer card_addr -= *offsetp;
2701 1.3.2.2 bouyer
2702 1.3.2.2 bouyer DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr "
2703 1.3.2.2 bouyer "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size,
2704 1.3.2.2 bouyer (u_long) card_addr));
2705 1.3.2.2 bouyer
2706 1.3.2.2 bouyer /*
2707 1.3.2.2 bouyer * include the offset in the size, and decrement size by one, since
2708 1.3.2.2 bouyer * the hw wants start/stop
2709 1.3.2.2 bouyer */
2710 1.3.2.2 bouyer size += *offsetp - 1;
2711 1.3.2.2 bouyer
2712 1.3.2.2 bouyer card_offset = (((long)card_addr) - ((long)busaddr));
2713 1.3.2.2 bouyer
2714 1.3.2.2 bouyer ph->mem[win].addr = busaddr;
2715 1.3.2.2 bouyer ph->mem[win].size = size;
2716 1.3.2.2 bouyer ph->mem[win].offset = card_offset;
2717 1.3.2.2 bouyer ph->mem[win].kind = kind;
2718 1.1 haya
2719 1.3.2.2 bouyer pccbb_pcmcia_do_mem_map(ph, win);
2720 1.1 haya
2721 1.3.2.2 bouyer return 0;
2722 1.1 haya }
2723 1.1 haya
2724 1.3.2.1 thorpej /*
2725 1.3.2.1 thorpej * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch,
2726 1.3.2.1 thorpej * int window)
2727 1.3.2.1 thorpej *
2728 1.3.2.2 bouyer * This function unmaps memory space which mapped by the function
2729 1.3.2.1 thorpej * pccbb_pcmcia_mem_map().
2730 1.3.2.1 thorpej */
2731 1.3.2.2 bouyer STATIC void
2732 1.1 haya pccbb_pcmcia_mem_unmap(pch, window)
2733 1.3.2.2 bouyer pcmcia_chipset_handle_t pch;
2734 1.3.2.2 bouyer int window;
2735 1.1 haya {
2736 1.3.2.2 bouyer struct pcic_handle *ph = (struct pcic_handle *)pch;
2737 1.3.2.2 bouyer int reg;
2738 1.1 haya
2739 1.3.2.2 bouyer if (window >= PCIC_MEM_WINS) {
2740 1.3.2.2 bouyer panic("pccbb_pcmcia_mem_unmap: window out of range");
2741 1.3.2.2 bouyer }
2742 1.1 haya
2743 1.3.2.2 bouyer reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
2744 1.3.2.2 bouyer reg &= ~(1 << window);
2745 1.3.2.2 bouyer Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg);
2746 1.1 haya
2747 1.3.2.2 bouyer ph->memalloc &= ~(1 << window);
2748 1.1 haya }
2749 1.1 haya
2750 1.1 haya #if defined PCCBB_PCMCIA_POLL
2751 1.1 haya struct pccbb_poll_str {
2752 1.3.2.2 bouyer void *arg;
2753 1.3.2.2 bouyer int (*func) __P((void *));
2754 1.3.2.2 bouyer int level;
2755 1.3.2.2 bouyer struct pcic_handle *ph;
2756 1.3.2.2 bouyer int count;
2757 1.3.2.2 bouyer int num;
2758 1.3.2.2 bouyer struct callout poll_ch;
2759 1.1 haya };
2760 1.1 haya
2761 1.1 haya static struct pccbb_poll_str pccbb_poll[10];
2762 1.1 haya static int pccbb_poll_n = 0;
2763 1.1 haya
2764 1.1 haya static void pccbb_pcmcia_poll __P((void *arg));
2765 1.1 haya
2766 1.1 haya static void
2767 1.1 haya pccbb_pcmcia_poll(arg)
2768 1.3.2.2 bouyer void *arg;
2769 1.1 haya {
2770 1.3.2.2 bouyer struct pccbb_poll_str *poll = arg;
2771 1.3.2.2 bouyer struct pcic_handle *ph = poll->ph;
2772 1.3.2.2 bouyer struct pccbb_softc *sc = ph->sc;
2773 1.3.2.2 bouyer int s;
2774 1.3.2.2 bouyer u_int32_t spsr; /* socket present-state reg */
2775 1.3.2.2 bouyer
2776 1.3.2.2 bouyer callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg);
2777 1.3.2.2 bouyer switch (poll->level) {
2778 1.3.2.2 bouyer case IPL_NET:
2779 1.3.2.2 bouyer s = splnet();
2780 1.3.2.2 bouyer break;
2781 1.3.2.2 bouyer case IPL_BIO:
2782 1.3.2.2 bouyer s = splbio();
2783 1.3.2.2 bouyer break;
2784 1.3.2.2 bouyer case IPL_TTY: /* fallthrough */
2785 1.3.2.2 bouyer default:
2786 1.3.2.2 bouyer s = spltty();
2787 1.3.2.2 bouyer break;
2788 1.3.2.2 bouyer }
2789 1.3.2.2 bouyer
2790 1.3.2.2 bouyer spsr =
2791 1.3.2.2 bouyer bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
2792 1.3.2.2 bouyer CB_SOCKET_STAT);
2793 1.1 haya
2794 1.1 haya #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2
2795 1.3.2.2 bouyer if (!(spsr & 0x40)) /* CINT low */
2796 1.1 haya #else
2797 1.3.2.2 bouyer if (1)
2798 1.1 haya #endif
2799 1.3.2.2 bouyer {
2800 1.3.2.2 bouyer if ((*poll->func) (poll->arg) > 0) {
2801 1.3.2.2 bouyer ++poll->count;
2802 1.3.2.2 bouyer // printf("intr: reported from poller, 0x%x\n", spsr);
2803 1.1 haya #if defined LEVEL2
2804 1.3.2.2 bouyer } else {
2805 1.3.2.2 bouyer printf("intr: miss! 0x%x\n", spsr);
2806 1.1 haya #endif
2807 1.3.2.2 bouyer }
2808 1.3.2.2 bouyer }
2809 1.3.2.2 bouyer splx(s);
2810 1.1 haya }
2811 1.1 haya #endif /* defined CB_PCMCIA_POLL */
2812 1.1 haya
2813 1.3.2.1 thorpej /*
2814 1.3.2.1 thorpej * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch,
2815 1.3.2.1 thorpej * struct pcmcia_function *pf,
2816 1.3.2.1 thorpej * int ipl,
2817 1.3.2.1 thorpej * int (*func)(void *),
2818 1.3.2.1 thorpej * void *arg);
2819 1.3.2.1 thorpej *
2820 1.3.2.1 thorpej * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line.
2821 1.3.2.1 thorpej */
2822 1.1 haya STATIC void *
2823 1.1 haya pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg)
2824 1.3.2.2 bouyer pcmcia_chipset_handle_t pch;
2825 1.3.2.2 bouyer struct pcmcia_function *pf;
2826 1.3.2.2 bouyer int ipl;
2827 1.3.2.2 bouyer int (*func) __P((void *));
2828 1.3.2.2 bouyer void *arg;
2829 1.3.2.2 bouyer {
2830 1.3.2.2 bouyer struct pcic_handle *ph = (struct pcic_handle *)pch;
2831 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
2832 1.3.2.2 bouyer
2833 1.3.2.2 bouyer if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) {
2834 1.3.2.2 bouyer /* what should I do? */
2835 1.3.2.2 bouyer if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) {
2836 1.3.2.2 bouyer DPRINTF(
2837 1.3.2.2 bouyer ("%s does not provide edge nor pulse interrupt\n",
2838 1.3.2.2 bouyer sc->sc_dev.dv_xname));
2839 1.3.2.2 bouyer return NULL;
2840 1.3.2.2 bouyer }
2841 1.3.2.2 bouyer /*
2842 1.3.2.2 bouyer * XXX Noooooo! The interrupt flag must set properly!!
2843 1.3.2.2 bouyer * dumb pcmcia driver!!
2844 1.3.2.2 bouyer */
2845 1.3.2.2 bouyer }
2846 1.1 haya
2847 1.3.2.2 bouyer return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg);
2848 1.1 haya }
2849 1.1 haya
2850 1.3.2.1 thorpej /*
2851 1.3.2.1 thorpej * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch,
2852 1.3.2.1 thorpej * void *ih)
2853 1.3.2.1 thorpej *
2854 1.3.2.1 thorpej * This function disables PC-Card interrupt.
2855 1.3.2.1 thorpej */
2856 1.1 haya STATIC void
2857 1.1 haya pccbb_pcmcia_intr_disestablish(pch, ih)
2858 1.3.2.2 bouyer pcmcia_chipset_handle_t pch;
2859 1.3.2.2 bouyer void *ih;
2860 1.1 haya {
2861 1.3.2.2 bouyer struct pcic_handle *ph = (struct pcic_handle *)pch;
2862 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
2863 1.1 haya
2864 1.3.2.2 bouyer pccbb_intr_disestablish(sc, ih);
2865 1.1 haya }
2866 1.1 haya
2867 1.1 haya #if rbus
2868 1.3.2.1 thorpej /*
2869 1.3.2.1 thorpej * static int
2870 1.3.2.1 thorpej * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb,
2871 1.3.2.1 thorpej * bus_addr_t addr, bus_size_t size,
2872 1.3.2.1 thorpej * bus_addr_t mask, bus_size_t align,
2873 1.3.2.1 thorpej * int flags, bus_addr_t *addrp;
2874 1.3.2.1 thorpej * bus_space_handle_t *bshp)
2875 1.3.2.1 thorpej *
2876 1.3.2.1 thorpej * This function allocates a portion of memory or io space for
2877 1.3.2.1 thorpej * clients. This function is called from CardBus card drivers.
2878 1.3.2.1 thorpej */
2879 1.1 haya static int
2880 1.1 haya pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp)
2881 1.3.2.2 bouyer cardbus_chipset_tag_t ct;
2882 1.3.2.2 bouyer rbus_tag_t rb;
2883 1.3.2.2 bouyer bus_addr_t addr;
2884 1.3.2.2 bouyer bus_size_t size;
2885 1.3.2.2 bouyer bus_addr_t mask;
2886 1.3.2.2 bouyer bus_size_t align;
2887 1.3.2.2 bouyer int flags;
2888 1.3.2.2 bouyer bus_addr_t *addrp;
2889 1.3.2.2 bouyer bus_space_handle_t *bshp;
2890 1.3.2.2 bouyer {
2891 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ct;
2892 1.3.2.2 bouyer
2893 1.3.2.2 bouyer DPRINTF(
2894 1.3.2.2 bouyer ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n",
2895 1.3.2.2 bouyer addr, size, mask, align));
2896 1.1 haya
2897 1.3.2.2 bouyer if (align == 0) {
2898 1.3.2.2 bouyer align = size;
2899 1.3.2.2 bouyer }
2900 1.1 haya
2901 1.3.2.2 bouyer if (rb->rb_bt == sc->sc_memt) {
2902 1.3.2.2 bouyer if (align < 16) {
2903 1.3.2.2 bouyer return 1;
2904 1.3.2.2 bouyer }
2905 1.3.2.2 bouyer } else if (rb->rb_bt == sc->sc_iot) {
2906 1.3.2.2 bouyer if (align < 4) {
2907 1.3.2.2 bouyer return 1;
2908 1.3.2.2 bouyer }
2909 1.3.2.2 bouyer /* XXX: hack for avoiding ISA image */
2910 1.3.2.2 bouyer if (mask < 0x0100) {
2911 1.3.2.2 bouyer mask = 0x3ff;
2912 1.3.2.2 bouyer addr = 0x300;
2913 1.3.2.2 bouyer }
2914 1.3.2.2 bouyer
2915 1.3.2.2 bouyer } else {
2916 1.3.2.2 bouyer DPRINTF(
2917 1.3.2.2 bouyer ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n",
2918 1.3.2.2 bouyer rb->rb_bt));
2919 1.3.2.2 bouyer return 1;
2920 1.3.2.2 bouyer /* XXX: panic here? */
2921 1.3.2.2 bouyer }
2922 1.1 haya
2923 1.3.2.2 bouyer if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) {
2924 1.3.2.2 bouyer printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname);
2925 1.3.2.2 bouyer return 1;
2926 1.3.2.2 bouyer }
2927 1.1 haya
2928 1.3.2.2 bouyer pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0);
2929 1.1 haya
2930 1.3.2.2 bouyer return 0;
2931 1.1 haya }
2932 1.1 haya
2933 1.3.2.1 thorpej /*
2934 1.3.2.1 thorpej * static int
2935 1.3.2.1 thorpej * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb,
2936 1.3.2.1 thorpej * bus_space_handle_t *bshp, bus_size_t size);
2937 1.3.2.1 thorpej *
2938 1.3.2.1 thorpej * This function is called from CardBus card drivers.
2939 1.3.2.1 thorpej */
2940 1.1 haya static int
2941 1.1 haya pccbb_rbus_cb_space_free(ct, rb, bsh, size)
2942 1.3.2.2 bouyer cardbus_chipset_tag_t ct;
2943 1.3.2.2 bouyer rbus_tag_t rb;
2944 1.3.2.2 bouyer bus_space_handle_t bsh;
2945 1.3.2.2 bouyer bus_size_t size;
2946 1.3.2.2 bouyer {
2947 1.3.2.2 bouyer struct pccbb_softc *sc = (struct pccbb_softc *)ct;
2948 1.3.2.2 bouyer bus_space_tag_t bt = rb->rb_bt;
2949 1.3.2.2 bouyer
2950 1.3.2.2 bouyer pccbb_close_win(sc, bt, bsh, size);
2951 1.3.2.2 bouyer
2952 1.3.2.2 bouyer if (bt == sc->sc_memt) {
2953 1.3.2.2 bouyer } else if (bt == sc->sc_iot) {
2954 1.3.2.2 bouyer } else {
2955 1.3.2.2 bouyer return 1;
2956 1.3.2.2 bouyer /* XXX: panic here? */
2957 1.3.2.2 bouyer }
2958 1.1 haya
2959 1.3.2.2 bouyer return rbus_space_free(rb, bsh, size, NULL);
2960 1.1 haya }
2961 1.1 haya #endif /* rbus */
2962 1.1 haya
2963 1.1 haya #if rbus
2964 1.1 haya
2965 1.1 haya static int
2966 1.1 haya pccbb_open_win(sc, bst, addr, size, bsh, flags)
2967 1.3.2.2 bouyer struct pccbb_softc *sc;
2968 1.3.2.2 bouyer bus_space_tag_t bst;
2969 1.3.2.2 bouyer bus_addr_t addr;
2970 1.3.2.2 bouyer bus_size_t size;
2971 1.3.2.2 bouyer bus_space_handle_t bsh;
2972 1.3.2.2 bouyer int flags;
2973 1.3.2.2 bouyer {
2974 1.3.2.2 bouyer struct pccbb_win_chain_head *head;
2975 1.3.2.2 bouyer bus_addr_t align;
2976 1.3.2.2 bouyer
2977 1.3.2.2 bouyer head = &sc->sc_iowindow;
2978 1.3.2.2 bouyer align = 0x04;
2979 1.3.2.2 bouyer if (sc->sc_memt == bst) {
2980 1.3.2.2 bouyer head = &sc->sc_memwindow;
2981 1.3.2.2 bouyer align = 0x1000;
2982 1.3.2.2 bouyer DPRINTF(("using memory window, %x %x %x\n\n",
2983 1.3.2.2 bouyer sc->sc_iot, sc->sc_memt, bst));
2984 1.3.2.2 bouyer }
2985 1.1 haya
2986 1.3.2.2 bouyer if (pccbb_winlist_insert(head, addr, size, bsh, flags)) {
2987 1.3.2.2 bouyer printf("%s: pccbb_open_win: %s winlist insert failed\n",
2988 1.3.2.2 bouyer sc->sc_dev.dv_xname,
2989 1.3.2.2 bouyer (head == &sc->sc_memwindow) ? "mem" : "io");
2990 1.3.2.2 bouyer }
2991 1.3.2.2 bouyer pccbb_winset(align, sc, bst);
2992 1.1 haya
2993 1.3.2.2 bouyer return 0;
2994 1.1 haya }
2995 1.1 haya
2996 1.1 haya static int
2997 1.1 haya pccbb_close_win(sc, bst, bsh, size)
2998 1.3.2.2 bouyer struct pccbb_softc *sc;
2999 1.3.2.2 bouyer bus_space_tag_t bst;
3000 1.3.2.2 bouyer bus_space_handle_t bsh;
3001 1.3.2.2 bouyer bus_size_t size;
3002 1.3.2.2 bouyer {
3003 1.3.2.2 bouyer struct pccbb_win_chain_head *head;
3004 1.3.2.2 bouyer bus_addr_t align;
3005 1.3.2.2 bouyer
3006 1.3.2.2 bouyer head = &sc->sc_iowindow;
3007 1.3.2.2 bouyer align = 0x04;
3008 1.3.2.2 bouyer if (sc->sc_memt == bst) {
3009 1.3.2.2 bouyer head = &sc->sc_memwindow;
3010 1.3.2.2 bouyer align = 0x1000;
3011 1.3.2.2 bouyer }
3012 1.1 haya
3013 1.3.2.2 bouyer if (pccbb_winlist_delete(head, bsh, size)) {
3014 1.3.2.2 bouyer printf("%s: pccbb_close_win: %s winlist delete failed\n",
3015 1.3.2.2 bouyer sc->sc_dev.dv_xname,
3016 1.3.2.2 bouyer (head == &sc->sc_memwindow) ? "mem" : "io");
3017 1.3.2.2 bouyer }
3018 1.3.2.2 bouyer pccbb_winset(align, sc, bst);
3019 1.1 haya
3020 1.3.2.2 bouyer return 0;
3021 1.1 haya }
3022 1.1 haya
3023 1.1 haya static int
3024 1.3.2.2 bouyer pccbb_winlist_insert(head, start, size, bsh, flags)
3025 1.3.2.2 bouyer struct pccbb_win_chain_head *head;
3026 1.3.2.2 bouyer bus_addr_t start;
3027 1.3.2.2 bouyer bus_size_t size;
3028 1.3.2.2 bouyer bus_space_handle_t bsh;
3029 1.3.2.2 bouyer int flags;
3030 1.3.2.2 bouyer {
3031 1.3.2.2 bouyer struct pccbb_win_chain *chainp, *elem;
3032 1.3.2.2 bouyer
3033 1.3.2.2 bouyer if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF,
3034 1.3.2.2 bouyer M_NOWAIT)) == NULL)
3035 1.3.2.2 bouyer return (1); /* fail */
3036 1.3.2.2 bouyer
3037 1.3.2.2 bouyer elem->wc_start = start;
3038 1.3.2.2 bouyer elem->wc_end = start + (size - 1);
3039 1.3.2.2 bouyer elem->wc_handle = bsh;
3040 1.3.2.2 bouyer elem->wc_flags = flags;
3041 1.3.2.2 bouyer
3042 1.3.2.2 bouyer for (chainp = TAILQ_FIRST(head); chainp != NULL;
3043 1.3.2.2 bouyer chainp = TAILQ_NEXT(chainp, wc_list)) {
3044 1.3.2.2 bouyer if (chainp->wc_end < start)
3045 1.3.2.2 bouyer continue;
3046 1.3.2.2 bouyer TAILQ_INSERT_AFTER(head, chainp, elem, wc_list);
3047 1.3.2.2 bouyer return (0);
3048 1.3.2.2 bouyer }
3049 1.1 haya
3050 1.3.2.2 bouyer TAILQ_INSERT_TAIL(head, elem, wc_list);
3051 1.3.2.2 bouyer return (0);
3052 1.1 haya }
3053 1.1 haya
3054 1.3.2.2 bouyer static int
3055 1.3.2.2 bouyer pccbb_winlist_delete(head, bsh, size)
3056 1.3.2.2 bouyer struct pccbb_win_chain_head *head;
3057 1.3.2.2 bouyer bus_space_handle_t bsh;
3058 1.3.2.2 bouyer bus_size_t size;
3059 1.3.2.2 bouyer {
3060 1.3.2.2 bouyer struct pccbb_win_chain *chainp;
3061 1.3.2.2 bouyer
3062 1.3.2.2 bouyer for (chainp = TAILQ_FIRST(head); chainp != NULL;
3063 1.3.2.2 bouyer chainp = TAILQ_NEXT(chainp, wc_list)) {
3064 1.3.2.2 bouyer if (chainp->wc_handle != bsh)
3065 1.3.2.2 bouyer continue;
3066 1.3.2.2 bouyer if ((chainp->wc_end - chainp->wc_start) != (size - 1)) {
3067 1.3.2.2 bouyer printf("pccbb_winlist_delete: window 0x%lx size "
3068 1.3.2.2 bouyer "inconsistent: 0x%lx, 0x%lx\n",
3069 1.3.2.2 bouyer chainp->wc_start,
3070 1.3.2.2 bouyer chainp->wc_end - chainp->wc_start,
3071 1.3.2.2 bouyer size - 1);
3072 1.3.2.2 bouyer return 1;
3073 1.3.2.2 bouyer }
3074 1.1 haya
3075 1.3.2.2 bouyer TAILQ_REMOVE(head, chainp, wc_list);
3076 1.3.2.2 bouyer free(chainp, M_DEVBUF);
3077 1.1 haya
3078 1.3.2.2 bouyer return 0;
3079 1.3.2.2 bouyer }
3080 1.1 haya
3081 1.3.2.2 bouyer return 1; /* fail: no candidate to remove */
3082 1.3.2.2 bouyer }
3083 1.1 haya
3084 1.3.2.2 bouyer static void
3085 1.3.2.2 bouyer pccbb_winset(align, sc, bst)
3086 1.3.2.2 bouyer bus_addr_t align;
3087 1.3.2.2 bouyer struct pccbb_softc *sc;
3088 1.3.2.2 bouyer bus_space_tag_t bst;
3089 1.3.2.2 bouyer {
3090 1.3.2.2 bouyer pci_chipset_tag_t pc;
3091 1.3.2.2 bouyer pcitag_t tag;
3092 1.3.2.2 bouyer bus_addr_t mask = ~(align - 1);
3093 1.3.2.2 bouyer struct {
3094 1.3.2.2 bouyer cardbusreg_t win_start;
3095 1.3.2.2 bouyer cardbusreg_t win_limit;
3096 1.3.2.2 bouyer int win_flags;
3097 1.3.2.2 bouyer } win[2];
3098 1.3.2.2 bouyer struct pccbb_win_chain *chainp;
3099 1.3.2.2 bouyer int offs;
3100 1.3.2.2 bouyer
3101 1.3.2.9 bouyer win[0].win_start = win[1].win_start = 0xffffffff;
3102 1.3.2.9 bouyer win[0].win_limit = win[1].win_limit = 0;
3103 1.3.2.9 bouyer win[0].win_flags = win[1].win_flags = 0;
3104 1.3.2.2 bouyer
3105 1.3.2.2 bouyer chainp = TAILQ_FIRST(&sc->sc_iowindow);
3106 1.3.2.2 bouyer offs = 0x2c;
3107 1.3.2.2 bouyer if (sc->sc_memt == bst) {
3108 1.3.2.2 bouyer chainp = TAILQ_FIRST(&sc->sc_memwindow);
3109 1.3.2.2 bouyer offs = 0x1c;
3110 1.3.2.2 bouyer }
3111 1.1 haya
3112 1.3.2.2 bouyer if (chainp != NULL) {
3113 1.3.2.2 bouyer win[0].win_start = chainp->wc_start & mask;
3114 1.3.2.2 bouyer win[0].win_limit = chainp->wc_end & mask;
3115 1.3.2.2 bouyer win[0].win_flags = chainp->wc_flags;
3116 1.3.2.2 bouyer chainp = TAILQ_NEXT(chainp, wc_list);
3117 1.3.2.2 bouyer }
3118 1.1 haya
3119 1.3.2.2 bouyer for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) {
3120 1.3.2.2 bouyer if (win[1].win_start == 0xffffffff) {
3121 1.3.2.2 bouyer /* window 1 is not used */
3122 1.3.2.2 bouyer if ((win[0].win_flags == chainp->wc_flags) &&
3123 1.3.2.2 bouyer (win[0].win_limit + align >=
3124 1.3.2.2 bouyer (chainp->wc_start & mask))) {
3125 1.3.2.2 bouyer /* concatenate */
3126 1.3.2.2 bouyer win[0].win_limit = chainp->wc_end & mask;
3127 1.3.2.2 bouyer } else {
3128 1.3.2.2 bouyer /* make new window */
3129 1.3.2.2 bouyer win[1].win_start = chainp->wc_start & mask;
3130 1.3.2.2 bouyer win[1].win_limit = chainp->wc_end & mask;
3131 1.3.2.2 bouyer win[1].win_flags = chainp->wc_flags;
3132 1.3.2.2 bouyer }
3133 1.3.2.2 bouyer continue;
3134 1.3.2.2 bouyer }
3135 1.3.2.2 bouyer
3136 1.3.2.2 bouyer /* Both windows are engaged. */
3137 1.3.2.2 bouyer if (win[0].win_flags == win[1].win_flags) {
3138 1.3.2.2 bouyer /* same flags */
3139 1.3.2.2 bouyer if (win[0].win_flags == chainp->wc_flags) {
3140 1.3.2.2 bouyer if (win[1].win_start - (win[0].win_limit +
3141 1.3.2.2 bouyer align) <
3142 1.3.2.2 bouyer (chainp->wc_start & mask) -
3143 1.3.2.2 bouyer ((chainp->wc_end & mask) + align)) {
3144 1.3.2.2 bouyer /*
3145 1.3.2.2 bouyer * merge window 0 and 1, and set win1
3146 1.3.2.2 bouyer * to chainp
3147 1.3.2.2 bouyer */
3148 1.3.2.2 bouyer win[0].win_limit = win[1].win_limit;
3149 1.3.2.2 bouyer win[1].win_start =
3150 1.3.2.2 bouyer chainp->wc_start & mask;
3151 1.3.2.2 bouyer win[1].win_limit =
3152 1.3.2.2 bouyer chainp->wc_end & mask;
3153 1.3.2.2 bouyer } else {
3154 1.3.2.2 bouyer win[1].win_limit =
3155 1.3.2.2 bouyer chainp->wc_end & mask;
3156 1.3.2.2 bouyer }
3157 1.3.2.2 bouyer } else {
3158 1.3.2.2 bouyer /* different flags */
3159 1.3.2.2 bouyer
3160 1.3.2.2 bouyer /* concatenate win0 and win1 */
3161 1.3.2.2 bouyer win[0].win_limit = win[1].win_limit;
3162 1.3.2.2 bouyer /* allocate win[1] to new space */
3163 1.3.2.2 bouyer win[1].win_start = chainp->wc_start & mask;
3164 1.3.2.2 bouyer win[1].win_limit = chainp->wc_end & mask;
3165 1.3.2.2 bouyer win[1].win_flags = chainp->wc_flags;
3166 1.3.2.2 bouyer }
3167 1.3.2.2 bouyer } else {
3168 1.3.2.2 bouyer /* the flags of win[0] and win[1] is different */
3169 1.3.2.2 bouyer if (win[0].win_flags == chainp->wc_flags) {
3170 1.3.2.2 bouyer win[0].win_limit = chainp->wc_end & mask;
3171 1.3.2.2 bouyer /*
3172 1.3.2.2 bouyer * XXX this creates overlapping windows, so
3173 1.3.2.2 bouyer * what should the poor bridge do if one is
3174 1.3.2.2 bouyer * cachable, and the other is not?
3175 1.3.2.2 bouyer */
3176 1.3.2.2 bouyer printf("%s: overlapping windows\n",
3177 1.3.2.2 bouyer sc->sc_dev.dv_xname);
3178 1.3.2.2 bouyer } else {
3179 1.3.2.2 bouyer win[1].win_limit = chainp->wc_end & mask;
3180 1.3.2.2 bouyer }
3181 1.3.2.2 bouyer }
3182 1.3.2.2 bouyer }
3183 1.1 haya
3184 1.3.2.2 bouyer pc = sc->sc_pc;
3185 1.3.2.2 bouyer tag = sc->sc_tag;
3186 1.3.2.2 bouyer pci_conf_write(pc, tag, offs, win[0].win_start);
3187 1.3.2.2 bouyer pci_conf_write(pc, tag, offs + 4, win[0].win_limit);
3188 1.3.2.2 bouyer pci_conf_write(pc, tag, offs + 8, win[1].win_start);
3189 1.3.2.2 bouyer pci_conf_write(pc, tag, offs + 12, win[1].win_limit);
3190 1.3.2.2 bouyer DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n",
3191 1.3.2.2 bouyer pci_conf_read(pc, tag, offs),
3192 1.3.2.2 bouyer pci_conf_read(pc, tag, offs + 4) + align,
3193 1.3.2.2 bouyer pci_conf_read(pc, tag, offs + 8),
3194 1.3.2.2 bouyer pci_conf_read(pc, tag, offs + 12) + align));
3195 1.3.2.2 bouyer
3196 1.3.2.2 bouyer if (bst == sc->sc_memt) {
3197 1.3.2.9 bouyer pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR);
3198 1.3.2.9 bouyer
3199 1.3.2.9 bouyer bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1);
3200 1.3.2.9 bouyer if (win[0].win_flags & PCCBB_MEM_CACHABLE)
3201 1.3.2.2 bouyer bcr |= CB_BCR_PREFETCH_MEMWIN0;
3202 1.3.2.9 bouyer if (win[1].win_flags & PCCBB_MEM_CACHABLE)
3203 1.3.2.2 bouyer bcr |= CB_BCR_PREFETCH_MEMWIN1;
3204 1.3.2.9 bouyer pci_conf_write(pc, tag, PCI_BCR_INTR, bcr);
3205 1.3.2.2 bouyer }
3206 1.1 haya }
3207 1.1 haya
3208 1.3.2.2 bouyer #endif /* rbus */
3209 1.1 haya
3210 1.1 haya static void
3211 1.3.2.2 bouyer pccbb_powerhook(why, arg)
3212 1.3.2.2 bouyer int why;
3213 1.3.2.2 bouyer void *arg;
3214 1.3.2.2 bouyer {
3215 1.3.2.2 bouyer struct pccbb_softc *sc = arg;
3216 1.3.2.2 bouyer u_int32_t reg;
3217 1.3.2.2 bouyer bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */
3218 1.3.2.2 bouyer bus_space_handle_t base_memh = sc->sc_base_memh;
3219 1.3.2.2 bouyer
3220 1.3.2.2 bouyer DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why));
3221 1.3.2.2 bouyer
3222 1.3.2.2 bouyer if (why == PWR_SUSPEND || why == PWR_STANDBY) {
3223 1.3.2.2 bouyer DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why));
3224 1.3.2.2 bouyer if (sc->sc_pil_intr_enable) {
3225 1.3.2.2 bouyer (void)pccbbintr_function(sc);
3226 1.3.2.2 bouyer }
3227 1.3.2.2 bouyer sc->sc_pil_intr_enable = 0;
3228 1.1 haya
3229 1.3.2.2 bouyer /* ToDo: deactivate or suspend child devices */
3230 1.3.2.2 bouyer
3231 1.3.2.2 bouyer }
3232 1.1 haya
3233 1.3.2.2 bouyer if (why == PWR_RESUME) {
3234 1.3.2.9 bouyer if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0)
3235 1.3.2.9 bouyer /* BIOS did not recover this register */
3236 1.3.2.9 bouyer pci_conf_write (sc->sc_pc, sc->sc_tag,
3237 1.3.2.9 bouyer PCI_SOCKBASE, sc->sc_sockbase);
3238 1.3.2.9 bouyer if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0)
3239 1.3.2.9 bouyer /* BIOS did not recover this register */
3240 1.3.2.9 bouyer pci_conf_write (sc->sc_pc, sc->sc_tag,
3241 1.3.2.9 bouyer PCI_BUSNUM, sc->sc_busnum);
3242 1.3.2.2 bouyer /* CSC Interrupt: Card detect interrupt on */
3243 1.3.2.2 bouyer reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK);
3244 1.3.2.2 bouyer /* Card detect intr is turned on. */
3245 1.3.2.2 bouyer reg |= CB_SOCKET_MASK_CD;
3246 1.3.2.2 bouyer bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg);
3247 1.3.2.2 bouyer /* reset interrupt */
3248 1.3.2.2 bouyer reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT);
3249 1.3.2.2 bouyer bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg);
3250 1.3.2.2 bouyer
3251 1.3.2.2 bouyer /*
3252 1.3.2.2 bouyer * check for card insertion or removal during suspend period.
3253 1.3.2.2 bouyer * XXX: the code can't cope with card swap (remove then
3254 1.3.2.2 bouyer * insert). how can we detect such situation?
3255 1.3.2.2 bouyer */
3256 1.3.2.2 bouyer (void)pccbbintr(sc);
3257 1.1 haya
3258 1.3.2.2 bouyer sc->sc_pil_intr_enable = 1;
3259 1.3.2.2 bouyer DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname));
3260 1.3.2.2 bouyer
3261 1.3.2.2 bouyer /* ToDo: activate or wakeup child devices */
3262 1.3.2.2 bouyer }
3263 1.3.2.2 bouyer }
3264