pccbb.c revision 1.102
1 /* $NetBSD: pccbb.c,v 1.102 2004/08/11 01:04:40 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.102 2004/08/11 01:04:40 mycroft Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC void pccbb_pcmcia_socket_settype __P((pcmcia_chipset_handle_t, int)); 188 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 189 190 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 191 static int pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 192 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 193 static void pccbb_powerhook __P((int, void *)); 194 195 /* bus-space allocation and deallocation functions */ 196 #if rbus 197 198 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 199 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 200 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 201 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 202 bus_space_handle_t, bus_size_t)); 203 204 #endif /* rbus */ 205 206 #if rbus 207 208 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 209 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 210 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 211 bus_space_handle_t, bus_size_t)); 212 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 213 bus_size_t, bus_space_handle_t, int)); 214 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 215 bus_space_handle_t, bus_size_t)); 216 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 217 bus_space_tag_t)); 218 void pccbb_winlist_show(struct pccbb_win_chain *); 219 220 #endif /* rbus */ 221 222 /* for config_defer */ 223 static void pccbb_pci_callback __P((struct device *)); 224 225 #if defined SHOW_REGS 226 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 227 bus_space_tag_t memt, bus_space_handle_t memh)); 228 #endif 229 230 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 231 pcicbbmatch, pccbbattach, NULL, NULL); 232 233 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 234 pccbb_pcmcia_mem_alloc, 235 pccbb_pcmcia_mem_free, 236 pccbb_pcmcia_mem_map, 237 pccbb_pcmcia_mem_unmap, 238 pccbb_pcmcia_io_alloc, 239 pccbb_pcmcia_io_free, 240 pccbb_pcmcia_io_map, 241 pccbb_pcmcia_io_unmap, 242 pccbb_pcmcia_intr_establish, 243 pccbb_pcmcia_intr_disestablish, 244 pccbb_pcmcia_socket_enable, 245 pccbb_pcmcia_socket_disable, 246 pccbb_pcmcia_socket_settype, 247 pccbb_pcmcia_card_detect 248 }; 249 250 #if rbus 251 static struct cardbus_functions pccbb_funcs = { 252 pccbb_rbus_cb_space_alloc, 253 pccbb_rbus_cb_space_free, 254 pccbb_cb_intr_establish, 255 pccbb_cb_intr_disestablish, 256 pccbb_ctrl, 257 pccbb_power, 258 pccbb_make_tag, 259 pccbb_free_tag, 260 pccbb_conf_read, 261 pccbb_conf_write, 262 }; 263 #else 264 static struct cardbus_functions pccbb_funcs = { 265 pccbb_ctrl, 266 pccbb_power, 267 pccbb_mem_open, 268 pccbb_mem_close, 269 pccbb_io_open, 270 pccbb_io_close, 271 pccbb_cb_intr_establish, 272 pccbb_cb_intr_disestablish, 273 pccbb_make_tag, 274 pccbb_conf_read, 275 pccbb_conf_write, 276 }; 277 #endif 278 279 int 280 pcicbbmatch(parent, match, aux) 281 struct device *parent; 282 struct cfdata *match; 283 void *aux; 284 { 285 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 286 287 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 288 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 289 PCI_INTERFACE(pa->pa_class) == 0) { 290 return 1; 291 } 292 293 return 0; 294 } 295 296 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 297 | ((prod) << PCI_PRODUCT_SHIFT)) 298 299 const struct yenta_chipinfo { 300 pcireg_t yc_id; /* vendor tag | product tag */ 301 int yc_chiptype; 302 int yc_flags; 303 } yc_chipsets[] = { 304 /* Texas Instruments chips */ 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 332 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 334 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 336 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 337 338 /* Ricoh chips */ 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 344 PCCBB_PCMCIA_MEM_32}, 345 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 346 PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 348 PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 350 PCCBB_PCMCIA_MEM_32}, 351 352 /* Toshiba products */ 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 354 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 355 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 356 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 358 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 360 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 361 362 /* Cirrus Logic products */ 363 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 364 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 365 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 366 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 367 368 /* sentinel, or Generic chip */ 369 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 370 }; 371 372 static int 373 cb_chipset(pci_id, flagp) 374 u_int32_t pci_id; 375 int *flagp; 376 { 377 const struct yenta_chipinfo *yc; 378 379 /* Loop over except the last default entry. */ 380 for (yc = yc_chipsets; yc < yc_chipsets + 381 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 382 if (pci_id == yc->yc_id) 383 break; 384 385 if (flagp != NULL) 386 *flagp = yc->yc_flags; 387 388 return (yc->yc_chiptype); 389 } 390 391 static void 392 pccbb_shutdown(void *arg) 393 { 394 struct pccbb_softc *sc = arg; 395 pcireg_t command; 396 397 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 398 399 /* 400 * turn off power 401 * 402 * XXX - do not turn off power if chipset is TI 113X because 403 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 404 */ 405 if (sc->sc_chipset != CB_TI113X) { 406 pccbb_power((cardbus_chipset_tag_t)sc, 407 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 408 } 409 410 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 411 0); 412 413 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 414 415 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 416 PCI_COMMAND_MASTER_ENABLE); 417 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 418 419 } 420 421 void 422 pccbbattach(parent, self, aux) 423 struct device *parent; 424 struct device *self; 425 void *aux; 426 { 427 struct pccbb_softc *sc = (void *)self; 428 struct pci_attach_args *pa = aux; 429 pci_chipset_tag_t pc = pa->pa_pc; 430 pcireg_t busreg, reg, sock_base; 431 bus_addr_t sockbase; 432 char devinfo[256]; 433 int flags; 434 int pwrmgt_offs; 435 436 #ifdef __HAVE_PCCBB_ATTACH_HOOK 437 pccbb_attach_hook(parent, self, pa); 438 #endif 439 440 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 441 442 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 443 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 444 #ifdef CBB_DEBUG 445 printf(" (chipflags %x)", flags); 446 #endif 447 printf("\n"); 448 449 TAILQ_INIT(&sc->sc_memwindow); 450 TAILQ_INIT(&sc->sc_iowindow); 451 452 #if rbus 453 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 454 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 455 456 #if 0 457 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 458 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 459 #endif 460 #endif /* rbus */ 461 462 sc->sc_flags &= ~CBB_MEMHMAPPED; 463 464 /* power management: set D0 state */ 465 sc->sc_pwrmgt_offs = 0; 466 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 467 &pwrmgt_offs, 0)) { 468 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 469 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 470 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 471 reg &= ~PCI_PMCSR_STATE_MASK; 472 reg |= PCI_PMCSR_STATE_D0; 473 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 474 pci_conf_write(pc, pa->pa_tag, 475 pwrmgt_offs + PCI_PMCSR, reg); 476 } 477 478 sc->sc_pwrmgt_offs = pwrmgt_offs; 479 } 480 481 /* 482 * MAP socket registers and ExCA registers on memory-space 483 * When no valid address is set on socket base registers (on pci 484 * config space), get it not polite way. 485 */ 486 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 487 488 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 489 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 490 /* The address must be valid. */ 491 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 492 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 493 printf("%s: can't map socket base address 0x%lx\n", 494 sc->sc_dev.dv_xname, (unsigned long)sock_base); 495 /* 496 * I think it's funny: socket base registers must be 497 * mapped on memory space, but ... 498 */ 499 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 500 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 501 NULL)) { 502 printf("%s: can't map socket base address" 503 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 504 (unsigned long)sockbase); 505 /* give up... allocate reg space via rbus. */ 506 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 507 } else 508 sc->sc_flags |= CBB_MEMHMAPPED; 509 } else { 510 DPRINTF(("%s: socket base address 0x%lx\n", 511 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 512 sc->sc_flags |= CBB_MEMHMAPPED; 513 } 514 } 515 516 sc->sc_mem_start = 0; /* XXX */ 517 sc->sc_mem_end = 0xffffffff; /* XXX */ 518 519 /* 520 * When interrupt isn't routed correctly, give up probing cbb and do 521 * not kill pcic-compatible port. 522 */ 523 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 524 printf("%s: NOT USED because of unconfigured interrupt\n", 525 sc->sc_dev.dv_xname); 526 return; 527 } 528 529 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 530 531 /* pccbb_machdep.c end */ 532 533 #if defined CBB_DEBUG 534 { 535 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 536 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 537 intrname[pa->pa_intrpin], pa->pa_intrline); 538 } 539 #endif 540 541 /* setup softc */ 542 sc->sc_pc = pc; 543 sc->sc_iot = pa->pa_iot; 544 sc->sc_memt = pa->pa_memt; 545 sc->sc_dmat = pa->pa_dmat; 546 sc->sc_tag = pa->pa_tag; 547 sc->sc_function = pa->pa_function; 548 sc->sc_sockbase = sock_base; 549 sc->sc_busnum = busreg; 550 551 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 552 553 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 554 555 shutdownhook_establish(pccbb_shutdown, sc); 556 557 /* Disable legacy register mapping. */ 558 switch (sc->sc_chipset) { 559 case CB_RX5C46X: /* fallthrough */ 560 #if 0 561 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 562 case CB_RX5C47X: 563 #endif 564 /* 565 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 566 * cannot be disabled by substituting 0 into PCI_LEGACY 567 * register. Ricoh CardBus bridges have special bits on Bridge 568 * control reg (addr 0x3e on PCI config space). 569 */ 570 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 571 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 572 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 573 break; 574 575 default: 576 /* XXX I don't know proper way to kill legacy I/O. */ 577 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 578 break; 579 } 580 581 config_defer(self, pccbb_pci_callback); 582 } 583 584 585 586 587 /* 588 * static void pccbb_pci_callback(struct device *self) 589 * 590 * The actual attach routine: get memory space for YENTA register 591 * space, setup YENTA register and route interrupt. 592 * 593 * This function should be deferred because this device may obtain 594 * memory space dynamically. This function must avoid obtaining 595 * memory area which has already kept for another device. 596 */ 597 static void 598 pccbb_pci_callback(self) 599 struct device *self; 600 { 601 struct pccbb_softc *sc = (void *)self; 602 pci_chipset_tag_t pc = sc->sc_pc; 603 pci_intr_handle_t ih; 604 const char *intrstr = NULL; 605 bus_addr_t sockbase; 606 struct cbslot_attach_args cba; 607 struct pcmciabus_attach_args paa; 608 struct cardslot_attach_args caa; 609 struct cardslot_softc *csc; 610 611 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 612 /* The socket registers aren't mapped correctly. */ 613 #if rbus 614 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 615 (sc->sc_chipset == CB_RX5C47X 616 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 617 0, &sockbase, &sc->sc_base_memh)) { 618 return; 619 } 620 sc->sc_base_memt = sc->sc_memt; 621 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 622 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 623 sc->sc_dev.dv_xname, (unsigned long)sockbase, 624 (unsigned long)pci_conf_read(pc, sc->sc_tag, 625 PCI_SOCKBASE))); 626 #else 627 sc->sc_base_memt = sc->sc_memt; 628 #if !defined CBB_PCI_BASE 629 #define CBB_PCI_BASE 0x20000000 630 #endif 631 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 632 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 633 /* cannot allocate memory space */ 634 return; 635 } 636 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 637 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 638 sc->sc_dev.dv_xname, (unsigned long)sock_base, 639 (unsigned long)pci_conf_read(pc, 640 sc->sc_tag, PCI_SOCKBASE))); 641 sc->sc_sockbase = sockbase; 642 #endif 643 sc->sc_flags |= CBB_MEMHMAPPED; 644 } 645 646 /* bus bridge initialization */ 647 pccbb_chipinit(sc); 648 649 /* clear data structure for child device interrupt handlers */ 650 LIST_INIT(&sc->sc_pil); 651 sc->sc_pil_intr_enable = 1; 652 653 /* Map and establish the interrupt. */ 654 if (pci_intr_map(&sc->sc_pa, &ih)) { 655 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 656 return; 657 } 658 intrstr = pci_intr_string(pc, ih); 659 660 /* 661 * XXX pccbbintr should be called under the priority lower 662 * than any other hard interrputs. 663 */ 664 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 665 666 if (sc->sc_ih == NULL) { 667 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 668 if (intrstr != NULL) { 669 printf(" at %s", intrstr); 670 } 671 printf("\n"); 672 return; 673 } 674 675 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 676 powerhook_establish(pccbb_powerhook, sc); 677 678 { 679 u_int32_t sockstat; 680 681 sockstat = bus_space_read_4(sc->sc_base_memt, 682 sc->sc_base_memh, CB_SOCKET_STAT); 683 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 684 sc->sc_flags |= CBB_CARDEXIST; 685 } 686 } 687 688 /* 689 * attach cardbus 690 */ 691 { 692 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 693 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 694 695 /* initialize cbslot_attach */ 696 cba.cba_busname = "cardbus"; 697 cba.cba_iot = sc->sc_iot; 698 cba.cba_memt = sc->sc_memt; 699 cba.cba_dmat = sc->sc_dmat; 700 cba.cba_bus = (busreg >> 8) & 0x0ff; 701 cba.cba_cc = (void *)sc; 702 cba.cba_cf = &pccbb_funcs; 703 cba.cba_intrline = sc->sc_pa.pa_intrline; 704 705 #if rbus 706 cba.cba_rbus_iot = sc->sc_rbus_iot; 707 cba.cba_rbus_memt = sc->sc_rbus_memt; 708 #endif 709 710 cba.cba_cacheline = PCI_CACHELINE(bhlc); 711 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 712 713 if (bootverbose) { 714 printf("%s: cacheline 0x%x lattimer 0x%x\n", 715 sc->sc_dev.dv_xname, cba.cba_cacheline, 716 cba.cba_lattimer); 717 printf("%s: bhlc 0x%x lscp 0x%x\n", 718 sc->sc_dev.dv_xname, bhlc, busreg); 719 } 720 #if defined SHOW_REGS 721 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 722 sc->sc_base_memh); 723 #endif 724 } 725 726 pccbb_pcmcia_attach_setup(sc, &paa); 727 caa.caa_cb_attach = NULL; 728 if (cba.cba_bus == 0) 729 printf("%s: secondary bus number uninitialized; try PCIBIOS_BUS_FIXUP\n", sc->sc_dev.dv_xname); 730 else 731 caa.caa_cb_attach = &cba; 732 caa.caa_16_attach = &paa; 733 caa.caa_ph = &sc->sc_pcmcia_h; 734 735 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 736 DPRINTF(("pccbbattach: found cardslot\n")); 737 sc->sc_csc = csc; 738 } 739 740 return; 741 } 742 743 744 745 746 747 /* 748 * static void pccbb_chipinit(struct pccbb_softc *sc) 749 * 750 * This function initialize YENTA chip registers listed below: 751 * 1) PCI command reg, 752 * 2) PCI and CardBus latency timer, 753 * 3) route PCI interrupt, 754 * 4) close all memory and io windows. 755 * 5) turn off bus power. 756 * 6) card detect interrupt on. 757 * 7) clear interrupt 758 */ 759 static void 760 pccbb_chipinit(sc) 761 struct pccbb_softc *sc; 762 { 763 pci_chipset_tag_t pc = sc->sc_pc; 764 pcitag_t tag = sc->sc_tag; 765 bus_space_tag_t bmt = sc->sc_base_memt; 766 bus_space_handle_t bmh = sc->sc_base_memh; 767 pcireg_t reg; 768 769 /* 770 * Set PCI command reg. 771 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 772 */ 773 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 774 /* I believe it is harmless. */ 775 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 776 PCI_COMMAND_MASTER_ENABLE); 777 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 778 779 /* 780 * Set CardBus latency timer. 781 */ 782 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 783 if (PCI_CB_LATENCY(reg) < 0x20) { 784 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 785 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 786 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 787 } 788 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 789 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 790 791 /* 792 * Set PCI latency timer. 793 */ 794 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 795 if (PCI_LATTIMER(reg) < 0x10) { 796 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 797 reg |= (0x10 << PCI_LATTIMER_SHIFT); 798 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 799 } 800 DPRINTF(("PCI latency timer 0x%x (%x)\n", 801 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 802 803 804 /* Route functional interrupts to PCI. */ 805 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 806 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 807 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 808 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 809 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 810 811 switch (sc->sc_chipset) { 812 case CB_TI113X: 813 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 814 /* This bit is shared, but may read as 0 on some chips, so set 815 it explicitly on both functions. */ 816 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 817 /* CSC intr enable */ 818 reg |= PCI113X_CBCTRL_PCI_CSC; 819 /* functional intr prohibit | prohibit ISA routing */ 820 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 821 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 822 break; 823 824 case CB_TI12XX: 825 /* 826 * Some TI 12xx (and [14][45]xx) based pci cards 827 * sometimes have issues with the MFUNC register not 828 * being initialized due to a bad EEPROM on board. 829 * Laptops that this matters on have this register 830 * properly initialized. 831 * 832 * The TI125X parts have a different register. 833 */ 834 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 835 if (reg == 0) { 836 reg &= ~PCI12XX_MFUNC_PIN0; 837 reg |= PCI12XX_MFUNC_PIN0_INTA; 838 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 839 PCI12XX_SYSCTRL_INTRTIE) == 0) { 840 reg &= ~PCI12XX_MFUNC_PIN1; 841 reg |= PCI12XX_MFUNC_PIN1_INTB; 842 } 843 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 844 } 845 /* fallthrough */ 846 847 case CB_TI125X: 848 /* 849 * Disable zoom video. Some machines initialize this 850 * improperly and experience has shown that this helps 851 * prevent strange behavior. 852 */ 853 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 854 855 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 856 reg |= PCI12XX_SYSCTRL_VCCPROT; 857 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 858 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 859 reg |= PCI12XX_CBCTRL_CSC; 860 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 861 break; 862 863 case CB_TOPIC95B: 864 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 865 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 866 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 867 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 868 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 869 sc->sc_dev.dv_xname, reg)); 870 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 871 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 872 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 873 DPRINTF(("0x%x\n", reg)); 874 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 875 break; 876 877 case CB_TOPIC97: 878 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 879 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 880 sc->sc_dev.dv_xname, reg)); 881 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 882 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 883 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 884 reg |= TOPIC97_SLOT_CTRL_PCIINT; 885 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 886 DPRINTF(("0x%x\n", reg)); 887 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 888 /* make sure to assert LV card support bits */ 889 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 890 0x800 + 0x3e, 891 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 892 0x800 + 0x3e) | 0x03); 893 break; 894 } 895 896 /* Close all memory and I/O windows. */ 897 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 898 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 899 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 900 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 901 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 902 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 903 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 904 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 905 906 /* reset 16-bit pcmcia bus */ 907 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 908 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 909 910 /* turn off power */ 911 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 912 913 /* CSC Interrupt: Card detect interrupt on */ 914 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 915 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 916 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 917 /* reset interrupt */ 918 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 919 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 920 } 921 922 923 924 925 /* 926 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 927 * struct pcmciabus_attach_args *paa) 928 * 929 * This function attaches 16-bit PCcard bus. 930 */ 931 STATIC void 932 pccbb_pcmcia_attach_setup(sc, paa) 933 struct pccbb_softc *sc; 934 struct pcmciabus_attach_args *paa; 935 { 936 struct pcic_handle *ph = &sc->sc_pcmcia_h; 937 #if rbus 938 rbus_tag_t rb; 939 #endif 940 941 /* initialize pcmcia part in pccbb_softc */ 942 ph->ph_parent = (struct device *)sc; 943 ph->sock = sc->sc_function; 944 ph->flags = 0; 945 ph->shutdown = 0; 946 ph->ih_irq = sc->sc_pa.pa_intrline; 947 ph->ph_bus_t = sc->sc_base_memt; 948 ph->ph_bus_h = sc->sc_base_memh; 949 ph->ph_read = pccbb_pcmcia_read; 950 ph->ph_write = pccbb_pcmcia_write; 951 sc->sc_pct = &pccbb_pcmcia_funcs; 952 953 /* 954 * We need to do a few things here: 955 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 956 * setting the IRQ numbers to 0. 957 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 958 * routing of CSC interrupts (e.g. card removal) to PCI while in 959 * PCMCIA mode. We just leave this set all the time. 960 * 3) Enable card insertion/removal interrupts in case the chip also 961 * needs that while in PCMCIA mode. 962 * 4) Clear any pending CSC interrupt. 963 */ 964 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 965 if (sc->sc_chipset == CB_TI113X) { 966 Pcic_write(ph, PCIC_CSC_INTR, 0); 967 } else { 968 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 969 Pcic_read(ph, PCIC_CSC); 970 } 971 972 /* initialize pcmcia bus attachment */ 973 paa->paa_busname = "pcmcia"; 974 paa->pct = sc->sc_pct; 975 paa->pch = ph; 976 paa->iobase = 0; /* I don't use them */ 977 paa->iosize = 0; 978 #if rbus 979 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 980 paa->iobase = rb->rb_start + rb->rb_offset; 981 paa->iosize = rb->rb_end - rb->rb_start; 982 #endif 983 984 return; 985 } 986 987 #if 0 988 STATIC void 989 pccbb_pcmcia_attach_card(ph) 990 struct pcic_handle *ph; 991 { 992 if (ph->flags & PCIC_FLAG_CARDP) { 993 panic("pccbb_pcmcia_attach_card: already attached"); 994 } 995 996 /* call the MI attach function */ 997 pcmcia_card_attach(ph->pcmcia); 998 999 ph->flags |= PCIC_FLAG_CARDP; 1000 } 1001 1002 STATIC void 1003 pccbb_pcmcia_detach_card(ph, flags) 1004 struct pcic_handle *ph; 1005 int flags; 1006 { 1007 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1008 panic("pccbb_pcmcia_detach_card: already detached"); 1009 } 1010 1011 ph->flags &= ~PCIC_FLAG_CARDP; 1012 1013 /* call the MI detach function */ 1014 pcmcia_card_detach(ph->pcmcia, flags); 1015 } 1016 #endif 1017 1018 /* 1019 * int pccbbintr(arg) 1020 * void *arg; 1021 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1022 * itself. 1023 */ 1024 int 1025 pccbbintr(arg) 1026 void *arg; 1027 { 1028 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1029 u_int32_t sockevent, sockstate; 1030 bus_space_tag_t memt = sc->sc_base_memt; 1031 bus_space_handle_t memh = sc->sc_base_memh; 1032 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1033 1034 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1035 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1036 Pcic_read(ph, PCIC_CSC); 1037 1038 if (sockevent == 0) { 1039 /* This intr is not for me: it may be for my child devices. */ 1040 if (sc->sc_pil_intr_enable) { 1041 return pccbbintr_function(sc); 1042 } else { 1043 return 0; 1044 } 1045 } 1046 1047 if (sockevent & CB_SOCKET_EVENT_CD) { 1048 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1049 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1050 /* A card should be removed. */ 1051 if (sc->sc_flags & CBB_CARDEXIST) { 1052 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1053 sockevent)); 1054 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1055 sc->sc_flags &= ~CBB_CARDEXIST; 1056 if (sc->sc_csc->sc_status & 1057 CARDSLOT_STATUS_CARD_16) { 1058 #if 0 1059 struct pcic_handle *ph = 1060 &sc->sc_pcmcia_h; 1061 1062 pcmcia_card_deactivate(ph->pcmcia); 1063 pccbb_pcmcia_socket_disable(ph); 1064 pccbb_pcmcia_detach_card(ph, 1065 DETACH_FORCE); 1066 #endif 1067 cardslot_event_throw(sc->sc_csc, 1068 CARDSLOT_EVENT_REMOVAL_16); 1069 } else if (sc->sc_csc->sc_status & 1070 CARDSLOT_STATUS_CARD_CB) { 1071 /* Cardbus intr removed */ 1072 cardslot_event_throw(sc->sc_csc, 1073 CARDSLOT_EVENT_REMOVAL_CB); 1074 } 1075 } else if (sc->sc_flags & CBB_INSERTING) { 1076 sc->sc_flags &= ~CBB_INSERTING; 1077 callout_stop(&sc->sc_insert_ch); 1078 } 1079 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1080 /* 1081 * The pccbbintr may called from powerdown hook when 1082 * the system resumed, to detect the card 1083 * insertion/removal during suspension. 1084 */ 1085 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1086 if (sc->sc_flags & CBB_INSERTING) { 1087 callout_stop(&sc->sc_insert_ch); 1088 } 1089 callout_reset(&sc->sc_insert_ch, hz / 5, 1090 pci113x_insert, sc); 1091 sc->sc_flags |= CBB_INSERTING; 1092 } 1093 } 1094 1095 return (1); 1096 } 1097 1098 /* 1099 * static int pccbbintr_function(struct pccbb_softc *sc) 1100 * 1101 * This function calls each interrupt handler registered at the 1102 * bridge. The interrupt handlers are called in registered order. 1103 */ 1104 static int 1105 pccbbintr_function(sc) 1106 struct pccbb_softc *sc; 1107 { 1108 int retval = 0, val; 1109 struct pccbb_intrhand_list *pil; 1110 int s, splchanged; 1111 1112 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1113 pil = LIST_NEXT(pil, pil_next)) { 1114 /* 1115 * XXX priority change. gross. I use if-else 1116 * sentense instead of switch-case sentense because of 1117 * avoiding duplicate case value error. More than one 1118 * IPL_XXX use same value. It depends on 1119 * implimentation. 1120 */ 1121 splchanged = 1; 1122 if (pil->pil_level == IPL_SERIAL) { 1123 s = splserial(); 1124 } else if (pil->pil_level == IPL_HIGH) { 1125 s = splhigh(); 1126 } else if (pil->pil_level == IPL_CLOCK) { 1127 s = splclock(); 1128 } else if (pil->pil_level == IPL_AUDIO) { 1129 s = splaudio(); 1130 } else if (pil->pil_level == IPL_VM) { 1131 s = splvm(); 1132 } else if (pil->pil_level == IPL_TTY) { 1133 s = spltty(); 1134 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1135 s = splsoftserial(); 1136 } else if (pil->pil_level == IPL_NET) { 1137 s = splnet(); 1138 } else { 1139 s = 0; /* XXX: gcc */ 1140 splchanged = 0; 1141 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1142 } 1143 1144 val = (*pil->pil_func)(pil->pil_arg); 1145 1146 if (splchanged != 0) { 1147 splx(s); 1148 } 1149 1150 retval = retval == 1 ? 1 : 1151 retval == 0 ? val : val != 0 ? val : retval; 1152 } 1153 1154 return retval; 1155 } 1156 1157 static void 1158 pci113x_insert(arg) 1159 void *arg; 1160 { 1161 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1162 u_int32_t sockevent, sockstate; 1163 1164 if (!(sc->sc_flags & CBB_INSERTING)) { 1165 /* We add a card only under inserting state. */ 1166 return; 1167 } 1168 sc->sc_flags &= ~CBB_INSERTING; 1169 1170 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1171 CB_SOCKET_EVENT); 1172 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1173 CB_SOCKET_STAT); 1174 1175 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1176 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1177 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1178 sc->sc_flags |= CBB_CARDEXIST; 1179 /* call pccard interrupt handler here */ 1180 if (sockstate & CB_SOCKET_STAT_16BIT) { 1181 /* 16-bit card found */ 1182 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1183 cardslot_event_throw(sc->sc_csc, 1184 CARDSLOT_EVENT_INSERTION_16); 1185 } else if (sockstate & CB_SOCKET_STAT_CB) { 1186 /* cardbus card found */ 1187 /* cardbus_attach_card(sc->sc_csc); */ 1188 cardslot_event_throw(sc->sc_csc, 1189 CARDSLOT_EVENT_INSERTION_CB); 1190 } else { 1191 /* who are you? */ 1192 } 1193 } else { 1194 callout_reset(&sc->sc_insert_ch, hz / 10, 1195 pci113x_insert, sc); 1196 } 1197 } 1198 1199 #define PCCBB_PCMCIA_OFFSET 0x800 1200 static u_int8_t 1201 pccbb_pcmcia_read(ph, reg) 1202 struct pcic_handle *ph; 1203 int reg; 1204 { 1205 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1206 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1207 1208 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1209 PCCBB_PCMCIA_OFFSET + reg); 1210 } 1211 1212 static void 1213 pccbb_pcmcia_write(ph, reg, val) 1214 struct pcic_handle *ph; 1215 int reg; 1216 u_int8_t val; 1217 { 1218 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1219 val); 1220 1221 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1222 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1223 } 1224 1225 /* 1226 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1227 */ 1228 STATIC int 1229 pccbb_ctrl(ct, command) 1230 cardbus_chipset_tag_t ct; 1231 int command; 1232 { 1233 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1234 1235 switch (command) { 1236 case CARDBUS_CD: 1237 if (2 == pccbb_detect_card(sc)) { 1238 int retval = 0; 1239 int status = cb_detect_voltage(sc); 1240 if (PCCARD_VCC_5V & status) { 1241 retval |= CARDBUS_5V_CARD; 1242 } 1243 if (PCCARD_VCC_3V & status) { 1244 retval |= CARDBUS_3V_CARD; 1245 } 1246 if (PCCARD_VCC_XV & status) { 1247 retval |= CARDBUS_XV_CARD; 1248 } 1249 if (PCCARD_VCC_YV & status) { 1250 retval |= CARDBUS_YV_CARD; 1251 } 1252 return retval; 1253 } else { 1254 return 0; 1255 } 1256 case CARDBUS_RESET: 1257 return cb_reset(sc); 1258 case CARDBUS_IO_ENABLE: /* fallthrough */ 1259 case CARDBUS_IO_DISABLE: /* fallthrough */ 1260 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1261 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1262 case CARDBUS_BM_ENABLE: /* fallthrough */ 1263 case CARDBUS_BM_DISABLE: /* fallthrough */ 1264 /* XXX: I think we don't need to call this function below. */ 1265 return pccbb_cardenable(sc, command); 1266 } 1267 1268 return 0; 1269 } 1270 1271 /* 1272 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1273 * This function returns true when it succeeds and returns false when 1274 * it fails. 1275 */ 1276 STATIC int 1277 pccbb_power(ct, command) 1278 cardbus_chipset_tag_t ct; 1279 int command; 1280 { 1281 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1282 1283 u_int32_t status, sock_ctrl, reg_ctrl; 1284 bus_space_tag_t memt = sc->sc_base_memt; 1285 bus_space_handle_t memh = sc->sc_base_memh; 1286 1287 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1288 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1289 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1290 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1291 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1292 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1293 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1294 "UNKNOWN", 1295 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1296 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1297 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1298 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1299 "UNKNOWN", command)); 1300 1301 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1302 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1303 1304 switch (command & CARDBUS_VCCMASK) { 1305 case CARDBUS_VCC_UC: 1306 break; 1307 case CARDBUS_VCC_5V: 1308 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1309 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1310 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1311 } else { 1312 printf("%s: BAD voltage request: no 5 V card\n", 1313 sc->sc_dev.dv_xname); 1314 return 0; 1315 } 1316 break; 1317 case CARDBUS_VCC_3V: 1318 if (CB_SOCKET_STAT_3VCARD & status) { 1319 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1320 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1321 } else { 1322 printf("%s: BAD voltage request: no 3.3 V card\n", 1323 sc->sc_dev.dv_xname); 1324 return 0; 1325 } 1326 break; 1327 case CARDBUS_VCC_0V: 1328 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1329 break; 1330 default: 1331 return 0; /* power NEVER changed */ 1332 } 1333 1334 switch (command & CARDBUS_VPPMASK) { 1335 case CARDBUS_VPP_UC: 1336 break; 1337 case CARDBUS_VPP_0V: 1338 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1339 break; 1340 case CARDBUS_VPP_VCC: 1341 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1342 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1343 break; 1344 case CARDBUS_VPP_12V: 1345 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1346 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1347 break; 1348 } 1349 1350 #if 0 1351 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1352 #endif 1353 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1354 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1355 1356 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1357 printf 1358 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1359 sc->sc_dev.dv_xname, sock_ctrl, status); 1360 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1361 (command & CARDBUS_VCCMASK) == 1362 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1363 CARDBUS_VCCMASK) == 1364 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1365 CARDBUS_VCCMASK) == 1366 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1367 CARDBUS_VCCMASK) == 1368 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1369 CARDBUS_VCCMASK) == 1370 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1371 CARDBUS_VCCMASK) == 1372 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1373 (command & CARDBUS_VPPMASK) == 1374 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1375 CARDBUS_VPPMASK) == 1376 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1377 CARDBUS_VPPMASK) == 1378 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1379 CARDBUS_VPPMASK) == 1380 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1381 #if 0 1382 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1383 u_int32_t force = 1384 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1385 /* Reset Bad Vcc request */ 1386 force &= ~CB_SOCKET_FORCE_BADVCC; 1387 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1388 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1389 CB_SOCKET_STAT)); 1390 return 1; 1391 } 1392 #endif 1393 return 0; 1394 } 1395 1396 if (sc->sc_chipset == CB_TOPIC97) { 1397 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1398 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1399 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1400 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1401 else 1402 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1403 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1404 } 1405 1406 /* 1407 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1408 * time is 20 ms, some PC-Card bridge requires longer duration. 1409 */ 1410 #if 0 /* XXX called on interrupt context */ 1411 DELAY_MS(300, sc); 1412 #else 1413 delay(300 * 1000); 1414 #endif 1415 1416 return 1; /* power changed correctly */ 1417 } 1418 1419 #if defined CB_PCMCIA_POLL 1420 struct cb_poll_str { 1421 void *arg; 1422 int (*func) __P((void *)); 1423 int level; 1424 pccard_chipset_tag_t ct; 1425 int count; 1426 struct callout poll_ch; 1427 }; 1428 1429 static struct cb_poll_str cb_poll[10]; 1430 static int cb_poll_n = 0; 1431 1432 static void cb_pcmcia_poll __P((void *arg)); 1433 1434 static void 1435 cb_pcmcia_poll(arg) 1436 void *arg; 1437 { 1438 struct cb_poll_str *poll = arg; 1439 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1440 struct pccbb_softc *sc = psc->cpc_parent; 1441 int s; 1442 u_int32_t spsr; /* socket present-state reg */ 1443 1444 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1445 switch (poll->level) { 1446 case IPL_NET: 1447 s = splnet(); 1448 break; 1449 case IPL_BIO: 1450 s = splbio(); 1451 break; 1452 case IPL_TTY: /* fallthrough */ 1453 default: 1454 s = spltty(); 1455 break; 1456 } 1457 1458 spsr = 1459 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1460 CB_SOCKET_STAT); 1461 1462 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1463 if (!(spsr & 0x40)) { /* CINT low */ 1464 #else 1465 if (1) { 1466 #endif 1467 if ((*poll->func) (poll->arg) == 1) { 1468 ++poll->count; 1469 printf("intr: reported from poller, 0x%x\n", spsr); 1470 #if defined LEVEL2 1471 } else { 1472 printf("intr: miss! 0x%x\n", spsr); 1473 #endif 1474 } 1475 } 1476 splx(s); 1477 } 1478 #endif /* defined CB_PCMCIA_POLL */ 1479 1480 /* 1481 * static int pccbb_detect_card(struct pccbb_softc *sc) 1482 * return value: 0 if no card exists. 1483 * 1 if 16-bit card exists. 1484 * 2 if cardbus card exists. 1485 */ 1486 static int 1487 pccbb_detect_card(sc) 1488 struct pccbb_softc *sc; 1489 { 1490 bus_space_handle_t base_memh = sc->sc_base_memh; 1491 bus_space_tag_t base_memt = sc->sc_base_memt; 1492 u_int32_t sockstat = 1493 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1494 int retval = 0; 1495 1496 /* CD1 and CD2 asserted */ 1497 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1498 /* card must be present */ 1499 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1500 /* NOTACARD DEASSERTED */ 1501 if (CB_SOCKET_STAT_CB & sockstat) { 1502 /* CardBus mode */ 1503 retval = 2; 1504 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1505 /* 16-bit mode */ 1506 retval = 1; 1507 } 1508 } 1509 } 1510 return retval; 1511 } 1512 1513 /* 1514 * STATIC int cb_reset(struct pccbb_softc *sc) 1515 * This function resets CardBus card. 1516 */ 1517 STATIC int 1518 cb_reset(sc) 1519 struct pccbb_softc *sc; 1520 { 1521 /* 1522 * Reset Assert at least 20 ms 1523 * Some machines request longer duration. 1524 */ 1525 int reset_duration = 1526 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1527 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1528 1529 /* Reset bit Assert (bit 6 at 0x3E) */ 1530 bcr |= CB_BCR_RESET_ENABLE; 1531 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1532 DELAY_MS(reset_duration, sc); 1533 1534 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1535 /* Reset bit Deassert (bit 6 at 0x3E) */ 1536 bcr &= ~CB_BCR_RESET_ENABLE; 1537 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1538 DELAY_MS(reset_duration, sc); 1539 } 1540 /* No card found on the slot. Keep Reset. */ 1541 return 1; 1542 } 1543 1544 /* 1545 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1546 * This function detect card Voltage. 1547 */ 1548 STATIC int 1549 cb_detect_voltage(sc) 1550 struct pccbb_softc *sc; 1551 { 1552 u_int32_t psr; /* socket present-state reg */ 1553 bus_space_tag_t iot = sc->sc_base_memt; 1554 bus_space_handle_t ioh = sc->sc_base_memh; 1555 int vol = PCCARD_VCC_UKN; /* set 0 */ 1556 1557 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1558 1559 if (0x400u & psr) { 1560 vol |= PCCARD_VCC_5V; 1561 } 1562 if (0x800u & psr) { 1563 vol |= PCCARD_VCC_3V; 1564 } 1565 1566 return vol; 1567 } 1568 1569 STATIC int 1570 cbbprint(aux, pcic) 1571 void *aux; 1572 const char *pcic; 1573 { 1574 /* 1575 struct cbslot_attach_args *cba = aux; 1576 1577 if (cba->cba_slot >= 0) { 1578 aprint_normal(" slot %d", cba->cba_slot); 1579 } 1580 */ 1581 return UNCONF; 1582 } 1583 1584 /* 1585 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1586 * This function enables and disables the card 1587 */ 1588 STATIC int 1589 pccbb_cardenable(sc, function) 1590 struct pccbb_softc *sc; 1591 int function; 1592 { 1593 u_int32_t command = 1594 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1595 1596 DPRINTF(("pccbb_cardenable:")); 1597 switch (function) { 1598 case CARDBUS_IO_ENABLE: 1599 command |= PCI_COMMAND_IO_ENABLE; 1600 break; 1601 case CARDBUS_IO_DISABLE: 1602 command &= ~PCI_COMMAND_IO_ENABLE; 1603 break; 1604 case CARDBUS_MEM_ENABLE: 1605 command |= PCI_COMMAND_MEM_ENABLE; 1606 break; 1607 case CARDBUS_MEM_DISABLE: 1608 command &= ~PCI_COMMAND_MEM_ENABLE; 1609 break; 1610 case CARDBUS_BM_ENABLE: 1611 command |= PCI_COMMAND_MASTER_ENABLE; 1612 break; 1613 case CARDBUS_BM_DISABLE: 1614 command &= ~PCI_COMMAND_MASTER_ENABLE; 1615 break; 1616 default: 1617 return 0; 1618 } 1619 1620 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1621 DPRINTF((" command reg 0x%x\n", command)); 1622 return 1; 1623 } 1624 1625 #if !rbus 1626 /* 1627 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1628 */ 1629 static int 1630 pccbb_io_open(ct, win, start, end) 1631 cardbus_chipset_tag_t ct; 1632 int win; 1633 u_int32_t start, end; 1634 { 1635 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1636 int basereg; 1637 int limitreg; 1638 1639 if ((win < 0) || (win > 2)) { 1640 #if defined DIAGNOSTIC 1641 printf("cardbus_io_open: window out of range %d\n", win); 1642 #endif 1643 return 0; 1644 } 1645 1646 basereg = win * 8 + 0x2c; 1647 limitreg = win * 8 + 0x30; 1648 1649 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1650 start, basereg, end, limitreg)); 1651 1652 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1653 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1654 return 1; 1655 } 1656 1657 /* 1658 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1659 */ 1660 static int 1661 pccbb_io_close(ct, win) 1662 cardbus_chipset_tag_t ct; 1663 int win; 1664 { 1665 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1666 int basereg; 1667 int limitreg; 1668 1669 if ((win < 0) || (win > 2)) { 1670 #if defined DIAGNOSTIC 1671 printf("cardbus_io_close: window out of range %d\n", win); 1672 #endif 1673 return 0; 1674 } 1675 1676 basereg = win * 8 + 0x2c; 1677 limitreg = win * 8 + 0x30; 1678 1679 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1680 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1681 return 1; 1682 } 1683 1684 /* 1685 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1686 */ 1687 static int 1688 pccbb_mem_open(ct, win, start, end) 1689 cardbus_chipset_tag_t ct; 1690 int win; 1691 u_int32_t start, end; 1692 { 1693 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1694 int basereg; 1695 int limitreg; 1696 1697 if ((win < 0) || (win > 2)) { 1698 #if defined DIAGNOSTIC 1699 printf("cardbus_mem_open: window out of range %d\n", win); 1700 #endif 1701 return 0; 1702 } 1703 1704 basereg = win * 8 + 0x1c; 1705 limitreg = win * 8 + 0x20; 1706 1707 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1708 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1709 return 1; 1710 } 1711 1712 /* 1713 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1714 */ 1715 static int 1716 pccbb_mem_close(ct, win) 1717 cardbus_chipset_tag_t ct; 1718 int win; 1719 { 1720 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1721 int basereg; 1722 int limitreg; 1723 1724 if ((win < 0) || (win > 2)) { 1725 #if defined DIAGNOSTIC 1726 printf("cardbus_mem_close: window out of range %d\n", win); 1727 #endif 1728 return 0; 1729 } 1730 1731 basereg = win * 8 + 0x1c; 1732 limitreg = win * 8 + 0x20; 1733 1734 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1735 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1736 return 1; 1737 } 1738 #endif 1739 1740 /* 1741 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1742 * int irq, 1743 * int level, 1744 * int (* func) __P((void *)), 1745 * void *arg) 1746 * 1747 * This function registers an interrupt handler at the bridge, in 1748 * order not to call the interrupt handlers of child devices when 1749 * a card-deletion interrupt occurs. 1750 * 1751 * The arguments irq and level are not used. 1752 */ 1753 static void * 1754 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1755 cardbus_chipset_tag_t ct; 1756 int irq, level; 1757 int (*func) __P((void *)); 1758 void *arg; 1759 { 1760 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1761 1762 return pccbb_intr_establish(sc, irq, level, func, arg); 1763 } 1764 1765 1766 /* 1767 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1768 * void *ih) 1769 * 1770 * This function removes an interrupt handler pointed by ih. 1771 */ 1772 static void 1773 pccbb_cb_intr_disestablish(ct, ih) 1774 cardbus_chipset_tag_t ct; 1775 void *ih; 1776 { 1777 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1778 1779 pccbb_intr_disestablish(sc, ih); 1780 } 1781 1782 1783 void 1784 pccbb_intr_route(sc) 1785 struct pccbb_softc *sc; 1786 { 1787 pcireg_t reg; 1788 1789 /* initialize bridge intr routing */ 1790 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1791 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1792 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1793 1794 switch (sc->sc_chipset) { 1795 case CB_TI113X: 1796 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1797 /* functional intr enabled */ 1798 reg |= PCI113X_CBCTRL_PCI_INTR; 1799 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1800 break; 1801 default: 1802 break; 1803 } 1804 } 1805 1806 /* 1807 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1808 * int irq, 1809 * int level, 1810 * int (* func) __P((void *)), 1811 * void *arg) 1812 * 1813 * This function registers an interrupt handler at the bridge, in 1814 * order not to call the interrupt handlers of child devices when 1815 * a card-deletion interrupt occurs. 1816 * 1817 * The arguments irq is not used because pccbb selects intr vector. 1818 */ 1819 static void * 1820 pccbb_intr_establish(sc, irq, level, func, arg) 1821 struct pccbb_softc *sc; 1822 int irq, level; 1823 int (*func) __P((void *)); 1824 void *arg; 1825 { 1826 struct pccbb_intrhand_list *pil, *newpil; 1827 1828 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1829 1830 if (LIST_EMPTY(&sc->sc_pil)) { 1831 pccbb_intr_route(sc); 1832 } 1833 1834 /* 1835 * Allocate a room for interrupt handler structure. 1836 */ 1837 if (NULL == (newpil = 1838 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1839 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1840 return NULL; 1841 } 1842 1843 newpil->pil_func = func; 1844 newpil->pil_arg = arg; 1845 newpil->pil_level = level; 1846 1847 if (LIST_EMPTY(&sc->sc_pil)) { 1848 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1849 } else { 1850 for (pil = LIST_FIRST(&sc->sc_pil); 1851 LIST_NEXT(pil, pil_next) != NULL; 1852 pil = LIST_NEXT(pil, pil_next)); 1853 LIST_INSERT_AFTER(pil, newpil, pil_next); 1854 } 1855 1856 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1857 LIST_FIRST(&sc->sc_pil))); 1858 1859 return newpil; 1860 } 1861 1862 /* 1863 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1864 * void *ih) 1865 * 1866 * This function removes an interrupt handler pointed by ih. ih 1867 * should be the value returned by cardbus_intr_establish() or 1868 * NULL. 1869 * 1870 * When ih is NULL, this function will do nothing. 1871 */ 1872 static void 1873 pccbb_intr_disestablish(sc, ih) 1874 struct pccbb_softc *sc; 1875 void *ih; 1876 { 1877 struct pccbb_intrhand_list *pil; 1878 pcireg_t reg; 1879 1880 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1881 LIST_FIRST(&sc->sc_pil))); 1882 1883 if (ih == NULL) { 1884 /* intr handler is not set */ 1885 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1886 return; 1887 } 1888 1889 #ifdef DIAGNOSTIC 1890 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1891 pil = LIST_NEXT(pil, pil_next)) { 1892 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1893 if (pil == ih) { 1894 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1895 break; 1896 } 1897 } 1898 if (pil == NULL) { 1899 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1900 sc->sc_dev.dv_xname, ih); 1901 } 1902 #endif 1903 1904 pil = (struct pccbb_intrhand_list *)ih; 1905 LIST_REMOVE(pil, pil_next); 1906 free(pil, M_DEVBUF); 1907 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1908 1909 if (LIST_EMPTY(&sc->sc_pil)) { 1910 /* No interrupt handlers */ 1911 1912 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1913 1914 /* stop routing PCI intr */ 1915 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1916 reg |= CB_BCR_INTR_IREQ_ENABLE; 1917 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1918 1919 switch (sc->sc_chipset) { 1920 case CB_TI113X: 1921 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1922 /* functional intr disabled */ 1923 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1924 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1925 break; 1926 default: 1927 break; 1928 } 1929 } 1930 } 1931 1932 #if defined SHOW_REGS 1933 static void 1934 cb_show_regs(pc, tag, memt, memh) 1935 pci_chipset_tag_t pc; 1936 pcitag_t tag; 1937 bus_space_tag_t memt; 1938 bus_space_handle_t memh; 1939 { 1940 int i; 1941 printf("PCI config regs:"); 1942 for (i = 0; i < 0x50; i += 4) { 1943 if (i % 16 == 0) { 1944 printf("\n 0x%02x:", i); 1945 } 1946 printf(" %08x", pci_conf_read(pc, tag, i)); 1947 } 1948 for (i = 0x80; i < 0xb0; i += 4) { 1949 if (i % 16 == 0) { 1950 printf("\n 0x%02x:", i); 1951 } 1952 printf(" %08x", pci_conf_read(pc, tag, i)); 1953 } 1954 1955 if (memh == 0) { 1956 printf("\n"); 1957 return; 1958 } 1959 1960 printf("\nsocket regs:"); 1961 for (i = 0; i <= 0x10; i += 0x04) { 1962 printf(" %08x", bus_space_read_4(memt, memh, i)); 1963 } 1964 printf("\nExCA regs:"); 1965 for (i = 0; i < 0x08; ++i) { 1966 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1967 } 1968 printf("\n"); 1969 return; 1970 } 1971 #endif 1972 1973 /* 1974 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1975 * int busno, int devno, int function) 1976 * This is the function to make a tag to access config space of 1977 * a CardBus Card. It works same as pci_conf_read. 1978 */ 1979 static cardbustag_t 1980 pccbb_make_tag(cc, busno, devno, function) 1981 cardbus_chipset_tag_t cc; 1982 int busno, devno, function; 1983 { 1984 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1985 1986 return pci_make_tag(sc->sc_pc, busno, devno, function); 1987 } 1988 1989 static void 1990 pccbb_free_tag(cc, tag) 1991 cardbus_chipset_tag_t cc; 1992 cardbustag_t tag; 1993 { 1994 } 1995 1996 /* 1997 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1998 * cardbustag_t tag, int offset) 1999 * This is the function to read the config space of a CardBus Card. 2000 * It works same as pci_conf_read. 2001 */ 2002 static cardbusreg_t 2003 pccbb_conf_read(cc, tag, offset) 2004 cardbus_chipset_tag_t cc; 2005 cardbustag_t tag; 2006 int offset; /* register offset */ 2007 { 2008 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2009 2010 return pci_conf_read(sc->sc_pc, tag, offset); 2011 } 2012 2013 /* 2014 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 2015 * int offs, cardbusreg_t val) 2016 * This is the function to write the config space of a CardBus Card. 2017 * It works same as pci_conf_write. 2018 */ 2019 static void 2020 pccbb_conf_write(cc, tag, reg, val) 2021 cardbus_chipset_tag_t cc; 2022 cardbustag_t tag; 2023 int reg; /* register offset */ 2024 cardbusreg_t val; 2025 { 2026 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2027 2028 pci_conf_write(sc->sc_pc, tag, reg, val); 2029 } 2030 2031 #if 0 2032 STATIC int 2033 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2034 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2035 int speed, int flags, 2036 bus_space_handle_t * iohp) 2037 #endif 2038 /* 2039 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2040 * bus_addr_t start, bus_size_t size, 2041 * bus_size_t align, 2042 * struct pcmcia_io_handle *pcihp 2043 * 2044 * This function only allocates I/O region for pccard. This function 2045 * never maps the allocated region to pccard I/O area. 2046 * 2047 * XXX: The interface of this function is not very good, I believe. 2048 */ 2049 STATIC int 2050 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2051 pcmcia_chipset_handle_t pch; 2052 bus_addr_t start; /* start address */ 2053 bus_size_t size; 2054 bus_size_t align; 2055 struct pcmcia_io_handle *pcihp; 2056 { 2057 struct pcic_handle *ph = (struct pcic_handle *)pch; 2058 bus_addr_t ioaddr; 2059 int flags = 0; 2060 bus_space_tag_t iot; 2061 bus_space_handle_t ioh; 2062 bus_addr_t mask; 2063 #if rbus 2064 rbus_tag_t rb; 2065 #endif 2066 if (align == 0) { 2067 align = size; /* XXX: funny??? */ 2068 } 2069 2070 if (start != 0) { 2071 /* XXX: assume all card decode lower 10 bits by its hardware */ 2072 mask = 0x3ff; 2073 /* enforce to use only masked address */ 2074 start &= mask; 2075 } else { 2076 /* 2077 * calculate mask: 2078 * 1. get the most significant bit of size (call it msb). 2079 * 2. compare msb with the value of size. 2080 * 3. if size is larger, shift msb left once. 2081 * 4. obtain mask value to decrement msb. 2082 */ 2083 bus_size_t size_tmp = size; 2084 int shifts = 0; 2085 2086 mask = 1; 2087 while (size_tmp) { 2088 ++shifts; 2089 size_tmp >>= 1; 2090 } 2091 mask = (1 << shifts); 2092 if (mask < size) { 2093 mask <<= 1; 2094 } 2095 --mask; 2096 } 2097 2098 /* 2099 * Allocate some arbitrary I/O space. 2100 */ 2101 2102 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2103 2104 #if rbus 2105 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2106 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2107 return 1; 2108 } 2109 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2110 (u_long) ioaddr, (u_long) size)); 2111 #else 2112 if (start) { 2113 ioaddr = start; 2114 if (bus_space_map(iot, start, size, 0, &ioh)) { 2115 return 1; 2116 } 2117 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2118 (u_long) ioaddr, (u_long) size)); 2119 } else { 2120 flags |= PCMCIA_IO_ALLOCATED; 2121 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2122 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2123 size, align, 0, 0, &ioaddr, &ioh)) { 2124 /* No room be able to be get. */ 2125 return 1; 2126 } 2127 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2128 (u_long) ioaddr, (u_long) size)); 2129 } 2130 #endif 2131 2132 pcihp->iot = iot; 2133 pcihp->ioh = ioh; 2134 pcihp->addr = ioaddr; 2135 pcihp->size = size; 2136 pcihp->flags = flags; 2137 2138 return 0; 2139 } 2140 2141 /* 2142 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2143 * struct pcmcia_io_handle *pcihp) 2144 * 2145 * This function only frees I/O region for pccard. 2146 * 2147 * XXX: The interface of this function is not very good, I believe. 2148 */ 2149 void 2150 pccbb_pcmcia_io_free(pch, pcihp) 2151 pcmcia_chipset_handle_t pch; 2152 struct pcmcia_io_handle *pcihp; 2153 { 2154 #if !rbus 2155 bus_space_tag_t iot = pcihp->iot; 2156 #endif 2157 bus_space_handle_t ioh = pcihp->ioh; 2158 bus_size_t size = pcihp->size; 2159 2160 #if rbus 2161 struct pccbb_softc *sc = 2162 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2163 rbus_tag_t rb = sc->sc_rbus_iot; 2164 2165 rbus_space_free(rb, ioh, size, NULL); 2166 #else 2167 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2168 bus_space_free(iot, ioh, size); 2169 else 2170 bus_space_unmap(iot, ioh, size); 2171 #endif 2172 } 2173 2174 /* 2175 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2176 * bus_addr_t offset, bus_size_t size, 2177 * struct pcmcia_io_handle *pcihp, 2178 * int *windowp) 2179 * 2180 * This function maps the allocated I/O region to pccard. This function 2181 * never allocates any I/O region for pccard I/O area. I don't 2182 * understand why the original authors of pcmciabus separated alloc and 2183 * map. I believe the two must be unite. 2184 * 2185 * XXX: no wait timing control? 2186 */ 2187 int 2188 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2189 pcmcia_chipset_handle_t pch; 2190 int width; 2191 bus_addr_t offset; 2192 bus_size_t size; 2193 struct pcmcia_io_handle *pcihp; 2194 int *windowp; 2195 { 2196 struct pcic_handle *ph = (struct pcic_handle *)pch; 2197 bus_addr_t ioaddr = pcihp->addr + offset; 2198 int i, win; 2199 #if defined CBB_DEBUG 2200 static char *width_names[] = { "dynamic", "io8", "io16" }; 2201 #endif 2202 2203 /* Sanity check I/O handle. */ 2204 2205 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2206 panic("pccbb_pcmcia_io_map iot is bogus"); 2207 } 2208 2209 /* XXX Sanity check offset/size. */ 2210 2211 win = -1; 2212 for (i = 0; i < PCIC_IO_WINS; i++) { 2213 if ((ph->ioalloc & (1 << i)) == 0) { 2214 win = i; 2215 ph->ioalloc |= (1 << i); 2216 break; 2217 } 2218 } 2219 2220 if (win == -1) { 2221 return 1; 2222 } 2223 2224 *windowp = win; 2225 2226 /* XXX this is pretty gross */ 2227 2228 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2229 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2230 2231 /* XXX wtf is this doing here? */ 2232 2233 #if 0 2234 printf(" port 0x%lx", (u_long) ioaddr); 2235 if (size > 1) { 2236 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2237 } 2238 #endif 2239 2240 ph->io[win].addr = ioaddr; 2241 ph->io[win].size = size; 2242 ph->io[win].width = width; 2243 2244 /* actual dirty register-value changing in the function below. */ 2245 pccbb_pcmcia_do_io_map(ph, win); 2246 2247 return 0; 2248 } 2249 2250 /* 2251 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2252 * 2253 * This function changes register-value to map I/O region for pccard. 2254 */ 2255 static void 2256 pccbb_pcmcia_do_io_map(ph, win) 2257 struct pcic_handle *ph; 2258 int win; 2259 { 2260 static u_int8_t pcic_iowidth[3] = { 2261 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2262 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2263 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2264 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2265 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2266 }; 2267 2268 #define PCIC_SIA_START_LOW 0 2269 #define PCIC_SIA_START_HIGH 1 2270 #define PCIC_SIA_STOP_LOW 2 2271 #define PCIC_SIA_STOP_HIGH 3 2272 2273 int regbase_win = 0x8 + win * 0x04; 2274 u_int8_t ioctl, enable; 2275 2276 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2277 "width %d\n", win, (unsigned long)ph->io[win].addr, 2278 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2279 2280 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2281 ph->io[win].addr & 0xff); 2282 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2283 (ph->io[win].addr >> 8) & 0xff); 2284 2285 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2286 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2287 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2288 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2289 2290 ioctl = Pcic_read(ph, PCIC_IOCTL); 2291 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2292 switch (win) { 2293 case 0: 2294 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2295 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2296 PCIC_IOCTL_IO0_DATASIZE_MASK); 2297 ioctl |= pcic_iowidth[ph->io[win].width]; 2298 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2299 break; 2300 case 1: 2301 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2302 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2303 PCIC_IOCTL_IO1_DATASIZE_MASK); 2304 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2305 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2306 break; 2307 } 2308 Pcic_write(ph, PCIC_IOCTL, ioctl); 2309 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2310 #if defined CBB_DEBUG 2311 { 2312 u_int8_t start_low = 2313 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2314 u_int8_t start_high = 2315 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2316 u_int8_t stop_low = 2317 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2318 u_int8_t stop_high = 2319 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2320 printf 2321 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2322 start_low, start_high, stop_low, stop_high, ioctl, enable); 2323 } 2324 #endif 2325 } 2326 2327 /* 2328 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2329 * 2330 * This function unmaps I/O region. No return value. 2331 */ 2332 STATIC void 2333 pccbb_pcmcia_io_unmap(pch, win) 2334 pcmcia_chipset_handle_t pch; 2335 int win; 2336 { 2337 struct pcic_handle *ph = (struct pcic_handle *)pch; 2338 int reg; 2339 2340 if (win >= PCIC_IO_WINS || win < 0) { 2341 panic("pccbb_pcmcia_io_unmap: window out of range"); 2342 } 2343 2344 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2345 switch (win) { 2346 case 0: 2347 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2348 break; 2349 case 1: 2350 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2351 break; 2352 } 2353 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2354 2355 ph->ioalloc &= ~(1 << win); 2356 } 2357 2358 /* 2359 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2360 * 2361 * This function enables the card. All information is stored in 2362 * the first argument, pcmcia_chipset_handle_t. 2363 */ 2364 static int 2365 pccbb_pcmcia_wait_ready(ph) 2366 struct pcic_handle *ph; 2367 { 2368 u_char stat; 2369 int i; 2370 2371 DPRINTF(("entering pccbb_pcmcia_wait_ready: status 0x%02x\n", 2372 Pcic_read(ph, PCIC_IF_STATUS))); 2373 2374 for (i = 0; i < 2000; i++) { 2375 stat = Pcic_read(ph, PCIC_IF_STATUS); 2376 if (stat & PCIC_IF_STATUS_READY) 2377 return 1; 2378 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2379 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2380 return 0; 2381 DELAY_MS(2, ph->ph_parent); 2382 #ifdef CBB_DEBUG 2383 if ((i > 1000) && (i % 25 == 24)) 2384 printf("."); 2385 #endif 2386 } 2387 2388 #ifdef DIAGNOSTIC 2389 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2390 Pcic_read(ph, PCIC_IF_STATUS)); 2391 #endif 2392 2393 return 0; 2394 } 2395 2396 /* 2397 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2398 * 2399 * This function enables the card. All information is stored in 2400 * the first argument, pcmcia_chipset_handle_t. 2401 */ 2402 STATIC void 2403 pccbb_pcmcia_socket_enable(pch) 2404 pcmcia_chipset_handle_t pch; 2405 { 2406 struct pcic_handle *ph = (struct pcic_handle *)pch; 2407 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2408 int win; 2409 u_int8_t power, intr; 2410 pcireg_t spsr; 2411 int voltage; 2412 2413 /* this bit is mostly stolen from pcic_attach_card */ 2414 2415 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2416 2417 /* get card Vcc info */ 2418 2419 spsr = 2420 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2421 CB_SOCKET_STAT); 2422 if (spsr & CB_SOCKET_STAT_5VCARD) { 2423 DPRINTF(("5V card\n")); 2424 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2425 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2426 DPRINTF(("3V card\n")); 2427 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2428 } else { 2429 printf("?V card, 0x%x\n", spsr); /* XXX */ 2430 return; 2431 } 2432 2433 /* power down the socket to reset it, clear the card reset pin */ 2434 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2435 2436 /* disable socket: negate output enable bit and power off */ 2437 power = 0; 2438 Pcic_write(ph, PCIC_PWRCTL, power); 2439 2440 /* 2441 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2442 * we are changing Vcc (Toff). 2443 */ 2444 /* delay(300*1000); too much */ 2445 2446 /* assert reset bit */ 2447 intr = Pcic_read(ph, PCIC_INTR); 2448 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2449 Pcic_write(ph, PCIC_INTR, intr); 2450 2451 /* power up the socket */ 2452 power = Pcic_read(ph, PCIC_PWRCTL); 2453 Pcic_write(ph, PCIC_PWRCTL, (power & ~PCIC_PWRCTL_OE)); 2454 pccbb_power(sc, voltage); 2455 2456 /* now output enable */ 2457 power = Pcic_read(ph, PCIC_PWRCTL); 2458 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2459 2460 if (pccbb_power(sc, voltage) == 0) { 2461 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2462 power &= ~PCIC_PWRCTL_OE; 2463 Pcic_write(ph, PCIC_PWRCTL, power); 2464 intr |= PCIC_INTR_RESET; 2465 Pcic_write(ph, PCIC_INTR, intr); 2466 return; 2467 } 2468 2469 /* 2470 * hold RESET at least 20 ms: the spec says only 10 us is 2471 * enough, but TI1130 requires at least 20 ms. 2472 */ 2473 #if 0 /* XXX called on interrupt context */ 2474 DELAY_MS(20, sc); 2475 #else 2476 delay(20 * 1000); 2477 #endif 2478 2479 /* clear the reset flag */ 2480 2481 intr |= PCIC_INTR_RESET; 2482 Pcic_write(ph, PCIC_INTR, intr); 2483 2484 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2485 2486 #if 0 /* XXX called on interrupt context */ 2487 DELAY_MS(20, sc); 2488 #else 2489 delay(20 * 1000); 2490 #endif 2491 2492 /* wait for the chip to finish initializing */ 2493 2494 if (pccbb_pcmcia_wait_ready(ph) == 0) { 2495 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2496 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2497 return; 2498 } 2499 2500 /* zero out the address windows */ 2501 2502 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2503 2504 /* reinstall all the memory and io mappings */ 2505 2506 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2507 if (ph->memalloc & (1 << win)) { 2508 pccbb_pcmcia_do_mem_map(ph, win); 2509 } 2510 } 2511 2512 for (win = 0; win < PCIC_IO_WINS; ++win) { 2513 if (ph->ioalloc & (1 << win)) { 2514 pccbb_pcmcia_do_io_map(ph, win); 2515 } 2516 } 2517 } 2518 2519 /* 2520 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2521 * 2522 * This function disables the card. All information is stored in 2523 * the first argument, pcmcia_chipset_handle_t. 2524 */ 2525 STATIC void 2526 pccbb_pcmcia_socket_disable(pch) 2527 pcmcia_chipset_handle_t pch; 2528 { 2529 struct pcic_handle *ph = (struct pcic_handle *)pch; 2530 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2531 u_int8_t intr, power; 2532 2533 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2534 2535 /* disable interrupts */ 2536 intr = Pcic_read(h, PCIC_INTR); 2537 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2538 Pcic_write(h, PCIC_INTR, intr); 2539 2540 /* zero out the address windows */ 2541 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2542 2543 /* power down the socket to reset it, clear the card reset pin */ 2544 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2545 2546 /* disable socket: negate output enable bit and power off */ 2547 power = 0; 2548 Pcic_write(ph, PCIC_PWRCTL, power); 2549 2550 /* 2551 * wait 300ms until power fails (Tpf). 2552 */ 2553 #if 0 /* XXX called on interrupt context */ 2554 DELAY_MS(300, sc); 2555 #else 2556 delay(300 * 1000); 2557 #endif 2558 2559 /* reset signal asserting... */ 2560 } 2561 2562 STATIC void 2563 pccbb_pcmcia_socket_settype(pch, type) 2564 pcmcia_chipset_handle_t pch; 2565 int type; 2566 { 2567 struct pcic_handle *ph = (struct pcic_handle *)pch; 2568 u_int8_t intr; 2569 2570 /* set the card type */ 2571 2572 intr = Pcic_read(ph, PCIC_INTR); 2573 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2574 if (type == PCMCIA_IFTYPE_IO) 2575 intr |= PCIC_INTR_CARDTYPE_IO; 2576 else 2577 intr |= PCIC_INTR_CARDTYPE_MEM; 2578 Pcic_write(ph, PCIC_INTR, intr); 2579 2580 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2581 ph->ph_parent->dv_xname, ph->sock, 2582 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2583 } 2584 2585 /* 2586 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2587 * 2588 * This function detects whether a card is in the slot or not. 2589 * If a card is inserted, return 1. Otherwise, return 0. 2590 */ 2591 STATIC int 2592 pccbb_pcmcia_card_detect(pch) 2593 pcmcia_chipset_handle_t pch; 2594 { 2595 struct pcic_handle *ph = (struct pcic_handle *)pch; 2596 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2597 2598 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2599 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2600 } 2601 2602 #if 0 2603 STATIC int 2604 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2605 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2606 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2607 #endif 2608 /* 2609 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2610 * bus_size_t size, 2611 * struct pcmcia_mem_handle *pcmhp) 2612 * 2613 * This function only allocates memory region for pccard. This 2614 * function never maps the allocated region to pccard memory area. 2615 * 2616 * XXX: Why the argument of start address is not in? 2617 */ 2618 STATIC int 2619 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2620 pcmcia_chipset_handle_t pch; 2621 bus_size_t size; 2622 struct pcmcia_mem_handle *pcmhp; 2623 { 2624 struct pcic_handle *ph = (struct pcic_handle *)pch; 2625 bus_space_handle_t memh; 2626 bus_addr_t addr; 2627 bus_size_t sizepg; 2628 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2629 #if rbus 2630 rbus_tag_t rb; 2631 #endif 2632 2633 /* Check that the card is still there. */ 2634 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2635 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2636 return 1; 2637 2638 /* out of sc->memh, allocate as many pages as necessary */ 2639 2640 /* convert size to PCIC pages */ 2641 /* 2642 * This is not enough; when the requested region is on the page 2643 * boundaries, this may calculate wrong result. 2644 */ 2645 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2646 #if 0 2647 if (sizepg > PCIC_MAX_MEM_PAGES) { 2648 return 1; 2649 } 2650 #endif 2651 2652 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2653 return 1; 2654 } 2655 2656 addr = 0; /* XXX gcc -Wuninitialized */ 2657 2658 #if rbus 2659 rb = sc->sc_rbus_memt; 2660 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2661 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2662 &addr, &memh)) { 2663 return 1; 2664 } 2665 #else 2666 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2667 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2668 0, /* boundary */ 2669 0, /* flags */ 2670 &addr, &memh)) { 2671 return 1; 2672 } 2673 #endif 2674 2675 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2676 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2677 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2678 2679 pcmhp->memt = sc->sc_memt; 2680 pcmhp->memh = memh; 2681 pcmhp->addr = addr; 2682 pcmhp->size = size; 2683 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2684 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2685 pcmhp->mhandle = 0; 2686 /* No offset??? Funny. */ 2687 2688 return 0; 2689 } 2690 2691 /* 2692 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2693 * struct pcmcia_mem_handle *pcmhp) 2694 * 2695 * This function release the memory space allocated by the function 2696 * pccbb_pcmcia_mem_alloc(). 2697 */ 2698 STATIC void 2699 pccbb_pcmcia_mem_free(pch, pcmhp) 2700 pcmcia_chipset_handle_t pch; 2701 struct pcmcia_mem_handle *pcmhp; 2702 { 2703 #if rbus 2704 struct pcic_handle *ph = (struct pcic_handle *)pch; 2705 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2706 2707 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2708 #else 2709 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2710 #endif 2711 } 2712 2713 /* 2714 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2715 * 2716 * This function release the memory space allocated by the function 2717 * pccbb_pcmcia_mem_alloc(). 2718 */ 2719 STATIC void 2720 pccbb_pcmcia_do_mem_map(ph, win) 2721 struct pcic_handle *ph; 2722 int win; 2723 { 2724 int regbase_win; 2725 bus_addr_t phys_addr; 2726 bus_addr_t phys_end; 2727 2728 #define PCIC_SMM_START_LOW 0 2729 #define PCIC_SMM_START_HIGH 1 2730 #define PCIC_SMM_STOP_LOW 2 2731 #define PCIC_SMM_STOP_HIGH 3 2732 #define PCIC_CMA_LOW 4 2733 #define PCIC_CMA_HIGH 5 2734 2735 u_int8_t start_low, start_high = 0; 2736 u_int8_t stop_low, stop_high; 2737 u_int8_t off_low, off_high; 2738 u_int8_t mem_window; 2739 int reg; 2740 2741 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2742 int mem8 = 2743 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2744 || (kind == PCMCIA_MEM_ATTR); 2745 2746 regbase_win = 0x10 + win * 0x08; 2747 2748 phys_addr = ph->mem[win].addr; 2749 phys_end = phys_addr + ph->mem[win].size; 2750 2751 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2752 (unsigned long)phys_addr, (unsigned long)phys_end, 2753 (unsigned long)ph->mem[win].offset)); 2754 2755 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2756 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2757 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2758 2759 /* bit 19:12 */ 2760 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2761 /* bit 23:20 and bit 7 on */ 2762 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2763 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2764 /* bit 31:24, for 32-bit address */ 2765 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2766 2767 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2768 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2769 2770 if (((struct pccbb_softc *)ph-> 2771 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2772 Pcic_write(ph, 0x40 + win, mem_window); 2773 } 2774 2775 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2776 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2777 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2778 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2779 2780 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2781 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2782 2783 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2784 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2785 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2786 | ((kind == PCMCIA_MEM_ATTR) ? 2787 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2788 2789 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2790 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2791 2792 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2793 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2794 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2795 2796 #if defined CBB_DEBUG 2797 { 2798 int r1, r2, r3, r4, r5, r6, r7 = 0; 2799 2800 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2801 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2802 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2803 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2804 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2805 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2806 if (((struct pccbb_softc *)(ph-> 2807 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2808 r7 = Pcic_read(ph, 0x40 + win); 2809 } 2810 2811 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2812 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2813 if (((struct pccbb_softc *)(ph-> 2814 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2815 DPRINTF((" %02x", r7)); 2816 } 2817 DPRINTF(("\n")); 2818 } 2819 #endif 2820 } 2821 2822 /* 2823 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2824 * bus_addr_t card_addr, bus_size_t size, 2825 * struct pcmcia_mem_handle *pcmhp, 2826 * bus_addr_t *offsetp, int *windowp) 2827 * 2828 * This function maps memory space allocated by the function 2829 * pccbb_pcmcia_mem_alloc(). 2830 */ 2831 STATIC int 2832 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2833 pcmcia_chipset_handle_t pch; 2834 int kind; 2835 bus_addr_t card_addr; 2836 bus_size_t size; 2837 struct pcmcia_mem_handle *pcmhp; 2838 bus_addr_t *offsetp; 2839 int *windowp; 2840 { 2841 struct pcic_handle *ph = (struct pcic_handle *)pch; 2842 bus_addr_t busaddr; 2843 long card_offset; 2844 int win; 2845 2846 /* Check that the card is still there. */ 2847 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2848 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2849 return 1; 2850 2851 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2852 if ((ph->memalloc & (1 << win)) == 0) { 2853 ph->memalloc |= (1 << win); 2854 break; 2855 } 2856 } 2857 2858 if (win == PCIC_MEM_WINS) { 2859 return 1; 2860 } 2861 2862 *windowp = win; 2863 2864 /* XXX this is pretty gross */ 2865 2866 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2867 panic("pccbb_pcmcia_mem_map memt is bogus"); 2868 } 2869 2870 busaddr = pcmhp->addr; 2871 2872 /* 2873 * compute the address offset to the pcmcia address space for the 2874 * pcic. this is intentionally signed. The masks and shifts below 2875 * will cause TRT to happen in the pcic registers. Deal with making 2876 * sure the address is aligned, and return the alignment offset. 2877 */ 2878 2879 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2880 card_addr -= *offsetp; 2881 2882 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2883 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2884 (u_long) card_addr)); 2885 2886 /* 2887 * include the offset in the size, and decrement size by one, since 2888 * the hw wants start/stop 2889 */ 2890 size += *offsetp - 1; 2891 2892 card_offset = (((long)card_addr) - ((long)busaddr)); 2893 2894 ph->mem[win].addr = busaddr; 2895 ph->mem[win].size = size; 2896 ph->mem[win].offset = card_offset; 2897 ph->mem[win].kind = kind; 2898 2899 pccbb_pcmcia_do_mem_map(ph, win); 2900 2901 return 0; 2902 } 2903 2904 /* 2905 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2906 * int window) 2907 * 2908 * This function unmaps memory space which mapped by the function 2909 * pccbb_pcmcia_mem_map(). 2910 */ 2911 STATIC void 2912 pccbb_pcmcia_mem_unmap(pch, window) 2913 pcmcia_chipset_handle_t pch; 2914 int window; 2915 { 2916 struct pcic_handle *ph = (struct pcic_handle *)pch; 2917 int reg; 2918 2919 if (window >= PCIC_MEM_WINS) { 2920 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2921 } 2922 2923 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2924 reg &= ~(1 << window); 2925 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2926 2927 ph->memalloc &= ~(1 << window); 2928 } 2929 2930 #if defined PCCBB_PCMCIA_POLL 2931 struct pccbb_poll_str { 2932 void *arg; 2933 int (*func) __P((void *)); 2934 int level; 2935 struct pcic_handle *ph; 2936 int count; 2937 int num; 2938 struct callout poll_ch; 2939 }; 2940 2941 static struct pccbb_poll_str pccbb_poll[10]; 2942 static int pccbb_poll_n = 0; 2943 2944 static void pccbb_pcmcia_poll __P((void *arg)); 2945 2946 static void 2947 pccbb_pcmcia_poll(arg) 2948 void *arg; 2949 { 2950 struct pccbb_poll_str *poll = arg; 2951 struct pcic_handle *ph = poll->ph; 2952 struct pccbb_softc *sc = ph->sc; 2953 int s; 2954 u_int32_t spsr; /* socket present-state reg */ 2955 2956 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2957 switch (poll->level) { 2958 case IPL_NET: 2959 s = splnet(); 2960 break; 2961 case IPL_BIO: 2962 s = splbio(); 2963 break; 2964 case IPL_TTY: /* fallthrough */ 2965 default: 2966 s = spltty(); 2967 break; 2968 } 2969 2970 spsr = 2971 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2972 CB_SOCKET_STAT); 2973 2974 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2975 if (!(spsr & 0x40)) /* CINT low */ 2976 #else 2977 if (1) 2978 #endif 2979 { 2980 if ((*poll->func) (poll->arg) > 0) { 2981 ++poll->count; 2982 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2983 #if defined LEVEL2 2984 } else { 2985 printf("intr: miss! 0x%x\n", spsr); 2986 #endif 2987 } 2988 } 2989 splx(s); 2990 } 2991 #endif /* defined CB_PCMCIA_POLL */ 2992 2993 /* 2994 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2995 * struct pcmcia_function *pf, 2996 * int ipl, 2997 * int (*func)(void *), 2998 * void *arg); 2999 * 3000 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 3001 */ 3002 STATIC void * 3003 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 3004 pcmcia_chipset_handle_t pch; 3005 struct pcmcia_function *pf; 3006 int ipl; 3007 int (*func) __P((void *)); 3008 void *arg; 3009 { 3010 struct pcic_handle *ph = (struct pcic_handle *)pch; 3011 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3012 3013 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3014 /* what should I do? */ 3015 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3016 DPRINTF(("%s does not provide edge nor pulse " 3017 "interrupt\n", sc->sc_dev.dv_xname)); 3018 return NULL; 3019 } 3020 /* 3021 * XXX Noooooo! The interrupt flag must set properly!! 3022 * dumb pcmcia driver!! 3023 */ 3024 } 3025 3026 return pccbb_intr_establish(sc, 0, ipl, func, arg); 3027 } 3028 3029 /* 3030 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 3031 * void *ih) 3032 * 3033 * This function disables PC-Card interrupt. 3034 */ 3035 STATIC void 3036 pccbb_pcmcia_intr_disestablish(pch, ih) 3037 pcmcia_chipset_handle_t pch; 3038 void *ih; 3039 { 3040 struct pcic_handle *ph = (struct pcic_handle *)pch; 3041 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3042 3043 pccbb_intr_disestablish(sc, ih); 3044 } 3045 3046 #if rbus 3047 /* 3048 * static int 3049 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3050 * bus_addr_t addr, bus_size_t size, 3051 * bus_addr_t mask, bus_size_t align, 3052 * int flags, bus_addr_t *addrp; 3053 * bus_space_handle_t *bshp) 3054 * 3055 * This function allocates a portion of memory or io space for 3056 * clients. This function is called from CardBus card drivers. 3057 */ 3058 static int 3059 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3060 cardbus_chipset_tag_t ct; 3061 rbus_tag_t rb; 3062 bus_addr_t addr; 3063 bus_size_t size; 3064 bus_addr_t mask; 3065 bus_size_t align; 3066 int flags; 3067 bus_addr_t *addrp; 3068 bus_space_handle_t *bshp; 3069 { 3070 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3071 3072 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3073 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3074 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3075 3076 if (align == 0) { 3077 align = size; 3078 } 3079 3080 if (rb->rb_bt == sc->sc_memt) { 3081 if (align < 16) { 3082 return 1; 3083 } 3084 /* 3085 * XXX: align more than 0x1000 to avoid overwrapping 3086 * memory windows for two or more devices. 0x1000 3087 * means memory window's granularity. 3088 * 3089 * Two or more devices should be able to share same 3090 * memory window region. However, overrapping memory 3091 * window is not good because some devices, such as 3092 * 3Com 3C575[BC], have a broken address decoder and 3093 * intrude other's memory region. 3094 */ 3095 if (align < 0x1000) { 3096 align = 0x1000; 3097 } 3098 } else if (rb->rb_bt == sc->sc_iot) { 3099 if (align < 4) { 3100 return 1; 3101 } 3102 /* XXX: hack for avoiding ISA image */ 3103 if (mask < 0x0100) { 3104 mask = 0x3ff; 3105 addr = 0x300; 3106 } 3107 3108 } else { 3109 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3110 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3111 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3112 (unsigned long)sc->sc_memt)); 3113 return 1; 3114 /* XXX: panic here? */ 3115 } 3116 3117 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3118 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3119 return 1; 3120 } 3121 3122 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3123 3124 return 0; 3125 } 3126 3127 /* 3128 * static int 3129 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3130 * bus_space_handle_t *bshp, bus_size_t size); 3131 * 3132 * This function is called from CardBus card drivers. 3133 */ 3134 static int 3135 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3136 cardbus_chipset_tag_t ct; 3137 rbus_tag_t rb; 3138 bus_space_handle_t bsh; 3139 bus_size_t size; 3140 { 3141 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3142 bus_space_tag_t bt = rb->rb_bt; 3143 3144 pccbb_close_win(sc, bt, bsh, size); 3145 3146 if (bt == sc->sc_memt) { 3147 } else if (bt == sc->sc_iot) { 3148 } else { 3149 return 1; 3150 /* XXX: panic here? */ 3151 } 3152 3153 return rbus_space_free(rb, bsh, size, NULL); 3154 } 3155 #endif /* rbus */ 3156 3157 #if rbus 3158 3159 static int 3160 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3161 struct pccbb_softc *sc; 3162 bus_space_tag_t bst; 3163 bus_addr_t addr; 3164 bus_size_t size; 3165 bus_space_handle_t bsh; 3166 int flags; 3167 { 3168 struct pccbb_win_chain_head *head; 3169 bus_addr_t align; 3170 3171 head = &sc->sc_iowindow; 3172 align = 0x04; 3173 if (sc->sc_memt == bst) { 3174 head = &sc->sc_memwindow; 3175 align = 0x1000; 3176 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3177 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3178 (unsigned long)bst)); 3179 } 3180 3181 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3182 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3183 sc->sc_dev.dv_xname, 3184 (head == &sc->sc_memwindow) ? "mem" : "io"); 3185 } 3186 pccbb_winset(align, sc, bst); 3187 3188 return 0; 3189 } 3190 3191 static int 3192 pccbb_close_win(sc, bst, bsh, size) 3193 struct pccbb_softc *sc; 3194 bus_space_tag_t bst; 3195 bus_space_handle_t bsh; 3196 bus_size_t size; 3197 { 3198 struct pccbb_win_chain_head *head; 3199 bus_addr_t align; 3200 3201 head = &sc->sc_iowindow; 3202 align = 0x04; 3203 if (sc->sc_memt == bst) { 3204 head = &sc->sc_memwindow; 3205 align = 0x1000; 3206 } 3207 3208 if (pccbb_winlist_delete(head, bsh, size)) { 3209 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3210 sc->sc_dev.dv_xname, 3211 (head == &sc->sc_memwindow) ? "mem" : "io"); 3212 } 3213 pccbb_winset(align, sc, bst); 3214 3215 return 0; 3216 } 3217 3218 static int 3219 pccbb_winlist_insert(head, start, size, bsh, flags) 3220 struct pccbb_win_chain_head *head; 3221 bus_addr_t start; 3222 bus_size_t size; 3223 bus_space_handle_t bsh; 3224 int flags; 3225 { 3226 struct pccbb_win_chain *chainp, *elem; 3227 3228 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3229 M_NOWAIT)) == NULL) 3230 return (1); /* fail */ 3231 3232 elem->wc_start = start; 3233 elem->wc_end = start + (size - 1); 3234 elem->wc_handle = bsh; 3235 elem->wc_flags = flags; 3236 3237 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3238 chainp = TAILQ_NEXT(chainp, wc_list)) { 3239 if (chainp->wc_end < start) 3240 continue; 3241 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3242 return (0); 3243 } 3244 3245 TAILQ_INSERT_TAIL(head, elem, wc_list); 3246 return (0); 3247 } 3248 3249 static int 3250 pccbb_winlist_delete(head, bsh, size) 3251 struct pccbb_win_chain_head *head; 3252 bus_space_handle_t bsh; 3253 bus_size_t size; 3254 { 3255 struct pccbb_win_chain *chainp; 3256 3257 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3258 chainp = TAILQ_NEXT(chainp, wc_list)) { 3259 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3260 continue; 3261 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3262 printf("pccbb_winlist_delete: window 0x%lx size " 3263 "inconsistent: 0x%lx, 0x%lx\n", 3264 (unsigned long)chainp->wc_start, 3265 (unsigned long)(chainp->wc_end - chainp->wc_start), 3266 (unsigned long)(size - 1)); 3267 return 1; 3268 } 3269 3270 TAILQ_REMOVE(head, chainp, wc_list); 3271 free(chainp, M_DEVBUF); 3272 3273 return 0; 3274 } 3275 3276 return 1; /* fail: no candidate to remove */ 3277 } 3278 3279 static void 3280 pccbb_winset(align, sc, bst) 3281 bus_addr_t align; 3282 struct pccbb_softc *sc; 3283 bus_space_tag_t bst; 3284 { 3285 pci_chipset_tag_t pc; 3286 pcitag_t tag; 3287 bus_addr_t mask = ~(align - 1); 3288 struct { 3289 cardbusreg_t win_start; 3290 cardbusreg_t win_limit; 3291 int win_flags; 3292 } win[2]; 3293 struct pccbb_win_chain *chainp; 3294 int offs; 3295 3296 win[0].win_start = win[1].win_start = 0xffffffff; 3297 win[0].win_limit = win[1].win_limit = 0; 3298 win[0].win_flags = win[1].win_flags = 0; 3299 3300 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3301 offs = 0x2c; 3302 if (sc->sc_memt == bst) { 3303 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3304 offs = 0x1c; 3305 } 3306 3307 if (chainp != NULL) { 3308 win[0].win_start = chainp->wc_start & mask; 3309 win[0].win_limit = chainp->wc_end & mask; 3310 win[0].win_flags = chainp->wc_flags; 3311 chainp = TAILQ_NEXT(chainp, wc_list); 3312 } 3313 3314 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3315 if (win[1].win_start == 0xffffffff) { 3316 /* window 1 is not used */ 3317 if ((win[0].win_flags == chainp->wc_flags) && 3318 (win[0].win_limit + align >= 3319 (chainp->wc_start & mask))) { 3320 /* concatenate */ 3321 win[0].win_limit = chainp->wc_end & mask; 3322 } else { 3323 /* make new window */ 3324 win[1].win_start = chainp->wc_start & mask; 3325 win[1].win_limit = chainp->wc_end & mask; 3326 win[1].win_flags = chainp->wc_flags; 3327 } 3328 continue; 3329 } 3330 3331 /* Both windows are engaged. */ 3332 if (win[0].win_flags == win[1].win_flags) { 3333 /* same flags */ 3334 if (win[0].win_flags == chainp->wc_flags) { 3335 if (win[1].win_start - (win[0].win_limit + 3336 align) < 3337 (chainp->wc_start & mask) - 3338 ((chainp->wc_end & mask) + align)) { 3339 /* 3340 * merge window 0 and 1, and set win1 3341 * to chainp 3342 */ 3343 win[0].win_limit = win[1].win_limit; 3344 win[1].win_start = 3345 chainp->wc_start & mask; 3346 win[1].win_limit = 3347 chainp->wc_end & mask; 3348 } else { 3349 win[1].win_limit = 3350 chainp->wc_end & mask; 3351 } 3352 } else { 3353 /* different flags */ 3354 3355 /* concatenate win0 and win1 */ 3356 win[0].win_limit = win[1].win_limit; 3357 /* allocate win[1] to new space */ 3358 win[1].win_start = chainp->wc_start & mask; 3359 win[1].win_limit = chainp->wc_end & mask; 3360 win[1].win_flags = chainp->wc_flags; 3361 } 3362 } else { 3363 /* the flags of win[0] and win[1] is different */ 3364 if (win[0].win_flags == chainp->wc_flags) { 3365 win[0].win_limit = chainp->wc_end & mask; 3366 /* 3367 * XXX this creates overlapping windows, so 3368 * what should the poor bridge do if one is 3369 * cachable, and the other is not? 3370 */ 3371 printf("%s: overlapping windows\n", 3372 sc->sc_dev.dv_xname); 3373 } else { 3374 win[1].win_limit = chainp->wc_end & mask; 3375 } 3376 } 3377 } 3378 3379 pc = sc->sc_pc; 3380 tag = sc->sc_tag; 3381 pci_conf_write(pc, tag, offs, win[0].win_start); 3382 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3383 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3384 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3385 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3386 (unsigned long)pci_conf_read(pc, tag, offs), 3387 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3388 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3389 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3390 3391 if (bst == sc->sc_memt) { 3392 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3393 3394 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3395 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3396 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3397 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3398 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3399 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3400 } 3401 } 3402 3403 #endif /* rbus */ 3404 3405 static void 3406 pccbb_powerhook(why, arg) 3407 int why; 3408 void *arg; 3409 { 3410 struct pccbb_softc *sc = arg; 3411 pcireg_t reg; 3412 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3413 bus_space_handle_t base_memh = sc->sc_base_memh; 3414 3415 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3416 3417 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3418 DPRINTF(("%s: power: why %d stopping intr\n", 3419 sc->sc_dev.dv_xname, why)); 3420 if (sc->sc_pil_intr_enable) { 3421 (void)pccbbintr_function(sc); 3422 } 3423 sc->sc_pil_intr_enable = 0; 3424 3425 /* ToDo: deactivate or suspend child devices */ 3426 3427 } 3428 3429 if (why == PWR_RESUME) { 3430 if (sc->sc_pwrmgt_offs != 0) { 3431 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3432 sc->sc_pwrmgt_offs + 4); 3433 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3434 reg & 0x100) { 3435 /* powrstate != D0 */ 3436 3437 printf("%s going back to D0 mode\n", 3438 sc->sc_dev.dv_xname); 3439 reg &= ~PCI_PMCSR_STATE_MASK; 3440 reg |= PCI_PMCSR_STATE_D0; 3441 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3442 pci_conf_write(sc->sc_pc, sc->sc_tag, 3443 sc->sc_pwrmgt_offs + 4, reg); 3444 3445 pci_conf_write(sc->sc_pc, sc->sc_tag, 3446 PCI_SOCKBASE, sc->sc_sockbase); 3447 pci_conf_write(sc->sc_pc, sc->sc_tag, 3448 PCI_BUSNUM, sc->sc_busnum); 3449 pccbb_chipinit(sc); 3450 /* setup memory and io space window for CB */ 3451 pccbb_winset(0x1000, sc, sc->sc_memt); 3452 pccbb_winset(0x04, sc, sc->sc_iot); 3453 } 3454 } 3455 3456 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3457 /* BIOS did not recover this register */ 3458 pci_conf_write (sc->sc_pc, sc->sc_tag, 3459 PCI_SOCKBASE, sc->sc_sockbase); 3460 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3461 /* BIOS did not recover this register */ 3462 pci_conf_write (sc->sc_pc, sc->sc_tag, 3463 PCI_BUSNUM, sc->sc_busnum); 3464 /* CSC Interrupt: Card detect interrupt on */ 3465 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3466 /* Card detect intr is turned on. */ 3467 reg |= CB_SOCKET_MASK_CD; 3468 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3469 /* reset interrupt */ 3470 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3471 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3472 3473 /* 3474 * check for card insertion or removal during suspend period. 3475 * XXX: the code can't cope with card swap (remove then 3476 * insert). how can we detect such situation? 3477 */ 3478 (void)pccbbintr(sc); 3479 3480 sc->sc_pil_intr_enable = 1; 3481 DPRINTF(("%s: power: RESUME enabling intr\n", 3482 sc->sc_dev.dv_xname)); 3483 3484 /* ToDo: activate or wakeup child devices */ 3485 } 3486 } 3487
Indexes created Fri Sep 26 20:09:58 GMT 2025