pccbb.c revision 1.104
1 /* $NetBSD: pccbb.c,v 1.104 2004/08/12 07:15:49 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.104 2004/08/12 07:15:49 mycroft Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC void pccbb_pcmcia_socket_settype __P((pcmcia_chipset_handle_t, int)); 188 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 189 190 static int pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_delay __P((struct pcic_handle *, int, const char *)); 192 193 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 194 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 195 static void pccbb_powerhook __P((int, void *)); 196 197 /* bus-space allocation and deallocation functions */ 198 #if rbus 199 200 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 202 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 203 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 204 bus_space_handle_t, bus_size_t)); 205 206 #endif /* rbus */ 207 208 #if rbus 209 210 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 211 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 212 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 213 bus_space_handle_t, bus_size_t)); 214 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 215 bus_size_t, bus_space_handle_t, int)); 216 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 217 bus_space_handle_t, bus_size_t)); 218 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 219 bus_space_tag_t)); 220 void pccbb_winlist_show(struct pccbb_win_chain *); 221 222 #endif /* rbus */ 223 224 /* for config_defer */ 225 static void pccbb_pci_callback __P((struct device *)); 226 227 #if defined SHOW_REGS 228 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 229 bus_space_tag_t memt, bus_space_handle_t memh)); 230 #endif 231 232 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 233 pcicbbmatch, pccbbattach, NULL, NULL); 234 235 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 236 pccbb_pcmcia_mem_alloc, 237 pccbb_pcmcia_mem_free, 238 pccbb_pcmcia_mem_map, 239 pccbb_pcmcia_mem_unmap, 240 pccbb_pcmcia_io_alloc, 241 pccbb_pcmcia_io_free, 242 pccbb_pcmcia_io_map, 243 pccbb_pcmcia_io_unmap, 244 pccbb_pcmcia_intr_establish, 245 pccbb_pcmcia_intr_disestablish, 246 pccbb_pcmcia_socket_enable, 247 pccbb_pcmcia_socket_disable, 248 pccbb_pcmcia_socket_settype, 249 pccbb_pcmcia_card_detect 250 }; 251 252 #if rbus 253 static struct cardbus_functions pccbb_funcs = { 254 pccbb_rbus_cb_space_alloc, 255 pccbb_rbus_cb_space_free, 256 pccbb_cb_intr_establish, 257 pccbb_cb_intr_disestablish, 258 pccbb_ctrl, 259 pccbb_power, 260 pccbb_make_tag, 261 pccbb_free_tag, 262 pccbb_conf_read, 263 pccbb_conf_write, 264 }; 265 #else 266 static struct cardbus_functions pccbb_funcs = { 267 pccbb_ctrl, 268 pccbb_power, 269 pccbb_mem_open, 270 pccbb_mem_close, 271 pccbb_io_open, 272 pccbb_io_close, 273 pccbb_cb_intr_establish, 274 pccbb_cb_intr_disestablish, 275 pccbb_make_tag, 276 pccbb_conf_read, 277 pccbb_conf_write, 278 }; 279 #endif 280 281 int 282 pcicbbmatch(parent, match, aux) 283 struct device *parent; 284 struct cfdata *match; 285 void *aux; 286 { 287 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 288 289 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 290 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 291 PCI_INTERFACE(pa->pa_class) == 0) { 292 return 1; 293 } 294 295 return 0; 296 } 297 298 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 299 | ((prod) << PCI_PRODUCT_SHIFT)) 300 301 const struct yenta_chipinfo { 302 pcireg_t yc_id; /* vendor tag | product tag */ 303 int yc_chiptype; 304 int yc_flags; 305 } yc_chipsets[] = { 306 /* Texas Instruments chips */ 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 332 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 334 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 336 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 338 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 339 340 /* Ricoh chips */ 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 344 PCCBB_PCMCIA_MEM_32}, 345 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 346 PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 348 PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 350 PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 352 PCCBB_PCMCIA_MEM_32}, 353 354 /* Toshiba products */ 355 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 356 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 358 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 360 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 361 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 362 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 363 364 /* Cirrus Logic products */ 365 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 366 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 367 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 368 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 369 370 /* sentinel, or Generic chip */ 371 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 372 }; 373 374 static int 375 cb_chipset(pci_id, flagp) 376 u_int32_t pci_id; 377 int *flagp; 378 { 379 const struct yenta_chipinfo *yc; 380 381 /* Loop over except the last default entry. */ 382 for (yc = yc_chipsets; yc < yc_chipsets + 383 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 384 if (pci_id == yc->yc_id) 385 break; 386 387 if (flagp != NULL) 388 *flagp = yc->yc_flags; 389 390 return (yc->yc_chiptype); 391 } 392 393 static void 394 pccbb_shutdown(void *arg) 395 { 396 struct pccbb_softc *sc = arg; 397 pcireg_t command; 398 399 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 400 401 /* 402 * turn off power 403 * 404 * XXX - do not turn off power if chipset is TI 113X because 405 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 406 */ 407 if (sc->sc_chipset != CB_TI113X) { 408 pccbb_power((cardbus_chipset_tag_t)sc, 409 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 410 } 411 412 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 413 0); 414 415 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 416 417 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 418 PCI_COMMAND_MASTER_ENABLE); 419 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 420 421 } 422 423 void 424 pccbbattach(parent, self, aux) 425 struct device *parent; 426 struct device *self; 427 void *aux; 428 { 429 struct pccbb_softc *sc = (void *)self; 430 struct pci_attach_args *pa = aux; 431 pci_chipset_tag_t pc = pa->pa_pc; 432 pcireg_t busreg, reg, sock_base; 433 bus_addr_t sockbase; 434 char devinfo[256]; 435 int flags; 436 int pwrmgt_offs; 437 438 #ifdef __HAVE_PCCBB_ATTACH_HOOK 439 pccbb_attach_hook(parent, self, pa); 440 #endif 441 442 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 443 444 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 445 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 446 #ifdef CBB_DEBUG 447 printf(" (chipflags %x)", flags); 448 #endif 449 printf("\n"); 450 451 TAILQ_INIT(&sc->sc_memwindow); 452 TAILQ_INIT(&sc->sc_iowindow); 453 454 #if rbus 455 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 456 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 457 458 #if 0 459 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 460 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 461 #endif 462 #endif /* rbus */ 463 464 sc->sc_flags &= ~CBB_MEMHMAPPED; 465 466 /* power management: set D0 state */ 467 sc->sc_pwrmgt_offs = 0; 468 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 469 &pwrmgt_offs, 0)) { 470 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 471 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 472 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 473 reg &= ~PCI_PMCSR_STATE_MASK; 474 reg |= PCI_PMCSR_STATE_D0; 475 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 476 pci_conf_write(pc, pa->pa_tag, 477 pwrmgt_offs + PCI_PMCSR, reg); 478 } 479 480 sc->sc_pwrmgt_offs = pwrmgt_offs; 481 } 482 483 /* 484 * MAP socket registers and ExCA registers on memory-space 485 * When no valid address is set on socket base registers (on pci 486 * config space), get it not polite way. 487 */ 488 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 489 490 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 491 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 492 /* The address must be valid. */ 493 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 494 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 495 printf("%s: can't map socket base address 0x%lx\n", 496 sc->sc_dev.dv_xname, (unsigned long)sock_base); 497 /* 498 * I think it's funny: socket base registers must be 499 * mapped on memory space, but ... 500 */ 501 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 502 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 503 NULL)) { 504 printf("%s: can't map socket base address" 505 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 506 (unsigned long)sockbase); 507 /* give up... allocate reg space via rbus. */ 508 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 509 } else 510 sc->sc_flags |= CBB_MEMHMAPPED; 511 } else { 512 DPRINTF(("%s: socket base address 0x%lx\n", 513 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 514 sc->sc_flags |= CBB_MEMHMAPPED; 515 } 516 } 517 518 sc->sc_mem_start = 0; /* XXX */ 519 sc->sc_mem_end = 0xffffffff; /* XXX */ 520 521 /* 522 * When interrupt isn't routed correctly, give up probing cbb and do 523 * not kill pcic-compatible port. 524 */ 525 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 526 printf("%s: NOT USED because of unconfigured interrupt\n", 527 sc->sc_dev.dv_xname); 528 return; 529 } 530 531 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 532 533 /* pccbb_machdep.c end */ 534 535 #if defined CBB_DEBUG 536 { 537 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 538 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 539 intrname[pa->pa_intrpin], pa->pa_intrline); 540 } 541 #endif 542 543 /* setup softc */ 544 sc->sc_pc = pc; 545 sc->sc_iot = pa->pa_iot; 546 sc->sc_memt = pa->pa_memt; 547 sc->sc_dmat = pa->pa_dmat; 548 sc->sc_tag = pa->pa_tag; 549 sc->sc_function = pa->pa_function; 550 sc->sc_sockbase = sock_base; 551 sc->sc_busnum = busreg; 552 553 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 554 555 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 556 557 shutdownhook_establish(pccbb_shutdown, sc); 558 559 /* Disable legacy register mapping. */ 560 switch (sc->sc_chipset) { 561 case CB_RX5C46X: /* fallthrough */ 562 #if 0 563 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 564 case CB_RX5C47X: 565 #endif 566 /* 567 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 568 * cannot be disabled by substituting 0 into PCI_LEGACY 569 * register. Ricoh CardBus bridges have special bits on Bridge 570 * control reg (addr 0x3e on PCI config space). 571 */ 572 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 573 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 574 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 575 break; 576 577 default: 578 /* XXX I don't know proper way to kill legacy I/O. */ 579 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 580 break; 581 } 582 583 config_defer(self, pccbb_pci_callback); 584 } 585 586 587 588 589 /* 590 * static void pccbb_pci_callback(struct device *self) 591 * 592 * The actual attach routine: get memory space for YENTA register 593 * space, setup YENTA register and route interrupt. 594 * 595 * This function should be deferred because this device may obtain 596 * memory space dynamically. This function must avoid obtaining 597 * memory area which has already kept for another device. 598 */ 599 static void 600 pccbb_pci_callback(self) 601 struct device *self; 602 { 603 struct pccbb_softc *sc = (void *)self; 604 pci_chipset_tag_t pc = sc->sc_pc; 605 pci_intr_handle_t ih; 606 const char *intrstr = NULL; 607 bus_addr_t sockbase; 608 struct cbslot_attach_args cba; 609 struct pcmciabus_attach_args paa; 610 struct cardslot_attach_args caa; 611 struct cardslot_softc *csc; 612 613 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 614 /* The socket registers aren't mapped correctly. */ 615 #if rbus 616 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 617 (sc->sc_chipset == CB_RX5C47X 618 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 619 0, &sockbase, &sc->sc_base_memh)) { 620 return; 621 } 622 sc->sc_base_memt = sc->sc_memt; 623 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 624 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 625 sc->sc_dev.dv_xname, (unsigned long)sockbase, 626 (unsigned long)pci_conf_read(pc, sc->sc_tag, 627 PCI_SOCKBASE))); 628 #else 629 sc->sc_base_memt = sc->sc_memt; 630 #if !defined CBB_PCI_BASE 631 #define CBB_PCI_BASE 0x20000000 632 #endif 633 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 634 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 635 /* cannot allocate memory space */ 636 return; 637 } 638 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 639 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 640 sc->sc_dev.dv_xname, (unsigned long)sock_base, 641 (unsigned long)pci_conf_read(pc, 642 sc->sc_tag, PCI_SOCKBASE))); 643 sc->sc_sockbase = sockbase; 644 #endif 645 sc->sc_flags |= CBB_MEMHMAPPED; 646 } 647 648 /* bus bridge initialization */ 649 pccbb_chipinit(sc); 650 651 /* clear data structure for child device interrupt handlers */ 652 LIST_INIT(&sc->sc_pil); 653 sc->sc_pil_intr_enable = 1; 654 655 /* Map and establish the interrupt. */ 656 if (pci_intr_map(&sc->sc_pa, &ih)) { 657 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 658 return; 659 } 660 intrstr = pci_intr_string(pc, ih); 661 662 /* 663 * XXX pccbbintr should be called under the priority lower 664 * than any other hard interrputs. 665 */ 666 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 667 668 if (sc->sc_ih == NULL) { 669 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 670 if (intrstr != NULL) { 671 printf(" at %s", intrstr); 672 } 673 printf("\n"); 674 return; 675 } 676 677 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 678 powerhook_establish(pccbb_powerhook, sc); 679 680 { 681 u_int32_t sockstat; 682 683 sockstat = bus_space_read_4(sc->sc_base_memt, 684 sc->sc_base_memh, CB_SOCKET_STAT); 685 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 686 sc->sc_flags |= CBB_CARDEXIST; 687 } 688 } 689 690 /* 691 * attach cardbus 692 */ 693 { 694 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 695 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 696 697 /* initialize cbslot_attach */ 698 cba.cba_busname = "cardbus"; 699 cba.cba_iot = sc->sc_iot; 700 cba.cba_memt = sc->sc_memt; 701 cba.cba_dmat = sc->sc_dmat; 702 cba.cba_bus = (busreg >> 8) & 0x0ff; 703 cba.cba_cc = (void *)sc; 704 cba.cba_cf = &pccbb_funcs; 705 cba.cba_intrline = sc->sc_pa.pa_intrline; 706 707 #if rbus 708 cba.cba_rbus_iot = sc->sc_rbus_iot; 709 cba.cba_rbus_memt = sc->sc_rbus_memt; 710 #endif 711 712 cba.cba_cacheline = PCI_CACHELINE(bhlc); 713 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 714 715 if (bootverbose) { 716 printf("%s: cacheline 0x%x lattimer 0x%x\n", 717 sc->sc_dev.dv_xname, cba.cba_cacheline, 718 cba.cba_lattimer); 719 printf("%s: bhlc 0x%x lscp 0x%x\n", 720 sc->sc_dev.dv_xname, bhlc, busreg); 721 } 722 #if defined SHOW_REGS 723 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 724 sc->sc_base_memh); 725 #endif 726 } 727 728 pccbb_pcmcia_attach_setup(sc, &paa); 729 caa.caa_cb_attach = NULL; 730 if (cba.cba_bus == 0) 731 printf("%s: secondary bus number uninitialized; try PCIBIOS_BUS_FIXUP\n", sc->sc_dev.dv_xname); 732 else 733 caa.caa_cb_attach = &cba; 734 caa.caa_16_attach = &paa; 735 caa.caa_ph = &sc->sc_pcmcia_h; 736 737 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 738 DPRINTF(("pccbbattach: found cardslot\n")); 739 sc->sc_csc = csc; 740 } 741 742 return; 743 } 744 745 746 747 748 749 /* 750 * static void pccbb_chipinit(struct pccbb_softc *sc) 751 * 752 * This function initialize YENTA chip registers listed below: 753 * 1) PCI command reg, 754 * 2) PCI and CardBus latency timer, 755 * 3) route PCI interrupt, 756 * 4) close all memory and io windows. 757 * 5) turn off bus power. 758 * 6) card detect interrupt on. 759 * 7) clear interrupt 760 */ 761 static void 762 pccbb_chipinit(sc) 763 struct pccbb_softc *sc; 764 { 765 pci_chipset_tag_t pc = sc->sc_pc; 766 pcitag_t tag = sc->sc_tag; 767 bus_space_tag_t bmt = sc->sc_base_memt; 768 bus_space_handle_t bmh = sc->sc_base_memh; 769 pcireg_t reg; 770 771 /* 772 * Set PCI command reg. 773 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 774 */ 775 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 776 /* I believe it is harmless. */ 777 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 778 PCI_COMMAND_MASTER_ENABLE); 779 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 780 781 /* 782 * Set CardBus latency timer. 783 */ 784 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 785 if (PCI_CB_LATENCY(reg) < 0x20) { 786 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 787 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 788 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 789 } 790 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 791 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 792 793 /* 794 * Set PCI latency timer. 795 */ 796 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 797 if (PCI_LATTIMER(reg) < 0x10) { 798 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 799 reg |= (0x10 << PCI_LATTIMER_SHIFT); 800 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 801 } 802 DPRINTF(("PCI latency timer 0x%x (%x)\n", 803 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 804 805 806 /* Route functional interrupts to PCI. */ 807 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 808 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 809 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 810 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 811 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 812 813 switch (sc->sc_chipset) { 814 case CB_TI113X: 815 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 816 /* This bit is shared, but may read as 0 on some chips, so set 817 it explicitly on both functions. */ 818 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 819 /* CSC intr enable */ 820 reg |= PCI113X_CBCTRL_PCI_CSC; 821 /* functional intr prohibit | prohibit ISA routing */ 822 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 823 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 824 break; 825 826 case CB_TI12XX: 827 /* 828 * Some TI 12xx (and [14][45]xx) based pci cards 829 * sometimes have issues with the MFUNC register not 830 * being initialized due to a bad EEPROM on board. 831 * Laptops that this matters on have this register 832 * properly initialized. 833 * 834 * The TI125X parts have a different register. 835 */ 836 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 837 if (reg == 0) { 838 reg &= ~PCI12XX_MFUNC_PIN0; 839 reg |= PCI12XX_MFUNC_PIN0_INTA; 840 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 841 PCI12XX_SYSCTRL_INTRTIE) == 0) { 842 reg &= ~PCI12XX_MFUNC_PIN1; 843 reg |= PCI12XX_MFUNC_PIN1_INTB; 844 } 845 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 846 } 847 /* fallthrough */ 848 849 case CB_TI125X: 850 /* 851 * Disable zoom video. Some machines initialize this 852 * improperly and experience has shown that this helps 853 * prevent strange behavior. 854 */ 855 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 856 857 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 858 reg |= PCI12XX_SYSCTRL_VCCPROT; 859 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 860 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 861 reg |= PCI12XX_CBCTRL_CSC; 862 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 863 break; 864 865 case CB_TOPIC95B: 866 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 867 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 868 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 869 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 870 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 871 sc->sc_dev.dv_xname, reg)); 872 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 873 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 874 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 875 DPRINTF(("0x%x\n", reg)); 876 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 877 break; 878 879 case CB_TOPIC97: 880 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 881 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 882 sc->sc_dev.dv_xname, reg)); 883 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 884 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 885 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 886 reg |= TOPIC97_SLOT_CTRL_PCIINT; 887 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 888 DPRINTF(("0x%x\n", reg)); 889 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 890 /* make sure to assert LV card support bits */ 891 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 892 0x800 + 0x3e, 893 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 894 0x800 + 0x3e) | 0x03); 895 break; 896 } 897 898 /* Close all memory and I/O windows. */ 899 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 900 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 901 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 902 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 903 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 904 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 905 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 906 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 907 908 /* reset 16-bit pcmcia bus */ 909 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 910 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 911 912 /* turn off power */ 913 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 914 915 /* CSC Interrupt: Card detect interrupt on */ 916 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 917 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 918 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 919 /* reset interrupt */ 920 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 921 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 922 } 923 924 925 926 927 /* 928 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 929 * struct pcmciabus_attach_args *paa) 930 * 931 * This function attaches 16-bit PCcard bus. 932 */ 933 STATIC void 934 pccbb_pcmcia_attach_setup(sc, paa) 935 struct pccbb_softc *sc; 936 struct pcmciabus_attach_args *paa; 937 { 938 struct pcic_handle *ph = &sc->sc_pcmcia_h; 939 #if rbus 940 rbus_tag_t rb; 941 #endif 942 943 /* initialize pcmcia part in pccbb_softc */ 944 ph->ph_parent = (struct device *)sc; 945 ph->sock = sc->sc_function; 946 ph->flags = 0; 947 ph->shutdown = 0; 948 ph->ih_irq = sc->sc_pa.pa_intrline; 949 ph->ph_bus_t = sc->sc_base_memt; 950 ph->ph_bus_h = sc->sc_base_memh; 951 ph->ph_read = pccbb_pcmcia_read; 952 ph->ph_write = pccbb_pcmcia_write; 953 sc->sc_pct = &pccbb_pcmcia_funcs; 954 955 /* 956 * We need to do a few things here: 957 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 958 * setting the IRQ numbers to 0. 959 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 960 * routing of CSC interrupts (e.g. card removal) to PCI while in 961 * PCMCIA mode. We just leave this set all the time. 962 * 3) Enable card insertion/removal interrupts in case the chip also 963 * needs that while in PCMCIA mode. 964 * 4) Clear any pending CSC interrupt. 965 */ 966 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 967 if (sc->sc_chipset == CB_TI113X) { 968 Pcic_write(ph, PCIC_CSC_INTR, 0); 969 } else { 970 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 971 Pcic_read(ph, PCIC_CSC); 972 } 973 974 /* initialize pcmcia bus attachment */ 975 paa->paa_busname = "pcmcia"; 976 paa->pct = sc->sc_pct; 977 paa->pch = ph; 978 paa->iobase = 0; /* I don't use them */ 979 paa->iosize = 0; 980 #if rbus 981 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 982 paa->iobase = rb->rb_start + rb->rb_offset; 983 paa->iosize = rb->rb_end - rb->rb_start; 984 #endif 985 986 return; 987 } 988 989 #if 0 990 STATIC void 991 pccbb_pcmcia_attach_card(ph) 992 struct pcic_handle *ph; 993 { 994 if (ph->flags & PCIC_FLAG_CARDP) { 995 panic("pccbb_pcmcia_attach_card: already attached"); 996 } 997 998 /* call the MI attach function */ 999 pcmcia_card_attach(ph->pcmcia); 1000 1001 ph->flags |= PCIC_FLAG_CARDP; 1002 } 1003 1004 STATIC void 1005 pccbb_pcmcia_detach_card(ph, flags) 1006 struct pcic_handle *ph; 1007 int flags; 1008 { 1009 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1010 panic("pccbb_pcmcia_detach_card: already detached"); 1011 } 1012 1013 ph->flags &= ~PCIC_FLAG_CARDP; 1014 1015 /* call the MI detach function */ 1016 pcmcia_card_detach(ph->pcmcia, flags); 1017 } 1018 #endif 1019 1020 /* 1021 * int pccbbintr(arg) 1022 * void *arg; 1023 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1024 * itself. 1025 */ 1026 int 1027 pccbbintr(arg) 1028 void *arg; 1029 { 1030 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1031 u_int32_t sockevent, sockstate; 1032 bus_space_tag_t memt = sc->sc_base_memt; 1033 bus_space_handle_t memh = sc->sc_base_memh; 1034 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1035 1036 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1037 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1038 Pcic_read(ph, PCIC_CSC); 1039 1040 if (sockevent == 0) { 1041 /* This intr is not for me: it may be for my child devices. */ 1042 if (sc->sc_pil_intr_enable) { 1043 return pccbbintr_function(sc); 1044 } else { 1045 return 0; 1046 } 1047 } 1048 1049 if (sockevent & CB_SOCKET_EVENT_CD) { 1050 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1051 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1052 /* A card should be removed. */ 1053 if (sc->sc_flags & CBB_CARDEXIST) { 1054 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1055 sockevent)); 1056 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1057 sc->sc_flags &= ~CBB_CARDEXIST; 1058 if (sc->sc_csc->sc_status & 1059 CARDSLOT_STATUS_CARD_16) { 1060 #if 0 1061 struct pcic_handle *ph = 1062 &sc->sc_pcmcia_h; 1063 1064 pcmcia_card_deactivate(ph->pcmcia); 1065 pccbb_pcmcia_socket_disable(ph); 1066 pccbb_pcmcia_detach_card(ph, 1067 DETACH_FORCE); 1068 #endif 1069 cardslot_event_throw(sc->sc_csc, 1070 CARDSLOT_EVENT_REMOVAL_16); 1071 } else if (sc->sc_csc->sc_status & 1072 CARDSLOT_STATUS_CARD_CB) { 1073 /* Cardbus intr removed */ 1074 cardslot_event_throw(sc->sc_csc, 1075 CARDSLOT_EVENT_REMOVAL_CB); 1076 } 1077 } else if (sc->sc_flags & CBB_INSERTING) { 1078 sc->sc_flags &= ~CBB_INSERTING; 1079 callout_stop(&sc->sc_insert_ch); 1080 } 1081 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1082 /* 1083 * The pccbbintr may called from powerdown hook when 1084 * the system resumed, to detect the card 1085 * insertion/removal during suspension. 1086 */ 1087 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1088 if (sc->sc_flags & CBB_INSERTING) { 1089 callout_stop(&sc->sc_insert_ch); 1090 } 1091 callout_reset(&sc->sc_insert_ch, hz / 5, 1092 pci113x_insert, sc); 1093 sc->sc_flags |= CBB_INSERTING; 1094 } 1095 } 1096 1097 return (1); 1098 } 1099 1100 /* 1101 * static int pccbbintr_function(struct pccbb_softc *sc) 1102 * 1103 * This function calls each interrupt handler registered at the 1104 * bridge. The interrupt handlers are called in registered order. 1105 */ 1106 static int 1107 pccbbintr_function(sc) 1108 struct pccbb_softc *sc; 1109 { 1110 int retval = 0, val; 1111 struct pccbb_intrhand_list *pil; 1112 int s, splchanged; 1113 1114 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1115 pil = LIST_NEXT(pil, pil_next)) { 1116 /* 1117 * XXX priority change. gross. I use if-else 1118 * sentense instead of switch-case sentense because of 1119 * avoiding duplicate case value error. More than one 1120 * IPL_XXX use same value. It depends on 1121 * implimentation. 1122 */ 1123 splchanged = 1; 1124 if (pil->pil_level == IPL_SERIAL) { 1125 s = splserial(); 1126 } else if (pil->pil_level == IPL_HIGH) { 1127 s = splhigh(); 1128 } else if (pil->pil_level == IPL_CLOCK) { 1129 s = splclock(); 1130 } else if (pil->pil_level == IPL_AUDIO) { 1131 s = splaudio(); 1132 } else if (pil->pil_level == IPL_VM) { 1133 s = splvm(); 1134 } else if (pil->pil_level == IPL_TTY) { 1135 s = spltty(); 1136 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1137 s = splsoftserial(); 1138 } else if (pil->pil_level == IPL_NET) { 1139 s = splnet(); 1140 } else { 1141 s = 0; /* XXX: gcc */ 1142 splchanged = 0; 1143 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1144 } 1145 1146 val = (*pil->pil_func)(pil->pil_arg); 1147 1148 if (splchanged != 0) { 1149 splx(s); 1150 } 1151 1152 retval = retval == 1 ? 1 : 1153 retval == 0 ? val : val != 0 ? val : retval; 1154 } 1155 1156 return retval; 1157 } 1158 1159 static void 1160 pci113x_insert(arg) 1161 void *arg; 1162 { 1163 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1164 u_int32_t sockevent, sockstate; 1165 1166 if (!(sc->sc_flags & CBB_INSERTING)) { 1167 /* We add a card only under inserting state. */ 1168 return; 1169 } 1170 sc->sc_flags &= ~CBB_INSERTING; 1171 1172 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1173 CB_SOCKET_EVENT); 1174 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1175 CB_SOCKET_STAT); 1176 1177 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1178 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1179 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1180 sc->sc_flags |= CBB_CARDEXIST; 1181 /* call pccard interrupt handler here */ 1182 if (sockstate & CB_SOCKET_STAT_16BIT) { 1183 /* 16-bit card found */ 1184 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1185 cardslot_event_throw(sc->sc_csc, 1186 CARDSLOT_EVENT_INSERTION_16); 1187 } else if (sockstate & CB_SOCKET_STAT_CB) { 1188 /* cardbus card found */ 1189 /* cardbus_attach_card(sc->sc_csc); */ 1190 cardslot_event_throw(sc->sc_csc, 1191 CARDSLOT_EVENT_INSERTION_CB); 1192 } else { 1193 /* who are you? */ 1194 } 1195 } else { 1196 callout_reset(&sc->sc_insert_ch, hz / 10, 1197 pci113x_insert, sc); 1198 } 1199 } 1200 1201 #define PCCBB_PCMCIA_OFFSET 0x800 1202 static u_int8_t 1203 pccbb_pcmcia_read(ph, reg) 1204 struct pcic_handle *ph; 1205 int reg; 1206 { 1207 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1208 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1209 1210 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1211 PCCBB_PCMCIA_OFFSET + reg); 1212 } 1213 1214 static void 1215 pccbb_pcmcia_write(ph, reg, val) 1216 struct pcic_handle *ph; 1217 int reg; 1218 u_int8_t val; 1219 { 1220 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1221 val); 1222 1223 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1224 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1225 } 1226 1227 /* 1228 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1229 */ 1230 STATIC int 1231 pccbb_ctrl(ct, command) 1232 cardbus_chipset_tag_t ct; 1233 int command; 1234 { 1235 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1236 1237 switch (command) { 1238 case CARDBUS_CD: 1239 if (2 == pccbb_detect_card(sc)) { 1240 int retval = 0; 1241 int status = cb_detect_voltage(sc); 1242 if (PCCARD_VCC_5V & status) { 1243 retval |= CARDBUS_5V_CARD; 1244 } 1245 if (PCCARD_VCC_3V & status) { 1246 retval |= CARDBUS_3V_CARD; 1247 } 1248 if (PCCARD_VCC_XV & status) { 1249 retval |= CARDBUS_XV_CARD; 1250 } 1251 if (PCCARD_VCC_YV & status) { 1252 retval |= CARDBUS_YV_CARD; 1253 } 1254 return retval; 1255 } else { 1256 return 0; 1257 } 1258 case CARDBUS_RESET: 1259 return cb_reset(sc); 1260 case CARDBUS_IO_ENABLE: /* fallthrough */ 1261 case CARDBUS_IO_DISABLE: /* fallthrough */ 1262 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1263 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1264 case CARDBUS_BM_ENABLE: /* fallthrough */ 1265 case CARDBUS_BM_DISABLE: /* fallthrough */ 1266 /* XXX: I think we don't need to call this function below. */ 1267 return pccbb_cardenable(sc, command); 1268 } 1269 1270 return 0; 1271 } 1272 1273 /* 1274 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1275 * This function returns true when it succeeds and returns false when 1276 * it fails. 1277 */ 1278 STATIC int 1279 pccbb_power(ct, command) 1280 cardbus_chipset_tag_t ct; 1281 int command; 1282 { 1283 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1284 1285 u_int32_t status, sock_ctrl, reg_ctrl; 1286 bus_space_tag_t memt = sc->sc_base_memt; 1287 bus_space_handle_t memh = sc->sc_base_memh; 1288 1289 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1290 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1291 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1292 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1293 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1294 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1295 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1296 "UNKNOWN", 1297 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1298 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1299 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1300 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1301 "UNKNOWN", command)); 1302 1303 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1304 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1305 #if 0 1306 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, 0); 1307 #endif 1308 1309 switch (command & CARDBUS_VCCMASK) { 1310 case CARDBUS_VCC_UC: 1311 break; 1312 case CARDBUS_VCC_5V: 1313 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1314 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1315 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1316 } else { 1317 printf("%s: BAD voltage request: no 5 V card\n", 1318 sc->sc_dev.dv_xname); 1319 return 0; 1320 } 1321 break; 1322 case CARDBUS_VCC_3V: 1323 if (CB_SOCKET_STAT_3VCARD & status) { 1324 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1325 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1326 } else { 1327 printf("%s: BAD voltage request: no 3.3 V card\n", 1328 sc->sc_dev.dv_xname); 1329 return 0; 1330 } 1331 break; 1332 case CARDBUS_VCC_0V: 1333 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1334 break; 1335 default: 1336 return 0; /* power NEVER changed */ 1337 } 1338 1339 switch (command & CARDBUS_VPPMASK) { 1340 case CARDBUS_VPP_UC: 1341 break; 1342 case CARDBUS_VPP_0V: 1343 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1344 break; 1345 case CARDBUS_VPP_VCC: 1346 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1347 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1348 break; 1349 case CARDBUS_VPP_12V: 1350 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1351 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1352 break; 1353 } 1354 1355 #if 0 1356 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1357 #endif 1358 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1359 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1360 1361 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1362 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1363 sc->sc_dev.dv_xname, sock_ctrl, status); 1364 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1365 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1366 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1367 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1368 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, 1369 CB_SOCKET_FORCE_BADVCC); 1370 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1371 CB_SOCKET_STAT)); 1372 return 0; 1373 } 1374 1375 if (sc->sc_chipset == CB_TOPIC97) { 1376 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1377 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1378 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1379 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1380 else 1381 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1382 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1383 } 1384 1385 #if 0 1386 /* 1387 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1388 * time is 20 ms, some PC-Card bridge requires longer duration. 1389 */ 1390 #if 0 /* XXX called on interrupt context */ 1391 DELAY_MS(300, sc); 1392 #else 1393 delay(300 * 1000); 1394 #endif 1395 #endif 1396 1397 return 1; /* power changed correctly */ 1398 } 1399 1400 #if defined CB_PCMCIA_POLL 1401 struct cb_poll_str { 1402 void *arg; 1403 int (*func) __P((void *)); 1404 int level; 1405 pccard_chipset_tag_t ct; 1406 int count; 1407 struct callout poll_ch; 1408 }; 1409 1410 static struct cb_poll_str cb_poll[10]; 1411 static int cb_poll_n = 0; 1412 1413 static void cb_pcmcia_poll __P((void *arg)); 1414 1415 static void 1416 cb_pcmcia_poll(arg) 1417 void *arg; 1418 { 1419 struct cb_poll_str *poll = arg; 1420 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1421 struct pccbb_softc *sc = psc->cpc_parent; 1422 int s; 1423 u_int32_t spsr; /* socket present-state reg */ 1424 1425 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1426 switch (poll->level) { 1427 case IPL_NET: 1428 s = splnet(); 1429 break; 1430 case IPL_BIO: 1431 s = splbio(); 1432 break; 1433 case IPL_TTY: /* fallthrough */ 1434 default: 1435 s = spltty(); 1436 break; 1437 } 1438 1439 spsr = 1440 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1441 CB_SOCKET_STAT); 1442 1443 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1444 if (!(spsr & 0x40)) { /* CINT low */ 1445 #else 1446 if (1) { 1447 #endif 1448 if ((*poll->func) (poll->arg) == 1) { 1449 ++poll->count; 1450 printf("intr: reported from poller, 0x%x\n", spsr); 1451 #if defined LEVEL2 1452 } else { 1453 printf("intr: miss! 0x%x\n", spsr); 1454 #endif 1455 } 1456 } 1457 splx(s); 1458 } 1459 #endif /* defined CB_PCMCIA_POLL */ 1460 1461 /* 1462 * static int pccbb_detect_card(struct pccbb_softc *sc) 1463 * return value: 0 if no card exists. 1464 * 1 if 16-bit card exists. 1465 * 2 if cardbus card exists. 1466 */ 1467 static int 1468 pccbb_detect_card(sc) 1469 struct pccbb_softc *sc; 1470 { 1471 bus_space_handle_t base_memh = sc->sc_base_memh; 1472 bus_space_tag_t base_memt = sc->sc_base_memt; 1473 u_int32_t sockstat = 1474 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1475 int retval = 0; 1476 1477 /* CD1 and CD2 asserted */ 1478 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1479 /* card must be present */ 1480 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1481 /* NOTACARD DEASSERTED */ 1482 if (CB_SOCKET_STAT_CB & sockstat) { 1483 /* CardBus mode */ 1484 retval = 2; 1485 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1486 /* 16-bit mode */ 1487 retval = 1; 1488 } 1489 } 1490 } 1491 return retval; 1492 } 1493 1494 /* 1495 * STATIC int cb_reset(struct pccbb_softc *sc) 1496 * This function resets CardBus card. 1497 */ 1498 STATIC int 1499 cb_reset(sc) 1500 struct pccbb_softc *sc; 1501 { 1502 /* 1503 * Reset Assert at least 20 ms 1504 * Some machines request longer duration. 1505 */ 1506 int reset_duration = 1507 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1508 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1509 1510 /* Reset bit Assert (bit 6 at 0x3E) */ 1511 bcr |= CB_BCR_RESET_ENABLE; 1512 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1513 DELAY_MS(reset_duration, sc); 1514 1515 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1516 /* Reset bit Deassert (bit 6 at 0x3E) */ 1517 bcr &= ~CB_BCR_RESET_ENABLE; 1518 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1519 DELAY_MS(reset_duration, sc); 1520 } 1521 /* No card found on the slot. Keep Reset. */ 1522 return 1; 1523 } 1524 1525 /* 1526 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1527 * This function detect card Voltage. 1528 */ 1529 STATIC int 1530 cb_detect_voltage(sc) 1531 struct pccbb_softc *sc; 1532 { 1533 u_int32_t psr; /* socket present-state reg */ 1534 bus_space_tag_t iot = sc->sc_base_memt; 1535 bus_space_handle_t ioh = sc->sc_base_memh; 1536 int vol = PCCARD_VCC_UKN; /* set 0 */ 1537 1538 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1539 1540 if (0x400u & psr) { 1541 vol |= PCCARD_VCC_5V; 1542 } 1543 if (0x800u & psr) { 1544 vol |= PCCARD_VCC_3V; 1545 } 1546 1547 return vol; 1548 } 1549 1550 STATIC int 1551 cbbprint(aux, pcic) 1552 void *aux; 1553 const char *pcic; 1554 { 1555 /* 1556 struct cbslot_attach_args *cba = aux; 1557 1558 if (cba->cba_slot >= 0) { 1559 aprint_normal(" slot %d", cba->cba_slot); 1560 } 1561 */ 1562 return UNCONF; 1563 } 1564 1565 /* 1566 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1567 * This function enables and disables the card 1568 */ 1569 STATIC int 1570 pccbb_cardenable(sc, function) 1571 struct pccbb_softc *sc; 1572 int function; 1573 { 1574 u_int32_t command = 1575 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1576 1577 DPRINTF(("pccbb_cardenable:")); 1578 switch (function) { 1579 case CARDBUS_IO_ENABLE: 1580 command |= PCI_COMMAND_IO_ENABLE; 1581 break; 1582 case CARDBUS_IO_DISABLE: 1583 command &= ~PCI_COMMAND_IO_ENABLE; 1584 break; 1585 case CARDBUS_MEM_ENABLE: 1586 command |= PCI_COMMAND_MEM_ENABLE; 1587 break; 1588 case CARDBUS_MEM_DISABLE: 1589 command &= ~PCI_COMMAND_MEM_ENABLE; 1590 break; 1591 case CARDBUS_BM_ENABLE: 1592 command |= PCI_COMMAND_MASTER_ENABLE; 1593 break; 1594 case CARDBUS_BM_DISABLE: 1595 command &= ~PCI_COMMAND_MASTER_ENABLE; 1596 break; 1597 default: 1598 return 0; 1599 } 1600 1601 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1602 DPRINTF((" command reg 0x%x\n", command)); 1603 return 1; 1604 } 1605 1606 #if !rbus 1607 /* 1608 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1609 */ 1610 static int 1611 pccbb_io_open(ct, win, start, end) 1612 cardbus_chipset_tag_t ct; 1613 int win; 1614 u_int32_t start, end; 1615 { 1616 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1617 int basereg; 1618 int limitreg; 1619 1620 if ((win < 0) || (win > 2)) { 1621 #if defined DIAGNOSTIC 1622 printf("cardbus_io_open: window out of range %d\n", win); 1623 #endif 1624 return 0; 1625 } 1626 1627 basereg = win * 8 + 0x2c; 1628 limitreg = win * 8 + 0x30; 1629 1630 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1631 start, basereg, end, limitreg)); 1632 1633 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1634 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1635 return 1; 1636 } 1637 1638 /* 1639 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1640 */ 1641 static int 1642 pccbb_io_close(ct, win) 1643 cardbus_chipset_tag_t ct; 1644 int win; 1645 { 1646 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1647 int basereg; 1648 int limitreg; 1649 1650 if ((win < 0) || (win > 2)) { 1651 #if defined DIAGNOSTIC 1652 printf("cardbus_io_close: window out of range %d\n", win); 1653 #endif 1654 return 0; 1655 } 1656 1657 basereg = win * 8 + 0x2c; 1658 limitreg = win * 8 + 0x30; 1659 1660 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1661 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1662 return 1; 1663 } 1664 1665 /* 1666 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1667 */ 1668 static int 1669 pccbb_mem_open(ct, win, start, end) 1670 cardbus_chipset_tag_t ct; 1671 int win; 1672 u_int32_t start, end; 1673 { 1674 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1675 int basereg; 1676 int limitreg; 1677 1678 if ((win < 0) || (win > 2)) { 1679 #if defined DIAGNOSTIC 1680 printf("cardbus_mem_open: window out of range %d\n", win); 1681 #endif 1682 return 0; 1683 } 1684 1685 basereg = win * 8 + 0x1c; 1686 limitreg = win * 8 + 0x20; 1687 1688 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1689 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1690 return 1; 1691 } 1692 1693 /* 1694 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1695 */ 1696 static int 1697 pccbb_mem_close(ct, win) 1698 cardbus_chipset_tag_t ct; 1699 int win; 1700 { 1701 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1702 int basereg; 1703 int limitreg; 1704 1705 if ((win < 0) || (win > 2)) { 1706 #if defined DIAGNOSTIC 1707 printf("cardbus_mem_close: window out of range %d\n", win); 1708 #endif 1709 return 0; 1710 } 1711 1712 basereg = win * 8 + 0x1c; 1713 limitreg = win * 8 + 0x20; 1714 1715 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1716 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1717 return 1; 1718 } 1719 #endif 1720 1721 /* 1722 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1723 * int irq, 1724 * int level, 1725 * int (* func) __P((void *)), 1726 * void *arg) 1727 * 1728 * This function registers an interrupt handler at the bridge, in 1729 * order not to call the interrupt handlers of child devices when 1730 * a card-deletion interrupt occurs. 1731 * 1732 * The arguments irq and level are not used. 1733 */ 1734 static void * 1735 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1736 cardbus_chipset_tag_t ct; 1737 int irq, level; 1738 int (*func) __P((void *)); 1739 void *arg; 1740 { 1741 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1742 1743 return pccbb_intr_establish(sc, irq, level, func, arg); 1744 } 1745 1746 1747 /* 1748 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1749 * void *ih) 1750 * 1751 * This function removes an interrupt handler pointed by ih. 1752 */ 1753 static void 1754 pccbb_cb_intr_disestablish(ct, ih) 1755 cardbus_chipset_tag_t ct; 1756 void *ih; 1757 { 1758 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1759 1760 pccbb_intr_disestablish(sc, ih); 1761 } 1762 1763 1764 void 1765 pccbb_intr_route(sc) 1766 struct pccbb_softc *sc; 1767 { 1768 pcireg_t reg; 1769 1770 /* initialize bridge intr routing */ 1771 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1772 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1773 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1774 1775 switch (sc->sc_chipset) { 1776 case CB_TI113X: 1777 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1778 /* functional intr enabled */ 1779 reg |= PCI113X_CBCTRL_PCI_INTR; 1780 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1781 break; 1782 default: 1783 break; 1784 } 1785 } 1786 1787 /* 1788 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1789 * int irq, 1790 * int level, 1791 * int (* func) __P((void *)), 1792 * void *arg) 1793 * 1794 * This function registers an interrupt handler at the bridge, in 1795 * order not to call the interrupt handlers of child devices when 1796 * a card-deletion interrupt occurs. 1797 * 1798 * The arguments irq is not used because pccbb selects intr vector. 1799 */ 1800 static void * 1801 pccbb_intr_establish(sc, irq, level, func, arg) 1802 struct pccbb_softc *sc; 1803 int irq, level; 1804 int (*func) __P((void *)); 1805 void *arg; 1806 { 1807 struct pccbb_intrhand_list *pil, *newpil; 1808 1809 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1810 1811 if (LIST_EMPTY(&sc->sc_pil)) { 1812 pccbb_intr_route(sc); 1813 } 1814 1815 /* 1816 * Allocate a room for interrupt handler structure. 1817 */ 1818 if (NULL == (newpil = 1819 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1820 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1821 return NULL; 1822 } 1823 1824 newpil->pil_func = func; 1825 newpil->pil_arg = arg; 1826 newpil->pil_level = level; 1827 1828 if (LIST_EMPTY(&sc->sc_pil)) { 1829 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1830 } else { 1831 for (pil = LIST_FIRST(&sc->sc_pil); 1832 LIST_NEXT(pil, pil_next) != NULL; 1833 pil = LIST_NEXT(pil, pil_next)); 1834 LIST_INSERT_AFTER(pil, newpil, pil_next); 1835 } 1836 1837 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1838 LIST_FIRST(&sc->sc_pil))); 1839 1840 return newpil; 1841 } 1842 1843 /* 1844 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1845 * void *ih) 1846 * 1847 * This function removes an interrupt handler pointed by ih. ih 1848 * should be the value returned by cardbus_intr_establish() or 1849 * NULL. 1850 * 1851 * When ih is NULL, this function will do nothing. 1852 */ 1853 static void 1854 pccbb_intr_disestablish(sc, ih) 1855 struct pccbb_softc *sc; 1856 void *ih; 1857 { 1858 struct pccbb_intrhand_list *pil; 1859 pcireg_t reg; 1860 1861 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1862 LIST_FIRST(&sc->sc_pil))); 1863 1864 if (ih == NULL) { 1865 /* intr handler is not set */ 1866 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1867 return; 1868 } 1869 1870 #ifdef DIAGNOSTIC 1871 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1872 pil = LIST_NEXT(pil, pil_next)) { 1873 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1874 if (pil == ih) { 1875 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1876 break; 1877 } 1878 } 1879 if (pil == NULL) { 1880 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1881 sc->sc_dev.dv_xname, ih); 1882 } 1883 #endif 1884 1885 pil = (struct pccbb_intrhand_list *)ih; 1886 LIST_REMOVE(pil, pil_next); 1887 free(pil, M_DEVBUF); 1888 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1889 1890 if (LIST_EMPTY(&sc->sc_pil)) { 1891 /* No interrupt handlers */ 1892 1893 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1894 1895 /* stop routing PCI intr */ 1896 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1897 reg |= CB_BCR_INTR_IREQ_ENABLE; 1898 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1899 1900 switch (sc->sc_chipset) { 1901 case CB_TI113X: 1902 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1903 /* functional intr disabled */ 1904 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1905 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1906 break; 1907 default: 1908 break; 1909 } 1910 } 1911 } 1912 1913 #if defined SHOW_REGS 1914 static void 1915 cb_show_regs(pc, tag, memt, memh) 1916 pci_chipset_tag_t pc; 1917 pcitag_t tag; 1918 bus_space_tag_t memt; 1919 bus_space_handle_t memh; 1920 { 1921 int i; 1922 printf("PCI config regs:"); 1923 for (i = 0; i < 0x50; i += 4) { 1924 if (i % 16 == 0) { 1925 printf("\n 0x%02x:", i); 1926 } 1927 printf(" %08x", pci_conf_read(pc, tag, i)); 1928 } 1929 for (i = 0x80; i < 0xb0; i += 4) { 1930 if (i % 16 == 0) { 1931 printf("\n 0x%02x:", i); 1932 } 1933 printf(" %08x", pci_conf_read(pc, tag, i)); 1934 } 1935 1936 if (memh == 0) { 1937 printf("\n"); 1938 return; 1939 } 1940 1941 printf("\nsocket regs:"); 1942 for (i = 0; i <= 0x10; i += 0x04) { 1943 printf(" %08x", bus_space_read_4(memt, memh, i)); 1944 } 1945 printf("\nExCA regs:"); 1946 for (i = 0; i < 0x08; ++i) { 1947 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1948 } 1949 printf("\n"); 1950 return; 1951 } 1952 #endif 1953 1954 /* 1955 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1956 * int busno, int devno, int function) 1957 * This is the function to make a tag to access config space of 1958 * a CardBus Card. It works same as pci_conf_read. 1959 */ 1960 static cardbustag_t 1961 pccbb_make_tag(cc, busno, devno, function) 1962 cardbus_chipset_tag_t cc; 1963 int busno, devno, function; 1964 { 1965 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1966 1967 return pci_make_tag(sc->sc_pc, busno, devno, function); 1968 } 1969 1970 static void 1971 pccbb_free_tag(cc, tag) 1972 cardbus_chipset_tag_t cc; 1973 cardbustag_t tag; 1974 { 1975 } 1976 1977 /* 1978 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1979 * cardbustag_t tag, int offset) 1980 * This is the function to read the config space of a CardBus Card. 1981 * It works same as pci_conf_read. 1982 */ 1983 static cardbusreg_t 1984 pccbb_conf_read(cc, tag, offset) 1985 cardbus_chipset_tag_t cc; 1986 cardbustag_t tag; 1987 int offset; /* register offset */ 1988 { 1989 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1990 1991 return pci_conf_read(sc->sc_pc, tag, offset); 1992 } 1993 1994 /* 1995 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1996 * int offs, cardbusreg_t val) 1997 * This is the function to write the config space of a CardBus Card. 1998 * It works same as pci_conf_write. 1999 */ 2000 static void 2001 pccbb_conf_write(cc, tag, reg, val) 2002 cardbus_chipset_tag_t cc; 2003 cardbustag_t tag; 2004 int reg; /* register offset */ 2005 cardbusreg_t val; 2006 { 2007 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2008 2009 pci_conf_write(sc->sc_pc, tag, reg, val); 2010 } 2011 2012 #if 0 2013 STATIC int 2014 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2015 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2016 int speed, int flags, 2017 bus_space_handle_t * iohp) 2018 #endif 2019 /* 2020 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2021 * bus_addr_t start, bus_size_t size, 2022 * bus_size_t align, 2023 * struct pcmcia_io_handle *pcihp 2024 * 2025 * This function only allocates I/O region for pccard. This function 2026 * never maps the allocated region to pccard I/O area. 2027 * 2028 * XXX: The interface of this function is not very good, I believe. 2029 */ 2030 STATIC int 2031 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2032 pcmcia_chipset_handle_t pch; 2033 bus_addr_t start; /* start address */ 2034 bus_size_t size; 2035 bus_size_t align; 2036 struct pcmcia_io_handle *pcihp; 2037 { 2038 struct pcic_handle *ph = (struct pcic_handle *)pch; 2039 bus_addr_t ioaddr; 2040 int flags = 0; 2041 bus_space_tag_t iot; 2042 bus_space_handle_t ioh; 2043 bus_addr_t mask; 2044 #if rbus 2045 rbus_tag_t rb; 2046 #endif 2047 if (align == 0) { 2048 align = size; /* XXX: funny??? */ 2049 } 2050 2051 if (start != 0) { 2052 /* XXX: assume all card decode lower 10 bits by its hardware */ 2053 mask = 0x3ff; 2054 /* enforce to use only masked address */ 2055 start &= mask; 2056 } else { 2057 /* 2058 * calculate mask: 2059 * 1. get the most significant bit of size (call it msb). 2060 * 2. compare msb with the value of size. 2061 * 3. if size is larger, shift msb left once. 2062 * 4. obtain mask value to decrement msb. 2063 */ 2064 bus_size_t size_tmp = size; 2065 int shifts = 0; 2066 2067 mask = 1; 2068 while (size_tmp) { 2069 ++shifts; 2070 size_tmp >>= 1; 2071 } 2072 mask = (1 << shifts); 2073 if (mask < size) { 2074 mask <<= 1; 2075 } 2076 --mask; 2077 } 2078 2079 /* 2080 * Allocate some arbitrary I/O space. 2081 */ 2082 2083 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2084 2085 #if rbus 2086 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2087 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2088 return 1; 2089 } 2090 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2091 (u_long) ioaddr, (u_long) size)); 2092 #else 2093 if (start) { 2094 ioaddr = start; 2095 if (bus_space_map(iot, start, size, 0, &ioh)) { 2096 return 1; 2097 } 2098 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2099 (u_long) ioaddr, (u_long) size)); 2100 } else { 2101 flags |= PCMCIA_IO_ALLOCATED; 2102 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2103 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2104 size, align, 0, 0, &ioaddr, &ioh)) { 2105 /* No room be able to be get. */ 2106 return 1; 2107 } 2108 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2109 (u_long) ioaddr, (u_long) size)); 2110 } 2111 #endif 2112 2113 pcihp->iot = iot; 2114 pcihp->ioh = ioh; 2115 pcihp->addr = ioaddr; 2116 pcihp->size = size; 2117 pcihp->flags = flags; 2118 2119 return 0; 2120 } 2121 2122 /* 2123 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2124 * struct pcmcia_io_handle *pcihp) 2125 * 2126 * This function only frees I/O region for pccard. 2127 * 2128 * XXX: The interface of this function is not very good, I believe. 2129 */ 2130 void 2131 pccbb_pcmcia_io_free(pch, pcihp) 2132 pcmcia_chipset_handle_t pch; 2133 struct pcmcia_io_handle *pcihp; 2134 { 2135 #if !rbus 2136 bus_space_tag_t iot = pcihp->iot; 2137 #endif 2138 bus_space_handle_t ioh = pcihp->ioh; 2139 bus_size_t size = pcihp->size; 2140 2141 #if rbus 2142 struct pccbb_softc *sc = 2143 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2144 rbus_tag_t rb = sc->sc_rbus_iot; 2145 2146 rbus_space_free(rb, ioh, size, NULL); 2147 #else 2148 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2149 bus_space_free(iot, ioh, size); 2150 else 2151 bus_space_unmap(iot, ioh, size); 2152 #endif 2153 } 2154 2155 /* 2156 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2157 * bus_addr_t offset, bus_size_t size, 2158 * struct pcmcia_io_handle *pcihp, 2159 * int *windowp) 2160 * 2161 * This function maps the allocated I/O region to pccard. This function 2162 * never allocates any I/O region for pccard I/O area. I don't 2163 * understand why the original authors of pcmciabus separated alloc and 2164 * map. I believe the two must be unite. 2165 * 2166 * XXX: no wait timing control? 2167 */ 2168 int 2169 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2170 pcmcia_chipset_handle_t pch; 2171 int width; 2172 bus_addr_t offset; 2173 bus_size_t size; 2174 struct pcmcia_io_handle *pcihp; 2175 int *windowp; 2176 { 2177 struct pcic_handle *ph = (struct pcic_handle *)pch; 2178 bus_addr_t ioaddr = pcihp->addr + offset; 2179 int i, win; 2180 #if defined CBB_DEBUG 2181 static char *width_names[] = { "dynamic", "io8", "io16" }; 2182 #endif 2183 2184 /* Sanity check I/O handle. */ 2185 2186 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2187 panic("pccbb_pcmcia_io_map iot is bogus"); 2188 } 2189 2190 /* XXX Sanity check offset/size. */ 2191 2192 win = -1; 2193 for (i = 0; i < PCIC_IO_WINS; i++) { 2194 if ((ph->ioalloc & (1 << i)) == 0) { 2195 win = i; 2196 ph->ioalloc |= (1 << i); 2197 break; 2198 } 2199 } 2200 2201 if (win == -1) { 2202 return 1; 2203 } 2204 2205 *windowp = win; 2206 2207 /* XXX this is pretty gross */ 2208 2209 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2210 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2211 2212 /* XXX wtf is this doing here? */ 2213 2214 #if 0 2215 printf(" port 0x%lx", (u_long) ioaddr); 2216 if (size > 1) { 2217 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2218 } 2219 #endif 2220 2221 ph->io[win].addr = ioaddr; 2222 ph->io[win].size = size; 2223 ph->io[win].width = width; 2224 2225 /* actual dirty register-value changing in the function below. */ 2226 pccbb_pcmcia_do_io_map(ph, win); 2227 2228 return 0; 2229 } 2230 2231 /* 2232 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2233 * 2234 * This function changes register-value to map I/O region for pccard. 2235 */ 2236 static void 2237 pccbb_pcmcia_do_io_map(ph, win) 2238 struct pcic_handle *ph; 2239 int win; 2240 { 2241 static u_int8_t pcic_iowidth[3] = { 2242 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2243 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2244 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2245 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2246 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2247 }; 2248 2249 #define PCIC_SIA_START_LOW 0 2250 #define PCIC_SIA_START_HIGH 1 2251 #define PCIC_SIA_STOP_LOW 2 2252 #define PCIC_SIA_STOP_HIGH 3 2253 2254 int regbase_win = 0x8 + win * 0x04; 2255 u_int8_t ioctl, enable; 2256 2257 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2258 "width %d\n", win, (unsigned long)ph->io[win].addr, 2259 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2260 2261 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2262 ph->io[win].addr & 0xff); 2263 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2264 (ph->io[win].addr >> 8) & 0xff); 2265 2266 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2267 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2268 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2269 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2270 2271 ioctl = Pcic_read(ph, PCIC_IOCTL); 2272 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2273 switch (win) { 2274 case 0: 2275 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2276 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2277 PCIC_IOCTL_IO0_DATASIZE_MASK); 2278 ioctl |= pcic_iowidth[ph->io[win].width]; 2279 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2280 break; 2281 case 1: 2282 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2283 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2284 PCIC_IOCTL_IO1_DATASIZE_MASK); 2285 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2286 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2287 break; 2288 } 2289 Pcic_write(ph, PCIC_IOCTL, ioctl); 2290 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2291 #if defined CBB_DEBUG 2292 { 2293 u_int8_t start_low = 2294 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2295 u_int8_t start_high = 2296 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2297 u_int8_t stop_low = 2298 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2299 u_int8_t stop_high = 2300 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2301 printf 2302 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2303 start_low, start_high, stop_low, stop_high, ioctl, enable); 2304 } 2305 #endif 2306 } 2307 2308 /* 2309 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2310 * 2311 * This function unmaps I/O region. No return value. 2312 */ 2313 STATIC void 2314 pccbb_pcmcia_io_unmap(pch, win) 2315 pcmcia_chipset_handle_t pch; 2316 int win; 2317 { 2318 struct pcic_handle *ph = (struct pcic_handle *)pch; 2319 int reg; 2320 2321 if (win >= PCIC_IO_WINS || win < 0) { 2322 panic("pccbb_pcmcia_io_unmap: window out of range"); 2323 } 2324 2325 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2326 switch (win) { 2327 case 0: 2328 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2329 break; 2330 case 1: 2331 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2332 break; 2333 } 2334 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2335 2336 ph->ioalloc &= ~(1 << win); 2337 } 2338 2339 static int 2340 pccbb_pcmcia_wait_ready(ph) 2341 struct pcic_handle *ph; 2342 { 2343 u_int8_t stat; 2344 int i; 2345 2346 /* wait an initial 10ms for quick cards */ 2347 stat = Pcic_read(ph, PCIC_IF_STATUS); 2348 if (stat & PCIC_IF_STATUS_READY) 2349 return (0); 2350 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2351 for (i = 0; i < 50; i++) { 2352 stat = Pcic_read(ph, PCIC_IF_STATUS); 2353 if (stat & PCIC_IF_STATUS_READY) 2354 return (0); 2355 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2356 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2357 return (ENXIO); 2358 /* wait .1s (100ms) each iteration now */ 2359 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2360 } 2361 2362 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2363 return (EWOULDBLOCK); 2364 } 2365 2366 /* 2367 * Perform long (msec order) delay. 2368 */ 2369 static void 2370 pccbb_pcmcia_delay(ph, timo, wmesg) 2371 struct pcic_handle *ph; 2372 int timo; /* in ms. must not be zero */ 2373 const char *wmesg; 2374 { 2375 2376 #ifdef DIAGNOSTIC 2377 if (timo <= 0) 2378 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2379 if (!curlwp) 2380 panic("pccbb_pcmcia_delay: called in interrupt context"); 2381 #if 0 2382 if (!ph->event_thread) 2383 panic("pccbb_pcmcia_delay: no event thread"); 2384 #endif 2385 #endif 2386 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2387 wmesg, h->event_thread, timo)); 2388 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2389 } 2390 2391 /* 2392 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2393 * 2394 * This function enables the card. All information is stored in 2395 * the first argument, pcmcia_chipset_handle_t. 2396 */ 2397 STATIC void 2398 pccbb_pcmcia_socket_enable(pch) 2399 pcmcia_chipset_handle_t pch; 2400 { 2401 struct pcic_handle *ph = (struct pcic_handle *)pch; 2402 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2403 pcireg_t spsr; 2404 int voltage; 2405 int win; 2406 u_int8_t power, intr; 2407 #ifdef DIAGNOSTIC 2408 int reg; 2409 #endif 2410 2411 /* this bit is mostly stolen from pcic_attach_card */ 2412 2413 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2414 2415 /* get card Vcc info */ 2416 spsr = 2417 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2418 CB_SOCKET_STAT); 2419 if (spsr & CB_SOCKET_STAT_5VCARD) { 2420 DPRINTF(("5V card\n")); 2421 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2422 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2423 DPRINTF(("3V card\n")); 2424 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2425 } else { 2426 printf("?V card, 0x%x\n", spsr); /* XXX */ 2427 return; 2428 } 2429 2430 /* disable interrupts */ 2431 intr = Pcic_read(ph, PCIC_INTR); 2432 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2433 Pcic_write(ph, PCIC_INTR, intr); 2434 2435 /* zero out the address windows */ 2436 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2437 2438 /* disable socket: negate output enable bit and power off */ 2439 power = 0; 2440 Pcic_write(ph, PCIC_PWRCTL, power); 2441 2442 /* power down the socket to reset it, clear the card reset pin */ 2443 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2444 2445 /* now make sure we have reset# active */ 2446 intr &= ~PCIC_INTR_RESET; 2447 Pcic_write(ph, PCIC_INTR, intr); 2448 2449 if (pccbb_power(sc, voltage) == 0) 2450 return; 2451 2452 /* 2453 * wait 100ms until power raise (Tpr) and 20ms to become 2454 * stable (Tsu(Vcc)). 2455 * 2456 * some machines require some more time to be settled 2457 * (300ms is added here). 2458 */ 2459 pccbb_pcmcia_delay(ph, 100 + 20 + 300, "pccen1"); 2460 2461 power |= PCIC_PWRCTL_OE; 2462 Pcic_write(ph, PCIC_PWRCTL, power); 2463 2464 if (pccbb_power(sc, voltage) == 0) 2465 return; 2466 2467 /* 2468 * hold RESET at least 10us, this is a min allow for slop in 2469 * delay routine. 2470 */ 2471 pccbb_pcmcia_delay(ph, 20, "pccen1.5"); 2472 2473 /* clear the reset flag */ 2474 intr |= PCIC_INTR_RESET; 2475 Pcic_write(ph, PCIC_INTR, intr); 2476 2477 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2478 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2479 2480 #ifdef DIAGNOSTIC 2481 reg = Pcic_read(ph, PCIC_IF_STATUS); 2482 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2483 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2484 #endif 2485 2486 /* wait for the chip to finish initializing */ 2487 if (pccbb_pcmcia_wait_ready(ph)) { 2488 /* XXX return a failure status?? */ 2489 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2490 Pcic_write(ph, PCIC_PWRCTL, 0); 2491 return; 2492 } 2493 2494 /* reinstall all the memory and io mappings */ 2495 for (win = 0; win < PCIC_MEM_WINS; ++win) 2496 if (ph->memalloc & (1 << win)) 2497 pccbb_pcmcia_do_mem_map(ph, win); 2498 for (win = 0; win < PCIC_IO_WINS; ++win) 2499 if (ph->ioalloc & (1 << win)) 2500 pccbb_pcmcia_do_io_map(ph, win); 2501 } 2502 2503 /* 2504 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2505 * 2506 * This function disables the card. All information is stored in 2507 * the first argument, pcmcia_chipset_handle_t. 2508 */ 2509 STATIC void 2510 pccbb_pcmcia_socket_disable(pch) 2511 pcmcia_chipset_handle_t pch; 2512 { 2513 struct pcic_handle *ph = (struct pcic_handle *)pch; 2514 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2515 u_int8_t intr; 2516 2517 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2518 2519 /* disable interrupts */ 2520 intr = Pcic_read(ph, PCIC_INTR); 2521 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2522 Pcic_write(ph, PCIC_INTR, intr); 2523 2524 /* zero out the address windows */ 2525 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2526 2527 /* disable socket: negate output enable bit and power off */ 2528 Pcic_write(ph, PCIC_PWRCTL, 0); 2529 2530 /* power down the socket to reset it, clear the card reset pin */ 2531 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2532 2533 /* wait 300ms for power to fall */ 2534 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2535 } 2536 2537 STATIC void 2538 pccbb_pcmcia_socket_settype(pch, type) 2539 pcmcia_chipset_handle_t pch; 2540 int type; 2541 { 2542 struct pcic_handle *ph = (struct pcic_handle *)pch; 2543 u_int8_t intr; 2544 2545 /* set the card type */ 2546 2547 intr = Pcic_read(ph, PCIC_INTR); 2548 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2549 if (type == PCMCIA_IFTYPE_IO) 2550 intr |= PCIC_INTR_CARDTYPE_IO; 2551 else 2552 intr |= PCIC_INTR_CARDTYPE_MEM; 2553 Pcic_write(ph, PCIC_INTR, intr); 2554 2555 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2556 ph->ph_parent->dv_xname, ph->sock, 2557 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2558 } 2559 2560 /* 2561 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2562 * 2563 * This function detects whether a card is in the slot or not. 2564 * If a card is inserted, return 1. Otherwise, return 0. 2565 */ 2566 STATIC int 2567 pccbb_pcmcia_card_detect(pch) 2568 pcmcia_chipset_handle_t pch; 2569 { 2570 struct pcic_handle *ph = (struct pcic_handle *)pch; 2571 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2572 2573 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2574 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2575 } 2576 2577 #if 0 2578 STATIC int 2579 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2580 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2581 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2582 #endif 2583 /* 2584 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2585 * bus_size_t size, 2586 * struct pcmcia_mem_handle *pcmhp) 2587 * 2588 * This function only allocates memory region for pccard. This 2589 * function never maps the allocated region to pccard memory area. 2590 * 2591 * XXX: Why the argument of start address is not in? 2592 */ 2593 STATIC int 2594 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2595 pcmcia_chipset_handle_t pch; 2596 bus_size_t size; 2597 struct pcmcia_mem_handle *pcmhp; 2598 { 2599 struct pcic_handle *ph = (struct pcic_handle *)pch; 2600 bus_space_handle_t memh; 2601 bus_addr_t addr; 2602 bus_size_t sizepg; 2603 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2604 #if rbus 2605 rbus_tag_t rb; 2606 #endif 2607 2608 /* Check that the card is still there. */ 2609 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2610 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2611 return 1; 2612 2613 /* out of sc->memh, allocate as many pages as necessary */ 2614 2615 /* convert size to PCIC pages */ 2616 /* 2617 * This is not enough; when the requested region is on the page 2618 * boundaries, this may calculate wrong result. 2619 */ 2620 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2621 #if 0 2622 if (sizepg > PCIC_MAX_MEM_PAGES) { 2623 return 1; 2624 } 2625 #endif 2626 2627 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2628 return 1; 2629 } 2630 2631 addr = 0; /* XXX gcc -Wuninitialized */ 2632 2633 #if rbus 2634 rb = sc->sc_rbus_memt; 2635 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2636 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2637 &addr, &memh)) { 2638 return 1; 2639 } 2640 #else 2641 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2642 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2643 0, /* boundary */ 2644 0, /* flags */ 2645 &addr, &memh)) { 2646 return 1; 2647 } 2648 #endif 2649 2650 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2651 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2652 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2653 2654 pcmhp->memt = sc->sc_memt; 2655 pcmhp->memh = memh; 2656 pcmhp->addr = addr; 2657 pcmhp->size = size; 2658 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2659 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2660 pcmhp->mhandle = 0; 2661 /* No offset??? Funny. */ 2662 2663 return 0; 2664 } 2665 2666 /* 2667 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2668 * struct pcmcia_mem_handle *pcmhp) 2669 * 2670 * This function release the memory space allocated by the function 2671 * pccbb_pcmcia_mem_alloc(). 2672 */ 2673 STATIC void 2674 pccbb_pcmcia_mem_free(pch, pcmhp) 2675 pcmcia_chipset_handle_t pch; 2676 struct pcmcia_mem_handle *pcmhp; 2677 { 2678 #if rbus 2679 struct pcic_handle *ph = (struct pcic_handle *)pch; 2680 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2681 2682 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2683 #else 2684 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2685 #endif 2686 } 2687 2688 /* 2689 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2690 * 2691 * This function release the memory space allocated by the function 2692 * pccbb_pcmcia_mem_alloc(). 2693 */ 2694 STATIC void 2695 pccbb_pcmcia_do_mem_map(ph, win) 2696 struct pcic_handle *ph; 2697 int win; 2698 { 2699 int regbase_win; 2700 bus_addr_t phys_addr; 2701 bus_addr_t phys_end; 2702 2703 #define PCIC_SMM_START_LOW 0 2704 #define PCIC_SMM_START_HIGH 1 2705 #define PCIC_SMM_STOP_LOW 2 2706 #define PCIC_SMM_STOP_HIGH 3 2707 #define PCIC_CMA_LOW 4 2708 #define PCIC_CMA_HIGH 5 2709 2710 u_int8_t start_low, start_high = 0; 2711 u_int8_t stop_low, stop_high; 2712 u_int8_t off_low, off_high; 2713 u_int8_t mem_window; 2714 int reg; 2715 2716 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2717 int mem8 = 2718 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2719 || (kind == PCMCIA_MEM_ATTR); 2720 2721 regbase_win = 0x10 + win * 0x08; 2722 2723 phys_addr = ph->mem[win].addr; 2724 phys_end = phys_addr + ph->mem[win].size; 2725 2726 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2727 (unsigned long)phys_addr, (unsigned long)phys_end, 2728 (unsigned long)ph->mem[win].offset)); 2729 2730 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2731 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2732 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2733 2734 /* bit 19:12 */ 2735 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2736 /* bit 23:20 and bit 7 on */ 2737 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2738 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2739 /* bit 31:24, for 32-bit address */ 2740 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2741 2742 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2743 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2744 2745 if (((struct pccbb_softc *)ph-> 2746 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2747 Pcic_write(ph, 0x40 + win, mem_window); 2748 } 2749 2750 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2751 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2752 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2753 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2754 2755 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2756 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2757 2758 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2759 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2760 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2761 | ((kind == PCMCIA_MEM_ATTR) ? 2762 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2763 2764 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2765 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2766 2767 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2768 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2769 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2770 2771 #if defined CBB_DEBUG 2772 { 2773 int r1, r2, r3, r4, r5, r6, r7 = 0; 2774 2775 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2776 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2777 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2778 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2779 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2780 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2781 if (((struct pccbb_softc *)(ph-> 2782 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2783 r7 = Pcic_read(ph, 0x40 + win); 2784 } 2785 2786 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2787 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2788 if (((struct pccbb_softc *)(ph-> 2789 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2790 DPRINTF((" %02x", r7)); 2791 } 2792 DPRINTF(("\n")); 2793 } 2794 #endif 2795 } 2796 2797 /* 2798 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2799 * bus_addr_t card_addr, bus_size_t size, 2800 * struct pcmcia_mem_handle *pcmhp, 2801 * bus_addr_t *offsetp, int *windowp) 2802 * 2803 * This function maps memory space allocated by the function 2804 * pccbb_pcmcia_mem_alloc(). 2805 */ 2806 STATIC int 2807 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2808 pcmcia_chipset_handle_t pch; 2809 int kind; 2810 bus_addr_t card_addr; 2811 bus_size_t size; 2812 struct pcmcia_mem_handle *pcmhp; 2813 bus_addr_t *offsetp; 2814 int *windowp; 2815 { 2816 struct pcic_handle *ph = (struct pcic_handle *)pch; 2817 bus_addr_t busaddr; 2818 long card_offset; 2819 int win; 2820 2821 /* Check that the card is still there. */ 2822 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2823 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2824 return 1; 2825 2826 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2827 if ((ph->memalloc & (1 << win)) == 0) { 2828 ph->memalloc |= (1 << win); 2829 break; 2830 } 2831 } 2832 2833 if (win == PCIC_MEM_WINS) { 2834 return 1; 2835 } 2836 2837 *windowp = win; 2838 2839 /* XXX this is pretty gross */ 2840 2841 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2842 panic("pccbb_pcmcia_mem_map memt is bogus"); 2843 } 2844 2845 busaddr = pcmhp->addr; 2846 2847 /* 2848 * compute the address offset to the pcmcia address space for the 2849 * pcic. this is intentionally signed. The masks and shifts below 2850 * will cause TRT to happen in the pcic registers. Deal with making 2851 * sure the address is aligned, and return the alignment offset. 2852 */ 2853 2854 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2855 card_addr -= *offsetp; 2856 2857 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2858 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2859 (u_long) card_addr)); 2860 2861 /* 2862 * include the offset in the size, and decrement size by one, since 2863 * the hw wants start/stop 2864 */ 2865 size += *offsetp - 1; 2866 2867 card_offset = (((long)card_addr) - ((long)busaddr)); 2868 2869 ph->mem[win].addr = busaddr; 2870 ph->mem[win].size = size; 2871 ph->mem[win].offset = card_offset; 2872 ph->mem[win].kind = kind; 2873 2874 pccbb_pcmcia_do_mem_map(ph, win); 2875 2876 return 0; 2877 } 2878 2879 /* 2880 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2881 * int window) 2882 * 2883 * This function unmaps memory space which mapped by the function 2884 * pccbb_pcmcia_mem_map(). 2885 */ 2886 STATIC void 2887 pccbb_pcmcia_mem_unmap(pch, window) 2888 pcmcia_chipset_handle_t pch; 2889 int window; 2890 { 2891 struct pcic_handle *ph = (struct pcic_handle *)pch; 2892 int reg; 2893 2894 if (window >= PCIC_MEM_WINS) { 2895 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2896 } 2897 2898 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2899 reg &= ~(1 << window); 2900 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2901 2902 ph->memalloc &= ~(1 << window); 2903 } 2904 2905 #if defined PCCBB_PCMCIA_POLL 2906 struct pccbb_poll_str { 2907 void *arg; 2908 int (*func) __P((void *)); 2909 int level; 2910 struct pcic_handle *ph; 2911 int count; 2912 int num; 2913 struct callout poll_ch; 2914 }; 2915 2916 static struct pccbb_poll_str pccbb_poll[10]; 2917 static int pccbb_poll_n = 0; 2918 2919 static void pccbb_pcmcia_poll __P((void *arg)); 2920 2921 static void 2922 pccbb_pcmcia_poll(arg) 2923 void *arg; 2924 { 2925 struct pccbb_poll_str *poll = arg; 2926 struct pcic_handle *ph = poll->ph; 2927 struct pccbb_softc *sc = ph->sc; 2928 int s; 2929 u_int32_t spsr; /* socket present-state reg */ 2930 2931 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2932 switch (poll->level) { 2933 case IPL_NET: 2934 s = splnet(); 2935 break; 2936 case IPL_BIO: 2937 s = splbio(); 2938 break; 2939 case IPL_TTY: /* fallthrough */ 2940 default: 2941 s = spltty(); 2942 break; 2943 } 2944 2945 spsr = 2946 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2947 CB_SOCKET_STAT); 2948 2949 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2950 if (!(spsr & 0x40)) /* CINT low */ 2951 #else 2952 if (1) 2953 #endif 2954 { 2955 if ((*poll->func) (poll->arg) > 0) { 2956 ++poll->count; 2957 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2958 #if defined LEVEL2 2959 } else { 2960 printf("intr: miss! 0x%x\n", spsr); 2961 #endif 2962 } 2963 } 2964 splx(s); 2965 } 2966 #endif /* defined CB_PCMCIA_POLL */ 2967 2968 /* 2969 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2970 * struct pcmcia_function *pf, 2971 * int ipl, 2972 * int (*func)(void *), 2973 * void *arg); 2974 * 2975 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2976 */ 2977 STATIC void * 2978 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2979 pcmcia_chipset_handle_t pch; 2980 struct pcmcia_function *pf; 2981 int ipl; 2982 int (*func) __P((void *)); 2983 void *arg; 2984 { 2985 struct pcic_handle *ph = (struct pcic_handle *)pch; 2986 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2987 2988 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2989 /* what should I do? */ 2990 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2991 DPRINTF(("%s does not provide edge nor pulse " 2992 "interrupt\n", sc->sc_dev.dv_xname)); 2993 return NULL; 2994 } 2995 /* 2996 * XXX Noooooo! The interrupt flag must set properly!! 2997 * dumb pcmcia driver!! 2998 */ 2999 } 3000 3001 return pccbb_intr_establish(sc, 0, ipl, func, arg); 3002 } 3003 3004 /* 3005 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 3006 * void *ih) 3007 * 3008 * This function disables PC-Card interrupt. 3009 */ 3010 STATIC void 3011 pccbb_pcmcia_intr_disestablish(pch, ih) 3012 pcmcia_chipset_handle_t pch; 3013 void *ih; 3014 { 3015 struct pcic_handle *ph = (struct pcic_handle *)pch; 3016 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3017 3018 pccbb_intr_disestablish(sc, ih); 3019 } 3020 3021 #if rbus 3022 /* 3023 * static int 3024 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3025 * bus_addr_t addr, bus_size_t size, 3026 * bus_addr_t mask, bus_size_t align, 3027 * int flags, bus_addr_t *addrp; 3028 * bus_space_handle_t *bshp) 3029 * 3030 * This function allocates a portion of memory or io space for 3031 * clients. This function is called from CardBus card drivers. 3032 */ 3033 static int 3034 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3035 cardbus_chipset_tag_t ct; 3036 rbus_tag_t rb; 3037 bus_addr_t addr; 3038 bus_size_t size; 3039 bus_addr_t mask; 3040 bus_size_t align; 3041 int flags; 3042 bus_addr_t *addrp; 3043 bus_space_handle_t *bshp; 3044 { 3045 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3046 3047 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3048 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3049 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3050 3051 if (align == 0) { 3052 align = size; 3053 } 3054 3055 if (rb->rb_bt == sc->sc_memt) { 3056 if (align < 16) { 3057 return 1; 3058 } 3059 /* 3060 * XXX: align more than 0x1000 to avoid overwrapping 3061 * memory windows for two or more devices. 0x1000 3062 * means memory window's granularity. 3063 * 3064 * Two or more devices should be able to share same 3065 * memory window region. However, overrapping memory 3066 * window is not good because some devices, such as 3067 * 3Com 3C575[BC], have a broken address decoder and 3068 * intrude other's memory region. 3069 */ 3070 if (align < 0x1000) { 3071 align = 0x1000; 3072 } 3073 } else if (rb->rb_bt == sc->sc_iot) { 3074 if (align < 4) { 3075 return 1; 3076 } 3077 /* XXX: hack for avoiding ISA image */ 3078 if (mask < 0x0100) { 3079 mask = 0x3ff; 3080 addr = 0x300; 3081 } 3082 3083 } else { 3084 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3085 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3086 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3087 (unsigned long)sc->sc_memt)); 3088 return 1; 3089 /* XXX: panic here? */ 3090 } 3091 3092 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3093 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3094 return 1; 3095 } 3096 3097 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3098 3099 return 0; 3100 } 3101 3102 /* 3103 * static int 3104 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3105 * bus_space_handle_t *bshp, bus_size_t size); 3106 * 3107 * This function is called from CardBus card drivers. 3108 */ 3109 static int 3110 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3111 cardbus_chipset_tag_t ct; 3112 rbus_tag_t rb; 3113 bus_space_handle_t bsh; 3114 bus_size_t size; 3115 { 3116 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3117 bus_space_tag_t bt = rb->rb_bt; 3118 3119 pccbb_close_win(sc, bt, bsh, size); 3120 3121 if (bt == sc->sc_memt) { 3122 } else if (bt == sc->sc_iot) { 3123 } else { 3124 return 1; 3125 /* XXX: panic here? */ 3126 } 3127 3128 return rbus_space_free(rb, bsh, size, NULL); 3129 } 3130 #endif /* rbus */ 3131 3132 #if rbus 3133 3134 static int 3135 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3136 struct pccbb_softc *sc; 3137 bus_space_tag_t bst; 3138 bus_addr_t addr; 3139 bus_size_t size; 3140 bus_space_handle_t bsh; 3141 int flags; 3142 { 3143 struct pccbb_win_chain_head *head; 3144 bus_addr_t align; 3145 3146 head = &sc->sc_iowindow; 3147 align = 0x04; 3148 if (sc->sc_memt == bst) { 3149 head = &sc->sc_memwindow; 3150 align = 0x1000; 3151 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3152 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3153 (unsigned long)bst)); 3154 } 3155 3156 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3157 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3158 sc->sc_dev.dv_xname, 3159 (head == &sc->sc_memwindow) ? "mem" : "io"); 3160 } 3161 pccbb_winset(align, sc, bst); 3162 3163 return 0; 3164 } 3165 3166 static int 3167 pccbb_close_win(sc, bst, bsh, size) 3168 struct pccbb_softc *sc; 3169 bus_space_tag_t bst; 3170 bus_space_handle_t bsh; 3171 bus_size_t size; 3172 { 3173 struct pccbb_win_chain_head *head; 3174 bus_addr_t align; 3175 3176 head = &sc->sc_iowindow; 3177 align = 0x04; 3178 if (sc->sc_memt == bst) { 3179 head = &sc->sc_memwindow; 3180 align = 0x1000; 3181 } 3182 3183 if (pccbb_winlist_delete(head, bsh, size)) { 3184 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3185 sc->sc_dev.dv_xname, 3186 (head == &sc->sc_memwindow) ? "mem" : "io"); 3187 } 3188 pccbb_winset(align, sc, bst); 3189 3190 return 0; 3191 } 3192 3193 static int 3194 pccbb_winlist_insert(head, start, size, bsh, flags) 3195 struct pccbb_win_chain_head *head; 3196 bus_addr_t start; 3197 bus_size_t size; 3198 bus_space_handle_t bsh; 3199 int flags; 3200 { 3201 struct pccbb_win_chain *chainp, *elem; 3202 3203 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3204 M_NOWAIT)) == NULL) 3205 return (1); /* fail */ 3206 3207 elem->wc_start = start; 3208 elem->wc_end = start + (size - 1); 3209 elem->wc_handle = bsh; 3210 elem->wc_flags = flags; 3211 3212 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3213 chainp = TAILQ_NEXT(chainp, wc_list)) { 3214 if (chainp->wc_end < start) 3215 continue; 3216 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3217 return (0); 3218 } 3219 3220 TAILQ_INSERT_TAIL(head, elem, wc_list); 3221 return (0); 3222 } 3223 3224 static int 3225 pccbb_winlist_delete(head, bsh, size) 3226 struct pccbb_win_chain_head *head; 3227 bus_space_handle_t bsh; 3228 bus_size_t size; 3229 { 3230 struct pccbb_win_chain *chainp; 3231 3232 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3233 chainp = TAILQ_NEXT(chainp, wc_list)) { 3234 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3235 continue; 3236 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3237 printf("pccbb_winlist_delete: window 0x%lx size " 3238 "inconsistent: 0x%lx, 0x%lx\n", 3239 (unsigned long)chainp->wc_start, 3240 (unsigned long)(chainp->wc_end - chainp->wc_start), 3241 (unsigned long)(size - 1)); 3242 return 1; 3243 } 3244 3245 TAILQ_REMOVE(head, chainp, wc_list); 3246 free(chainp, M_DEVBUF); 3247 3248 return 0; 3249 } 3250 3251 return 1; /* fail: no candidate to remove */ 3252 } 3253 3254 static void 3255 pccbb_winset(align, sc, bst) 3256 bus_addr_t align; 3257 struct pccbb_softc *sc; 3258 bus_space_tag_t bst; 3259 { 3260 pci_chipset_tag_t pc; 3261 pcitag_t tag; 3262 bus_addr_t mask = ~(align - 1); 3263 struct { 3264 cardbusreg_t win_start; 3265 cardbusreg_t win_limit; 3266 int win_flags; 3267 } win[2]; 3268 struct pccbb_win_chain *chainp; 3269 int offs; 3270 3271 win[0].win_start = win[1].win_start = 0xffffffff; 3272 win[0].win_limit = win[1].win_limit = 0; 3273 win[0].win_flags = win[1].win_flags = 0; 3274 3275 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3276 offs = 0x2c; 3277 if (sc->sc_memt == bst) { 3278 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3279 offs = 0x1c; 3280 } 3281 3282 if (chainp != NULL) { 3283 win[0].win_start = chainp->wc_start & mask; 3284 win[0].win_limit = chainp->wc_end & mask; 3285 win[0].win_flags = chainp->wc_flags; 3286 chainp = TAILQ_NEXT(chainp, wc_list); 3287 } 3288 3289 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3290 if (win[1].win_start == 0xffffffff) { 3291 /* window 1 is not used */ 3292 if ((win[0].win_flags == chainp->wc_flags) && 3293 (win[0].win_limit + align >= 3294 (chainp->wc_start & mask))) { 3295 /* concatenate */ 3296 win[0].win_limit = chainp->wc_end & mask; 3297 } else { 3298 /* make new window */ 3299 win[1].win_start = chainp->wc_start & mask; 3300 win[1].win_limit = chainp->wc_end & mask; 3301 win[1].win_flags = chainp->wc_flags; 3302 } 3303 continue; 3304 } 3305 3306 /* Both windows are engaged. */ 3307 if (win[0].win_flags == win[1].win_flags) { 3308 /* same flags */ 3309 if (win[0].win_flags == chainp->wc_flags) { 3310 if (win[1].win_start - (win[0].win_limit + 3311 align) < 3312 (chainp->wc_start & mask) - 3313 ((chainp->wc_end & mask) + align)) { 3314 /* 3315 * merge window 0 and 1, and set win1 3316 * to chainp 3317 */ 3318 win[0].win_limit = win[1].win_limit; 3319 win[1].win_start = 3320 chainp->wc_start & mask; 3321 win[1].win_limit = 3322 chainp->wc_end & mask; 3323 } else { 3324 win[1].win_limit = 3325 chainp->wc_end & mask; 3326 } 3327 } else { 3328 /* different flags */ 3329 3330 /* concatenate win0 and win1 */ 3331 win[0].win_limit = win[1].win_limit; 3332 /* allocate win[1] to new space */ 3333 win[1].win_start = chainp->wc_start & mask; 3334 win[1].win_limit = chainp->wc_end & mask; 3335 win[1].win_flags = chainp->wc_flags; 3336 } 3337 } else { 3338 /* the flags of win[0] and win[1] is different */ 3339 if (win[0].win_flags == chainp->wc_flags) { 3340 win[0].win_limit = chainp->wc_end & mask; 3341 /* 3342 * XXX this creates overlapping windows, so 3343 * what should the poor bridge do if one is 3344 * cachable, and the other is not? 3345 */ 3346 printf("%s: overlapping windows\n", 3347 sc->sc_dev.dv_xname); 3348 } else { 3349 win[1].win_limit = chainp->wc_end & mask; 3350 } 3351 } 3352 } 3353 3354 pc = sc->sc_pc; 3355 tag = sc->sc_tag; 3356 pci_conf_write(pc, tag, offs, win[0].win_start); 3357 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3358 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3359 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3360 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3361 (unsigned long)pci_conf_read(pc, tag, offs), 3362 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3363 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3364 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3365 3366 if (bst == sc->sc_memt) { 3367 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3368 3369 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3370 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3371 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3372 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3373 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3374 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3375 } 3376 } 3377 3378 #endif /* rbus */ 3379 3380 static void 3381 pccbb_powerhook(why, arg) 3382 int why; 3383 void *arg; 3384 { 3385 struct pccbb_softc *sc = arg; 3386 pcireg_t reg; 3387 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3388 bus_space_handle_t base_memh = sc->sc_base_memh; 3389 3390 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3391 3392 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3393 DPRINTF(("%s: power: why %d stopping intr\n", 3394 sc->sc_dev.dv_xname, why)); 3395 if (sc->sc_pil_intr_enable) { 3396 (void)pccbbintr_function(sc); 3397 } 3398 sc->sc_pil_intr_enable = 0; 3399 3400 /* ToDo: deactivate or suspend child devices */ 3401 3402 } 3403 3404 if (why == PWR_RESUME) { 3405 if (sc->sc_pwrmgt_offs != 0) { 3406 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3407 sc->sc_pwrmgt_offs + 4); 3408 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3409 reg & 0x100) { 3410 /* powrstate != D0 */ 3411 3412 printf("%s going back to D0 mode\n", 3413 sc->sc_dev.dv_xname); 3414 reg &= ~PCI_PMCSR_STATE_MASK; 3415 reg |= PCI_PMCSR_STATE_D0; 3416 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3417 pci_conf_write(sc->sc_pc, sc->sc_tag, 3418 sc->sc_pwrmgt_offs + 4, reg); 3419 3420 pci_conf_write(sc->sc_pc, sc->sc_tag, 3421 PCI_SOCKBASE, sc->sc_sockbase); 3422 pci_conf_write(sc->sc_pc, sc->sc_tag, 3423 PCI_BUSNUM, sc->sc_busnum); 3424 pccbb_chipinit(sc); 3425 /* setup memory and io space window for CB */ 3426 pccbb_winset(0x1000, sc, sc->sc_memt); 3427 pccbb_winset(0x04, sc, sc->sc_iot); 3428 } 3429 } 3430 3431 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3432 /* BIOS did not recover this register */ 3433 pci_conf_write (sc->sc_pc, sc->sc_tag, 3434 PCI_SOCKBASE, sc->sc_sockbase); 3435 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3436 /* BIOS did not recover this register */ 3437 pci_conf_write (sc->sc_pc, sc->sc_tag, 3438 PCI_BUSNUM, sc->sc_busnum); 3439 /* CSC Interrupt: Card detect interrupt on */ 3440 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3441 /* Card detect intr is turned on. */ 3442 reg |= CB_SOCKET_MASK_CD; 3443 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3444 /* reset interrupt */ 3445 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3446 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3447 3448 /* 3449 * check for card insertion or removal during suspend period. 3450 * XXX: the code can't cope with card swap (remove then 3451 * insert). how can we detect such situation? 3452 */ 3453 (void)pccbbintr(sc); 3454 3455 sc->sc_pil_intr_enable = 1; 3456 DPRINTF(("%s: power: RESUME enabling intr\n", 3457 sc->sc_dev.dv_xname)); 3458 3459 /* ToDo: activate or wakeup child devices */ 3460 } 3461 } 3462
Indexes created Thu Sep 25 16:09:42 GMT 2025