pccbb.c revision 1.105
1 /* $NetBSD: pccbb.c,v 1.105 2004/08/12 13:42:17 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.105 2004/08/12 13:42:17 mycroft Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC void pccbb_pcmcia_socket_settype __P((pcmcia_chipset_handle_t, int)); 188 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 189 190 static int pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_delay __P((struct pcic_handle *, int, const char *)); 192 193 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 194 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 195 static void pccbb_powerhook __P((int, void *)); 196 197 /* bus-space allocation and deallocation functions */ 198 #if rbus 199 200 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 202 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 203 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 204 bus_space_handle_t, bus_size_t)); 205 206 #endif /* rbus */ 207 208 #if rbus 209 210 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 211 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 212 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 213 bus_space_handle_t, bus_size_t)); 214 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 215 bus_size_t, bus_space_handle_t, int)); 216 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 217 bus_space_handle_t, bus_size_t)); 218 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 219 bus_space_tag_t)); 220 void pccbb_winlist_show(struct pccbb_win_chain *); 221 222 #endif /* rbus */ 223 224 /* for config_defer */ 225 static void pccbb_pci_callback __P((struct device *)); 226 227 #if defined SHOW_REGS 228 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 229 bus_space_tag_t memt, bus_space_handle_t memh)); 230 #endif 231 232 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 233 pcicbbmatch, pccbbattach, NULL, NULL); 234 235 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 236 pccbb_pcmcia_mem_alloc, 237 pccbb_pcmcia_mem_free, 238 pccbb_pcmcia_mem_map, 239 pccbb_pcmcia_mem_unmap, 240 pccbb_pcmcia_io_alloc, 241 pccbb_pcmcia_io_free, 242 pccbb_pcmcia_io_map, 243 pccbb_pcmcia_io_unmap, 244 pccbb_pcmcia_intr_establish, 245 pccbb_pcmcia_intr_disestablish, 246 pccbb_pcmcia_socket_enable, 247 pccbb_pcmcia_socket_disable, 248 pccbb_pcmcia_socket_settype, 249 pccbb_pcmcia_card_detect 250 }; 251 252 #if rbus 253 static struct cardbus_functions pccbb_funcs = { 254 pccbb_rbus_cb_space_alloc, 255 pccbb_rbus_cb_space_free, 256 pccbb_cb_intr_establish, 257 pccbb_cb_intr_disestablish, 258 pccbb_ctrl, 259 pccbb_power, 260 pccbb_make_tag, 261 pccbb_free_tag, 262 pccbb_conf_read, 263 pccbb_conf_write, 264 }; 265 #else 266 static struct cardbus_functions pccbb_funcs = { 267 pccbb_ctrl, 268 pccbb_power, 269 pccbb_mem_open, 270 pccbb_mem_close, 271 pccbb_io_open, 272 pccbb_io_close, 273 pccbb_cb_intr_establish, 274 pccbb_cb_intr_disestablish, 275 pccbb_make_tag, 276 pccbb_conf_read, 277 pccbb_conf_write, 278 }; 279 #endif 280 281 int 282 pcicbbmatch(parent, match, aux) 283 struct device *parent; 284 struct cfdata *match; 285 void *aux; 286 { 287 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 288 289 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 290 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 291 PCI_INTERFACE(pa->pa_class) == 0) { 292 return 1; 293 } 294 295 return 0; 296 } 297 298 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 299 | ((prod) << PCI_PRODUCT_SHIFT)) 300 301 const struct yenta_chipinfo { 302 pcireg_t yc_id; /* vendor tag | product tag */ 303 int yc_chiptype; 304 int yc_flags; 305 } yc_chipsets[] = { 306 /* Texas Instruments chips */ 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 332 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 334 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 336 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 338 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 339 340 /* Ricoh chips */ 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 344 PCCBB_PCMCIA_MEM_32}, 345 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 346 PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 348 PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 350 PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 352 PCCBB_PCMCIA_MEM_32}, 353 354 /* Toshiba products */ 355 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 356 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 358 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 360 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 361 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 362 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 363 364 /* Cirrus Logic products */ 365 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 366 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 367 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 368 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 369 370 /* sentinel, or Generic chip */ 371 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 372 }; 373 374 static int 375 cb_chipset(pci_id, flagp) 376 u_int32_t pci_id; 377 int *flagp; 378 { 379 const struct yenta_chipinfo *yc; 380 381 /* Loop over except the last default entry. */ 382 for (yc = yc_chipsets; yc < yc_chipsets + 383 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 384 if (pci_id == yc->yc_id) 385 break; 386 387 if (flagp != NULL) 388 *flagp = yc->yc_flags; 389 390 return (yc->yc_chiptype); 391 } 392 393 static void 394 pccbb_shutdown(void *arg) 395 { 396 struct pccbb_softc *sc = arg; 397 pcireg_t command; 398 399 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 400 401 /* 402 * turn off power 403 * 404 * XXX - do not turn off power if chipset is TI 113X because 405 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 406 */ 407 if (sc->sc_chipset != CB_TI113X) { 408 pccbb_power((cardbus_chipset_tag_t)sc, 409 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 410 } 411 412 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 413 0); 414 415 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 416 417 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 418 PCI_COMMAND_MASTER_ENABLE); 419 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 420 421 } 422 423 void 424 pccbbattach(parent, self, aux) 425 struct device *parent; 426 struct device *self; 427 void *aux; 428 { 429 struct pccbb_softc *sc = (void *)self; 430 struct pci_attach_args *pa = aux; 431 pci_chipset_tag_t pc = pa->pa_pc; 432 pcireg_t busreg, reg, sock_base; 433 bus_addr_t sockbase; 434 char devinfo[256]; 435 int flags; 436 int pwrmgt_offs; 437 438 #ifdef __HAVE_PCCBB_ATTACH_HOOK 439 pccbb_attach_hook(parent, self, pa); 440 #endif 441 442 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 443 444 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 445 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 446 #ifdef CBB_DEBUG 447 printf(" (chipflags %x)", flags); 448 #endif 449 printf("\n"); 450 451 TAILQ_INIT(&sc->sc_memwindow); 452 TAILQ_INIT(&sc->sc_iowindow); 453 454 #if rbus 455 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 456 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 457 458 #if 0 459 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 460 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 461 #endif 462 #endif /* rbus */ 463 464 sc->sc_flags &= ~CBB_MEMHMAPPED; 465 466 /* power management: set D0 state */ 467 sc->sc_pwrmgt_offs = 0; 468 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 469 &pwrmgt_offs, 0)) { 470 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 471 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 472 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 473 reg &= ~PCI_PMCSR_STATE_MASK; 474 reg |= PCI_PMCSR_STATE_D0; 475 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 476 pci_conf_write(pc, pa->pa_tag, 477 pwrmgt_offs + PCI_PMCSR, reg); 478 } 479 480 sc->sc_pwrmgt_offs = pwrmgt_offs; 481 } 482 483 /* 484 * MAP socket registers and ExCA registers on memory-space 485 * When no valid address is set on socket base registers (on pci 486 * config space), get it not polite way. 487 */ 488 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 489 490 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 491 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 492 /* The address must be valid. */ 493 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 494 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 495 printf("%s: can't map socket base address 0x%lx\n", 496 sc->sc_dev.dv_xname, (unsigned long)sock_base); 497 /* 498 * I think it's funny: socket base registers must be 499 * mapped on memory space, but ... 500 */ 501 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 502 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 503 NULL)) { 504 printf("%s: can't map socket base address" 505 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 506 (unsigned long)sockbase); 507 /* give up... allocate reg space via rbus. */ 508 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 509 } else 510 sc->sc_flags |= CBB_MEMHMAPPED; 511 } else { 512 DPRINTF(("%s: socket base address 0x%lx\n", 513 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 514 sc->sc_flags |= CBB_MEMHMAPPED; 515 } 516 } 517 518 sc->sc_mem_start = 0; /* XXX */ 519 sc->sc_mem_end = 0xffffffff; /* XXX */ 520 521 /* 522 * When interrupt isn't routed correctly, give up probing cbb and do 523 * not kill pcic-compatible port. 524 */ 525 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 526 printf("%s: NOT USED because of unconfigured interrupt\n", 527 sc->sc_dev.dv_xname); 528 return; 529 } 530 531 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 532 533 /* pccbb_machdep.c end */ 534 535 #if defined CBB_DEBUG 536 { 537 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 538 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 539 intrname[pa->pa_intrpin], pa->pa_intrline); 540 } 541 #endif 542 543 /* setup softc */ 544 sc->sc_pc = pc; 545 sc->sc_iot = pa->pa_iot; 546 sc->sc_memt = pa->pa_memt; 547 sc->sc_dmat = pa->pa_dmat; 548 sc->sc_tag = pa->pa_tag; 549 sc->sc_function = pa->pa_function; 550 sc->sc_sockbase = sock_base; 551 sc->sc_busnum = busreg; 552 553 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 554 555 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 556 557 shutdownhook_establish(pccbb_shutdown, sc); 558 559 /* Disable legacy register mapping. */ 560 switch (sc->sc_chipset) { 561 case CB_RX5C46X: /* fallthrough */ 562 #if 0 563 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 564 case CB_RX5C47X: 565 #endif 566 /* 567 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 568 * cannot be disabled by substituting 0 into PCI_LEGACY 569 * register. Ricoh CardBus bridges have special bits on Bridge 570 * control reg (addr 0x3e on PCI config space). 571 */ 572 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 573 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 574 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 575 break; 576 577 default: 578 /* XXX I don't know proper way to kill legacy I/O. */ 579 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 580 break; 581 } 582 583 config_defer(self, pccbb_pci_callback); 584 } 585 586 587 588 589 /* 590 * static void pccbb_pci_callback(struct device *self) 591 * 592 * The actual attach routine: get memory space for YENTA register 593 * space, setup YENTA register and route interrupt. 594 * 595 * This function should be deferred because this device may obtain 596 * memory space dynamically. This function must avoid obtaining 597 * memory area which has already kept for another device. 598 */ 599 static void 600 pccbb_pci_callback(self) 601 struct device *self; 602 { 603 struct pccbb_softc *sc = (void *)self; 604 pci_chipset_tag_t pc = sc->sc_pc; 605 pci_intr_handle_t ih; 606 const char *intrstr = NULL; 607 bus_addr_t sockbase; 608 struct cbslot_attach_args cba; 609 struct pcmciabus_attach_args paa; 610 struct cardslot_attach_args caa; 611 struct cardslot_softc *csc; 612 613 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 614 /* The socket registers aren't mapped correctly. */ 615 #if rbus 616 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 617 (sc->sc_chipset == CB_RX5C47X 618 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 619 0, &sockbase, &sc->sc_base_memh)) { 620 return; 621 } 622 sc->sc_base_memt = sc->sc_memt; 623 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 624 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 625 sc->sc_dev.dv_xname, (unsigned long)sockbase, 626 (unsigned long)pci_conf_read(pc, sc->sc_tag, 627 PCI_SOCKBASE))); 628 #else 629 sc->sc_base_memt = sc->sc_memt; 630 #if !defined CBB_PCI_BASE 631 #define CBB_PCI_BASE 0x20000000 632 #endif 633 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 634 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 635 /* cannot allocate memory space */ 636 return; 637 } 638 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 639 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 640 sc->sc_dev.dv_xname, (unsigned long)sock_base, 641 (unsigned long)pci_conf_read(pc, 642 sc->sc_tag, PCI_SOCKBASE))); 643 sc->sc_sockbase = sockbase; 644 #endif 645 sc->sc_flags |= CBB_MEMHMAPPED; 646 } 647 648 /* bus bridge initialization */ 649 pccbb_chipinit(sc); 650 651 /* clear data structure for child device interrupt handlers */ 652 LIST_INIT(&sc->sc_pil); 653 sc->sc_pil_intr_enable = 1; 654 655 /* Map and establish the interrupt. */ 656 if (pci_intr_map(&sc->sc_pa, &ih)) { 657 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 658 return; 659 } 660 intrstr = pci_intr_string(pc, ih); 661 662 /* 663 * XXX pccbbintr should be called under the priority lower 664 * than any other hard interrputs. 665 */ 666 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 667 668 if (sc->sc_ih == NULL) { 669 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 670 if (intrstr != NULL) { 671 printf(" at %s", intrstr); 672 } 673 printf("\n"); 674 return; 675 } 676 677 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 678 powerhook_establish(pccbb_powerhook, sc); 679 680 { 681 u_int32_t sockstat; 682 683 sockstat = bus_space_read_4(sc->sc_base_memt, 684 sc->sc_base_memh, CB_SOCKET_STAT); 685 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 686 sc->sc_flags |= CBB_CARDEXIST; 687 } 688 } 689 690 /* 691 * attach cardbus 692 */ 693 { 694 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 695 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 696 697 /* initialize cbslot_attach */ 698 cba.cba_busname = "cardbus"; 699 cba.cba_iot = sc->sc_iot; 700 cba.cba_memt = sc->sc_memt; 701 cba.cba_dmat = sc->sc_dmat; 702 cba.cba_bus = (busreg >> 8) & 0x0ff; 703 cba.cba_cc = (void *)sc; 704 cba.cba_cf = &pccbb_funcs; 705 cba.cba_intrline = sc->sc_pa.pa_intrline; 706 707 #if rbus 708 cba.cba_rbus_iot = sc->sc_rbus_iot; 709 cba.cba_rbus_memt = sc->sc_rbus_memt; 710 #endif 711 712 cba.cba_cacheline = PCI_CACHELINE(bhlc); 713 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 714 715 if (bootverbose) { 716 printf("%s: cacheline 0x%x lattimer 0x%x\n", 717 sc->sc_dev.dv_xname, cba.cba_cacheline, 718 cba.cba_lattimer); 719 printf("%s: bhlc 0x%x lscp 0x%x\n", 720 sc->sc_dev.dv_xname, bhlc, busreg); 721 } 722 #if defined SHOW_REGS 723 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 724 sc->sc_base_memh); 725 #endif 726 } 727 728 pccbb_pcmcia_attach_setup(sc, &paa); 729 caa.caa_cb_attach = NULL; 730 if (cba.cba_bus == 0) 731 printf("%s: secondary bus number uninitialized; try PCIBIOS_BUS_FIXUP\n", sc->sc_dev.dv_xname); 732 else 733 caa.caa_cb_attach = &cba; 734 caa.caa_16_attach = &paa; 735 caa.caa_ph = &sc->sc_pcmcia_h; 736 737 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 738 DPRINTF(("pccbbattach: found cardslot\n")); 739 sc->sc_csc = csc; 740 } 741 742 return; 743 } 744 745 746 747 748 749 /* 750 * static void pccbb_chipinit(struct pccbb_softc *sc) 751 * 752 * This function initialize YENTA chip registers listed below: 753 * 1) PCI command reg, 754 * 2) PCI and CardBus latency timer, 755 * 3) route PCI interrupt, 756 * 4) close all memory and io windows. 757 * 5) turn off bus power. 758 * 6) card detect interrupt on. 759 * 7) clear interrupt 760 */ 761 static void 762 pccbb_chipinit(sc) 763 struct pccbb_softc *sc; 764 { 765 pci_chipset_tag_t pc = sc->sc_pc; 766 pcitag_t tag = sc->sc_tag; 767 bus_space_tag_t bmt = sc->sc_base_memt; 768 bus_space_handle_t bmh = sc->sc_base_memh; 769 pcireg_t reg; 770 771 /* 772 * Set PCI command reg. 773 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 774 */ 775 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 776 /* I believe it is harmless. */ 777 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 778 PCI_COMMAND_MASTER_ENABLE); 779 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 780 781 /* 782 * Set CardBus latency timer. 783 */ 784 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 785 if (PCI_CB_LATENCY(reg) < 0x20) { 786 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 787 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 788 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 789 } 790 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 791 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 792 793 /* 794 * Set PCI latency timer. 795 */ 796 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 797 if (PCI_LATTIMER(reg) < 0x10) { 798 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 799 reg |= (0x10 << PCI_LATTIMER_SHIFT); 800 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 801 } 802 DPRINTF(("PCI latency timer 0x%x (%x)\n", 803 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 804 805 806 /* Route functional interrupts to PCI. */ 807 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 808 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 809 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 810 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 811 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 812 813 switch (sc->sc_chipset) { 814 case CB_TI113X: 815 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 816 /* This bit is shared, but may read as 0 on some chips, so set 817 it explicitly on both functions. */ 818 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 819 /* CSC intr enable */ 820 reg |= PCI113X_CBCTRL_PCI_CSC; 821 /* functional intr prohibit | prohibit ISA routing */ 822 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 823 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 824 break; 825 826 case CB_TI12XX: 827 /* 828 * Some TI 12xx (and [14][45]xx) based pci cards 829 * sometimes have issues with the MFUNC register not 830 * being initialized due to a bad EEPROM on board. 831 * Laptops that this matters on have this register 832 * properly initialized. 833 * 834 * The TI125X parts have a different register. 835 */ 836 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 837 if (reg == 0) { 838 reg &= ~PCI12XX_MFUNC_PIN0; 839 reg |= PCI12XX_MFUNC_PIN0_INTA; 840 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 841 PCI12XX_SYSCTRL_INTRTIE) == 0) { 842 reg &= ~PCI12XX_MFUNC_PIN1; 843 reg |= PCI12XX_MFUNC_PIN1_INTB; 844 } 845 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 846 } 847 /* fallthrough */ 848 849 case CB_TI125X: 850 /* 851 * Disable zoom video. Some machines initialize this 852 * improperly and experience has shown that this helps 853 * prevent strange behavior. 854 */ 855 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 856 857 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 858 reg |= PCI12XX_SYSCTRL_VCCPROT; 859 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 860 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 861 reg |= PCI12XX_CBCTRL_CSC; 862 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 863 break; 864 865 case CB_TOPIC95B: 866 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 867 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 868 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 869 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 870 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 871 sc->sc_dev.dv_xname, reg)); 872 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 873 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 874 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 875 DPRINTF(("0x%x\n", reg)); 876 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 877 break; 878 879 case CB_TOPIC97: 880 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 881 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 882 sc->sc_dev.dv_xname, reg)); 883 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 884 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 885 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 886 reg |= TOPIC97_SLOT_CTRL_PCIINT; 887 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 888 DPRINTF(("0x%x\n", reg)); 889 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 890 /* make sure to assert LV card support bits */ 891 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 892 0x800 + 0x3e, 893 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 894 0x800 + 0x3e) | 0x03); 895 break; 896 } 897 898 /* Close all memory and I/O windows. */ 899 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 900 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 901 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 902 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 903 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 904 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 905 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 906 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 907 908 /* reset 16-bit pcmcia bus */ 909 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 910 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 911 912 /* turn off power */ 913 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 914 915 /* CSC Interrupt: Card detect interrupt on */ 916 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 917 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 918 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 919 /* reset interrupt */ 920 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 921 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 922 } 923 924 925 926 927 /* 928 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 929 * struct pcmciabus_attach_args *paa) 930 * 931 * This function attaches 16-bit PCcard bus. 932 */ 933 STATIC void 934 pccbb_pcmcia_attach_setup(sc, paa) 935 struct pccbb_softc *sc; 936 struct pcmciabus_attach_args *paa; 937 { 938 struct pcic_handle *ph = &sc->sc_pcmcia_h; 939 #if rbus 940 rbus_tag_t rb; 941 #endif 942 943 /* initialize pcmcia part in pccbb_softc */ 944 ph->ph_parent = (struct device *)sc; 945 ph->sock = sc->sc_function; 946 ph->flags = 0; 947 ph->shutdown = 0; 948 ph->ih_irq = sc->sc_pa.pa_intrline; 949 ph->ph_bus_t = sc->sc_base_memt; 950 ph->ph_bus_h = sc->sc_base_memh; 951 ph->ph_read = pccbb_pcmcia_read; 952 ph->ph_write = pccbb_pcmcia_write; 953 sc->sc_pct = &pccbb_pcmcia_funcs; 954 955 /* 956 * We need to do a few things here: 957 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 958 * setting the IRQ numbers to 0. 959 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 960 * routing of CSC interrupts (e.g. card removal) to PCI while in 961 * PCMCIA mode. We just leave this set all the time. 962 * 3) Enable card insertion/removal interrupts in case the chip also 963 * needs that while in PCMCIA mode. 964 * 4) Clear any pending CSC interrupt. 965 */ 966 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 967 if (sc->sc_chipset == CB_TI113X) { 968 Pcic_write(ph, PCIC_CSC_INTR, 0); 969 } else { 970 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 971 Pcic_read(ph, PCIC_CSC); 972 } 973 974 /* initialize pcmcia bus attachment */ 975 paa->paa_busname = "pcmcia"; 976 paa->pct = sc->sc_pct; 977 paa->pch = ph; 978 paa->iobase = 0; /* I don't use them */ 979 paa->iosize = 0; 980 #if rbus 981 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 982 paa->iobase = rb->rb_start + rb->rb_offset; 983 paa->iosize = rb->rb_end - rb->rb_start; 984 #endif 985 986 return; 987 } 988 989 #if 0 990 STATIC void 991 pccbb_pcmcia_attach_card(ph) 992 struct pcic_handle *ph; 993 { 994 if (ph->flags & PCIC_FLAG_CARDP) { 995 panic("pccbb_pcmcia_attach_card: already attached"); 996 } 997 998 /* call the MI attach function */ 999 pcmcia_card_attach(ph->pcmcia); 1000 1001 ph->flags |= PCIC_FLAG_CARDP; 1002 } 1003 1004 STATIC void 1005 pccbb_pcmcia_detach_card(ph, flags) 1006 struct pcic_handle *ph; 1007 int flags; 1008 { 1009 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1010 panic("pccbb_pcmcia_detach_card: already detached"); 1011 } 1012 1013 ph->flags &= ~PCIC_FLAG_CARDP; 1014 1015 /* call the MI detach function */ 1016 pcmcia_card_detach(ph->pcmcia, flags); 1017 } 1018 #endif 1019 1020 /* 1021 * int pccbbintr(arg) 1022 * void *arg; 1023 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1024 * itself. 1025 */ 1026 int 1027 pccbbintr(arg) 1028 void *arg; 1029 { 1030 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1031 u_int32_t sockevent, sockstate; 1032 bus_space_tag_t memt = sc->sc_base_memt; 1033 bus_space_handle_t memh = sc->sc_base_memh; 1034 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1035 1036 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1037 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1038 Pcic_read(ph, PCIC_CSC); 1039 1040 if (sockevent == 0) { 1041 /* This intr is not for me: it may be for my child devices. */ 1042 if (sc->sc_pil_intr_enable) { 1043 return pccbbintr_function(sc); 1044 } else { 1045 return 0; 1046 } 1047 } 1048 1049 if (sockevent & CB_SOCKET_EVENT_CD) { 1050 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1051 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1052 /* A card should be removed. */ 1053 if (sc->sc_flags & CBB_CARDEXIST) { 1054 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1055 sockevent)); 1056 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1057 sc->sc_flags &= ~CBB_CARDEXIST; 1058 if (sc->sc_csc->sc_status & 1059 CARDSLOT_STATUS_CARD_16) { 1060 #if 0 1061 struct pcic_handle *ph = 1062 &sc->sc_pcmcia_h; 1063 1064 pcmcia_card_deactivate(ph->pcmcia); 1065 pccbb_pcmcia_socket_disable(ph); 1066 pccbb_pcmcia_detach_card(ph, 1067 DETACH_FORCE); 1068 #endif 1069 cardslot_event_throw(sc->sc_csc, 1070 CARDSLOT_EVENT_REMOVAL_16); 1071 } else if (sc->sc_csc->sc_status & 1072 CARDSLOT_STATUS_CARD_CB) { 1073 /* Cardbus intr removed */ 1074 cardslot_event_throw(sc->sc_csc, 1075 CARDSLOT_EVENT_REMOVAL_CB); 1076 } 1077 } else if (sc->sc_flags & CBB_INSERTING) { 1078 sc->sc_flags &= ~CBB_INSERTING; 1079 callout_stop(&sc->sc_insert_ch); 1080 } 1081 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1082 /* 1083 * The pccbbintr may called from powerdown hook when 1084 * the system resumed, to detect the card 1085 * insertion/removal during suspension. 1086 */ 1087 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1088 if (sc->sc_flags & CBB_INSERTING) { 1089 callout_stop(&sc->sc_insert_ch); 1090 } 1091 callout_reset(&sc->sc_insert_ch, hz / 5, 1092 pci113x_insert, sc); 1093 sc->sc_flags |= CBB_INSERTING; 1094 } 1095 } 1096 1097 return (1); 1098 } 1099 1100 /* 1101 * static int pccbbintr_function(struct pccbb_softc *sc) 1102 * 1103 * This function calls each interrupt handler registered at the 1104 * bridge. The interrupt handlers are called in registered order. 1105 */ 1106 static int 1107 pccbbintr_function(sc) 1108 struct pccbb_softc *sc; 1109 { 1110 int retval = 0, val; 1111 struct pccbb_intrhand_list *pil; 1112 int s, splchanged; 1113 1114 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1115 pil = LIST_NEXT(pil, pil_next)) { 1116 /* 1117 * XXX priority change. gross. I use if-else 1118 * sentense instead of switch-case sentense because of 1119 * avoiding duplicate case value error. More than one 1120 * IPL_XXX use same value. It depends on 1121 * implimentation. 1122 */ 1123 splchanged = 1; 1124 if (pil->pil_level == IPL_SERIAL) { 1125 s = splserial(); 1126 } else if (pil->pil_level == IPL_HIGH) { 1127 s = splhigh(); 1128 } else if (pil->pil_level == IPL_CLOCK) { 1129 s = splclock(); 1130 } else if (pil->pil_level == IPL_AUDIO) { 1131 s = splaudio(); 1132 } else if (pil->pil_level == IPL_VM) { 1133 s = splvm(); 1134 } else if (pil->pil_level == IPL_TTY) { 1135 s = spltty(); 1136 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1137 s = splsoftserial(); 1138 } else if (pil->pil_level == IPL_NET) { 1139 s = splnet(); 1140 } else { 1141 s = 0; /* XXX: gcc */ 1142 splchanged = 0; 1143 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1144 } 1145 1146 val = (*pil->pil_func)(pil->pil_arg); 1147 1148 if (splchanged != 0) { 1149 splx(s); 1150 } 1151 1152 retval = retval == 1 ? 1 : 1153 retval == 0 ? val : val != 0 ? val : retval; 1154 } 1155 1156 return retval; 1157 } 1158 1159 static void 1160 pci113x_insert(arg) 1161 void *arg; 1162 { 1163 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1164 u_int32_t sockevent, sockstate; 1165 1166 if (!(sc->sc_flags & CBB_INSERTING)) { 1167 /* We add a card only under inserting state. */ 1168 return; 1169 } 1170 sc->sc_flags &= ~CBB_INSERTING; 1171 1172 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1173 CB_SOCKET_EVENT); 1174 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1175 CB_SOCKET_STAT); 1176 1177 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1178 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1179 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1180 sc->sc_flags |= CBB_CARDEXIST; 1181 /* call pccard interrupt handler here */ 1182 if (sockstate & CB_SOCKET_STAT_16BIT) { 1183 /* 16-bit card found */ 1184 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1185 cardslot_event_throw(sc->sc_csc, 1186 CARDSLOT_EVENT_INSERTION_16); 1187 } else if (sockstate & CB_SOCKET_STAT_CB) { 1188 /* cardbus card found */ 1189 /* cardbus_attach_card(sc->sc_csc); */ 1190 cardslot_event_throw(sc->sc_csc, 1191 CARDSLOT_EVENT_INSERTION_CB); 1192 } else { 1193 /* who are you? */ 1194 } 1195 } else { 1196 callout_reset(&sc->sc_insert_ch, hz / 10, 1197 pci113x_insert, sc); 1198 } 1199 } 1200 1201 #define PCCBB_PCMCIA_OFFSET 0x800 1202 static u_int8_t 1203 pccbb_pcmcia_read(ph, reg) 1204 struct pcic_handle *ph; 1205 int reg; 1206 { 1207 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1208 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1209 1210 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1211 PCCBB_PCMCIA_OFFSET + reg); 1212 } 1213 1214 static void 1215 pccbb_pcmcia_write(ph, reg, val) 1216 struct pcic_handle *ph; 1217 int reg; 1218 u_int8_t val; 1219 { 1220 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1221 val); 1222 1223 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1224 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1225 } 1226 1227 /* 1228 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1229 */ 1230 STATIC int 1231 pccbb_ctrl(ct, command) 1232 cardbus_chipset_tag_t ct; 1233 int command; 1234 { 1235 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1236 1237 switch (command) { 1238 case CARDBUS_CD: 1239 if (2 == pccbb_detect_card(sc)) { 1240 int retval = 0; 1241 int status = cb_detect_voltage(sc); 1242 if (PCCARD_VCC_5V & status) { 1243 retval |= CARDBUS_5V_CARD; 1244 } 1245 if (PCCARD_VCC_3V & status) { 1246 retval |= CARDBUS_3V_CARD; 1247 } 1248 if (PCCARD_VCC_XV & status) { 1249 retval |= CARDBUS_XV_CARD; 1250 } 1251 if (PCCARD_VCC_YV & status) { 1252 retval |= CARDBUS_YV_CARD; 1253 } 1254 return retval; 1255 } else { 1256 return 0; 1257 } 1258 case CARDBUS_RESET: 1259 return cb_reset(sc); 1260 case CARDBUS_IO_ENABLE: /* fallthrough */ 1261 case CARDBUS_IO_DISABLE: /* fallthrough */ 1262 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1263 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1264 case CARDBUS_BM_ENABLE: /* fallthrough */ 1265 case CARDBUS_BM_DISABLE: /* fallthrough */ 1266 /* XXX: I think we don't need to call this function below. */ 1267 return pccbb_cardenable(sc, command); 1268 } 1269 1270 return 0; 1271 } 1272 1273 /* 1274 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1275 * This function returns true when it succeeds and returns false when 1276 * it fails. 1277 */ 1278 STATIC int 1279 pccbb_power(ct, command) 1280 cardbus_chipset_tag_t ct; 1281 int command; 1282 { 1283 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1284 1285 u_int32_t status, sock_ctrl, reg_ctrl; 1286 bus_space_tag_t memt = sc->sc_base_memt; 1287 bus_space_handle_t memh = sc->sc_base_memh; 1288 1289 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1290 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1291 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1292 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1293 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1294 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1295 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1296 "UNKNOWN", 1297 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1298 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1299 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1300 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1301 "UNKNOWN", command)); 1302 1303 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1304 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1305 1306 switch (command & CARDBUS_VCCMASK) { 1307 case CARDBUS_VCC_UC: 1308 break; 1309 case CARDBUS_VCC_5V: 1310 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1311 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1312 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1313 } else { 1314 printf("%s: BAD voltage request: no 5 V card\n", 1315 sc->sc_dev.dv_xname); 1316 return 0; 1317 } 1318 break; 1319 case CARDBUS_VCC_3V: 1320 if (CB_SOCKET_STAT_3VCARD & status) { 1321 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1322 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1323 } else { 1324 printf("%s: BAD voltage request: no 3.3 V card\n", 1325 sc->sc_dev.dv_xname); 1326 return 0; 1327 } 1328 break; 1329 case CARDBUS_VCC_0V: 1330 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1331 break; 1332 default: 1333 return 0; /* power NEVER changed */ 1334 } 1335 1336 switch (command & CARDBUS_VPPMASK) { 1337 case CARDBUS_VPP_UC: 1338 break; 1339 case CARDBUS_VPP_0V: 1340 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1341 break; 1342 case CARDBUS_VPP_VCC: 1343 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1344 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1345 break; 1346 case CARDBUS_VPP_12V: 1347 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1348 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1349 break; 1350 } 1351 1352 #if 0 1353 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1354 #endif 1355 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1356 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1357 1358 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1359 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1360 sc->sc_dev.dv_xname, sock_ctrl, status); 1361 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1362 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1363 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1364 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1365 #if 0 1366 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, 1367 CB_SOCKET_FORCE_BADVCC); 1368 #endif 1369 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1370 CB_SOCKET_STAT)); 1371 return 0; 1372 } 1373 1374 if (sc->sc_chipset == CB_TOPIC97) { 1375 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1376 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1377 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1378 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1379 else 1380 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1381 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1382 } 1383 1384 #if 0 1385 /* 1386 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1387 * time is 20 ms, some PC-Card bridge requires longer duration. 1388 */ 1389 #if 0 /* XXX called on interrupt context */ 1390 DELAY_MS(300, sc); 1391 #else 1392 delay(300 * 1000); 1393 #endif 1394 #endif 1395 1396 return 1; /* power changed correctly */ 1397 } 1398 1399 #if defined CB_PCMCIA_POLL 1400 struct cb_poll_str { 1401 void *arg; 1402 int (*func) __P((void *)); 1403 int level; 1404 pccard_chipset_tag_t ct; 1405 int count; 1406 struct callout poll_ch; 1407 }; 1408 1409 static struct cb_poll_str cb_poll[10]; 1410 static int cb_poll_n = 0; 1411 1412 static void cb_pcmcia_poll __P((void *arg)); 1413 1414 static void 1415 cb_pcmcia_poll(arg) 1416 void *arg; 1417 { 1418 struct cb_poll_str *poll = arg; 1419 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1420 struct pccbb_softc *sc = psc->cpc_parent; 1421 int s; 1422 u_int32_t spsr; /* socket present-state reg */ 1423 1424 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1425 switch (poll->level) { 1426 case IPL_NET: 1427 s = splnet(); 1428 break; 1429 case IPL_BIO: 1430 s = splbio(); 1431 break; 1432 case IPL_TTY: /* fallthrough */ 1433 default: 1434 s = spltty(); 1435 break; 1436 } 1437 1438 spsr = 1439 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1440 CB_SOCKET_STAT); 1441 1442 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1443 if (!(spsr & 0x40)) { /* CINT low */ 1444 #else 1445 if (1) { 1446 #endif 1447 if ((*poll->func) (poll->arg) == 1) { 1448 ++poll->count; 1449 printf("intr: reported from poller, 0x%x\n", spsr); 1450 #if defined LEVEL2 1451 } else { 1452 printf("intr: miss! 0x%x\n", spsr); 1453 #endif 1454 } 1455 } 1456 splx(s); 1457 } 1458 #endif /* defined CB_PCMCIA_POLL */ 1459 1460 /* 1461 * static int pccbb_detect_card(struct pccbb_softc *sc) 1462 * return value: 0 if no card exists. 1463 * 1 if 16-bit card exists. 1464 * 2 if cardbus card exists. 1465 */ 1466 static int 1467 pccbb_detect_card(sc) 1468 struct pccbb_softc *sc; 1469 { 1470 bus_space_handle_t base_memh = sc->sc_base_memh; 1471 bus_space_tag_t base_memt = sc->sc_base_memt; 1472 u_int32_t sockstat = 1473 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1474 int retval = 0; 1475 1476 /* CD1 and CD2 asserted */ 1477 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1478 /* card must be present */ 1479 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1480 /* NOTACARD DEASSERTED */ 1481 if (CB_SOCKET_STAT_CB & sockstat) { 1482 /* CardBus mode */ 1483 retval = 2; 1484 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1485 /* 16-bit mode */ 1486 retval = 1; 1487 } 1488 } 1489 } 1490 return retval; 1491 } 1492 1493 /* 1494 * STATIC int cb_reset(struct pccbb_softc *sc) 1495 * This function resets CardBus card. 1496 */ 1497 STATIC int 1498 cb_reset(sc) 1499 struct pccbb_softc *sc; 1500 { 1501 /* 1502 * Reset Assert at least 20 ms 1503 * Some machines request longer duration. 1504 */ 1505 int reset_duration = 1506 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1507 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1508 1509 /* Reset bit Assert (bit 6 at 0x3E) */ 1510 bcr |= CB_BCR_RESET_ENABLE; 1511 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1512 DELAY_MS(reset_duration, sc); 1513 1514 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1515 /* Reset bit Deassert (bit 6 at 0x3E) */ 1516 bcr &= ~CB_BCR_RESET_ENABLE; 1517 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1518 DELAY_MS(reset_duration, sc); 1519 } 1520 /* No card found on the slot. Keep Reset. */ 1521 return 1; 1522 } 1523 1524 /* 1525 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1526 * This function detect card Voltage. 1527 */ 1528 STATIC int 1529 cb_detect_voltage(sc) 1530 struct pccbb_softc *sc; 1531 { 1532 u_int32_t psr; /* socket present-state reg */ 1533 bus_space_tag_t iot = sc->sc_base_memt; 1534 bus_space_handle_t ioh = sc->sc_base_memh; 1535 int vol = PCCARD_VCC_UKN; /* set 0 */ 1536 1537 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1538 1539 if (0x400u & psr) { 1540 vol |= PCCARD_VCC_5V; 1541 } 1542 if (0x800u & psr) { 1543 vol |= PCCARD_VCC_3V; 1544 } 1545 1546 return vol; 1547 } 1548 1549 STATIC int 1550 cbbprint(aux, pcic) 1551 void *aux; 1552 const char *pcic; 1553 { 1554 /* 1555 struct cbslot_attach_args *cba = aux; 1556 1557 if (cba->cba_slot >= 0) { 1558 aprint_normal(" slot %d", cba->cba_slot); 1559 } 1560 */ 1561 return UNCONF; 1562 } 1563 1564 /* 1565 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1566 * This function enables and disables the card 1567 */ 1568 STATIC int 1569 pccbb_cardenable(sc, function) 1570 struct pccbb_softc *sc; 1571 int function; 1572 { 1573 u_int32_t command = 1574 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1575 1576 DPRINTF(("pccbb_cardenable:")); 1577 switch (function) { 1578 case CARDBUS_IO_ENABLE: 1579 command |= PCI_COMMAND_IO_ENABLE; 1580 break; 1581 case CARDBUS_IO_DISABLE: 1582 command &= ~PCI_COMMAND_IO_ENABLE; 1583 break; 1584 case CARDBUS_MEM_ENABLE: 1585 command |= PCI_COMMAND_MEM_ENABLE; 1586 break; 1587 case CARDBUS_MEM_DISABLE: 1588 command &= ~PCI_COMMAND_MEM_ENABLE; 1589 break; 1590 case CARDBUS_BM_ENABLE: 1591 command |= PCI_COMMAND_MASTER_ENABLE; 1592 break; 1593 case CARDBUS_BM_DISABLE: 1594 command &= ~PCI_COMMAND_MASTER_ENABLE; 1595 break; 1596 default: 1597 return 0; 1598 } 1599 1600 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1601 DPRINTF((" command reg 0x%x\n", command)); 1602 return 1; 1603 } 1604 1605 #if !rbus 1606 /* 1607 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1608 */ 1609 static int 1610 pccbb_io_open(ct, win, start, end) 1611 cardbus_chipset_tag_t ct; 1612 int win; 1613 u_int32_t start, end; 1614 { 1615 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1616 int basereg; 1617 int limitreg; 1618 1619 if ((win < 0) || (win > 2)) { 1620 #if defined DIAGNOSTIC 1621 printf("cardbus_io_open: window out of range %d\n", win); 1622 #endif 1623 return 0; 1624 } 1625 1626 basereg = win * 8 + 0x2c; 1627 limitreg = win * 8 + 0x30; 1628 1629 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1630 start, basereg, end, limitreg)); 1631 1632 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1633 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1634 return 1; 1635 } 1636 1637 /* 1638 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1639 */ 1640 static int 1641 pccbb_io_close(ct, win) 1642 cardbus_chipset_tag_t ct; 1643 int win; 1644 { 1645 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1646 int basereg; 1647 int limitreg; 1648 1649 if ((win < 0) || (win > 2)) { 1650 #if defined DIAGNOSTIC 1651 printf("cardbus_io_close: window out of range %d\n", win); 1652 #endif 1653 return 0; 1654 } 1655 1656 basereg = win * 8 + 0x2c; 1657 limitreg = win * 8 + 0x30; 1658 1659 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1660 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1661 return 1; 1662 } 1663 1664 /* 1665 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1666 */ 1667 static int 1668 pccbb_mem_open(ct, win, start, end) 1669 cardbus_chipset_tag_t ct; 1670 int win; 1671 u_int32_t start, end; 1672 { 1673 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1674 int basereg; 1675 int limitreg; 1676 1677 if ((win < 0) || (win > 2)) { 1678 #if defined DIAGNOSTIC 1679 printf("cardbus_mem_open: window out of range %d\n", win); 1680 #endif 1681 return 0; 1682 } 1683 1684 basereg = win * 8 + 0x1c; 1685 limitreg = win * 8 + 0x20; 1686 1687 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1688 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1689 return 1; 1690 } 1691 1692 /* 1693 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1694 */ 1695 static int 1696 pccbb_mem_close(ct, win) 1697 cardbus_chipset_tag_t ct; 1698 int win; 1699 { 1700 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1701 int basereg; 1702 int limitreg; 1703 1704 if ((win < 0) || (win > 2)) { 1705 #if defined DIAGNOSTIC 1706 printf("cardbus_mem_close: window out of range %d\n", win); 1707 #endif 1708 return 0; 1709 } 1710 1711 basereg = win * 8 + 0x1c; 1712 limitreg = win * 8 + 0x20; 1713 1714 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1715 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1716 return 1; 1717 } 1718 #endif 1719 1720 /* 1721 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1722 * int irq, 1723 * int level, 1724 * int (* func) __P((void *)), 1725 * void *arg) 1726 * 1727 * This function registers an interrupt handler at the bridge, in 1728 * order not to call the interrupt handlers of child devices when 1729 * a card-deletion interrupt occurs. 1730 * 1731 * The arguments irq and level are not used. 1732 */ 1733 static void * 1734 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1735 cardbus_chipset_tag_t ct; 1736 int irq, level; 1737 int (*func) __P((void *)); 1738 void *arg; 1739 { 1740 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1741 1742 return pccbb_intr_establish(sc, irq, level, func, arg); 1743 } 1744 1745 1746 /* 1747 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1748 * void *ih) 1749 * 1750 * This function removes an interrupt handler pointed by ih. 1751 */ 1752 static void 1753 pccbb_cb_intr_disestablish(ct, ih) 1754 cardbus_chipset_tag_t ct; 1755 void *ih; 1756 { 1757 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1758 1759 pccbb_intr_disestablish(sc, ih); 1760 } 1761 1762 1763 void 1764 pccbb_intr_route(sc) 1765 struct pccbb_softc *sc; 1766 { 1767 pcireg_t reg; 1768 1769 /* initialize bridge intr routing */ 1770 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1771 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1772 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1773 1774 switch (sc->sc_chipset) { 1775 case CB_TI113X: 1776 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1777 /* functional intr enabled */ 1778 reg |= PCI113X_CBCTRL_PCI_INTR; 1779 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1780 break; 1781 default: 1782 break; 1783 } 1784 } 1785 1786 /* 1787 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1788 * int irq, 1789 * int level, 1790 * int (* func) __P((void *)), 1791 * void *arg) 1792 * 1793 * This function registers an interrupt handler at the bridge, in 1794 * order not to call the interrupt handlers of child devices when 1795 * a card-deletion interrupt occurs. 1796 * 1797 * The arguments irq is not used because pccbb selects intr vector. 1798 */ 1799 static void * 1800 pccbb_intr_establish(sc, irq, level, func, arg) 1801 struct pccbb_softc *sc; 1802 int irq, level; 1803 int (*func) __P((void *)); 1804 void *arg; 1805 { 1806 struct pccbb_intrhand_list *pil, *newpil; 1807 1808 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1809 1810 if (LIST_EMPTY(&sc->sc_pil)) { 1811 pccbb_intr_route(sc); 1812 } 1813 1814 /* 1815 * Allocate a room for interrupt handler structure. 1816 */ 1817 if (NULL == (newpil = 1818 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1819 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1820 return NULL; 1821 } 1822 1823 newpil->pil_func = func; 1824 newpil->pil_arg = arg; 1825 newpil->pil_level = level; 1826 1827 if (LIST_EMPTY(&sc->sc_pil)) { 1828 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1829 } else { 1830 for (pil = LIST_FIRST(&sc->sc_pil); 1831 LIST_NEXT(pil, pil_next) != NULL; 1832 pil = LIST_NEXT(pil, pil_next)); 1833 LIST_INSERT_AFTER(pil, newpil, pil_next); 1834 } 1835 1836 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1837 LIST_FIRST(&sc->sc_pil))); 1838 1839 return newpil; 1840 } 1841 1842 /* 1843 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1844 * void *ih) 1845 * 1846 * This function removes an interrupt handler pointed by ih. ih 1847 * should be the value returned by cardbus_intr_establish() or 1848 * NULL. 1849 * 1850 * When ih is NULL, this function will do nothing. 1851 */ 1852 static void 1853 pccbb_intr_disestablish(sc, ih) 1854 struct pccbb_softc *sc; 1855 void *ih; 1856 { 1857 struct pccbb_intrhand_list *pil; 1858 pcireg_t reg; 1859 1860 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1861 LIST_FIRST(&sc->sc_pil))); 1862 1863 if (ih == NULL) { 1864 /* intr handler is not set */ 1865 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1866 return; 1867 } 1868 1869 #ifdef DIAGNOSTIC 1870 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1871 pil = LIST_NEXT(pil, pil_next)) { 1872 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1873 if (pil == ih) { 1874 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1875 break; 1876 } 1877 } 1878 if (pil == NULL) { 1879 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1880 sc->sc_dev.dv_xname, ih); 1881 } 1882 #endif 1883 1884 pil = (struct pccbb_intrhand_list *)ih; 1885 LIST_REMOVE(pil, pil_next); 1886 free(pil, M_DEVBUF); 1887 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1888 1889 if (LIST_EMPTY(&sc->sc_pil)) { 1890 /* No interrupt handlers */ 1891 1892 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1893 1894 /* stop routing PCI intr */ 1895 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1896 reg |= CB_BCR_INTR_IREQ_ENABLE; 1897 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1898 1899 switch (sc->sc_chipset) { 1900 case CB_TI113X: 1901 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1902 /* functional intr disabled */ 1903 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1904 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1905 break; 1906 default: 1907 break; 1908 } 1909 } 1910 } 1911 1912 #if defined SHOW_REGS 1913 static void 1914 cb_show_regs(pc, tag, memt, memh) 1915 pci_chipset_tag_t pc; 1916 pcitag_t tag; 1917 bus_space_tag_t memt; 1918 bus_space_handle_t memh; 1919 { 1920 int i; 1921 printf("PCI config regs:"); 1922 for (i = 0; i < 0x50; i += 4) { 1923 if (i % 16 == 0) { 1924 printf("\n 0x%02x:", i); 1925 } 1926 printf(" %08x", pci_conf_read(pc, tag, i)); 1927 } 1928 for (i = 0x80; i < 0xb0; i += 4) { 1929 if (i % 16 == 0) { 1930 printf("\n 0x%02x:", i); 1931 } 1932 printf(" %08x", pci_conf_read(pc, tag, i)); 1933 } 1934 1935 if (memh == 0) { 1936 printf("\n"); 1937 return; 1938 } 1939 1940 printf("\nsocket regs:"); 1941 for (i = 0; i <= 0x10; i += 0x04) { 1942 printf(" %08x", bus_space_read_4(memt, memh, i)); 1943 } 1944 printf("\nExCA regs:"); 1945 for (i = 0; i < 0x08; ++i) { 1946 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1947 } 1948 printf("\n"); 1949 return; 1950 } 1951 #endif 1952 1953 /* 1954 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1955 * int busno, int devno, int function) 1956 * This is the function to make a tag to access config space of 1957 * a CardBus Card. It works same as pci_conf_read. 1958 */ 1959 static cardbustag_t 1960 pccbb_make_tag(cc, busno, devno, function) 1961 cardbus_chipset_tag_t cc; 1962 int busno, devno, function; 1963 { 1964 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1965 1966 return pci_make_tag(sc->sc_pc, busno, devno, function); 1967 } 1968 1969 static void 1970 pccbb_free_tag(cc, tag) 1971 cardbus_chipset_tag_t cc; 1972 cardbustag_t tag; 1973 { 1974 } 1975 1976 /* 1977 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1978 * cardbustag_t tag, int offset) 1979 * This is the function to read the config space of a CardBus Card. 1980 * It works same as pci_conf_read. 1981 */ 1982 static cardbusreg_t 1983 pccbb_conf_read(cc, tag, offset) 1984 cardbus_chipset_tag_t cc; 1985 cardbustag_t tag; 1986 int offset; /* register offset */ 1987 { 1988 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1989 1990 return pci_conf_read(sc->sc_pc, tag, offset); 1991 } 1992 1993 /* 1994 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1995 * int offs, cardbusreg_t val) 1996 * This is the function to write the config space of a CardBus Card. 1997 * It works same as pci_conf_write. 1998 */ 1999 static void 2000 pccbb_conf_write(cc, tag, reg, val) 2001 cardbus_chipset_tag_t cc; 2002 cardbustag_t tag; 2003 int reg; /* register offset */ 2004 cardbusreg_t val; 2005 { 2006 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2007 2008 pci_conf_write(sc->sc_pc, tag, reg, val); 2009 } 2010 2011 #if 0 2012 STATIC int 2013 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2014 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2015 int speed, int flags, 2016 bus_space_handle_t * iohp) 2017 #endif 2018 /* 2019 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2020 * bus_addr_t start, bus_size_t size, 2021 * bus_size_t align, 2022 * struct pcmcia_io_handle *pcihp 2023 * 2024 * This function only allocates I/O region for pccard. This function 2025 * never maps the allocated region to pccard I/O area. 2026 * 2027 * XXX: The interface of this function is not very good, I believe. 2028 */ 2029 STATIC int 2030 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2031 pcmcia_chipset_handle_t pch; 2032 bus_addr_t start; /* start address */ 2033 bus_size_t size; 2034 bus_size_t align; 2035 struct pcmcia_io_handle *pcihp; 2036 { 2037 struct pcic_handle *ph = (struct pcic_handle *)pch; 2038 bus_addr_t ioaddr; 2039 int flags = 0; 2040 bus_space_tag_t iot; 2041 bus_space_handle_t ioh; 2042 bus_addr_t mask; 2043 #if rbus 2044 rbus_tag_t rb; 2045 #endif 2046 if (align == 0) { 2047 align = size; /* XXX: funny??? */ 2048 } 2049 2050 if (start != 0) { 2051 /* XXX: assume all card decode lower 10 bits by its hardware */ 2052 mask = 0x3ff; 2053 /* enforce to use only masked address */ 2054 start &= mask; 2055 } else { 2056 /* 2057 * calculate mask: 2058 * 1. get the most significant bit of size (call it msb). 2059 * 2. compare msb with the value of size. 2060 * 3. if size is larger, shift msb left once. 2061 * 4. obtain mask value to decrement msb. 2062 */ 2063 bus_size_t size_tmp = size; 2064 int shifts = 0; 2065 2066 mask = 1; 2067 while (size_tmp) { 2068 ++shifts; 2069 size_tmp >>= 1; 2070 } 2071 mask = (1 << shifts); 2072 if (mask < size) { 2073 mask <<= 1; 2074 } 2075 --mask; 2076 } 2077 2078 /* 2079 * Allocate some arbitrary I/O space. 2080 */ 2081 2082 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2083 2084 #if rbus 2085 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2086 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2087 return 1; 2088 } 2089 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2090 (u_long) ioaddr, (u_long) size)); 2091 #else 2092 if (start) { 2093 ioaddr = start; 2094 if (bus_space_map(iot, start, size, 0, &ioh)) { 2095 return 1; 2096 } 2097 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2098 (u_long) ioaddr, (u_long) size)); 2099 } else { 2100 flags |= PCMCIA_IO_ALLOCATED; 2101 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2102 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2103 size, align, 0, 0, &ioaddr, &ioh)) { 2104 /* No room be able to be get. */ 2105 return 1; 2106 } 2107 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2108 (u_long) ioaddr, (u_long) size)); 2109 } 2110 #endif 2111 2112 pcihp->iot = iot; 2113 pcihp->ioh = ioh; 2114 pcihp->addr = ioaddr; 2115 pcihp->size = size; 2116 pcihp->flags = flags; 2117 2118 return 0; 2119 } 2120 2121 /* 2122 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2123 * struct pcmcia_io_handle *pcihp) 2124 * 2125 * This function only frees I/O region for pccard. 2126 * 2127 * XXX: The interface of this function is not very good, I believe. 2128 */ 2129 void 2130 pccbb_pcmcia_io_free(pch, pcihp) 2131 pcmcia_chipset_handle_t pch; 2132 struct pcmcia_io_handle *pcihp; 2133 { 2134 #if !rbus 2135 bus_space_tag_t iot = pcihp->iot; 2136 #endif 2137 bus_space_handle_t ioh = pcihp->ioh; 2138 bus_size_t size = pcihp->size; 2139 2140 #if rbus 2141 struct pccbb_softc *sc = 2142 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2143 rbus_tag_t rb = sc->sc_rbus_iot; 2144 2145 rbus_space_free(rb, ioh, size, NULL); 2146 #else 2147 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2148 bus_space_free(iot, ioh, size); 2149 else 2150 bus_space_unmap(iot, ioh, size); 2151 #endif 2152 } 2153 2154 /* 2155 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2156 * bus_addr_t offset, bus_size_t size, 2157 * struct pcmcia_io_handle *pcihp, 2158 * int *windowp) 2159 * 2160 * This function maps the allocated I/O region to pccard. This function 2161 * never allocates any I/O region for pccard I/O area. I don't 2162 * understand why the original authors of pcmciabus separated alloc and 2163 * map. I believe the two must be unite. 2164 * 2165 * XXX: no wait timing control? 2166 */ 2167 int 2168 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2169 pcmcia_chipset_handle_t pch; 2170 int width; 2171 bus_addr_t offset; 2172 bus_size_t size; 2173 struct pcmcia_io_handle *pcihp; 2174 int *windowp; 2175 { 2176 struct pcic_handle *ph = (struct pcic_handle *)pch; 2177 bus_addr_t ioaddr = pcihp->addr + offset; 2178 int i, win; 2179 #if defined CBB_DEBUG 2180 static char *width_names[] = { "dynamic", "io8", "io16" }; 2181 #endif 2182 2183 /* Sanity check I/O handle. */ 2184 2185 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2186 panic("pccbb_pcmcia_io_map iot is bogus"); 2187 } 2188 2189 /* XXX Sanity check offset/size. */ 2190 2191 win = -1; 2192 for (i = 0; i < PCIC_IO_WINS; i++) { 2193 if ((ph->ioalloc & (1 << i)) == 0) { 2194 win = i; 2195 ph->ioalloc |= (1 << i); 2196 break; 2197 } 2198 } 2199 2200 if (win == -1) { 2201 return 1; 2202 } 2203 2204 *windowp = win; 2205 2206 /* XXX this is pretty gross */ 2207 2208 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2209 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2210 2211 /* XXX wtf is this doing here? */ 2212 2213 #if 0 2214 printf(" port 0x%lx", (u_long) ioaddr); 2215 if (size > 1) { 2216 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2217 } 2218 #endif 2219 2220 ph->io[win].addr = ioaddr; 2221 ph->io[win].size = size; 2222 ph->io[win].width = width; 2223 2224 /* actual dirty register-value changing in the function below. */ 2225 pccbb_pcmcia_do_io_map(ph, win); 2226 2227 return 0; 2228 } 2229 2230 /* 2231 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2232 * 2233 * This function changes register-value to map I/O region for pccard. 2234 */ 2235 static void 2236 pccbb_pcmcia_do_io_map(ph, win) 2237 struct pcic_handle *ph; 2238 int win; 2239 { 2240 static u_int8_t pcic_iowidth[3] = { 2241 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2242 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2243 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2244 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2245 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2246 }; 2247 2248 #define PCIC_SIA_START_LOW 0 2249 #define PCIC_SIA_START_HIGH 1 2250 #define PCIC_SIA_STOP_LOW 2 2251 #define PCIC_SIA_STOP_HIGH 3 2252 2253 int regbase_win = 0x8 + win * 0x04; 2254 u_int8_t ioctl, enable; 2255 2256 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2257 "width %d\n", win, (unsigned long)ph->io[win].addr, 2258 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2259 2260 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2261 ph->io[win].addr & 0xff); 2262 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2263 (ph->io[win].addr >> 8) & 0xff); 2264 2265 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2266 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2267 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2268 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2269 2270 ioctl = Pcic_read(ph, PCIC_IOCTL); 2271 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2272 switch (win) { 2273 case 0: 2274 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2275 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2276 PCIC_IOCTL_IO0_DATASIZE_MASK); 2277 ioctl |= pcic_iowidth[ph->io[win].width]; 2278 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2279 break; 2280 case 1: 2281 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2282 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2283 PCIC_IOCTL_IO1_DATASIZE_MASK); 2284 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2285 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2286 break; 2287 } 2288 Pcic_write(ph, PCIC_IOCTL, ioctl); 2289 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2290 #if defined CBB_DEBUG 2291 { 2292 u_int8_t start_low = 2293 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2294 u_int8_t start_high = 2295 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2296 u_int8_t stop_low = 2297 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2298 u_int8_t stop_high = 2299 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2300 printf 2301 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2302 start_low, start_high, stop_low, stop_high, ioctl, enable); 2303 } 2304 #endif 2305 } 2306 2307 /* 2308 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2309 * 2310 * This function unmaps I/O region. No return value. 2311 */ 2312 STATIC void 2313 pccbb_pcmcia_io_unmap(pch, win) 2314 pcmcia_chipset_handle_t pch; 2315 int win; 2316 { 2317 struct pcic_handle *ph = (struct pcic_handle *)pch; 2318 int reg; 2319 2320 if (win >= PCIC_IO_WINS || win < 0) { 2321 panic("pccbb_pcmcia_io_unmap: window out of range"); 2322 } 2323 2324 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2325 switch (win) { 2326 case 0: 2327 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2328 break; 2329 case 1: 2330 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2331 break; 2332 } 2333 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2334 2335 ph->ioalloc &= ~(1 << win); 2336 } 2337 2338 static int 2339 pccbb_pcmcia_wait_ready(ph) 2340 struct pcic_handle *ph; 2341 { 2342 u_int8_t stat; 2343 int i; 2344 2345 /* wait an initial 10ms for quick cards */ 2346 stat = Pcic_read(ph, PCIC_IF_STATUS); 2347 if (stat & PCIC_IF_STATUS_READY) 2348 return (0); 2349 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2350 for (i = 0; i < 50; i++) { 2351 stat = Pcic_read(ph, PCIC_IF_STATUS); 2352 if (stat & PCIC_IF_STATUS_READY) 2353 return (0); 2354 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2355 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2356 return (ENXIO); 2357 /* wait .1s (100ms) each iteration now */ 2358 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2359 } 2360 2361 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2362 return (EWOULDBLOCK); 2363 } 2364 2365 /* 2366 * Perform long (msec order) delay. 2367 */ 2368 static void 2369 pccbb_pcmcia_delay(ph, timo, wmesg) 2370 struct pcic_handle *ph; 2371 int timo; /* in ms. must not be zero */ 2372 const char *wmesg; 2373 { 2374 2375 #ifdef DIAGNOSTIC 2376 if (timo <= 0) 2377 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2378 if (!curlwp) 2379 panic("pccbb_pcmcia_delay: called in interrupt context"); 2380 #if 0 2381 if (!ph->event_thread) 2382 panic("pccbb_pcmcia_delay: no event thread"); 2383 #endif 2384 #endif 2385 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2386 wmesg, h->event_thread, timo)); 2387 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2388 } 2389 2390 /* 2391 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2392 * 2393 * This function enables the card. All information is stored in 2394 * the first argument, pcmcia_chipset_handle_t. 2395 */ 2396 STATIC void 2397 pccbb_pcmcia_socket_enable(pch) 2398 pcmcia_chipset_handle_t pch; 2399 { 2400 struct pcic_handle *ph = (struct pcic_handle *)pch; 2401 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2402 pcireg_t spsr; 2403 int voltage; 2404 int win; 2405 u_int8_t power, intr; 2406 #ifdef DIAGNOSTIC 2407 int reg; 2408 #endif 2409 2410 /* this bit is mostly stolen from pcic_attach_card */ 2411 2412 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2413 2414 /* get card Vcc info */ 2415 spsr = 2416 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2417 CB_SOCKET_STAT); 2418 if (spsr & CB_SOCKET_STAT_5VCARD) { 2419 DPRINTF(("5V card\n")); 2420 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2421 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2422 DPRINTF(("3V card\n")); 2423 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2424 } else { 2425 printf("?V card, 0x%x\n", spsr); /* XXX */ 2426 return; 2427 } 2428 2429 /* disable interrupts */ 2430 intr = Pcic_read(ph, PCIC_INTR); 2431 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2432 Pcic_write(ph, PCIC_INTR, intr); 2433 2434 /* zero out the address windows */ 2435 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2436 2437 /* disable socket: negate output enable bit and power off */ 2438 power = 0; 2439 Pcic_write(ph, PCIC_PWRCTL, power); 2440 2441 /* power down the socket to reset it, clear the card reset pin */ 2442 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2443 2444 /* now make sure we have reset# active */ 2445 intr &= ~PCIC_INTR_RESET; 2446 Pcic_write(ph, PCIC_INTR, intr); 2447 2448 if (pccbb_power(sc, voltage) == 0) 2449 return; 2450 2451 /* 2452 * wait 100ms until power raise (Tpr) and 20ms to become 2453 * stable (Tsu(Vcc)). 2454 * 2455 * some machines require some more time to be settled 2456 * (300ms is added here). 2457 */ 2458 pccbb_pcmcia_delay(ph, 100 + 20 + 300, "pccen1"); 2459 2460 power |= PCIC_PWRCTL_OE; 2461 Pcic_write(ph, PCIC_PWRCTL, power); 2462 2463 if (pccbb_power(sc, voltage) == 0) 2464 return; 2465 2466 /* 2467 * hold RESET at least 10us, this is a min allow for slop in 2468 * delay routine. 2469 */ 2470 pccbb_pcmcia_delay(ph, 20, "pccen1.5"); 2471 2472 /* clear the reset flag */ 2473 intr |= PCIC_INTR_RESET; 2474 Pcic_write(ph, PCIC_INTR, intr); 2475 2476 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2477 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2478 2479 #ifdef DIAGNOSTIC 2480 reg = Pcic_read(ph, PCIC_IF_STATUS); 2481 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2482 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2483 #endif 2484 2485 /* wait for the chip to finish initializing */ 2486 if (pccbb_pcmcia_wait_ready(ph)) { 2487 /* XXX return a failure status?? */ 2488 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2489 Pcic_write(ph, PCIC_PWRCTL, 0); 2490 return; 2491 } 2492 2493 /* reinstall all the memory and io mappings */ 2494 for (win = 0; win < PCIC_MEM_WINS; ++win) 2495 if (ph->memalloc & (1 << win)) 2496 pccbb_pcmcia_do_mem_map(ph, win); 2497 for (win = 0; win < PCIC_IO_WINS; ++win) 2498 if (ph->ioalloc & (1 << win)) 2499 pccbb_pcmcia_do_io_map(ph, win); 2500 } 2501 2502 /* 2503 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2504 * 2505 * This function disables the card. All information is stored in 2506 * the first argument, pcmcia_chipset_handle_t. 2507 */ 2508 STATIC void 2509 pccbb_pcmcia_socket_disable(pch) 2510 pcmcia_chipset_handle_t pch; 2511 { 2512 struct pcic_handle *ph = (struct pcic_handle *)pch; 2513 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2514 u_int8_t intr; 2515 2516 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2517 2518 /* disable interrupts */ 2519 intr = Pcic_read(ph, PCIC_INTR); 2520 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2521 Pcic_write(ph, PCIC_INTR, intr); 2522 2523 /* zero out the address windows */ 2524 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2525 2526 /* disable socket: negate output enable bit and power off */ 2527 Pcic_write(ph, PCIC_PWRCTL, 0); 2528 2529 /* power down the socket to reset it, clear the card reset pin */ 2530 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2531 2532 /* wait 300ms for power to fall */ 2533 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2534 } 2535 2536 STATIC void 2537 pccbb_pcmcia_socket_settype(pch, type) 2538 pcmcia_chipset_handle_t pch; 2539 int type; 2540 { 2541 struct pcic_handle *ph = (struct pcic_handle *)pch; 2542 u_int8_t intr; 2543 2544 /* set the card type */ 2545 2546 intr = Pcic_read(ph, PCIC_INTR); 2547 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2548 if (type == PCMCIA_IFTYPE_IO) 2549 intr |= PCIC_INTR_CARDTYPE_IO; 2550 else 2551 intr |= PCIC_INTR_CARDTYPE_MEM; 2552 Pcic_write(ph, PCIC_INTR, intr); 2553 2554 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2555 ph->ph_parent->dv_xname, ph->sock, 2556 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2557 } 2558 2559 /* 2560 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2561 * 2562 * This function detects whether a card is in the slot or not. 2563 * If a card is inserted, return 1. Otherwise, return 0. 2564 */ 2565 STATIC int 2566 pccbb_pcmcia_card_detect(pch) 2567 pcmcia_chipset_handle_t pch; 2568 { 2569 struct pcic_handle *ph = (struct pcic_handle *)pch; 2570 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2571 2572 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2573 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2574 } 2575 2576 #if 0 2577 STATIC int 2578 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2579 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2580 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2581 #endif 2582 /* 2583 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2584 * bus_size_t size, 2585 * struct pcmcia_mem_handle *pcmhp) 2586 * 2587 * This function only allocates memory region for pccard. This 2588 * function never maps the allocated region to pccard memory area. 2589 * 2590 * XXX: Why the argument of start address is not in? 2591 */ 2592 STATIC int 2593 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2594 pcmcia_chipset_handle_t pch; 2595 bus_size_t size; 2596 struct pcmcia_mem_handle *pcmhp; 2597 { 2598 struct pcic_handle *ph = (struct pcic_handle *)pch; 2599 bus_space_handle_t memh; 2600 bus_addr_t addr; 2601 bus_size_t sizepg; 2602 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2603 #if rbus 2604 rbus_tag_t rb; 2605 #endif 2606 2607 /* Check that the card is still there. */ 2608 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2609 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2610 return 1; 2611 2612 /* out of sc->memh, allocate as many pages as necessary */ 2613 2614 /* convert size to PCIC pages */ 2615 /* 2616 * This is not enough; when the requested region is on the page 2617 * boundaries, this may calculate wrong result. 2618 */ 2619 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2620 #if 0 2621 if (sizepg > PCIC_MAX_MEM_PAGES) { 2622 return 1; 2623 } 2624 #endif 2625 2626 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2627 return 1; 2628 } 2629 2630 addr = 0; /* XXX gcc -Wuninitialized */ 2631 2632 #if rbus 2633 rb = sc->sc_rbus_memt; 2634 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2635 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2636 &addr, &memh)) { 2637 return 1; 2638 } 2639 #else 2640 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2641 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2642 0, /* boundary */ 2643 0, /* flags */ 2644 &addr, &memh)) { 2645 return 1; 2646 } 2647 #endif 2648 2649 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2650 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2651 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2652 2653 pcmhp->memt = sc->sc_memt; 2654 pcmhp->memh = memh; 2655 pcmhp->addr = addr; 2656 pcmhp->size = size; 2657 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2658 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2659 pcmhp->mhandle = 0; 2660 /* No offset??? Funny. */ 2661 2662 return 0; 2663 } 2664 2665 /* 2666 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2667 * struct pcmcia_mem_handle *pcmhp) 2668 * 2669 * This function release the memory space allocated by the function 2670 * pccbb_pcmcia_mem_alloc(). 2671 */ 2672 STATIC void 2673 pccbb_pcmcia_mem_free(pch, pcmhp) 2674 pcmcia_chipset_handle_t pch; 2675 struct pcmcia_mem_handle *pcmhp; 2676 { 2677 #if rbus 2678 struct pcic_handle *ph = (struct pcic_handle *)pch; 2679 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2680 2681 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2682 #else 2683 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2684 #endif 2685 } 2686 2687 /* 2688 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2689 * 2690 * This function release the memory space allocated by the function 2691 * pccbb_pcmcia_mem_alloc(). 2692 */ 2693 STATIC void 2694 pccbb_pcmcia_do_mem_map(ph, win) 2695 struct pcic_handle *ph; 2696 int win; 2697 { 2698 int regbase_win; 2699 bus_addr_t phys_addr; 2700 bus_addr_t phys_end; 2701 2702 #define PCIC_SMM_START_LOW 0 2703 #define PCIC_SMM_START_HIGH 1 2704 #define PCIC_SMM_STOP_LOW 2 2705 #define PCIC_SMM_STOP_HIGH 3 2706 #define PCIC_CMA_LOW 4 2707 #define PCIC_CMA_HIGH 5 2708 2709 u_int8_t start_low, start_high = 0; 2710 u_int8_t stop_low, stop_high; 2711 u_int8_t off_low, off_high; 2712 u_int8_t mem_window; 2713 int reg; 2714 2715 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2716 int mem8 = 2717 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2718 || (kind == PCMCIA_MEM_ATTR); 2719 2720 regbase_win = 0x10 + win * 0x08; 2721 2722 phys_addr = ph->mem[win].addr; 2723 phys_end = phys_addr + ph->mem[win].size; 2724 2725 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2726 (unsigned long)phys_addr, (unsigned long)phys_end, 2727 (unsigned long)ph->mem[win].offset)); 2728 2729 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2730 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2731 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2732 2733 /* bit 19:12 */ 2734 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2735 /* bit 23:20 and bit 7 on */ 2736 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2737 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2738 /* bit 31:24, for 32-bit address */ 2739 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2740 2741 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2742 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2743 2744 if (((struct pccbb_softc *)ph-> 2745 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2746 Pcic_write(ph, 0x40 + win, mem_window); 2747 } 2748 2749 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2750 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2751 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2752 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2753 2754 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2755 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2756 2757 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2758 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2759 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2760 | ((kind == PCMCIA_MEM_ATTR) ? 2761 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2762 2763 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2764 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2765 2766 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2767 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2768 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2769 2770 #if defined CBB_DEBUG 2771 { 2772 int r1, r2, r3, r4, r5, r6, r7 = 0; 2773 2774 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2775 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2776 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2777 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2778 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2779 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2780 if (((struct pccbb_softc *)(ph-> 2781 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2782 r7 = Pcic_read(ph, 0x40 + win); 2783 } 2784 2785 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2786 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2787 if (((struct pccbb_softc *)(ph-> 2788 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2789 DPRINTF((" %02x", r7)); 2790 } 2791 DPRINTF(("\n")); 2792 } 2793 #endif 2794 } 2795 2796 /* 2797 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2798 * bus_addr_t card_addr, bus_size_t size, 2799 * struct pcmcia_mem_handle *pcmhp, 2800 * bus_addr_t *offsetp, int *windowp) 2801 * 2802 * This function maps memory space allocated by the function 2803 * pccbb_pcmcia_mem_alloc(). 2804 */ 2805 STATIC int 2806 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2807 pcmcia_chipset_handle_t pch; 2808 int kind; 2809 bus_addr_t card_addr; 2810 bus_size_t size; 2811 struct pcmcia_mem_handle *pcmhp; 2812 bus_addr_t *offsetp; 2813 int *windowp; 2814 { 2815 struct pcic_handle *ph = (struct pcic_handle *)pch; 2816 bus_addr_t busaddr; 2817 long card_offset; 2818 int win; 2819 2820 /* Check that the card is still there. */ 2821 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2822 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2823 return 1; 2824 2825 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2826 if ((ph->memalloc & (1 << win)) == 0) { 2827 ph->memalloc |= (1 << win); 2828 break; 2829 } 2830 } 2831 2832 if (win == PCIC_MEM_WINS) { 2833 return 1; 2834 } 2835 2836 *windowp = win; 2837 2838 /* XXX this is pretty gross */ 2839 2840 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2841 panic("pccbb_pcmcia_mem_map memt is bogus"); 2842 } 2843 2844 busaddr = pcmhp->addr; 2845 2846 /* 2847 * compute the address offset to the pcmcia address space for the 2848 * pcic. this is intentionally signed. The masks and shifts below 2849 * will cause TRT to happen in the pcic registers. Deal with making 2850 * sure the address is aligned, and return the alignment offset. 2851 */ 2852 2853 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2854 card_addr -= *offsetp; 2855 2856 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2857 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2858 (u_long) card_addr)); 2859 2860 /* 2861 * include the offset in the size, and decrement size by one, since 2862 * the hw wants start/stop 2863 */ 2864 size += *offsetp - 1; 2865 2866 card_offset = (((long)card_addr) - ((long)busaddr)); 2867 2868 ph->mem[win].addr = busaddr; 2869 ph->mem[win].size = size; 2870 ph->mem[win].offset = card_offset; 2871 ph->mem[win].kind = kind; 2872 2873 pccbb_pcmcia_do_mem_map(ph, win); 2874 2875 return 0; 2876 } 2877 2878 /* 2879 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2880 * int window) 2881 * 2882 * This function unmaps memory space which mapped by the function 2883 * pccbb_pcmcia_mem_map(). 2884 */ 2885 STATIC void 2886 pccbb_pcmcia_mem_unmap(pch, window) 2887 pcmcia_chipset_handle_t pch; 2888 int window; 2889 { 2890 struct pcic_handle *ph = (struct pcic_handle *)pch; 2891 int reg; 2892 2893 if (window >= PCIC_MEM_WINS) { 2894 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2895 } 2896 2897 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2898 reg &= ~(1 << window); 2899 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2900 2901 ph->memalloc &= ~(1 << window); 2902 } 2903 2904 #if defined PCCBB_PCMCIA_POLL 2905 struct pccbb_poll_str { 2906 void *arg; 2907 int (*func) __P((void *)); 2908 int level; 2909 struct pcic_handle *ph; 2910 int count; 2911 int num; 2912 struct callout poll_ch; 2913 }; 2914 2915 static struct pccbb_poll_str pccbb_poll[10]; 2916 static int pccbb_poll_n = 0; 2917 2918 static void pccbb_pcmcia_poll __P((void *arg)); 2919 2920 static void 2921 pccbb_pcmcia_poll(arg) 2922 void *arg; 2923 { 2924 struct pccbb_poll_str *poll = arg; 2925 struct pcic_handle *ph = poll->ph; 2926 struct pccbb_softc *sc = ph->sc; 2927 int s; 2928 u_int32_t spsr; /* socket present-state reg */ 2929 2930 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2931 switch (poll->level) { 2932 case IPL_NET: 2933 s = splnet(); 2934 break; 2935 case IPL_BIO: 2936 s = splbio(); 2937 break; 2938 case IPL_TTY: /* fallthrough */ 2939 default: 2940 s = spltty(); 2941 break; 2942 } 2943 2944 spsr = 2945 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2946 CB_SOCKET_STAT); 2947 2948 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2949 if (!(spsr & 0x40)) /* CINT low */ 2950 #else 2951 if (1) 2952 #endif 2953 { 2954 if ((*poll->func) (poll->arg) > 0) { 2955 ++poll->count; 2956 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2957 #if defined LEVEL2 2958 } else { 2959 printf("intr: miss! 0x%x\n", spsr); 2960 #endif 2961 } 2962 } 2963 splx(s); 2964 } 2965 #endif /* defined CB_PCMCIA_POLL */ 2966 2967 /* 2968 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2969 * struct pcmcia_function *pf, 2970 * int ipl, 2971 * int (*func)(void *), 2972 * void *arg); 2973 * 2974 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2975 */ 2976 STATIC void * 2977 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2978 pcmcia_chipset_handle_t pch; 2979 struct pcmcia_function *pf; 2980 int ipl; 2981 int (*func) __P((void *)); 2982 void *arg; 2983 { 2984 struct pcic_handle *ph = (struct pcic_handle *)pch; 2985 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2986 2987 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2988 /* what should I do? */ 2989 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2990 DPRINTF(("%s does not provide edge nor pulse " 2991 "interrupt\n", sc->sc_dev.dv_xname)); 2992 return NULL; 2993 } 2994 /* 2995 * XXX Noooooo! The interrupt flag must set properly!! 2996 * dumb pcmcia driver!! 2997 */ 2998 } 2999 3000 return pccbb_intr_establish(sc, 0, ipl, func, arg); 3001 } 3002 3003 /* 3004 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 3005 * void *ih) 3006 * 3007 * This function disables PC-Card interrupt. 3008 */ 3009 STATIC void 3010 pccbb_pcmcia_intr_disestablish(pch, ih) 3011 pcmcia_chipset_handle_t pch; 3012 void *ih; 3013 { 3014 struct pcic_handle *ph = (struct pcic_handle *)pch; 3015 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3016 3017 pccbb_intr_disestablish(sc, ih); 3018 } 3019 3020 #if rbus 3021 /* 3022 * static int 3023 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3024 * bus_addr_t addr, bus_size_t size, 3025 * bus_addr_t mask, bus_size_t align, 3026 * int flags, bus_addr_t *addrp; 3027 * bus_space_handle_t *bshp) 3028 * 3029 * This function allocates a portion of memory or io space for 3030 * clients. This function is called from CardBus card drivers. 3031 */ 3032 static int 3033 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3034 cardbus_chipset_tag_t ct; 3035 rbus_tag_t rb; 3036 bus_addr_t addr; 3037 bus_size_t size; 3038 bus_addr_t mask; 3039 bus_size_t align; 3040 int flags; 3041 bus_addr_t *addrp; 3042 bus_space_handle_t *bshp; 3043 { 3044 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3045 3046 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3047 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3048 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3049 3050 if (align == 0) { 3051 align = size; 3052 } 3053 3054 if (rb->rb_bt == sc->sc_memt) { 3055 if (align < 16) { 3056 return 1; 3057 } 3058 /* 3059 * XXX: align more than 0x1000 to avoid overwrapping 3060 * memory windows for two or more devices. 0x1000 3061 * means memory window's granularity. 3062 * 3063 * Two or more devices should be able to share same 3064 * memory window region. However, overrapping memory 3065 * window is not good because some devices, such as 3066 * 3Com 3C575[BC], have a broken address decoder and 3067 * intrude other's memory region. 3068 */ 3069 if (align < 0x1000) { 3070 align = 0x1000; 3071 } 3072 } else if (rb->rb_bt == sc->sc_iot) { 3073 if (align < 4) { 3074 return 1; 3075 } 3076 /* XXX: hack for avoiding ISA image */ 3077 if (mask < 0x0100) { 3078 mask = 0x3ff; 3079 addr = 0x300; 3080 } 3081 3082 } else { 3083 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3084 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3085 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3086 (unsigned long)sc->sc_memt)); 3087 return 1; 3088 /* XXX: panic here? */ 3089 } 3090 3091 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3092 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3093 return 1; 3094 } 3095 3096 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3097 3098 return 0; 3099 } 3100 3101 /* 3102 * static int 3103 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3104 * bus_space_handle_t *bshp, bus_size_t size); 3105 * 3106 * This function is called from CardBus card drivers. 3107 */ 3108 static int 3109 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3110 cardbus_chipset_tag_t ct; 3111 rbus_tag_t rb; 3112 bus_space_handle_t bsh; 3113 bus_size_t size; 3114 { 3115 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3116 bus_space_tag_t bt = rb->rb_bt; 3117 3118 pccbb_close_win(sc, bt, bsh, size); 3119 3120 if (bt == sc->sc_memt) { 3121 } else if (bt == sc->sc_iot) { 3122 } else { 3123 return 1; 3124 /* XXX: panic here? */ 3125 } 3126 3127 return rbus_space_free(rb, bsh, size, NULL); 3128 } 3129 #endif /* rbus */ 3130 3131 #if rbus 3132 3133 static int 3134 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3135 struct pccbb_softc *sc; 3136 bus_space_tag_t bst; 3137 bus_addr_t addr; 3138 bus_size_t size; 3139 bus_space_handle_t bsh; 3140 int flags; 3141 { 3142 struct pccbb_win_chain_head *head; 3143 bus_addr_t align; 3144 3145 head = &sc->sc_iowindow; 3146 align = 0x04; 3147 if (sc->sc_memt == bst) { 3148 head = &sc->sc_memwindow; 3149 align = 0x1000; 3150 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3151 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3152 (unsigned long)bst)); 3153 } 3154 3155 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3156 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3157 sc->sc_dev.dv_xname, 3158 (head == &sc->sc_memwindow) ? "mem" : "io"); 3159 } 3160 pccbb_winset(align, sc, bst); 3161 3162 return 0; 3163 } 3164 3165 static int 3166 pccbb_close_win(sc, bst, bsh, size) 3167 struct pccbb_softc *sc; 3168 bus_space_tag_t bst; 3169 bus_space_handle_t bsh; 3170 bus_size_t size; 3171 { 3172 struct pccbb_win_chain_head *head; 3173 bus_addr_t align; 3174 3175 head = &sc->sc_iowindow; 3176 align = 0x04; 3177 if (sc->sc_memt == bst) { 3178 head = &sc->sc_memwindow; 3179 align = 0x1000; 3180 } 3181 3182 if (pccbb_winlist_delete(head, bsh, size)) { 3183 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3184 sc->sc_dev.dv_xname, 3185 (head == &sc->sc_memwindow) ? "mem" : "io"); 3186 } 3187 pccbb_winset(align, sc, bst); 3188 3189 return 0; 3190 } 3191 3192 static int 3193 pccbb_winlist_insert(head, start, size, bsh, flags) 3194 struct pccbb_win_chain_head *head; 3195 bus_addr_t start; 3196 bus_size_t size; 3197 bus_space_handle_t bsh; 3198 int flags; 3199 { 3200 struct pccbb_win_chain *chainp, *elem; 3201 3202 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3203 M_NOWAIT)) == NULL) 3204 return (1); /* fail */ 3205 3206 elem->wc_start = start; 3207 elem->wc_end = start + (size - 1); 3208 elem->wc_handle = bsh; 3209 elem->wc_flags = flags; 3210 3211 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3212 chainp = TAILQ_NEXT(chainp, wc_list)) { 3213 if (chainp->wc_end < start) 3214 continue; 3215 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3216 return (0); 3217 } 3218 3219 TAILQ_INSERT_TAIL(head, elem, wc_list); 3220 return (0); 3221 } 3222 3223 static int 3224 pccbb_winlist_delete(head, bsh, size) 3225 struct pccbb_win_chain_head *head; 3226 bus_space_handle_t bsh; 3227 bus_size_t size; 3228 { 3229 struct pccbb_win_chain *chainp; 3230 3231 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3232 chainp = TAILQ_NEXT(chainp, wc_list)) { 3233 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3234 continue; 3235 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3236 printf("pccbb_winlist_delete: window 0x%lx size " 3237 "inconsistent: 0x%lx, 0x%lx\n", 3238 (unsigned long)chainp->wc_start, 3239 (unsigned long)(chainp->wc_end - chainp->wc_start), 3240 (unsigned long)(size - 1)); 3241 return 1; 3242 } 3243 3244 TAILQ_REMOVE(head, chainp, wc_list); 3245 free(chainp, M_DEVBUF); 3246 3247 return 0; 3248 } 3249 3250 return 1; /* fail: no candidate to remove */ 3251 } 3252 3253 static void 3254 pccbb_winset(align, sc, bst) 3255 bus_addr_t align; 3256 struct pccbb_softc *sc; 3257 bus_space_tag_t bst; 3258 { 3259 pci_chipset_tag_t pc; 3260 pcitag_t tag; 3261 bus_addr_t mask = ~(align - 1); 3262 struct { 3263 cardbusreg_t win_start; 3264 cardbusreg_t win_limit; 3265 int win_flags; 3266 } win[2]; 3267 struct pccbb_win_chain *chainp; 3268 int offs; 3269 3270 win[0].win_start = win[1].win_start = 0xffffffff; 3271 win[0].win_limit = win[1].win_limit = 0; 3272 win[0].win_flags = win[1].win_flags = 0; 3273 3274 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3275 offs = 0x2c; 3276 if (sc->sc_memt == bst) { 3277 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3278 offs = 0x1c; 3279 } 3280 3281 if (chainp != NULL) { 3282 win[0].win_start = chainp->wc_start & mask; 3283 win[0].win_limit = chainp->wc_end & mask; 3284 win[0].win_flags = chainp->wc_flags; 3285 chainp = TAILQ_NEXT(chainp, wc_list); 3286 } 3287 3288 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3289 if (win[1].win_start == 0xffffffff) { 3290 /* window 1 is not used */ 3291 if ((win[0].win_flags == chainp->wc_flags) && 3292 (win[0].win_limit + align >= 3293 (chainp->wc_start & mask))) { 3294 /* concatenate */ 3295 win[0].win_limit = chainp->wc_end & mask; 3296 } else { 3297 /* make new window */ 3298 win[1].win_start = chainp->wc_start & mask; 3299 win[1].win_limit = chainp->wc_end & mask; 3300 win[1].win_flags = chainp->wc_flags; 3301 } 3302 continue; 3303 } 3304 3305 /* Both windows are engaged. */ 3306 if (win[0].win_flags == win[1].win_flags) { 3307 /* same flags */ 3308 if (win[0].win_flags == chainp->wc_flags) { 3309 if (win[1].win_start - (win[0].win_limit + 3310 align) < 3311 (chainp->wc_start & mask) - 3312 ((chainp->wc_end & mask) + align)) { 3313 /* 3314 * merge window 0 and 1, and set win1 3315 * to chainp 3316 */ 3317 win[0].win_limit = win[1].win_limit; 3318 win[1].win_start = 3319 chainp->wc_start & mask; 3320 win[1].win_limit = 3321 chainp->wc_end & mask; 3322 } else { 3323 win[1].win_limit = 3324 chainp->wc_end & mask; 3325 } 3326 } else { 3327 /* different flags */ 3328 3329 /* concatenate win0 and win1 */ 3330 win[0].win_limit = win[1].win_limit; 3331 /* allocate win[1] to new space */ 3332 win[1].win_start = chainp->wc_start & mask; 3333 win[1].win_limit = chainp->wc_end & mask; 3334 win[1].win_flags = chainp->wc_flags; 3335 } 3336 } else { 3337 /* the flags of win[0] and win[1] is different */ 3338 if (win[0].win_flags == chainp->wc_flags) { 3339 win[0].win_limit = chainp->wc_end & mask; 3340 /* 3341 * XXX this creates overlapping windows, so 3342 * what should the poor bridge do if one is 3343 * cachable, and the other is not? 3344 */ 3345 printf("%s: overlapping windows\n", 3346 sc->sc_dev.dv_xname); 3347 } else { 3348 win[1].win_limit = chainp->wc_end & mask; 3349 } 3350 } 3351 } 3352 3353 pc = sc->sc_pc; 3354 tag = sc->sc_tag; 3355 pci_conf_write(pc, tag, offs, win[0].win_start); 3356 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3357 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3358 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3359 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3360 (unsigned long)pci_conf_read(pc, tag, offs), 3361 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3362 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3363 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3364 3365 if (bst == sc->sc_memt) { 3366 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3367 3368 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3369 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3370 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3371 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3372 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3373 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3374 } 3375 } 3376 3377 #endif /* rbus */ 3378 3379 static void 3380 pccbb_powerhook(why, arg) 3381 int why; 3382 void *arg; 3383 { 3384 struct pccbb_softc *sc = arg; 3385 pcireg_t reg; 3386 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3387 bus_space_handle_t base_memh = sc->sc_base_memh; 3388 3389 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3390 3391 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3392 DPRINTF(("%s: power: why %d stopping intr\n", 3393 sc->sc_dev.dv_xname, why)); 3394 if (sc->sc_pil_intr_enable) { 3395 (void)pccbbintr_function(sc); 3396 } 3397 sc->sc_pil_intr_enable = 0; 3398 3399 /* ToDo: deactivate or suspend child devices */ 3400 3401 } 3402 3403 if (why == PWR_RESUME) { 3404 if (sc->sc_pwrmgt_offs != 0) { 3405 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3406 sc->sc_pwrmgt_offs + 4); 3407 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3408 reg & 0x100) { 3409 /* powrstate != D0 */ 3410 3411 printf("%s going back to D0 mode\n", 3412 sc->sc_dev.dv_xname); 3413 reg &= ~PCI_PMCSR_STATE_MASK; 3414 reg |= PCI_PMCSR_STATE_D0; 3415 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3416 pci_conf_write(sc->sc_pc, sc->sc_tag, 3417 sc->sc_pwrmgt_offs + 4, reg); 3418 3419 pci_conf_write(sc->sc_pc, sc->sc_tag, 3420 PCI_SOCKBASE, sc->sc_sockbase); 3421 pci_conf_write(sc->sc_pc, sc->sc_tag, 3422 PCI_BUSNUM, sc->sc_busnum); 3423 pccbb_chipinit(sc); 3424 /* setup memory and io space window for CB */ 3425 pccbb_winset(0x1000, sc, sc->sc_memt); 3426 pccbb_winset(0x04, sc, sc->sc_iot); 3427 } 3428 } 3429 3430 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3431 /* BIOS did not recover this register */ 3432 pci_conf_write (sc->sc_pc, sc->sc_tag, 3433 PCI_SOCKBASE, sc->sc_sockbase); 3434 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3435 /* BIOS did not recover this register */ 3436 pci_conf_write (sc->sc_pc, sc->sc_tag, 3437 PCI_BUSNUM, sc->sc_busnum); 3438 /* CSC Interrupt: Card detect interrupt on */ 3439 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3440 /* Card detect intr is turned on. */ 3441 reg |= CB_SOCKET_MASK_CD; 3442 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3443 /* reset interrupt */ 3444 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3445 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3446 3447 /* 3448 * check for card insertion or removal during suspend period. 3449 * XXX: the code can't cope with card swap (remove then 3450 * insert). how can we detect such situation? 3451 */ 3452 (void)pccbbintr(sc); 3453 3454 sc->sc_pil_intr_enable = 1; 3455 DPRINTF(("%s: power: RESUME enabling intr\n", 3456 sc->sc_dev.dv_xname)); 3457 3458 /* ToDo: activate or wakeup child devices */ 3459 } 3460 } 3461
Indexes created Sat Sep 27 14:09:57 GMT 2025