pccbb.c revision 1.108
1 /* $NetBSD: pccbb.c,v 1.108 2004/08/16 15:40:35 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.108 2004/08/16 15:40:35 mycroft Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC void pccbb_pcmcia_socket_settype __P((pcmcia_chipset_handle_t, int)); 188 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 189 190 static int pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_delay __P((struct pcic_handle *, int, const char *)); 192 193 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 194 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 195 static void pccbb_powerhook __P((int, void *)); 196 197 /* bus-space allocation and deallocation functions */ 198 #if rbus 199 200 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 202 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 203 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 204 bus_space_handle_t, bus_size_t)); 205 206 #endif /* rbus */ 207 208 #if rbus 209 210 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 211 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 212 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 213 bus_space_handle_t, bus_size_t)); 214 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 215 bus_size_t, bus_space_handle_t, int)); 216 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 217 bus_space_handle_t, bus_size_t)); 218 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 219 bus_space_tag_t)); 220 void pccbb_winlist_show(struct pccbb_win_chain *); 221 222 #endif /* rbus */ 223 224 /* for config_defer */ 225 static void pccbb_pci_callback __P((struct device *)); 226 227 #if defined SHOW_REGS 228 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 229 bus_space_tag_t memt, bus_space_handle_t memh)); 230 #endif 231 232 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 233 pcicbbmatch, pccbbattach, NULL, NULL); 234 235 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 236 pccbb_pcmcia_mem_alloc, 237 pccbb_pcmcia_mem_free, 238 pccbb_pcmcia_mem_map, 239 pccbb_pcmcia_mem_unmap, 240 pccbb_pcmcia_io_alloc, 241 pccbb_pcmcia_io_free, 242 pccbb_pcmcia_io_map, 243 pccbb_pcmcia_io_unmap, 244 pccbb_pcmcia_intr_establish, 245 pccbb_pcmcia_intr_disestablish, 246 pccbb_pcmcia_socket_enable, 247 pccbb_pcmcia_socket_disable, 248 pccbb_pcmcia_socket_settype, 249 pccbb_pcmcia_card_detect 250 }; 251 252 #if rbus 253 static struct cardbus_functions pccbb_funcs = { 254 pccbb_rbus_cb_space_alloc, 255 pccbb_rbus_cb_space_free, 256 pccbb_cb_intr_establish, 257 pccbb_cb_intr_disestablish, 258 pccbb_ctrl, 259 pccbb_power, 260 pccbb_make_tag, 261 pccbb_free_tag, 262 pccbb_conf_read, 263 pccbb_conf_write, 264 }; 265 #else 266 static struct cardbus_functions pccbb_funcs = { 267 pccbb_ctrl, 268 pccbb_power, 269 pccbb_mem_open, 270 pccbb_mem_close, 271 pccbb_io_open, 272 pccbb_io_close, 273 pccbb_cb_intr_establish, 274 pccbb_cb_intr_disestablish, 275 pccbb_make_tag, 276 pccbb_conf_read, 277 pccbb_conf_write, 278 }; 279 #endif 280 281 int 282 pcicbbmatch(parent, match, aux) 283 struct device *parent; 284 struct cfdata *match; 285 void *aux; 286 { 287 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 288 289 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 290 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 291 PCI_INTERFACE(pa->pa_class) == 0) { 292 return 1; 293 } 294 295 return 0; 296 } 297 298 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 299 | ((prod) << PCI_PRODUCT_SHIFT)) 300 301 const struct yenta_chipinfo { 302 pcireg_t yc_id; /* vendor tag | product tag */ 303 int yc_chiptype; 304 int yc_flags; 305 } yc_chipsets[] = { 306 /* Texas Instruments chips */ 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 332 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 334 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 336 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 338 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 339 340 /* Ricoh chips */ 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 344 PCCBB_PCMCIA_MEM_32}, 345 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 346 PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 348 PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 350 PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 352 PCCBB_PCMCIA_MEM_32}, 353 354 /* Toshiba products */ 355 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 356 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 358 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 360 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 361 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 362 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 363 364 /* Cirrus Logic products */ 365 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 366 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 367 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 368 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 369 370 /* sentinel, or Generic chip */ 371 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 372 }; 373 374 static int 375 cb_chipset(pci_id, flagp) 376 u_int32_t pci_id; 377 int *flagp; 378 { 379 const struct yenta_chipinfo *yc; 380 381 /* Loop over except the last default entry. */ 382 for (yc = yc_chipsets; yc < yc_chipsets + 383 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 384 if (pci_id == yc->yc_id) 385 break; 386 387 if (flagp != NULL) 388 *flagp = yc->yc_flags; 389 390 return (yc->yc_chiptype); 391 } 392 393 static void 394 pccbb_shutdown(void *arg) 395 { 396 struct pccbb_softc *sc = arg; 397 pcireg_t command; 398 399 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 400 401 /* 402 * turn off power 403 * 404 * XXX - do not turn off power if chipset is TI 113X because 405 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 406 */ 407 if (sc->sc_chipset != CB_TI113X) { 408 pccbb_power((cardbus_chipset_tag_t)sc, 409 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 410 } 411 412 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 413 0); 414 415 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 416 417 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 418 PCI_COMMAND_MASTER_ENABLE); 419 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 420 421 } 422 423 void 424 pccbbattach(parent, self, aux) 425 struct device *parent; 426 struct device *self; 427 void *aux; 428 { 429 struct pccbb_softc *sc = (void *)self; 430 struct pci_attach_args *pa = aux; 431 pci_chipset_tag_t pc = pa->pa_pc; 432 pcireg_t busreg, reg, sock_base; 433 bus_addr_t sockbase; 434 char devinfo[256]; 435 int flags; 436 int pwrmgt_offs; 437 438 #ifdef __HAVE_PCCBB_ATTACH_HOOK 439 pccbb_attach_hook(parent, self, pa); 440 #endif 441 442 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 443 444 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 445 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 446 #ifdef CBB_DEBUG 447 printf(" (chipflags %x)", flags); 448 #endif 449 printf("\n"); 450 451 TAILQ_INIT(&sc->sc_memwindow); 452 TAILQ_INIT(&sc->sc_iowindow); 453 454 #if rbus 455 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 456 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 457 458 #if 0 459 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 460 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 461 #endif 462 #endif /* rbus */ 463 464 sc->sc_flags &= ~CBB_MEMHMAPPED; 465 466 /* power management: set D0 state */ 467 sc->sc_pwrmgt_offs = 0; 468 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 469 &pwrmgt_offs, 0)) { 470 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 471 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 472 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 473 reg &= ~PCI_PMCSR_STATE_MASK; 474 reg |= PCI_PMCSR_STATE_D0; 475 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 476 pci_conf_write(pc, pa->pa_tag, 477 pwrmgt_offs + PCI_PMCSR, reg); 478 } 479 480 sc->sc_pwrmgt_offs = pwrmgt_offs; 481 } 482 483 /* 484 * MAP socket registers and ExCA registers on memory-space 485 * When no valid address is set on socket base registers (on pci 486 * config space), get it not polite way. 487 */ 488 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 489 490 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 491 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 492 /* The address must be valid. */ 493 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 494 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 495 printf("%s: can't map socket base address 0x%lx\n", 496 sc->sc_dev.dv_xname, (unsigned long)sock_base); 497 /* 498 * I think it's funny: socket base registers must be 499 * mapped on memory space, but ... 500 */ 501 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 502 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 503 NULL)) { 504 printf("%s: can't map socket base address" 505 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 506 (unsigned long)sockbase); 507 /* give up... allocate reg space via rbus. */ 508 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 509 } else 510 sc->sc_flags |= CBB_MEMHMAPPED; 511 } else { 512 DPRINTF(("%s: socket base address 0x%lx\n", 513 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 514 sc->sc_flags |= CBB_MEMHMAPPED; 515 } 516 } 517 518 sc->sc_mem_start = 0; /* XXX */ 519 sc->sc_mem_end = 0xffffffff; /* XXX */ 520 521 /* 522 * When interrupt isn't routed correctly, give up probing cbb and do 523 * not kill pcic-compatible port. 524 */ 525 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 526 printf("%s: NOT USED because of unconfigured interrupt\n", 527 sc->sc_dev.dv_xname); 528 return; 529 } 530 531 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 532 533 /* pccbb_machdep.c end */ 534 535 #if defined CBB_DEBUG 536 { 537 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 538 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 539 intrname[pa->pa_intrpin], pa->pa_intrline); 540 } 541 #endif 542 543 /* setup softc */ 544 sc->sc_pc = pc; 545 sc->sc_iot = pa->pa_iot; 546 sc->sc_memt = pa->pa_memt; 547 sc->sc_dmat = pa->pa_dmat; 548 sc->sc_tag = pa->pa_tag; 549 sc->sc_function = pa->pa_function; 550 sc->sc_sockbase = sock_base; 551 sc->sc_busnum = busreg; 552 553 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 554 555 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 556 557 shutdownhook_establish(pccbb_shutdown, sc); 558 559 /* Disable legacy register mapping. */ 560 switch (sc->sc_chipset) { 561 case CB_RX5C46X: /* fallthrough */ 562 #if 0 563 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 564 case CB_RX5C47X: 565 #endif 566 /* 567 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 568 * cannot be disabled by substituting 0 into PCI_LEGACY 569 * register. Ricoh CardBus bridges have special bits on Bridge 570 * control reg (addr 0x3e on PCI config space). 571 */ 572 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 573 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 574 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 575 break; 576 577 default: 578 /* XXX I don't know proper way to kill legacy I/O. */ 579 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 580 break; 581 } 582 583 config_defer(self, pccbb_pci_callback); 584 } 585 586 587 588 589 /* 590 * static void pccbb_pci_callback(struct device *self) 591 * 592 * The actual attach routine: get memory space for YENTA register 593 * space, setup YENTA register and route interrupt. 594 * 595 * This function should be deferred because this device may obtain 596 * memory space dynamically. This function must avoid obtaining 597 * memory area which has already kept for another device. 598 */ 599 static void 600 pccbb_pci_callback(self) 601 struct device *self; 602 { 603 struct pccbb_softc *sc = (void *)self; 604 pci_chipset_tag_t pc = sc->sc_pc; 605 pci_intr_handle_t ih; 606 const char *intrstr = NULL; 607 bus_addr_t sockbase; 608 struct cbslot_attach_args cba; 609 struct pcmciabus_attach_args paa; 610 struct cardslot_attach_args caa; 611 struct cardslot_softc *csc; 612 613 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 614 /* The socket registers aren't mapped correctly. */ 615 #if rbus 616 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 617 (sc->sc_chipset == CB_RX5C47X 618 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 619 0, &sockbase, &sc->sc_base_memh)) { 620 return; 621 } 622 sc->sc_base_memt = sc->sc_memt; 623 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 624 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 625 sc->sc_dev.dv_xname, (unsigned long)sockbase, 626 (unsigned long)pci_conf_read(pc, sc->sc_tag, 627 PCI_SOCKBASE))); 628 #else 629 sc->sc_base_memt = sc->sc_memt; 630 #if !defined CBB_PCI_BASE 631 #define CBB_PCI_BASE 0x20000000 632 #endif 633 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 634 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 635 /* cannot allocate memory space */ 636 return; 637 } 638 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 639 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 640 sc->sc_dev.dv_xname, (unsigned long)sock_base, 641 (unsigned long)pci_conf_read(pc, 642 sc->sc_tag, PCI_SOCKBASE))); 643 sc->sc_sockbase = sockbase; 644 #endif 645 sc->sc_flags |= CBB_MEMHMAPPED; 646 } 647 648 /* bus bridge initialization */ 649 pccbb_chipinit(sc); 650 651 /* clear data structure for child device interrupt handlers */ 652 LIST_INIT(&sc->sc_pil); 653 sc->sc_pil_intr_enable = 1; 654 655 /* Map and establish the interrupt. */ 656 if (pci_intr_map(&sc->sc_pa, &ih)) { 657 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 658 return; 659 } 660 intrstr = pci_intr_string(pc, ih); 661 662 /* 663 * XXX pccbbintr should be called under the priority lower 664 * than any other hard interrputs. 665 */ 666 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 667 668 if (sc->sc_ih == NULL) { 669 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 670 if (intrstr != NULL) { 671 printf(" at %s", intrstr); 672 } 673 printf("\n"); 674 return; 675 } 676 677 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 678 powerhook_establish(pccbb_powerhook, sc); 679 680 { 681 u_int32_t sockstat; 682 683 sockstat = bus_space_read_4(sc->sc_base_memt, 684 sc->sc_base_memh, CB_SOCKET_STAT); 685 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 686 sc->sc_flags |= CBB_CARDEXIST; 687 } 688 } 689 690 /* 691 * attach cardbus 692 */ 693 { 694 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 695 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 696 697 /* initialize cbslot_attach */ 698 cba.cba_busname = "cardbus"; 699 cba.cba_iot = sc->sc_iot; 700 cba.cba_memt = sc->sc_memt; 701 cba.cba_dmat = sc->sc_dmat; 702 cba.cba_bus = (busreg >> 8) & 0x0ff; 703 cba.cba_cc = (void *)sc; 704 cba.cba_cf = &pccbb_funcs; 705 cba.cba_intrline = sc->sc_pa.pa_intrline; 706 707 #if rbus 708 cba.cba_rbus_iot = sc->sc_rbus_iot; 709 cba.cba_rbus_memt = sc->sc_rbus_memt; 710 #endif 711 712 cba.cba_cacheline = PCI_CACHELINE(bhlc); 713 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 714 715 if (bootverbose) { 716 printf("%s: cacheline 0x%x lattimer 0x%x\n", 717 sc->sc_dev.dv_xname, cba.cba_cacheline, 718 cba.cba_lattimer); 719 printf("%s: bhlc 0x%x lscp 0x%x\n", 720 sc->sc_dev.dv_xname, bhlc, busreg); 721 } 722 #if defined SHOW_REGS 723 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 724 sc->sc_base_memh); 725 #endif 726 } 727 728 pccbb_pcmcia_attach_setup(sc, &paa); 729 caa.caa_cb_attach = NULL; 730 if (cba.cba_bus == 0) 731 printf("%s: secondary bus number uninitialized; try PCIBIOS_BUS_FIXUP\n", sc->sc_dev.dv_xname); 732 else 733 caa.caa_cb_attach = &cba; 734 caa.caa_16_attach = &paa; 735 caa.caa_ph = &sc->sc_pcmcia_h; 736 737 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 738 DPRINTF(("pccbbattach: found cardslot\n")); 739 sc->sc_csc = csc; 740 } 741 742 return; 743 } 744 745 746 747 748 749 /* 750 * static void pccbb_chipinit(struct pccbb_softc *sc) 751 * 752 * This function initialize YENTA chip registers listed below: 753 * 1) PCI command reg, 754 * 2) PCI and CardBus latency timer, 755 * 3) route PCI interrupt, 756 * 4) close all memory and io windows. 757 * 5) turn off bus power. 758 * 6) card detect interrupt on. 759 * 7) clear interrupt 760 */ 761 static void 762 pccbb_chipinit(sc) 763 struct pccbb_softc *sc; 764 { 765 pci_chipset_tag_t pc = sc->sc_pc; 766 pcitag_t tag = sc->sc_tag; 767 bus_space_tag_t bmt = sc->sc_base_memt; 768 bus_space_handle_t bmh = sc->sc_base_memh; 769 pcireg_t reg; 770 771 /* 772 * Set PCI command reg. 773 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 774 */ 775 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 776 /* I believe it is harmless. */ 777 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 778 PCI_COMMAND_MASTER_ENABLE); 779 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 780 781 /* 782 * Set CardBus latency timer. 783 */ 784 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 785 if (PCI_CB_LATENCY(reg) < 0x20) { 786 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 787 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 788 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 789 } 790 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 791 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 792 793 /* 794 * Set PCI latency timer. 795 */ 796 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 797 if (PCI_LATTIMER(reg) < 0x10) { 798 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 799 reg |= (0x10 << PCI_LATTIMER_SHIFT); 800 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 801 } 802 DPRINTF(("PCI latency timer 0x%x (%x)\n", 803 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 804 805 806 /* Route functional interrupts to PCI. */ 807 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 808 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 809 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 810 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 811 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 812 813 switch (sc->sc_chipset) { 814 case CB_TI113X: 815 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 816 /* This bit is shared, but may read as 0 on some chips, so set 817 it explicitly on both functions. */ 818 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 819 /* CSC intr enable */ 820 reg |= PCI113X_CBCTRL_PCI_CSC; 821 /* functional intr prohibit | prohibit ISA routing */ 822 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 823 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 824 break; 825 826 case CB_TI12XX: 827 /* 828 * Some TI 12xx (and [14][45]xx) based pci cards 829 * sometimes have issues with the MFUNC register not 830 * being initialized due to a bad EEPROM on board. 831 * Laptops that this matters on have this register 832 * properly initialized. 833 * 834 * The TI125X parts have a different register. 835 */ 836 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 837 if (reg == 0) { 838 reg &= ~PCI12XX_MFUNC_PIN0; 839 reg |= PCI12XX_MFUNC_PIN0_INTA; 840 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 841 PCI12XX_SYSCTRL_INTRTIE) == 0) { 842 reg &= ~PCI12XX_MFUNC_PIN1; 843 reg |= PCI12XX_MFUNC_PIN1_INTB; 844 } 845 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 846 } 847 /* fallthrough */ 848 849 case CB_TI125X: 850 /* 851 * Disable zoom video. Some machines initialize this 852 * improperly and experience has shown that this helps 853 * prevent strange behavior. 854 */ 855 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 856 857 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 858 reg |= PCI12XX_SYSCTRL_VCCPROT; 859 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 860 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 861 reg |= PCI12XX_CBCTRL_CSC; 862 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 863 break; 864 865 case CB_TOPIC95B: 866 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 867 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 868 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 869 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 870 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 871 sc->sc_dev.dv_xname, reg)); 872 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 873 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 874 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 875 DPRINTF(("0x%x\n", reg)); 876 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 877 break; 878 879 case CB_TOPIC97: 880 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 881 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 882 sc->sc_dev.dv_xname, reg)); 883 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 884 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 885 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 886 reg |= TOPIC97_SLOT_CTRL_PCIINT; 887 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 888 DPRINTF(("0x%x\n", reg)); 889 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 890 /* make sure to assert LV card support bits */ 891 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 892 0x800 + 0x3e, 893 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 894 0x800 + 0x3e) | 0x03); 895 break; 896 } 897 898 /* Close all memory and I/O windows. */ 899 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 900 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 901 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 902 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 903 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 904 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 905 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 906 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 907 908 /* reset 16-bit pcmcia bus */ 909 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 910 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 911 912 /* turn off power */ 913 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 914 915 /* CSC Interrupt: Card detect interrupt on */ 916 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 917 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 918 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 919 /* reset interrupt */ 920 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 921 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 922 } 923 924 925 926 927 /* 928 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 929 * struct pcmciabus_attach_args *paa) 930 * 931 * This function attaches 16-bit PCcard bus. 932 */ 933 STATIC void 934 pccbb_pcmcia_attach_setup(sc, paa) 935 struct pccbb_softc *sc; 936 struct pcmciabus_attach_args *paa; 937 { 938 struct pcic_handle *ph = &sc->sc_pcmcia_h; 939 #if rbus 940 rbus_tag_t rb; 941 #endif 942 943 /* initialize pcmcia part in pccbb_softc */ 944 ph->ph_parent = (struct device *)sc; 945 ph->sock = sc->sc_function; 946 ph->flags = 0; 947 ph->shutdown = 0; 948 ph->ih_irq = sc->sc_pa.pa_intrline; 949 ph->ph_bus_t = sc->sc_base_memt; 950 ph->ph_bus_h = sc->sc_base_memh; 951 ph->ph_read = pccbb_pcmcia_read; 952 ph->ph_write = pccbb_pcmcia_write; 953 sc->sc_pct = &pccbb_pcmcia_funcs; 954 955 /* 956 * We need to do a few things here: 957 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 958 * setting the IRQ numbers to 0. 959 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 960 * routing of CSC interrupts (e.g. card removal) to PCI while in 961 * PCMCIA mode. We just leave this set all the time. 962 * 3) Enable card insertion/removal interrupts in case the chip also 963 * needs that while in PCMCIA mode. 964 * 4) Clear any pending CSC interrupt. 965 */ 966 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 967 if (sc->sc_chipset == CB_TI113X) { 968 Pcic_write(ph, PCIC_CSC_INTR, 0); 969 } else { 970 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 971 Pcic_read(ph, PCIC_CSC); 972 } 973 974 /* initialize pcmcia bus attachment */ 975 paa->paa_busname = "pcmcia"; 976 paa->pct = sc->sc_pct; 977 paa->pch = ph; 978 paa->iobase = 0; /* I don't use them */ 979 paa->iosize = 0; 980 #if rbus 981 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 982 paa->iobase = rb->rb_start + rb->rb_offset; 983 paa->iosize = rb->rb_end - rb->rb_start; 984 #endif 985 986 return; 987 } 988 989 #if 0 990 STATIC void 991 pccbb_pcmcia_attach_card(ph) 992 struct pcic_handle *ph; 993 { 994 if (ph->flags & PCIC_FLAG_CARDP) { 995 panic("pccbb_pcmcia_attach_card: already attached"); 996 } 997 998 /* call the MI attach function */ 999 pcmcia_card_attach(ph->pcmcia); 1000 1001 ph->flags |= PCIC_FLAG_CARDP; 1002 } 1003 1004 STATIC void 1005 pccbb_pcmcia_detach_card(ph, flags) 1006 struct pcic_handle *ph; 1007 int flags; 1008 { 1009 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1010 panic("pccbb_pcmcia_detach_card: already detached"); 1011 } 1012 1013 ph->flags &= ~PCIC_FLAG_CARDP; 1014 1015 /* call the MI detach function */ 1016 pcmcia_card_detach(ph->pcmcia, flags); 1017 } 1018 #endif 1019 1020 /* 1021 * int pccbbintr(arg) 1022 * void *arg; 1023 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1024 * itself. 1025 */ 1026 int 1027 pccbbintr(arg) 1028 void *arg; 1029 { 1030 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1031 u_int32_t sockevent, sockstate; 1032 bus_space_tag_t memt = sc->sc_base_memt; 1033 bus_space_handle_t memh = sc->sc_base_memh; 1034 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1035 1036 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1037 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1038 Pcic_read(ph, PCIC_CSC); 1039 1040 if (sockevent == 0) { 1041 /* This intr is not for me: it may be for my child devices. */ 1042 if (sc->sc_pil_intr_enable) { 1043 return pccbbintr_function(sc); 1044 } else { 1045 return 0; 1046 } 1047 } 1048 1049 if (sockevent & CB_SOCKET_EVENT_CD) { 1050 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1051 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1052 /* A card should be removed. */ 1053 if (sc->sc_flags & CBB_CARDEXIST) { 1054 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1055 sockevent)); 1056 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1057 sc->sc_flags &= ~CBB_CARDEXIST; 1058 if (sc->sc_csc->sc_status & 1059 CARDSLOT_STATUS_CARD_16) { 1060 #if 0 1061 struct pcic_handle *ph = 1062 &sc->sc_pcmcia_h; 1063 1064 pcmcia_card_deactivate(ph->pcmcia); 1065 pccbb_pcmcia_socket_disable(ph); 1066 pccbb_pcmcia_detach_card(ph, 1067 DETACH_FORCE); 1068 #endif 1069 cardslot_event_throw(sc->sc_csc, 1070 CARDSLOT_EVENT_REMOVAL_16); 1071 } else if (sc->sc_csc->sc_status & 1072 CARDSLOT_STATUS_CARD_CB) { 1073 /* Cardbus intr removed */ 1074 cardslot_event_throw(sc->sc_csc, 1075 CARDSLOT_EVENT_REMOVAL_CB); 1076 } 1077 } else if (sc->sc_flags & CBB_INSERTING) { 1078 sc->sc_flags &= ~CBB_INSERTING; 1079 callout_stop(&sc->sc_insert_ch); 1080 } 1081 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1082 /* 1083 * The pccbbintr may called from powerdown hook when 1084 * the system resumed, to detect the card 1085 * insertion/removal during suspension. 1086 */ 1087 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1088 if (sc->sc_flags & CBB_INSERTING) { 1089 callout_stop(&sc->sc_insert_ch); 1090 } 1091 callout_reset(&sc->sc_insert_ch, hz / 5, 1092 pci113x_insert, sc); 1093 sc->sc_flags |= CBB_INSERTING; 1094 } 1095 } 1096 1097 return (1); 1098 } 1099 1100 /* 1101 * static int pccbbintr_function(struct pccbb_softc *sc) 1102 * 1103 * This function calls each interrupt handler registered at the 1104 * bridge. The interrupt handlers are called in registered order. 1105 */ 1106 static int 1107 pccbbintr_function(sc) 1108 struct pccbb_softc *sc; 1109 { 1110 int retval = 0, val; 1111 struct pccbb_intrhand_list *pil; 1112 int s, splchanged; 1113 1114 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1115 pil = LIST_NEXT(pil, pil_next)) { 1116 /* 1117 * XXX priority change. gross. I use if-else 1118 * sentense instead of switch-case sentense because of 1119 * avoiding duplicate case value error. More than one 1120 * IPL_XXX use same value. It depends on 1121 * implimentation. 1122 */ 1123 splchanged = 1; 1124 if (pil->pil_level == IPL_SERIAL) { 1125 s = splserial(); 1126 } else if (pil->pil_level == IPL_HIGH) { 1127 s = splhigh(); 1128 } else if (pil->pil_level == IPL_CLOCK) { 1129 s = splclock(); 1130 } else if (pil->pil_level == IPL_AUDIO) { 1131 s = splaudio(); 1132 } else if (pil->pil_level == IPL_VM) { 1133 s = splvm(); 1134 } else if (pil->pil_level == IPL_TTY) { 1135 s = spltty(); 1136 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1137 s = splsoftserial(); 1138 } else if (pil->pil_level == IPL_NET) { 1139 s = splnet(); 1140 } else { 1141 s = 0; /* XXX: gcc */ 1142 splchanged = 0; 1143 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1144 } 1145 1146 val = (*pil->pil_func)(pil->pil_arg); 1147 1148 if (splchanged != 0) { 1149 splx(s); 1150 } 1151 1152 retval = retval == 1 ? 1 : 1153 retval == 0 ? val : val != 0 ? val : retval; 1154 } 1155 1156 return retval; 1157 } 1158 1159 static void 1160 pci113x_insert(arg) 1161 void *arg; 1162 { 1163 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1164 u_int32_t sockevent, sockstate; 1165 1166 if (!(sc->sc_flags & CBB_INSERTING)) { 1167 /* We add a card only under inserting state. */ 1168 return; 1169 } 1170 sc->sc_flags &= ~CBB_INSERTING; 1171 1172 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1173 CB_SOCKET_EVENT); 1174 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1175 CB_SOCKET_STAT); 1176 1177 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1178 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1179 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1180 sc->sc_flags |= CBB_CARDEXIST; 1181 /* call pccard interrupt handler here */ 1182 if (sockstate & CB_SOCKET_STAT_16BIT) { 1183 /* 16-bit card found */ 1184 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1185 cardslot_event_throw(sc->sc_csc, 1186 CARDSLOT_EVENT_INSERTION_16); 1187 } else if (sockstate & CB_SOCKET_STAT_CB) { 1188 /* cardbus card found */ 1189 /* cardbus_attach_card(sc->sc_csc); */ 1190 cardslot_event_throw(sc->sc_csc, 1191 CARDSLOT_EVENT_INSERTION_CB); 1192 } else { 1193 /* who are you? */ 1194 } 1195 } else { 1196 callout_reset(&sc->sc_insert_ch, hz / 10, 1197 pci113x_insert, sc); 1198 } 1199 } 1200 1201 #define PCCBB_PCMCIA_OFFSET 0x800 1202 static u_int8_t 1203 pccbb_pcmcia_read(ph, reg) 1204 struct pcic_handle *ph; 1205 int reg; 1206 { 1207 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1208 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1209 1210 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1211 PCCBB_PCMCIA_OFFSET + reg); 1212 } 1213 1214 static void 1215 pccbb_pcmcia_write(ph, reg, val) 1216 struct pcic_handle *ph; 1217 int reg; 1218 u_int8_t val; 1219 { 1220 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1221 val); 1222 1223 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1224 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1225 } 1226 1227 /* 1228 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1229 */ 1230 STATIC int 1231 pccbb_ctrl(ct, command) 1232 cardbus_chipset_tag_t ct; 1233 int command; 1234 { 1235 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1236 1237 switch (command) { 1238 case CARDBUS_CD: 1239 if (2 == pccbb_detect_card(sc)) { 1240 int retval = 0; 1241 int status = cb_detect_voltage(sc); 1242 if (PCCARD_VCC_5V & status) { 1243 retval |= CARDBUS_5V_CARD; 1244 } 1245 if (PCCARD_VCC_3V & status) { 1246 retval |= CARDBUS_3V_CARD; 1247 } 1248 if (PCCARD_VCC_XV & status) { 1249 retval |= CARDBUS_XV_CARD; 1250 } 1251 if (PCCARD_VCC_YV & status) { 1252 retval |= CARDBUS_YV_CARD; 1253 } 1254 return retval; 1255 } else { 1256 return 0; 1257 } 1258 case CARDBUS_RESET: 1259 return cb_reset(sc); 1260 case CARDBUS_IO_ENABLE: /* fallthrough */ 1261 case CARDBUS_IO_DISABLE: /* fallthrough */ 1262 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1263 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1264 case CARDBUS_BM_ENABLE: /* fallthrough */ 1265 case CARDBUS_BM_DISABLE: /* fallthrough */ 1266 /* XXX: I think we don't need to call this function below. */ 1267 return pccbb_cardenable(sc, command); 1268 } 1269 1270 return 0; 1271 } 1272 1273 /* 1274 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1275 * This function returns true when it succeeds and returns false when 1276 * it fails. 1277 */ 1278 STATIC int 1279 pccbb_power(ct, command) 1280 cardbus_chipset_tag_t ct; 1281 int command; 1282 { 1283 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1284 1285 u_int32_t status, sock_ctrl, reg_ctrl; 1286 bus_space_tag_t memt = sc->sc_base_memt; 1287 bus_space_handle_t memh = sc->sc_base_memh; 1288 1289 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1290 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1291 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1292 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1293 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1294 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1295 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1296 "UNKNOWN", 1297 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1298 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1299 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1300 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1301 "UNKNOWN", command)); 1302 1303 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1304 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1305 1306 switch (command & CARDBUS_VCCMASK) { 1307 case CARDBUS_VCC_UC: 1308 break; 1309 case CARDBUS_VCC_5V: 1310 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1311 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1312 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1313 } else { 1314 printf("%s: BAD voltage request: no 5 V card\n", 1315 sc->sc_dev.dv_xname); 1316 return 0; 1317 } 1318 break; 1319 case CARDBUS_VCC_3V: 1320 if (CB_SOCKET_STAT_3VCARD & status) { 1321 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1322 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1323 } else { 1324 printf("%s: BAD voltage request: no 3.3 V card\n", 1325 sc->sc_dev.dv_xname); 1326 return 0; 1327 } 1328 break; 1329 case CARDBUS_VCC_0V: 1330 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1331 break; 1332 default: 1333 return 0; /* power NEVER changed */ 1334 } 1335 1336 switch (command & CARDBUS_VPPMASK) { 1337 case CARDBUS_VPP_UC: 1338 break; 1339 case CARDBUS_VPP_0V: 1340 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1341 break; 1342 case CARDBUS_VPP_VCC: 1343 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1344 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1345 break; 1346 case CARDBUS_VPP_12V: 1347 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1348 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1349 break; 1350 } 1351 1352 #if 0 1353 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1354 #endif 1355 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1356 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1357 1358 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1359 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1360 sc->sc_dev.dv_xname, sock_ctrl, status); 1361 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1362 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1363 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1364 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1365 #if 0 1366 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, 1367 CB_SOCKET_FORCE_BADVCC); 1368 #endif 1369 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1370 CB_SOCKET_STAT)); 1371 return 0; 1372 } 1373 1374 if (sc->sc_chipset == CB_TOPIC97) { 1375 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1376 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1377 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1378 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1379 else 1380 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1381 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1382 } 1383 1384 return 1; /* power changed correctly */ 1385 } 1386 1387 #if defined CB_PCMCIA_POLL 1388 struct cb_poll_str { 1389 void *arg; 1390 int (*func) __P((void *)); 1391 int level; 1392 pccard_chipset_tag_t ct; 1393 int count; 1394 struct callout poll_ch; 1395 }; 1396 1397 static struct cb_poll_str cb_poll[10]; 1398 static int cb_poll_n = 0; 1399 1400 static void cb_pcmcia_poll __P((void *arg)); 1401 1402 static void 1403 cb_pcmcia_poll(arg) 1404 void *arg; 1405 { 1406 struct cb_poll_str *poll = arg; 1407 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1408 struct pccbb_softc *sc = psc->cpc_parent; 1409 int s; 1410 u_int32_t spsr; /* socket present-state reg */ 1411 1412 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1413 switch (poll->level) { 1414 case IPL_NET: 1415 s = splnet(); 1416 break; 1417 case IPL_BIO: 1418 s = splbio(); 1419 break; 1420 case IPL_TTY: /* fallthrough */ 1421 default: 1422 s = spltty(); 1423 break; 1424 } 1425 1426 spsr = 1427 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1428 CB_SOCKET_STAT); 1429 1430 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1431 if (!(spsr & 0x40)) { /* CINT low */ 1432 #else 1433 if (1) { 1434 #endif 1435 if ((*poll->func) (poll->arg) == 1) { 1436 ++poll->count; 1437 printf("intr: reported from poller, 0x%x\n", spsr); 1438 #if defined LEVEL2 1439 } else { 1440 printf("intr: miss! 0x%x\n", spsr); 1441 #endif 1442 } 1443 } 1444 splx(s); 1445 } 1446 #endif /* defined CB_PCMCIA_POLL */ 1447 1448 /* 1449 * static int pccbb_detect_card(struct pccbb_softc *sc) 1450 * return value: 0 if no card exists. 1451 * 1 if 16-bit card exists. 1452 * 2 if cardbus card exists. 1453 */ 1454 static int 1455 pccbb_detect_card(sc) 1456 struct pccbb_softc *sc; 1457 { 1458 bus_space_handle_t base_memh = sc->sc_base_memh; 1459 bus_space_tag_t base_memt = sc->sc_base_memt; 1460 u_int32_t sockstat = 1461 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1462 int retval = 0; 1463 1464 /* CD1 and CD2 asserted */ 1465 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1466 /* card must be present */ 1467 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1468 /* NOTACARD DEASSERTED */ 1469 if (CB_SOCKET_STAT_CB & sockstat) { 1470 /* CardBus mode */ 1471 retval = 2; 1472 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1473 /* 16-bit mode */ 1474 retval = 1; 1475 } 1476 } 1477 } 1478 return retval; 1479 } 1480 1481 /* 1482 * STATIC int cb_reset(struct pccbb_softc *sc) 1483 * This function resets CardBus card. 1484 */ 1485 STATIC int 1486 cb_reset(sc) 1487 struct pccbb_softc *sc; 1488 { 1489 /* 1490 * Reset Assert at least 20 ms 1491 * Some machines request longer duration. 1492 */ 1493 int reset_duration = 1494 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1495 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1496 1497 /* Reset bit Assert (bit 6 at 0x3E) */ 1498 bcr |= CB_BCR_RESET_ENABLE; 1499 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1500 DELAY_MS(reset_duration, sc); 1501 1502 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1503 /* Reset bit Deassert (bit 6 at 0x3E) */ 1504 bcr &= ~CB_BCR_RESET_ENABLE; 1505 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1506 DELAY_MS(reset_duration, sc); 1507 } 1508 /* No card found on the slot. Keep Reset. */ 1509 return 1; 1510 } 1511 1512 /* 1513 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1514 * This function detect card Voltage. 1515 */ 1516 STATIC int 1517 cb_detect_voltage(sc) 1518 struct pccbb_softc *sc; 1519 { 1520 u_int32_t psr; /* socket present-state reg */ 1521 bus_space_tag_t iot = sc->sc_base_memt; 1522 bus_space_handle_t ioh = sc->sc_base_memh; 1523 int vol = PCCARD_VCC_UKN; /* set 0 */ 1524 1525 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1526 1527 if (0x400u & psr) { 1528 vol |= PCCARD_VCC_5V; 1529 } 1530 if (0x800u & psr) { 1531 vol |= PCCARD_VCC_3V; 1532 } 1533 1534 return vol; 1535 } 1536 1537 STATIC int 1538 cbbprint(aux, pcic) 1539 void *aux; 1540 const char *pcic; 1541 { 1542 /* 1543 struct cbslot_attach_args *cba = aux; 1544 1545 if (cba->cba_slot >= 0) { 1546 aprint_normal(" slot %d", cba->cba_slot); 1547 } 1548 */ 1549 return UNCONF; 1550 } 1551 1552 /* 1553 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1554 * This function enables and disables the card 1555 */ 1556 STATIC int 1557 pccbb_cardenable(sc, function) 1558 struct pccbb_softc *sc; 1559 int function; 1560 { 1561 u_int32_t command = 1562 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1563 1564 DPRINTF(("pccbb_cardenable:")); 1565 switch (function) { 1566 case CARDBUS_IO_ENABLE: 1567 command |= PCI_COMMAND_IO_ENABLE; 1568 break; 1569 case CARDBUS_IO_DISABLE: 1570 command &= ~PCI_COMMAND_IO_ENABLE; 1571 break; 1572 case CARDBUS_MEM_ENABLE: 1573 command |= PCI_COMMAND_MEM_ENABLE; 1574 break; 1575 case CARDBUS_MEM_DISABLE: 1576 command &= ~PCI_COMMAND_MEM_ENABLE; 1577 break; 1578 case CARDBUS_BM_ENABLE: 1579 command |= PCI_COMMAND_MASTER_ENABLE; 1580 break; 1581 case CARDBUS_BM_DISABLE: 1582 command &= ~PCI_COMMAND_MASTER_ENABLE; 1583 break; 1584 default: 1585 return 0; 1586 } 1587 1588 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1589 DPRINTF((" command reg 0x%x\n", command)); 1590 return 1; 1591 } 1592 1593 #if !rbus 1594 /* 1595 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1596 */ 1597 static int 1598 pccbb_io_open(ct, win, start, end) 1599 cardbus_chipset_tag_t ct; 1600 int win; 1601 u_int32_t start, end; 1602 { 1603 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1604 int basereg; 1605 int limitreg; 1606 1607 if ((win < 0) || (win > 2)) { 1608 #if defined DIAGNOSTIC 1609 printf("cardbus_io_open: window out of range %d\n", win); 1610 #endif 1611 return 0; 1612 } 1613 1614 basereg = win * 8 + 0x2c; 1615 limitreg = win * 8 + 0x30; 1616 1617 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1618 start, basereg, end, limitreg)); 1619 1620 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1621 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1622 return 1; 1623 } 1624 1625 /* 1626 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1627 */ 1628 static int 1629 pccbb_io_close(ct, win) 1630 cardbus_chipset_tag_t ct; 1631 int win; 1632 { 1633 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1634 int basereg; 1635 int limitreg; 1636 1637 if ((win < 0) || (win > 2)) { 1638 #if defined DIAGNOSTIC 1639 printf("cardbus_io_close: window out of range %d\n", win); 1640 #endif 1641 return 0; 1642 } 1643 1644 basereg = win * 8 + 0x2c; 1645 limitreg = win * 8 + 0x30; 1646 1647 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1648 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1649 return 1; 1650 } 1651 1652 /* 1653 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1654 */ 1655 static int 1656 pccbb_mem_open(ct, win, start, end) 1657 cardbus_chipset_tag_t ct; 1658 int win; 1659 u_int32_t start, end; 1660 { 1661 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1662 int basereg; 1663 int limitreg; 1664 1665 if ((win < 0) || (win > 2)) { 1666 #if defined DIAGNOSTIC 1667 printf("cardbus_mem_open: window out of range %d\n", win); 1668 #endif 1669 return 0; 1670 } 1671 1672 basereg = win * 8 + 0x1c; 1673 limitreg = win * 8 + 0x20; 1674 1675 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1676 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1677 return 1; 1678 } 1679 1680 /* 1681 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1682 */ 1683 static int 1684 pccbb_mem_close(ct, win) 1685 cardbus_chipset_tag_t ct; 1686 int win; 1687 { 1688 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1689 int basereg; 1690 int limitreg; 1691 1692 if ((win < 0) || (win > 2)) { 1693 #if defined DIAGNOSTIC 1694 printf("cardbus_mem_close: window out of range %d\n", win); 1695 #endif 1696 return 0; 1697 } 1698 1699 basereg = win * 8 + 0x1c; 1700 limitreg = win * 8 + 0x20; 1701 1702 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1703 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1704 return 1; 1705 } 1706 #endif 1707 1708 /* 1709 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1710 * int irq, 1711 * int level, 1712 * int (* func) __P((void *)), 1713 * void *arg) 1714 * 1715 * This function registers an interrupt handler at the bridge, in 1716 * order not to call the interrupt handlers of child devices when 1717 * a card-deletion interrupt occurs. 1718 * 1719 * The arguments irq and level are not used. 1720 */ 1721 static void * 1722 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1723 cardbus_chipset_tag_t ct; 1724 int irq, level; 1725 int (*func) __P((void *)); 1726 void *arg; 1727 { 1728 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1729 1730 return pccbb_intr_establish(sc, irq, level, func, arg); 1731 } 1732 1733 1734 /* 1735 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1736 * void *ih) 1737 * 1738 * This function removes an interrupt handler pointed by ih. 1739 */ 1740 static void 1741 pccbb_cb_intr_disestablish(ct, ih) 1742 cardbus_chipset_tag_t ct; 1743 void *ih; 1744 { 1745 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1746 1747 pccbb_intr_disestablish(sc, ih); 1748 } 1749 1750 1751 void 1752 pccbb_intr_route(sc) 1753 struct pccbb_softc *sc; 1754 { 1755 pcireg_t reg; 1756 1757 /* initialize bridge intr routing */ 1758 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1759 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1760 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1761 1762 switch (sc->sc_chipset) { 1763 case CB_TI113X: 1764 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1765 /* functional intr enabled */ 1766 reg |= PCI113X_CBCTRL_PCI_INTR; 1767 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1768 break; 1769 default: 1770 break; 1771 } 1772 } 1773 1774 /* 1775 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1776 * int irq, 1777 * int level, 1778 * int (* func) __P((void *)), 1779 * void *arg) 1780 * 1781 * This function registers an interrupt handler at the bridge, in 1782 * order not to call the interrupt handlers of child devices when 1783 * a card-deletion interrupt occurs. 1784 * 1785 * The arguments irq is not used because pccbb selects intr vector. 1786 */ 1787 static void * 1788 pccbb_intr_establish(sc, irq, level, func, arg) 1789 struct pccbb_softc *sc; 1790 int irq, level; 1791 int (*func) __P((void *)); 1792 void *arg; 1793 { 1794 struct pccbb_intrhand_list *pil, *newpil; 1795 1796 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1797 1798 if (LIST_EMPTY(&sc->sc_pil)) { 1799 pccbb_intr_route(sc); 1800 } 1801 1802 /* 1803 * Allocate a room for interrupt handler structure. 1804 */ 1805 if (NULL == (newpil = 1806 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1807 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1808 return NULL; 1809 } 1810 1811 newpil->pil_func = func; 1812 newpil->pil_arg = arg; 1813 newpil->pil_level = level; 1814 1815 if (LIST_EMPTY(&sc->sc_pil)) { 1816 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1817 } else { 1818 for (pil = LIST_FIRST(&sc->sc_pil); 1819 LIST_NEXT(pil, pil_next) != NULL; 1820 pil = LIST_NEXT(pil, pil_next)); 1821 LIST_INSERT_AFTER(pil, newpil, pil_next); 1822 } 1823 1824 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1825 LIST_FIRST(&sc->sc_pil))); 1826 1827 return newpil; 1828 } 1829 1830 /* 1831 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1832 * void *ih) 1833 * 1834 * This function removes an interrupt handler pointed by ih. ih 1835 * should be the value returned by cardbus_intr_establish() or 1836 * NULL. 1837 * 1838 * When ih is NULL, this function will do nothing. 1839 */ 1840 static void 1841 pccbb_intr_disestablish(sc, ih) 1842 struct pccbb_softc *sc; 1843 void *ih; 1844 { 1845 struct pccbb_intrhand_list *pil; 1846 pcireg_t reg; 1847 1848 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1849 LIST_FIRST(&sc->sc_pil))); 1850 1851 if (ih == NULL) { 1852 /* intr handler is not set */ 1853 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1854 return; 1855 } 1856 1857 #ifdef DIAGNOSTIC 1858 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1859 pil = LIST_NEXT(pil, pil_next)) { 1860 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1861 if (pil == ih) { 1862 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1863 break; 1864 } 1865 } 1866 if (pil == NULL) { 1867 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1868 sc->sc_dev.dv_xname, ih); 1869 } 1870 #endif 1871 1872 pil = (struct pccbb_intrhand_list *)ih; 1873 LIST_REMOVE(pil, pil_next); 1874 free(pil, M_DEVBUF); 1875 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1876 1877 if (LIST_EMPTY(&sc->sc_pil)) { 1878 /* No interrupt handlers */ 1879 1880 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1881 1882 /* stop routing PCI intr */ 1883 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1884 reg |= CB_BCR_INTR_IREQ_ENABLE; 1885 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1886 1887 switch (sc->sc_chipset) { 1888 case CB_TI113X: 1889 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1890 /* functional intr disabled */ 1891 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1892 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1893 break; 1894 default: 1895 break; 1896 } 1897 } 1898 } 1899 1900 #if defined SHOW_REGS 1901 static void 1902 cb_show_regs(pc, tag, memt, memh) 1903 pci_chipset_tag_t pc; 1904 pcitag_t tag; 1905 bus_space_tag_t memt; 1906 bus_space_handle_t memh; 1907 { 1908 int i; 1909 printf("PCI config regs:"); 1910 for (i = 0; i < 0x50; i += 4) { 1911 if (i % 16 == 0) { 1912 printf("\n 0x%02x:", i); 1913 } 1914 printf(" %08x", pci_conf_read(pc, tag, i)); 1915 } 1916 for (i = 0x80; i < 0xb0; i += 4) { 1917 if (i % 16 == 0) { 1918 printf("\n 0x%02x:", i); 1919 } 1920 printf(" %08x", pci_conf_read(pc, tag, i)); 1921 } 1922 1923 if (memh == 0) { 1924 printf("\n"); 1925 return; 1926 } 1927 1928 printf("\nsocket regs:"); 1929 for (i = 0; i <= 0x10; i += 0x04) { 1930 printf(" %08x", bus_space_read_4(memt, memh, i)); 1931 } 1932 printf("\nExCA regs:"); 1933 for (i = 0; i < 0x08; ++i) { 1934 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1935 } 1936 printf("\n"); 1937 return; 1938 } 1939 #endif 1940 1941 /* 1942 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1943 * int busno, int devno, int function) 1944 * This is the function to make a tag to access config space of 1945 * a CardBus Card. It works same as pci_conf_read. 1946 */ 1947 static cardbustag_t 1948 pccbb_make_tag(cc, busno, devno, function) 1949 cardbus_chipset_tag_t cc; 1950 int busno, devno, function; 1951 { 1952 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1953 1954 return pci_make_tag(sc->sc_pc, busno, devno, function); 1955 } 1956 1957 static void 1958 pccbb_free_tag(cc, tag) 1959 cardbus_chipset_tag_t cc; 1960 cardbustag_t tag; 1961 { 1962 } 1963 1964 /* 1965 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1966 * cardbustag_t tag, int offset) 1967 * This is the function to read the config space of a CardBus Card. 1968 * It works same as pci_conf_read. 1969 */ 1970 static cardbusreg_t 1971 pccbb_conf_read(cc, tag, offset) 1972 cardbus_chipset_tag_t cc; 1973 cardbustag_t tag; 1974 int offset; /* register offset */ 1975 { 1976 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1977 1978 return pci_conf_read(sc->sc_pc, tag, offset); 1979 } 1980 1981 /* 1982 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1983 * int offs, cardbusreg_t val) 1984 * This is the function to write the config space of a CardBus Card. 1985 * It works same as pci_conf_write. 1986 */ 1987 static void 1988 pccbb_conf_write(cc, tag, reg, val) 1989 cardbus_chipset_tag_t cc; 1990 cardbustag_t tag; 1991 int reg; /* register offset */ 1992 cardbusreg_t val; 1993 { 1994 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1995 1996 pci_conf_write(sc->sc_pc, tag, reg, val); 1997 } 1998 1999 #if 0 2000 STATIC int 2001 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2002 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2003 int speed, int flags, 2004 bus_space_handle_t * iohp) 2005 #endif 2006 /* 2007 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2008 * bus_addr_t start, bus_size_t size, 2009 * bus_size_t align, 2010 * struct pcmcia_io_handle *pcihp 2011 * 2012 * This function only allocates I/O region for pccard. This function 2013 * never maps the allocated region to pccard I/O area. 2014 * 2015 * XXX: The interface of this function is not very good, I believe. 2016 */ 2017 STATIC int 2018 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2019 pcmcia_chipset_handle_t pch; 2020 bus_addr_t start; /* start address */ 2021 bus_size_t size; 2022 bus_size_t align; 2023 struct pcmcia_io_handle *pcihp; 2024 { 2025 struct pcic_handle *ph = (struct pcic_handle *)pch; 2026 bus_addr_t ioaddr; 2027 int flags = 0; 2028 bus_space_tag_t iot; 2029 bus_space_handle_t ioh; 2030 bus_addr_t mask; 2031 #if rbus 2032 rbus_tag_t rb; 2033 #endif 2034 if (align == 0) { 2035 align = size; /* XXX: funny??? */ 2036 } 2037 2038 if (start != 0) { 2039 /* XXX: assume all card decode lower 10 bits by its hardware */ 2040 mask = 0x3ff; 2041 /* enforce to use only masked address */ 2042 start &= mask; 2043 } else { 2044 /* 2045 * calculate mask: 2046 * 1. get the most significant bit of size (call it msb). 2047 * 2. compare msb with the value of size. 2048 * 3. if size is larger, shift msb left once. 2049 * 4. obtain mask value to decrement msb. 2050 */ 2051 bus_size_t size_tmp = size; 2052 int shifts = 0; 2053 2054 mask = 1; 2055 while (size_tmp) { 2056 ++shifts; 2057 size_tmp >>= 1; 2058 } 2059 mask = (1 << shifts); 2060 if (mask < size) { 2061 mask <<= 1; 2062 } 2063 --mask; 2064 } 2065 2066 /* 2067 * Allocate some arbitrary I/O space. 2068 */ 2069 2070 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2071 2072 #if rbus 2073 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2074 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2075 return 1; 2076 } 2077 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2078 (u_long) ioaddr, (u_long) size)); 2079 #else 2080 if (start) { 2081 ioaddr = start; 2082 if (bus_space_map(iot, start, size, 0, &ioh)) { 2083 return 1; 2084 } 2085 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2086 (u_long) ioaddr, (u_long) size)); 2087 } else { 2088 flags |= PCMCIA_IO_ALLOCATED; 2089 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2090 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2091 size, align, 0, 0, &ioaddr, &ioh)) { 2092 /* No room be able to be get. */ 2093 return 1; 2094 } 2095 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2096 (u_long) ioaddr, (u_long) size)); 2097 } 2098 #endif 2099 2100 pcihp->iot = iot; 2101 pcihp->ioh = ioh; 2102 pcihp->addr = ioaddr; 2103 pcihp->size = size; 2104 pcihp->flags = flags; 2105 2106 return 0; 2107 } 2108 2109 /* 2110 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2111 * struct pcmcia_io_handle *pcihp) 2112 * 2113 * This function only frees I/O region for pccard. 2114 * 2115 * XXX: The interface of this function is not very good, I believe. 2116 */ 2117 void 2118 pccbb_pcmcia_io_free(pch, pcihp) 2119 pcmcia_chipset_handle_t pch; 2120 struct pcmcia_io_handle *pcihp; 2121 { 2122 #if !rbus 2123 bus_space_tag_t iot = pcihp->iot; 2124 #endif 2125 bus_space_handle_t ioh = pcihp->ioh; 2126 bus_size_t size = pcihp->size; 2127 2128 #if rbus 2129 struct pccbb_softc *sc = 2130 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2131 rbus_tag_t rb = sc->sc_rbus_iot; 2132 2133 rbus_space_free(rb, ioh, size, NULL); 2134 #else 2135 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2136 bus_space_free(iot, ioh, size); 2137 else 2138 bus_space_unmap(iot, ioh, size); 2139 #endif 2140 } 2141 2142 /* 2143 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2144 * bus_addr_t offset, bus_size_t size, 2145 * struct pcmcia_io_handle *pcihp, 2146 * int *windowp) 2147 * 2148 * This function maps the allocated I/O region to pccard. This function 2149 * never allocates any I/O region for pccard I/O area. I don't 2150 * understand why the original authors of pcmciabus separated alloc and 2151 * map. I believe the two must be unite. 2152 * 2153 * XXX: no wait timing control? 2154 */ 2155 int 2156 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2157 pcmcia_chipset_handle_t pch; 2158 int width; 2159 bus_addr_t offset; 2160 bus_size_t size; 2161 struct pcmcia_io_handle *pcihp; 2162 int *windowp; 2163 { 2164 struct pcic_handle *ph = (struct pcic_handle *)pch; 2165 bus_addr_t ioaddr = pcihp->addr + offset; 2166 int i, win; 2167 #if defined CBB_DEBUG 2168 static char *width_names[] = { "dynamic", "io8", "io16" }; 2169 #endif 2170 2171 /* Sanity check I/O handle. */ 2172 2173 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2174 panic("pccbb_pcmcia_io_map iot is bogus"); 2175 } 2176 2177 /* XXX Sanity check offset/size. */ 2178 2179 win = -1; 2180 for (i = 0; i < PCIC_IO_WINS; i++) { 2181 if ((ph->ioalloc & (1 << i)) == 0) { 2182 win = i; 2183 ph->ioalloc |= (1 << i); 2184 break; 2185 } 2186 } 2187 2188 if (win == -1) { 2189 return 1; 2190 } 2191 2192 *windowp = win; 2193 2194 /* XXX this is pretty gross */ 2195 2196 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2197 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2198 2199 /* XXX wtf is this doing here? */ 2200 2201 #if 0 2202 printf(" port 0x%lx", (u_long) ioaddr); 2203 if (size > 1) { 2204 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2205 } 2206 #endif 2207 2208 ph->io[win].addr = ioaddr; 2209 ph->io[win].size = size; 2210 ph->io[win].width = width; 2211 2212 /* actual dirty register-value changing in the function below. */ 2213 pccbb_pcmcia_do_io_map(ph, win); 2214 2215 return 0; 2216 } 2217 2218 /* 2219 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2220 * 2221 * This function changes register-value to map I/O region for pccard. 2222 */ 2223 static void 2224 pccbb_pcmcia_do_io_map(ph, win) 2225 struct pcic_handle *ph; 2226 int win; 2227 { 2228 static u_int8_t pcic_iowidth[3] = { 2229 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2230 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2231 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2232 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2233 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2234 }; 2235 2236 #define PCIC_SIA_START_LOW 0 2237 #define PCIC_SIA_START_HIGH 1 2238 #define PCIC_SIA_STOP_LOW 2 2239 #define PCIC_SIA_STOP_HIGH 3 2240 2241 int regbase_win = 0x8 + win * 0x04; 2242 u_int8_t ioctl, enable; 2243 2244 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2245 "width %d\n", win, (unsigned long)ph->io[win].addr, 2246 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2247 2248 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2249 ph->io[win].addr & 0xff); 2250 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2251 (ph->io[win].addr >> 8) & 0xff); 2252 2253 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2254 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2255 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2256 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2257 2258 ioctl = Pcic_read(ph, PCIC_IOCTL); 2259 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2260 switch (win) { 2261 case 0: 2262 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2263 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2264 PCIC_IOCTL_IO0_DATASIZE_MASK); 2265 ioctl |= pcic_iowidth[ph->io[win].width]; 2266 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2267 break; 2268 case 1: 2269 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2270 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2271 PCIC_IOCTL_IO1_DATASIZE_MASK); 2272 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2273 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2274 break; 2275 } 2276 Pcic_write(ph, PCIC_IOCTL, ioctl); 2277 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2278 #if defined CBB_DEBUG 2279 { 2280 u_int8_t start_low = 2281 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2282 u_int8_t start_high = 2283 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2284 u_int8_t stop_low = 2285 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2286 u_int8_t stop_high = 2287 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2288 printf 2289 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2290 start_low, start_high, stop_low, stop_high, ioctl, enable); 2291 } 2292 #endif 2293 } 2294 2295 /* 2296 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2297 * 2298 * This function unmaps I/O region. No return value. 2299 */ 2300 STATIC void 2301 pccbb_pcmcia_io_unmap(pch, win) 2302 pcmcia_chipset_handle_t pch; 2303 int win; 2304 { 2305 struct pcic_handle *ph = (struct pcic_handle *)pch; 2306 int reg; 2307 2308 if (win >= PCIC_IO_WINS || win < 0) { 2309 panic("pccbb_pcmcia_io_unmap: window out of range"); 2310 } 2311 2312 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2313 switch (win) { 2314 case 0: 2315 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2316 break; 2317 case 1: 2318 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2319 break; 2320 } 2321 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2322 2323 ph->ioalloc &= ~(1 << win); 2324 } 2325 2326 static int 2327 pccbb_pcmcia_wait_ready(ph) 2328 struct pcic_handle *ph; 2329 { 2330 u_int8_t stat; 2331 int i; 2332 2333 /* wait an initial 10ms for quick cards */ 2334 stat = Pcic_read(ph, PCIC_IF_STATUS); 2335 if (stat & PCIC_IF_STATUS_READY) 2336 return (0); 2337 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2338 for (i = 0; i < 50; i++) { 2339 stat = Pcic_read(ph, PCIC_IF_STATUS); 2340 if (stat & PCIC_IF_STATUS_READY) 2341 return (0); 2342 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2343 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2344 return (ENXIO); 2345 /* wait .1s (100ms) each iteration now */ 2346 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2347 } 2348 2349 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2350 return (EWOULDBLOCK); 2351 } 2352 2353 /* 2354 * Perform long (msec order) delay. 2355 */ 2356 static void 2357 pccbb_pcmcia_delay(ph, timo, wmesg) 2358 struct pcic_handle *ph; 2359 int timo; /* in ms. must not be zero */ 2360 const char *wmesg; 2361 { 2362 2363 #ifdef DIAGNOSTIC 2364 if (timo <= 0) 2365 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2366 if (!curlwp) 2367 panic("pccbb_pcmcia_delay: called in interrupt context"); 2368 #if 0 2369 if (!ph->event_thread) 2370 panic("pccbb_pcmcia_delay: no event thread"); 2371 #endif 2372 #endif 2373 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2374 wmesg, h->event_thread, timo)); 2375 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2376 } 2377 2378 /* 2379 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2380 * 2381 * This function enables the card. All information is stored in 2382 * the first argument, pcmcia_chipset_handle_t. 2383 */ 2384 STATIC void 2385 pccbb_pcmcia_socket_enable(pch) 2386 pcmcia_chipset_handle_t pch; 2387 { 2388 struct pcic_handle *ph = (struct pcic_handle *)pch; 2389 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2390 pcireg_t spsr; 2391 int voltage; 2392 int win; 2393 u_int8_t power, intr; 2394 #ifdef DIAGNOSTIC 2395 int reg; 2396 #endif 2397 2398 /* this bit is mostly stolen from pcic_attach_card */ 2399 2400 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2401 2402 /* get card Vcc info */ 2403 spsr = 2404 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2405 CB_SOCKET_STAT); 2406 if (spsr & CB_SOCKET_STAT_5VCARD) { 2407 DPRINTF(("5V card\n")); 2408 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2409 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2410 DPRINTF(("3V card\n")); 2411 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2412 } else { 2413 printf("?V card, 0x%x\n", spsr); /* XXX */ 2414 return; 2415 } 2416 2417 /* disable interrupts; assert RESET */ 2418 intr = Pcic_read(ph, PCIC_INTR); 2419 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2420 intr &= ~PCIC_INTR_RESET; 2421 Pcic_write(ph, PCIC_INTR, intr); 2422 2423 /* zero out the address windows */ 2424 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2425 2426 /* power down the socket to reset it, clear the card reset pin */ 2427 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2428 2429 /* power off; assert output enable bit */ 2430 power = PCIC_PWRCTL_OE; 2431 Pcic_write(ph, PCIC_PWRCTL, power); 2432 2433 /* power up the socket */ 2434 if (pccbb_power(sc, voltage) == 0) 2435 return; 2436 2437 /* 2438 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2439 * Vcc Rising Time (Tpr) = 100ms 2440 * RESET Width (Th (Hi-z RESET)) = 1ms 2441 * RESET Width (Tw (RESET)) = 10us 2442 * 2443 * some machines require some more time to be settled 2444 * (100ms is added here). 2445 */ 2446 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2447 2448 /* negate RESET */ 2449 intr |= PCIC_INTR_RESET; 2450 Pcic_write(ph, PCIC_INTR, intr); 2451 2452 /* 2453 * RESET Setup Time (Tsu (RESET)) = 20ms 2454 */ 2455 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2456 2457 #ifdef DIAGNOSTIC 2458 reg = Pcic_read(ph, PCIC_IF_STATUS); 2459 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2460 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2461 #endif 2462 2463 /* wait for the chip to finish initializing */ 2464 if (pccbb_pcmcia_wait_ready(ph)) { 2465 /* XXX return a failure status?? */ 2466 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2467 Pcic_write(ph, PCIC_PWRCTL, 0); 2468 return; 2469 } 2470 2471 /* reinstall all the memory and io mappings */ 2472 for (win = 0; win < PCIC_MEM_WINS; ++win) 2473 if (ph->memalloc & (1 << win)) 2474 pccbb_pcmcia_do_mem_map(ph, win); 2475 for (win = 0; win < PCIC_IO_WINS; ++win) 2476 if (ph->ioalloc & (1 << win)) 2477 pccbb_pcmcia_do_io_map(ph, win); 2478 } 2479 2480 /* 2481 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2482 * 2483 * This function disables the card. All information is stored in 2484 * the first argument, pcmcia_chipset_handle_t. 2485 */ 2486 STATIC void 2487 pccbb_pcmcia_socket_disable(pch) 2488 pcmcia_chipset_handle_t pch; 2489 { 2490 struct pcic_handle *ph = (struct pcic_handle *)pch; 2491 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2492 u_int8_t intr; 2493 2494 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2495 2496 /* disable interrupts; assert RESET */ 2497 intr = Pcic_read(ph, PCIC_INTR); 2498 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2499 intr &= ~PCIC_INTR_RESET; 2500 Pcic_write(ph, PCIC_INTR, intr); 2501 2502 /* zero out the address windows */ 2503 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2504 2505 /* power down the socket to reset it, clear the card reset pin */ 2506 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2507 2508 /* disable socket: negate output enable bit and power off */ 2509 Pcic_write(ph, PCIC_PWRCTL, 0); 2510 2511 /* 2512 * Vcc Falling Time (Tpf) = 300ms 2513 */ 2514 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2515 } 2516 2517 STATIC void 2518 pccbb_pcmcia_socket_settype(pch, type) 2519 pcmcia_chipset_handle_t pch; 2520 int type; 2521 { 2522 struct pcic_handle *ph = (struct pcic_handle *)pch; 2523 u_int8_t intr; 2524 2525 /* set the card type */ 2526 2527 intr = Pcic_read(ph, PCIC_INTR); 2528 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2529 if (type == PCMCIA_IFTYPE_IO) 2530 intr |= PCIC_INTR_CARDTYPE_IO; 2531 else 2532 intr |= PCIC_INTR_CARDTYPE_MEM; 2533 Pcic_write(ph, PCIC_INTR, intr); 2534 2535 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2536 ph->ph_parent->dv_xname, ph->sock, 2537 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2538 } 2539 2540 /* 2541 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2542 * 2543 * This function detects whether a card is in the slot or not. 2544 * If a card is inserted, return 1. Otherwise, return 0. 2545 */ 2546 STATIC int 2547 pccbb_pcmcia_card_detect(pch) 2548 pcmcia_chipset_handle_t pch; 2549 { 2550 struct pcic_handle *ph = (struct pcic_handle *)pch; 2551 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2552 2553 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2554 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2555 } 2556 2557 #if 0 2558 STATIC int 2559 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2560 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2561 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2562 #endif 2563 /* 2564 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2565 * bus_size_t size, 2566 * struct pcmcia_mem_handle *pcmhp) 2567 * 2568 * This function only allocates memory region for pccard. This 2569 * function never maps the allocated region to pccard memory area. 2570 * 2571 * XXX: Why the argument of start address is not in? 2572 */ 2573 STATIC int 2574 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2575 pcmcia_chipset_handle_t pch; 2576 bus_size_t size; 2577 struct pcmcia_mem_handle *pcmhp; 2578 { 2579 struct pcic_handle *ph = (struct pcic_handle *)pch; 2580 bus_space_handle_t memh; 2581 bus_addr_t addr; 2582 bus_size_t sizepg; 2583 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2584 #if rbus 2585 rbus_tag_t rb; 2586 #endif 2587 2588 /* Check that the card is still there. */ 2589 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2590 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2591 return 1; 2592 2593 /* out of sc->memh, allocate as many pages as necessary */ 2594 2595 /* convert size to PCIC pages */ 2596 /* 2597 * This is not enough; when the requested region is on the page 2598 * boundaries, this may calculate wrong result. 2599 */ 2600 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2601 #if 0 2602 if (sizepg > PCIC_MAX_MEM_PAGES) { 2603 return 1; 2604 } 2605 #endif 2606 2607 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2608 return 1; 2609 } 2610 2611 addr = 0; /* XXX gcc -Wuninitialized */ 2612 2613 #if rbus 2614 rb = sc->sc_rbus_memt; 2615 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2616 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2617 &addr, &memh)) { 2618 return 1; 2619 } 2620 #else 2621 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2622 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2623 0, /* boundary */ 2624 0, /* flags */ 2625 &addr, &memh)) { 2626 return 1; 2627 } 2628 #endif 2629 2630 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2631 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2632 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2633 2634 pcmhp->memt = sc->sc_memt; 2635 pcmhp->memh = memh; 2636 pcmhp->addr = addr; 2637 pcmhp->size = size; 2638 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2639 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2640 pcmhp->mhandle = 0; 2641 /* No offset??? Funny. */ 2642 2643 return 0; 2644 } 2645 2646 /* 2647 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2648 * struct pcmcia_mem_handle *pcmhp) 2649 * 2650 * This function release the memory space allocated by the function 2651 * pccbb_pcmcia_mem_alloc(). 2652 */ 2653 STATIC void 2654 pccbb_pcmcia_mem_free(pch, pcmhp) 2655 pcmcia_chipset_handle_t pch; 2656 struct pcmcia_mem_handle *pcmhp; 2657 { 2658 #if rbus 2659 struct pcic_handle *ph = (struct pcic_handle *)pch; 2660 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2661 2662 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2663 #else 2664 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2665 #endif 2666 } 2667 2668 /* 2669 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2670 * 2671 * This function release the memory space allocated by the function 2672 * pccbb_pcmcia_mem_alloc(). 2673 */ 2674 STATIC void 2675 pccbb_pcmcia_do_mem_map(ph, win) 2676 struct pcic_handle *ph; 2677 int win; 2678 { 2679 int regbase_win; 2680 bus_addr_t phys_addr; 2681 bus_addr_t phys_end; 2682 2683 #define PCIC_SMM_START_LOW 0 2684 #define PCIC_SMM_START_HIGH 1 2685 #define PCIC_SMM_STOP_LOW 2 2686 #define PCIC_SMM_STOP_HIGH 3 2687 #define PCIC_CMA_LOW 4 2688 #define PCIC_CMA_HIGH 5 2689 2690 u_int8_t start_low, start_high = 0; 2691 u_int8_t stop_low, stop_high; 2692 u_int8_t off_low, off_high; 2693 u_int8_t mem_window; 2694 int reg; 2695 2696 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2697 int mem8 = 2698 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2699 || (kind == PCMCIA_MEM_ATTR); 2700 2701 regbase_win = 0x10 + win * 0x08; 2702 2703 phys_addr = ph->mem[win].addr; 2704 phys_end = phys_addr + ph->mem[win].size; 2705 2706 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2707 (unsigned long)phys_addr, (unsigned long)phys_end, 2708 (unsigned long)ph->mem[win].offset)); 2709 2710 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2711 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2712 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2713 2714 /* bit 19:12 */ 2715 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2716 /* bit 23:20 and bit 7 on */ 2717 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2718 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2719 /* bit 31:24, for 32-bit address */ 2720 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2721 2722 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2723 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2724 2725 if (((struct pccbb_softc *)ph-> 2726 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2727 Pcic_write(ph, 0x40 + win, mem_window); 2728 } 2729 2730 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2731 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2732 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2733 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2734 2735 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2736 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2737 2738 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2739 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2740 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2741 | ((kind == PCMCIA_MEM_ATTR) ? 2742 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2743 2744 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2745 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2746 2747 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2748 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2749 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2750 2751 #if defined CBB_DEBUG 2752 { 2753 int r1, r2, r3, r4, r5, r6, r7 = 0; 2754 2755 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2756 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2757 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2758 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2759 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2760 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2761 if (((struct pccbb_softc *)(ph-> 2762 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2763 r7 = Pcic_read(ph, 0x40 + win); 2764 } 2765 2766 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2767 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2768 if (((struct pccbb_softc *)(ph-> 2769 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2770 DPRINTF((" %02x", r7)); 2771 } 2772 DPRINTF(("\n")); 2773 } 2774 #endif 2775 } 2776 2777 /* 2778 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2779 * bus_addr_t card_addr, bus_size_t size, 2780 * struct pcmcia_mem_handle *pcmhp, 2781 * bus_addr_t *offsetp, int *windowp) 2782 * 2783 * This function maps memory space allocated by the function 2784 * pccbb_pcmcia_mem_alloc(). 2785 */ 2786 STATIC int 2787 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2788 pcmcia_chipset_handle_t pch; 2789 int kind; 2790 bus_addr_t card_addr; 2791 bus_size_t size; 2792 struct pcmcia_mem_handle *pcmhp; 2793 bus_addr_t *offsetp; 2794 int *windowp; 2795 { 2796 struct pcic_handle *ph = (struct pcic_handle *)pch; 2797 bus_addr_t busaddr; 2798 long card_offset; 2799 int win; 2800 2801 /* Check that the card is still there. */ 2802 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2803 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2804 return 1; 2805 2806 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2807 if ((ph->memalloc & (1 << win)) == 0) { 2808 ph->memalloc |= (1 << win); 2809 break; 2810 } 2811 } 2812 2813 if (win == PCIC_MEM_WINS) { 2814 return 1; 2815 } 2816 2817 *windowp = win; 2818 2819 /* XXX this is pretty gross */ 2820 2821 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2822 panic("pccbb_pcmcia_mem_map memt is bogus"); 2823 } 2824 2825 busaddr = pcmhp->addr; 2826 2827 /* 2828 * compute the address offset to the pcmcia address space for the 2829 * pcic. this is intentionally signed. The masks and shifts below 2830 * will cause TRT to happen in the pcic registers. Deal with making 2831 * sure the address is aligned, and return the alignment offset. 2832 */ 2833 2834 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2835 card_addr -= *offsetp; 2836 2837 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2838 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2839 (u_long) card_addr)); 2840 2841 /* 2842 * include the offset in the size, and decrement size by one, since 2843 * the hw wants start/stop 2844 */ 2845 size += *offsetp - 1; 2846 2847 card_offset = (((long)card_addr) - ((long)busaddr)); 2848 2849 ph->mem[win].addr = busaddr; 2850 ph->mem[win].size = size; 2851 ph->mem[win].offset = card_offset; 2852 ph->mem[win].kind = kind; 2853 2854 pccbb_pcmcia_do_mem_map(ph, win); 2855 2856 return 0; 2857 } 2858 2859 /* 2860 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2861 * int window) 2862 * 2863 * This function unmaps memory space which mapped by the function 2864 * pccbb_pcmcia_mem_map(). 2865 */ 2866 STATIC void 2867 pccbb_pcmcia_mem_unmap(pch, window) 2868 pcmcia_chipset_handle_t pch; 2869 int window; 2870 { 2871 struct pcic_handle *ph = (struct pcic_handle *)pch; 2872 int reg; 2873 2874 if (window >= PCIC_MEM_WINS) { 2875 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2876 } 2877 2878 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2879 reg &= ~(1 << window); 2880 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2881 2882 ph->memalloc &= ~(1 << window); 2883 } 2884 2885 #if defined PCCBB_PCMCIA_POLL 2886 struct pccbb_poll_str { 2887 void *arg; 2888 int (*func) __P((void *)); 2889 int level; 2890 struct pcic_handle *ph; 2891 int count; 2892 int num; 2893 struct callout poll_ch; 2894 }; 2895 2896 static struct pccbb_poll_str pccbb_poll[10]; 2897 static int pccbb_poll_n = 0; 2898 2899 static void pccbb_pcmcia_poll __P((void *arg)); 2900 2901 static void 2902 pccbb_pcmcia_poll(arg) 2903 void *arg; 2904 { 2905 struct pccbb_poll_str *poll = arg; 2906 struct pcic_handle *ph = poll->ph; 2907 struct pccbb_softc *sc = ph->sc; 2908 int s; 2909 u_int32_t spsr; /* socket present-state reg */ 2910 2911 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2912 switch (poll->level) { 2913 case IPL_NET: 2914 s = splnet(); 2915 break; 2916 case IPL_BIO: 2917 s = splbio(); 2918 break; 2919 case IPL_TTY: /* fallthrough */ 2920 default: 2921 s = spltty(); 2922 break; 2923 } 2924 2925 spsr = 2926 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2927 CB_SOCKET_STAT); 2928 2929 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2930 if (!(spsr & 0x40)) /* CINT low */ 2931 #else 2932 if (1) 2933 #endif 2934 { 2935 if ((*poll->func) (poll->arg) > 0) { 2936 ++poll->count; 2937 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2938 #if defined LEVEL2 2939 } else { 2940 printf("intr: miss! 0x%x\n", spsr); 2941 #endif 2942 } 2943 } 2944 splx(s); 2945 } 2946 #endif /* defined CB_PCMCIA_POLL */ 2947 2948 /* 2949 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2950 * struct pcmcia_function *pf, 2951 * int ipl, 2952 * int (*func)(void *), 2953 * void *arg); 2954 * 2955 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2956 */ 2957 STATIC void * 2958 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2959 pcmcia_chipset_handle_t pch; 2960 struct pcmcia_function *pf; 2961 int ipl; 2962 int (*func) __P((void *)); 2963 void *arg; 2964 { 2965 struct pcic_handle *ph = (struct pcic_handle *)pch; 2966 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2967 2968 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2969 /* what should I do? */ 2970 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2971 DPRINTF(("%s does not provide edge nor pulse " 2972 "interrupt\n", sc->sc_dev.dv_xname)); 2973 return NULL; 2974 } 2975 /* 2976 * XXX Noooooo! The interrupt flag must set properly!! 2977 * dumb pcmcia driver!! 2978 */ 2979 } 2980 2981 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2982 } 2983 2984 /* 2985 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2986 * void *ih) 2987 * 2988 * This function disables PC-Card interrupt. 2989 */ 2990 STATIC void 2991 pccbb_pcmcia_intr_disestablish(pch, ih) 2992 pcmcia_chipset_handle_t pch; 2993 void *ih; 2994 { 2995 struct pcic_handle *ph = (struct pcic_handle *)pch; 2996 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2997 2998 pccbb_intr_disestablish(sc, ih); 2999 } 3000 3001 #if rbus 3002 /* 3003 * static int 3004 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3005 * bus_addr_t addr, bus_size_t size, 3006 * bus_addr_t mask, bus_size_t align, 3007 * int flags, bus_addr_t *addrp; 3008 * bus_space_handle_t *bshp) 3009 * 3010 * This function allocates a portion of memory or io space for 3011 * clients. This function is called from CardBus card drivers. 3012 */ 3013 static int 3014 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3015 cardbus_chipset_tag_t ct; 3016 rbus_tag_t rb; 3017 bus_addr_t addr; 3018 bus_size_t size; 3019 bus_addr_t mask; 3020 bus_size_t align; 3021 int flags; 3022 bus_addr_t *addrp; 3023 bus_space_handle_t *bshp; 3024 { 3025 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3026 3027 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3028 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3029 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3030 3031 if (align == 0) { 3032 align = size; 3033 } 3034 3035 if (rb->rb_bt == sc->sc_memt) { 3036 if (align < 16) { 3037 return 1; 3038 } 3039 /* 3040 * XXX: align more than 0x1000 to avoid overwrapping 3041 * memory windows for two or more devices. 0x1000 3042 * means memory window's granularity. 3043 * 3044 * Two or more devices should be able to share same 3045 * memory window region. However, overrapping memory 3046 * window is not good because some devices, such as 3047 * 3Com 3C575[BC], have a broken address decoder and 3048 * intrude other's memory region. 3049 */ 3050 if (align < 0x1000) { 3051 align = 0x1000; 3052 } 3053 } else if (rb->rb_bt == sc->sc_iot) { 3054 if (align < 4) { 3055 return 1; 3056 } 3057 /* XXX: hack for avoiding ISA image */ 3058 if (mask < 0x0100) { 3059 mask = 0x3ff; 3060 addr = 0x300; 3061 } 3062 3063 } else { 3064 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3065 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3066 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3067 (unsigned long)sc->sc_memt)); 3068 return 1; 3069 /* XXX: panic here? */ 3070 } 3071 3072 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3073 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3074 return 1; 3075 } 3076 3077 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3078 3079 return 0; 3080 } 3081 3082 /* 3083 * static int 3084 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3085 * bus_space_handle_t *bshp, bus_size_t size); 3086 * 3087 * This function is called from CardBus card drivers. 3088 */ 3089 static int 3090 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3091 cardbus_chipset_tag_t ct; 3092 rbus_tag_t rb; 3093 bus_space_handle_t bsh; 3094 bus_size_t size; 3095 { 3096 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3097 bus_space_tag_t bt = rb->rb_bt; 3098 3099 pccbb_close_win(sc, bt, bsh, size); 3100 3101 if (bt == sc->sc_memt) { 3102 } else if (bt == sc->sc_iot) { 3103 } else { 3104 return 1; 3105 /* XXX: panic here? */ 3106 } 3107 3108 return rbus_space_free(rb, bsh, size, NULL); 3109 } 3110 #endif /* rbus */ 3111 3112 #if rbus 3113 3114 static int 3115 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3116 struct pccbb_softc *sc; 3117 bus_space_tag_t bst; 3118 bus_addr_t addr; 3119 bus_size_t size; 3120 bus_space_handle_t bsh; 3121 int flags; 3122 { 3123 struct pccbb_win_chain_head *head; 3124 bus_addr_t align; 3125 3126 head = &sc->sc_iowindow; 3127 align = 0x04; 3128 if (sc->sc_memt == bst) { 3129 head = &sc->sc_memwindow; 3130 align = 0x1000; 3131 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3132 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3133 (unsigned long)bst)); 3134 } 3135 3136 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3137 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3138 sc->sc_dev.dv_xname, 3139 (head == &sc->sc_memwindow) ? "mem" : "io"); 3140 } 3141 pccbb_winset(align, sc, bst); 3142 3143 return 0; 3144 } 3145 3146 static int 3147 pccbb_close_win(sc, bst, bsh, size) 3148 struct pccbb_softc *sc; 3149 bus_space_tag_t bst; 3150 bus_space_handle_t bsh; 3151 bus_size_t size; 3152 { 3153 struct pccbb_win_chain_head *head; 3154 bus_addr_t align; 3155 3156 head = &sc->sc_iowindow; 3157 align = 0x04; 3158 if (sc->sc_memt == bst) { 3159 head = &sc->sc_memwindow; 3160 align = 0x1000; 3161 } 3162 3163 if (pccbb_winlist_delete(head, bsh, size)) { 3164 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3165 sc->sc_dev.dv_xname, 3166 (head == &sc->sc_memwindow) ? "mem" : "io"); 3167 } 3168 pccbb_winset(align, sc, bst); 3169 3170 return 0; 3171 } 3172 3173 static int 3174 pccbb_winlist_insert(head, start, size, bsh, flags) 3175 struct pccbb_win_chain_head *head; 3176 bus_addr_t start; 3177 bus_size_t size; 3178 bus_space_handle_t bsh; 3179 int flags; 3180 { 3181 struct pccbb_win_chain *chainp, *elem; 3182 3183 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3184 M_NOWAIT)) == NULL) 3185 return (1); /* fail */ 3186 3187 elem->wc_start = start; 3188 elem->wc_end = start + (size - 1); 3189 elem->wc_handle = bsh; 3190 elem->wc_flags = flags; 3191 3192 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3193 chainp = TAILQ_NEXT(chainp, wc_list)) { 3194 if (chainp->wc_end < start) 3195 continue; 3196 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3197 return (0); 3198 } 3199 3200 TAILQ_INSERT_TAIL(head, elem, wc_list); 3201 return (0); 3202 } 3203 3204 static int 3205 pccbb_winlist_delete(head, bsh, size) 3206 struct pccbb_win_chain_head *head; 3207 bus_space_handle_t bsh; 3208 bus_size_t size; 3209 { 3210 struct pccbb_win_chain *chainp; 3211 3212 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3213 chainp = TAILQ_NEXT(chainp, wc_list)) { 3214 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3215 continue; 3216 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3217 printf("pccbb_winlist_delete: window 0x%lx size " 3218 "inconsistent: 0x%lx, 0x%lx\n", 3219 (unsigned long)chainp->wc_start, 3220 (unsigned long)(chainp->wc_end - chainp->wc_start), 3221 (unsigned long)(size - 1)); 3222 return 1; 3223 } 3224 3225 TAILQ_REMOVE(head, chainp, wc_list); 3226 free(chainp, M_DEVBUF); 3227 3228 return 0; 3229 } 3230 3231 return 1; /* fail: no candidate to remove */ 3232 } 3233 3234 static void 3235 pccbb_winset(align, sc, bst) 3236 bus_addr_t align; 3237 struct pccbb_softc *sc; 3238 bus_space_tag_t bst; 3239 { 3240 pci_chipset_tag_t pc; 3241 pcitag_t tag; 3242 bus_addr_t mask = ~(align - 1); 3243 struct { 3244 cardbusreg_t win_start; 3245 cardbusreg_t win_limit; 3246 int win_flags; 3247 } win[2]; 3248 struct pccbb_win_chain *chainp; 3249 int offs; 3250 3251 win[0].win_start = win[1].win_start = 0xffffffff; 3252 win[0].win_limit = win[1].win_limit = 0; 3253 win[0].win_flags = win[1].win_flags = 0; 3254 3255 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3256 offs = 0x2c; 3257 if (sc->sc_memt == bst) { 3258 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3259 offs = 0x1c; 3260 } 3261 3262 if (chainp != NULL) { 3263 win[0].win_start = chainp->wc_start & mask; 3264 win[0].win_limit = chainp->wc_end & mask; 3265 win[0].win_flags = chainp->wc_flags; 3266 chainp = TAILQ_NEXT(chainp, wc_list); 3267 } 3268 3269 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3270 if (win[1].win_start == 0xffffffff) { 3271 /* window 1 is not used */ 3272 if ((win[0].win_flags == chainp->wc_flags) && 3273 (win[0].win_limit + align >= 3274 (chainp->wc_start & mask))) { 3275 /* concatenate */ 3276 win[0].win_limit = chainp->wc_end & mask; 3277 } else { 3278 /* make new window */ 3279 win[1].win_start = chainp->wc_start & mask; 3280 win[1].win_limit = chainp->wc_end & mask; 3281 win[1].win_flags = chainp->wc_flags; 3282 } 3283 continue; 3284 } 3285 3286 /* Both windows are engaged. */ 3287 if (win[0].win_flags == win[1].win_flags) { 3288 /* same flags */ 3289 if (win[0].win_flags == chainp->wc_flags) { 3290 if (win[1].win_start - (win[0].win_limit + 3291 align) < 3292 (chainp->wc_start & mask) - 3293 ((chainp->wc_end & mask) + align)) { 3294 /* 3295 * merge window 0 and 1, and set win1 3296 * to chainp 3297 */ 3298 win[0].win_limit = win[1].win_limit; 3299 win[1].win_start = 3300 chainp->wc_start & mask; 3301 win[1].win_limit = 3302 chainp->wc_end & mask; 3303 } else { 3304 win[1].win_limit = 3305 chainp->wc_end & mask; 3306 } 3307 } else { 3308 /* different flags */ 3309 3310 /* concatenate win0 and win1 */ 3311 win[0].win_limit = win[1].win_limit; 3312 /* allocate win[1] to new space */ 3313 win[1].win_start = chainp->wc_start & mask; 3314 win[1].win_limit = chainp->wc_end & mask; 3315 win[1].win_flags = chainp->wc_flags; 3316 } 3317 } else { 3318 /* the flags of win[0] and win[1] is different */ 3319 if (win[0].win_flags == chainp->wc_flags) { 3320 win[0].win_limit = chainp->wc_end & mask; 3321 /* 3322 * XXX this creates overlapping windows, so 3323 * what should the poor bridge do if one is 3324 * cachable, and the other is not? 3325 */ 3326 printf("%s: overlapping windows\n", 3327 sc->sc_dev.dv_xname); 3328 } else { 3329 win[1].win_limit = chainp->wc_end & mask; 3330 } 3331 } 3332 } 3333 3334 pc = sc->sc_pc; 3335 tag = sc->sc_tag; 3336 pci_conf_write(pc, tag, offs, win[0].win_start); 3337 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3338 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3339 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3340 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3341 (unsigned long)pci_conf_read(pc, tag, offs), 3342 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3343 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3344 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3345 3346 if (bst == sc->sc_memt) { 3347 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3348 3349 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3350 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3351 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3352 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3353 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3354 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3355 } 3356 } 3357 3358 #endif /* rbus */ 3359 3360 static void 3361 pccbb_powerhook(why, arg) 3362 int why; 3363 void *arg; 3364 { 3365 struct pccbb_softc *sc = arg; 3366 pcireg_t reg; 3367 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3368 bus_space_handle_t base_memh = sc->sc_base_memh; 3369 3370 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3371 3372 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3373 DPRINTF(("%s: power: why %d stopping intr\n", 3374 sc->sc_dev.dv_xname, why)); 3375 if (sc->sc_pil_intr_enable) { 3376 (void)pccbbintr_function(sc); 3377 } 3378 sc->sc_pil_intr_enable = 0; 3379 3380 /* ToDo: deactivate or suspend child devices */ 3381 3382 } 3383 3384 if (why == PWR_RESUME) { 3385 if (sc->sc_pwrmgt_offs != 0) { 3386 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3387 sc->sc_pwrmgt_offs + 4); 3388 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3389 reg & 0x100) { 3390 /* powrstate != D0 */ 3391 3392 printf("%s going back to D0 mode\n", 3393 sc->sc_dev.dv_xname); 3394 reg &= ~PCI_PMCSR_STATE_MASK; 3395 reg |= PCI_PMCSR_STATE_D0; 3396 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3397 pci_conf_write(sc->sc_pc, sc->sc_tag, 3398 sc->sc_pwrmgt_offs + 4, reg); 3399 3400 pci_conf_write(sc->sc_pc, sc->sc_tag, 3401 PCI_SOCKBASE, sc->sc_sockbase); 3402 pci_conf_write(sc->sc_pc, sc->sc_tag, 3403 PCI_BUSNUM, sc->sc_busnum); 3404 pccbb_chipinit(sc); 3405 /* setup memory and io space window for CB */ 3406 pccbb_winset(0x1000, sc, sc->sc_memt); 3407 pccbb_winset(0x04, sc, sc->sc_iot); 3408 } 3409 } 3410 3411 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3412 /* BIOS did not recover this register */ 3413 pci_conf_write (sc->sc_pc, sc->sc_tag, 3414 PCI_SOCKBASE, sc->sc_sockbase); 3415 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3416 /* BIOS did not recover this register */ 3417 pci_conf_write (sc->sc_pc, sc->sc_tag, 3418 PCI_BUSNUM, sc->sc_busnum); 3419 /* CSC Interrupt: Card detect interrupt on */ 3420 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3421 /* Card detect intr is turned on. */ 3422 reg |= CB_SOCKET_MASK_CD; 3423 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3424 /* reset interrupt */ 3425 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3426 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3427 3428 /* 3429 * check for card insertion or removal during suspend period. 3430 * XXX: the code can't cope with card swap (remove then 3431 * insert). how can we detect such situation? 3432 */ 3433 (void)pccbbintr(sc); 3434 3435 sc->sc_pil_intr_enable = 1; 3436 DPRINTF(("%s: power: RESUME enabling intr\n", 3437 sc->sc_dev.dv_xname)); 3438 3439 /* ToDo: activate or wakeup child devices */ 3440 } 3441 } 3442
Indexes created Sat Sep 27 21:09:56 GMT 2025