pccbb.c revision 1.111
1 /* $NetBSD: pccbb.c,v 1.111 2005/01/16 08:51:55 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.111 2005/01/16 08:51:55 mycroft Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC void pccbb_pcmcia_socket_settype __P((pcmcia_chipset_handle_t, int)); 188 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 189 190 static int pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_delay __P((struct pcic_handle *, int, const char *)); 192 193 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 194 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 195 static void pccbb_powerhook __P((int, void *)); 196 197 /* bus-space allocation and deallocation functions */ 198 #if rbus 199 200 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 202 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 203 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 204 bus_space_handle_t, bus_size_t)); 205 206 #endif /* rbus */ 207 208 #if rbus 209 210 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 211 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 212 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 213 bus_space_handle_t, bus_size_t)); 214 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 215 bus_size_t, bus_space_handle_t, int)); 216 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 217 bus_space_handle_t, bus_size_t)); 218 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 219 bus_space_tag_t)); 220 void pccbb_winlist_show(struct pccbb_win_chain *); 221 222 #endif /* rbus */ 223 224 /* for config_defer */ 225 static void pccbb_pci_callback __P((struct device *)); 226 227 #if defined SHOW_REGS 228 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 229 bus_space_tag_t memt, bus_space_handle_t memh)); 230 #endif 231 232 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 233 pcicbbmatch, pccbbattach, NULL, NULL); 234 235 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 236 pccbb_pcmcia_mem_alloc, 237 pccbb_pcmcia_mem_free, 238 pccbb_pcmcia_mem_map, 239 pccbb_pcmcia_mem_unmap, 240 pccbb_pcmcia_io_alloc, 241 pccbb_pcmcia_io_free, 242 pccbb_pcmcia_io_map, 243 pccbb_pcmcia_io_unmap, 244 pccbb_pcmcia_intr_establish, 245 pccbb_pcmcia_intr_disestablish, 246 pccbb_pcmcia_socket_enable, 247 pccbb_pcmcia_socket_disable, 248 pccbb_pcmcia_socket_settype, 249 pccbb_pcmcia_card_detect 250 }; 251 252 #if rbus 253 static struct cardbus_functions pccbb_funcs = { 254 pccbb_rbus_cb_space_alloc, 255 pccbb_rbus_cb_space_free, 256 pccbb_cb_intr_establish, 257 pccbb_cb_intr_disestablish, 258 pccbb_ctrl, 259 pccbb_power, 260 pccbb_make_tag, 261 pccbb_free_tag, 262 pccbb_conf_read, 263 pccbb_conf_write, 264 }; 265 #else 266 static struct cardbus_functions pccbb_funcs = { 267 pccbb_ctrl, 268 pccbb_power, 269 pccbb_mem_open, 270 pccbb_mem_close, 271 pccbb_io_open, 272 pccbb_io_close, 273 pccbb_cb_intr_establish, 274 pccbb_cb_intr_disestablish, 275 pccbb_make_tag, 276 pccbb_conf_read, 277 pccbb_conf_write, 278 }; 279 #endif 280 281 int 282 pcicbbmatch(parent, match, aux) 283 struct device *parent; 284 struct cfdata *match; 285 void *aux; 286 { 287 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 288 289 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 290 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 291 PCI_INTERFACE(pa->pa_class) == 0) { 292 return 1; 293 } 294 295 return 0; 296 } 297 298 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 299 | ((prod) << PCI_PRODUCT_SHIFT)) 300 301 const struct yenta_chipinfo { 302 pcireg_t yc_id; /* vendor tag | product tag */ 303 int yc_chiptype; 304 int yc_flags; 305 } yc_chipsets[] = { 306 /* Texas Instruments chips */ 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 332 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 334 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 336 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 338 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 339 340 /* Ricoh chips */ 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 344 PCCBB_PCMCIA_MEM_32}, 345 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 346 PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 348 PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 350 PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 352 PCCBB_PCMCIA_MEM_32}, 353 354 /* Toshiba products */ 355 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 356 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 358 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 360 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 361 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 362 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 363 364 /* Cirrus Logic products */ 365 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 366 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 367 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 368 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 369 370 /* sentinel, or Generic chip */ 371 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 372 }; 373 374 static int 375 cb_chipset(pci_id, flagp) 376 u_int32_t pci_id; 377 int *flagp; 378 { 379 const struct yenta_chipinfo *yc; 380 381 /* Loop over except the last default entry. */ 382 for (yc = yc_chipsets; yc < yc_chipsets + 383 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 384 if (pci_id == yc->yc_id) 385 break; 386 387 if (flagp != NULL) 388 *flagp = yc->yc_flags; 389 390 return (yc->yc_chiptype); 391 } 392 393 static void 394 pccbb_shutdown(void *arg) 395 { 396 struct pccbb_softc *sc = arg; 397 pcireg_t command; 398 399 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 400 401 /* 402 * turn off power 403 * 404 * XXX - do not turn off power if chipset is TI 113X because 405 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 406 */ 407 if (sc->sc_chipset != CB_TI113X) { 408 pccbb_power((cardbus_chipset_tag_t)sc, 409 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 410 } 411 412 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 413 0); 414 415 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 416 417 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 418 PCI_COMMAND_MASTER_ENABLE); 419 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 420 421 } 422 423 void 424 pccbbattach(parent, self, aux) 425 struct device *parent; 426 struct device *self; 427 void *aux; 428 { 429 struct pccbb_softc *sc = (void *)self; 430 struct pci_attach_args *pa = aux; 431 pci_chipset_tag_t pc = pa->pa_pc; 432 pcireg_t busreg, reg, sock_base; 433 bus_addr_t sockbase; 434 char devinfo[256]; 435 int flags; 436 int pwrmgt_offs; 437 438 #ifdef __HAVE_PCCBB_ATTACH_HOOK 439 pccbb_attach_hook(parent, self, pa); 440 #endif 441 442 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 443 444 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 445 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 446 #ifdef CBB_DEBUG 447 printf(" (chipflags %x)", flags); 448 #endif 449 printf("\n"); 450 451 TAILQ_INIT(&sc->sc_memwindow); 452 TAILQ_INIT(&sc->sc_iowindow); 453 454 #if rbus 455 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 456 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 457 458 #if 0 459 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 460 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 461 #endif 462 #endif /* rbus */ 463 464 sc->sc_flags &= ~CBB_MEMHMAPPED; 465 466 /* power management: set D0 state */ 467 sc->sc_pwrmgt_offs = 0; 468 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 469 &pwrmgt_offs, 0)) { 470 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 471 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 472 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 473 reg &= ~PCI_PMCSR_STATE_MASK; 474 reg |= PCI_PMCSR_STATE_D0; 475 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 476 pci_conf_write(pc, pa->pa_tag, 477 pwrmgt_offs + PCI_PMCSR, reg); 478 } 479 480 sc->sc_pwrmgt_offs = pwrmgt_offs; 481 } 482 483 /* 484 * MAP socket registers and ExCA registers on memory-space 485 * When no valid address is set on socket base registers (on pci 486 * config space), get it not polite way. 487 */ 488 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 489 490 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 491 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 492 /* The address must be valid. */ 493 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 494 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 495 printf("%s: can't map socket base address 0x%lx\n", 496 sc->sc_dev.dv_xname, (unsigned long)sock_base); 497 /* 498 * I think it's funny: socket base registers must be 499 * mapped on memory space, but ... 500 */ 501 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 502 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 503 NULL)) { 504 printf("%s: can't map socket base address" 505 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 506 (unsigned long)sockbase); 507 /* give up... allocate reg space via rbus. */ 508 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 509 } else 510 sc->sc_flags |= CBB_MEMHMAPPED; 511 } else { 512 DPRINTF(("%s: socket base address 0x%lx\n", 513 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 514 sc->sc_flags |= CBB_MEMHMAPPED; 515 } 516 } 517 518 sc->sc_mem_start = 0; /* XXX */ 519 sc->sc_mem_end = 0xffffffff; /* XXX */ 520 521 /* 522 * When interrupt isn't routed correctly, give up probing cbb and do 523 * not kill pcic-compatible port. 524 */ 525 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 526 printf("%s: NOT USED because of unconfigured interrupt\n", 527 sc->sc_dev.dv_xname); 528 return; 529 } 530 531 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 532 533 /* pccbb_machdep.c end */ 534 535 #if defined CBB_DEBUG 536 { 537 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 538 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 539 intrname[pa->pa_intrpin], pa->pa_intrline); 540 } 541 #endif 542 543 /* setup softc */ 544 sc->sc_pc = pc; 545 sc->sc_iot = pa->pa_iot; 546 sc->sc_memt = pa->pa_memt; 547 sc->sc_dmat = pa->pa_dmat; 548 sc->sc_tag = pa->pa_tag; 549 sc->sc_function = pa->pa_function; 550 sc->sc_sockbase = sock_base; 551 sc->sc_busnum = busreg; 552 553 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 554 555 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 556 557 shutdownhook_establish(pccbb_shutdown, sc); 558 559 /* Disable legacy register mapping. */ 560 switch (sc->sc_chipset) { 561 case CB_RX5C46X: /* fallthrough */ 562 #if 0 563 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 564 case CB_RX5C47X: 565 #endif 566 /* 567 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 568 * cannot be disabled by substituting 0 into PCI_LEGACY 569 * register. Ricoh CardBus bridges have special bits on Bridge 570 * control reg (addr 0x3e on PCI config space). 571 */ 572 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 573 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 574 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 575 break; 576 577 default: 578 /* XXX I don't know proper way to kill legacy I/O. */ 579 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 580 break; 581 } 582 583 config_defer(self, pccbb_pci_callback); 584 } 585 586 587 588 589 /* 590 * static void pccbb_pci_callback(struct device *self) 591 * 592 * The actual attach routine: get memory space for YENTA register 593 * space, setup YENTA register and route interrupt. 594 * 595 * This function should be deferred because this device may obtain 596 * memory space dynamically. This function must avoid obtaining 597 * memory area which has already kept for another device. 598 */ 599 static void 600 pccbb_pci_callback(self) 601 struct device *self; 602 { 603 struct pccbb_softc *sc = (void *)self; 604 pci_chipset_tag_t pc = sc->sc_pc; 605 pci_intr_handle_t ih; 606 const char *intrstr = NULL; 607 bus_addr_t sockbase; 608 struct cbslot_attach_args cba; 609 struct pcmciabus_attach_args paa; 610 struct cardslot_attach_args caa; 611 struct cardslot_softc *csc; 612 613 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 614 /* The socket registers aren't mapped correctly. */ 615 #if rbus 616 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 617 (sc->sc_chipset == CB_RX5C47X 618 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 619 0, &sockbase, &sc->sc_base_memh)) { 620 return; 621 } 622 sc->sc_base_memt = sc->sc_memt; 623 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 624 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 625 sc->sc_dev.dv_xname, (unsigned long)sockbase, 626 (unsigned long)pci_conf_read(pc, sc->sc_tag, 627 PCI_SOCKBASE))); 628 #else 629 sc->sc_base_memt = sc->sc_memt; 630 #if !defined CBB_PCI_BASE 631 #define CBB_PCI_BASE 0x20000000 632 #endif 633 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 634 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 635 /* cannot allocate memory space */ 636 return; 637 } 638 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 639 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 640 sc->sc_dev.dv_xname, (unsigned long)sock_base, 641 (unsigned long)pci_conf_read(pc, 642 sc->sc_tag, PCI_SOCKBASE))); 643 sc->sc_sockbase = sockbase; 644 #endif 645 sc->sc_flags |= CBB_MEMHMAPPED; 646 } 647 648 /* bus bridge initialization */ 649 pccbb_chipinit(sc); 650 651 /* clear data structure for child device interrupt handlers */ 652 LIST_INIT(&sc->sc_pil); 653 sc->sc_pil_intr_enable = 1; 654 655 /* Map and establish the interrupt. */ 656 if (pci_intr_map(&sc->sc_pa, &ih)) { 657 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 658 return; 659 } 660 intrstr = pci_intr_string(pc, ih); 661 662 /* 663 * XXX pccbbintr should be called under the priority lower 664 * than any other hard interrputs. 665 */ 666 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 667 668 if (sc->sc_ih == NULL) { 669 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 670 if (intrstr != NULL) { 671 printf(" at %s", intrstr); 672 } 673 printf("\n"); 674 return; 675 } 676 677 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 678 powerhook_establish(pccbb_powerhook, sc); 679 680 { 681 u_int32_t sockstat; 682 683 sockstat = bus_space_read_4(sc->sc_base_memt, 684 sc->sc_base_memh, CB_SOCKET_STAT); 685 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 686 sc->sc_flags |= CBB_CARDEXIST; 687 } 688 } 689 690 /* 691 * attach cardbus 692 */ 693 { 694 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 695 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 696 697 /* initialize cbslot_attach */ 698 cba.cba_busname = "cardbus"; 699 cba.cba_iot = sc->sc_iot; 700 cba.cba_memt = sc->sc_memt; 701 cba.cba_dmat = sc->sc_dmat; 702 cba.cba_bus = (busreg >> 8) & 0x0ff; 703 cba.cba_cc = (void *)sc; 704 cba.cba_cf = &pccbb_funcs; 705 cba.cba_intrline = sc->sc_pa.pa_intrline; 706 707 #if rbus 708 cba.cba_rbus_iot = sc->sc_rbus_iot; 709 cba.cba_rbus_memt = sc->sc_rbus_memt; 710 #endif 711 712 cba.cba_cacheline = PCI_CACHELINE(bhlc); 713 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 714 715 if (bootverbose) { 716 printf("%s: cacheline 0x%x lattimer 0x%x\n", 717 sc->sc_dev.dv_xname, cba.cba_cacheline, 718 cba.cba_lattimer); 719 printf("%s: bhlc 0x%x lscp 0x%x\n", 720 sc->sc_dev.dv_xname, bhlc, busreg); 721 } 722 #if defined SHOW_REGS 723 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 724 sc->sc_base_memh); 725 #endif 726 } 727 728 pccbb_pcmcia_attach_setup(sc, &paa); 729 caa.caa_cb_attach = NULL; 730 if (cba.cba_bus == 0) 731 printf("%s: secondary bus number uninitialized; try PCIBIOS_BUS_FIXUP\n", sc->sc_dev.dv_xname); 732 else 733 caa.caa_cb_attach = &cba; 734 caa.caa_16_attach = &paa; 735 caa.caa_ph = &sc->sc_pcmcia_h; 736 737 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 738 DPRINTF(("pccbbattach: found cardslot\n")); 739 sc->sc_csc = csc; 740 } 741 742 return; 743 } 744 745 746 747 748 749 /* 750 * static void pccbb_chipinit(struct pccbb_softc *sc) 751 * 752 * This function initialize YENTA chip registers listed below: 753 * 1) PCI command reg, 754 * 2) PCI and CardBus latency timer, 755 * 3) route PCI interrupt, 756 * 4) close all memory and io windows. 757 * 5) turn off bus power. 758 * 6) card detect interrupt on. 759 * 7) clear interrupt 760 */ 761 static void 762 pccbb_chipinit(sc) 763 struct pccbb_softc *sc; 764 { 765 pci_chipset_tag_t pc = sc->sc_pc; 766 pcitag_t tag = sc->sc_tag; 767 bus_space_tag_t bmt = sc->sc_base_memt; 768 bus_space_handle_t bmh = sc->sc_base_memh; 769 pcireg_t reg; 770 771 /* 772 * Set PCI command reg. 773 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 774 */ 775 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 776 /* I believe it is harmless. */ 777 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 778 PCI_COMMAND_MASTER_ENABLE); 779 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 780 781 /* 782 * Set CardBus latency timer. 783 */ 784 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 785 if (PCI_CB_LATENCY(reg) < 0x20) { 786 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 787 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 788 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 789 } 790 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 791 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 792 793 /* 794 * Set PCI latency timer. 795 */ 796 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 797 if (PCI_LATTIMER(reg) < 0x10) { 798 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 799 reg |= (0x10 << PCI_LATTIMER_SHIFT); 800 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 801 } 802 DPRINTF(("PCI latency timer 0x%x (%x)\n", 803 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 804 805 806 /* Route functional interrupts to PCI. */ 807 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 808 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 809 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 810 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 811 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 812 813 switch (sc->sc_chipset) { 814 case CB_TI113X: 815 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 816 /* This bit is shared, but may read as 0 on some chips, so set 817 it explicitly on both functions. */ 818 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 819 /* CSC intr enable */ 820 reg |= PCI113X_CBCTRL_PCI_CSC; 821 /* functional intr prohibit | prohibit ISA routing */ 822 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 823 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 824 break; 825 826 case CB_TI12XX: 827 /* 828 * Some TI 12xx (and [14][45]xx) based pci cards 829 * sometimes have issues with the MFUNC register not 830 * being initialized due to a bad EEPROM on board. 831 * Laptops that this matters on have this register 832 * properly initialized. 833 * 834 * The TI125X parts have a different register. 835 */ 836 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 837 if (reg == 0) { 838 reg &= ~PCI12XX_MFUNC_PIN0; 839 reg |= PCI12XX_MFUNC_PIN0_INTA; 840 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 841 PCI12XX_SYSCTRL_INTRTIE) == 0) { 842 reg &= ~PCI12XX_MFUNC_PIN1; 843 reg |= PCI12XX_MFUNC_PIN1_INTB; 844 } 845 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 846 } 847 /* fallthrough */ 848 849 case CB_TI125X: 850 /* 851 * Disable zoom video. Some machines initialize this 852 * improperly and experience has shown that this helps 853 * prevent strange behavior. 854 */ 855 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 856 857 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 858 reg |= PCI12XX_SYSCTRL_VCCPROT; 859 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 860 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 861 reg |= PCI12XX_CBCTRL_CSC; 862 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 863 break; 864 865 case CB_TOPIC95B: 866 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 867 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 868 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 869 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 870 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 871 sc->sc_dev.dv_xname, reg)); 872 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 873 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 874 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 875 DPRINTF(("0x%x\n", reg)); 876 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 877 break; 878 879 case CB_TOPIC97: 880 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 881 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 882 sc->sc_dev.dv_xname, reg)); 883 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 884 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 885 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 886 reg |= TOPIC97_SLOT_CTRL_PCIINT; 887 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 888 DPRINTF(("0x%x\n", reg)); 889 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 890 /* make sure to assert LV card support bits */ 891 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 892 0x800 + 0x3e, 893 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 894 0x800 + 0x3e) | 0x03); 895 break; 896 } 897 898 /* Close all memory and I/O windows. */ 899 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 900 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 901 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 902 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 903 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 904 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 905 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 906 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 907 908 /* reset 16-bit pcmcia bus */ 909 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 910 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 911 912 /* turn off power */ 913 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 914 915 /* CSC Interrupt: Card detect interrupt on */ 916 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 917 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; /* Card detect intr is turned on. */ 918 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 919 /* reset interrupt */ 920 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 921 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 922 } 923 924 925 926 927 /* 928 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 929 * struct pcmciabus_attach_args *paa) 930 * 931 * This function attaches 16-bit PCcard bus. 932 */ 933 STATIC void 934 pccbb_pcmcia_attach_setup(sc, paa) 935 struct pccbb_softc *sc; 936 struct pcmciabus_attach_args *paa; 937 { 938 struct pcic_handle *ph = &sc->sc_pcmcia_h; 939 #if rbus 940 rbus_tag_t rb; 941 #endif 942 943 /* initialize pcmcia part in pccbb_softc */ 944 ph->ph_parent = (struct device *)sc; 945 ph->sock = sc->sc_function; 946 ph->flags = 0; 947 ph->shutdown = 0; 948 ph->ih_irq = sc->sc_pa.pa_intrline; 949 ph->ph_bus_t = sc->sc_base_memt; 950 ph->ph_bus_h = sc->sc_base_memh; 951 ph->ph_read = pccbb_pcmcia_read; 952 ph->ph_write = pccbb_pcmcia_write; 953 sc->sc_pct = &pccbb_pcmcia_funcs; 954 955 /* 956 * We need to do a few things here: 957 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 958 * setting the IRQ numbers to 0. 959 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 960 * routing of CSC interrupts (e.g. card removal) to PCI while in 961 * PCMCIA mode. We just leave this set all the time. 962 * 3) Enable card insertion/removal interrupts in case the chip also 963 * needs that while in PCMCIA mode. 964 * 4) Clear any pending CSC interrupt. 965 */ 966 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 967 if (sc->sc_chipset == CB_TI113X) { 968 Pcic_write(ph, PCIC_CSC_INTR, 0); 969 } else { 970 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 971 Pcic_read(ph, PCIC_CSC); 972 } 973 974 /* initialize pcmcia bus attachment */ 975 paa->paa_busname = "pcmcia"; 976 paa->pct = sc->sc_pct; 977 paa->pch = ph; 978 paa->iobase = 0; /* I don't use them */ 979 paa->iosize = 0; 980 #if rbus 981 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 982 paa->iobase = rb->rb_start + rb->rb_offset; 983 paa->iosize = rb->rb_end - rb->rb_start; 984 #endif 985 986 return; 987 } 988 989 #if 0 990 STATIC void 991 pccbb_pcmcia_attach_card(ph) 992 struct pcic_handle *ph; 993 { 994 if (ph->flags & PCIC_FLAG_CARDP) { 995 panic("pccbb_pcmcia_attach_card: already attached"); 996 } 997 998 /* call the MI attach function */ 999 pcmcia_card_attach(ph->pcmcia); 1000 1001 ph->flags |= PCIC_FLAG_CARDP; 1002 } 1003 1004 STATIC void 1005 pccbb_pcmcia_detach_card(ph, flags) 1006 struct pcic_handle *ph; 1007 int flags; 1008 { 1009 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1010 panic("pccbb_pcmcia_detach_card: already detached"); 1011 } 1012 1013 ph->flags &= ~PCIC_FLAG_CARDP; 1014 1015 /* call the MI detach function */ 1016 pcmcia_card_detach(ph->pcmcia, flags); 1017 } 1018 #endif 1019 1020 /* 1021 * int pccbbintr(arg) 1022 * void *arg; 1023 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1024 * itself. 1025 */ 1026 int 1027 pccbbintr(arg) 1028 void *arg; 1029 { 1030 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1031 u_int32_t sockevent, sockstate; 1032 bus_space_tag_t memt = sc->sc_base_memt; 1033 bus_space_handle_t memh = sc->sc_base_memh; 1034 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1035 1036 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1037 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1038 Pcic_read(ph, PCIC_CSC); 1039 1040 if (sockevent == 0) { 1041 /* This intr is not for me: it may be for my child devices. */ 1042 if (sc->sc_pil_intr_enable) { 1043 return pccbbintr_function(sc); 1044 } else { 1045 return 0; 1046 } 1047 } 1048 1049 if (sockevent & CB_SOCKET_EVENT_CD) { 1050 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1051 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1052 /* A card should be removed. */ 1053 if (sc->sc_flags & CBB_CARDEXIST) { 1054 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1055 sockevent)); 1056 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1057 sc->sc_flags &= ~CBB_CARDEXIST; 1058 if (sc->sc_csc->sc_status & 1059 CARDSLOT_STATUS_CARD_16) { 1060 #if 0 1061 struct pcic_handle *ph = 1062 &sc->sc_pcmcia_h; 1063 1064 pcmcia_card_deactivate(ph->pcmcia); 1065 pccbb_pcmcia_socket_disable(ph); 1066 pccbb_pcmcia_detach_card(ph, 1067 DETACH_FORCE); 1068 #endif 1069 cardslot_event_throw(sc->sc_csc, 1070 CARDSLOT_EVENT_REMOVAL_16); 1071 } else if (sc->sc_csc->sc_status & 1072 CARDSLOT_STATUS_CARD_CB) { 1073 /* Cardbus intr removed */ 1074 cardslot_event_throw(sc->sc_csc, 1075 CARDSLOT_EVENT_REMOVAL_CB); 1076 } 1077 } else if (sc->sc_flags & CBB_INSERTING) { 1078 sc->sc_flags &= ~CBB_INSERTING; 1079 callout_stop(&sc->sc_insert_ch); 1080 } 1081 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1082 /* 1083 * The pccbbintr may called from powerdown hook when 1084 * the system resumed, to detect the card 1085 * insertion/removal during suspension. 1086 */ 1087 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1088 if (sc->sc_flags & CBB_INSERTING) { 1089 callout_stop(&sc->sc_insert_ch); 1090 } 1091 callout_reset(&sc->sc_insert_ch, hz / 5, 1092 pci113x_insert, sc); 1093 sc->sc_flags |= CBB_INSERTING; 1094 } 1095 } 1096 1097 if (sockevent & CB_SOCKET_EVENT_POWER) { 1098 sc->sc_pwrcycle++; 1099 wakeup(&sc->sc_pwrcycle); 1100 } 1101 1102 return (1); 1103 } 1104 1105 /* 1106 * static int pccbbintr_function(struct pccbb_softc *sc) 1107 * 1108 * This function calls each interrupt handler registered at the 1109 * bridge. The interrupt handlers are called in registered order. 1110 */ 1111 static int 1112 pccbbintr_function(sc) 1113 struct pccbb_softc *sc; 1114 { 1115 int retval = 0, val; 1116 struct pccbb_intrhand_list *pil; 1117 int s, splchanged; 1118 1119 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1120 pil = LIST_NEXT(pil, pil_next)) { 1121 /* 1122 * XXX priority change. gross. I use if-else 1123 * sentense instead of switch-case sentense because of 1124 * avoiding duplicate case value error. More than one 1125 * IPL_XXX use same value. It depends on 1126 * implimentation. 1127 */ 1128 splchanged = 1; 1129 if (pil->pil_level == IPL_SERIAL) { 1130 s = splserial(); 1131 } else if (pil->pil_level == IPL_HIGH) { 1132 s = splhigh(); 1133 } else if (pil->pil_level == IPL_CLOCK) { 1134 s = splclock(); 1135 } else if (pil->pil_level == IPL_AUDIO) { 1136 s = splaudio(); 1137 } else if (pil->pil_level == IPL_VM) { 1138 s = splvm(); 1139 } else if (pil->pil_level == IPL_TTY) { 1140 s = spltty(); 1141 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1142 s = splsoftserial(); 1143 } else if (pil->pil_level == IPL_NET) { 1144 s = splnet(); 1145 } else { 1146 s = 0; /* XXX: gcc */ 1147 splchanged = 0; 1148 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1149 } 1150 1151 val = (*pil->pil_func)(pil->pil_arg); 1152 1153 if (splchanged != 0) { 1154 splx(s); 1155 } 1156 1157 retval = retval == 1 ? 1 : 1158 retval == 0 ? val : val != 0 ? val : retval; 1159 } 1160 1161 return retval; 1162 } 1163 1164 static void 1165 pci113x_insert(arg) 1166 void *arg; 1167 { 1168 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1169 u_int32_t sockevent, sockstate; 1170 1171 if (!(sc->sc_flags & CBB_INSERTING)) { 1172 /* We add a card only under inserting state. */ 1173 return; 1174 } 1175 sc->sc_flags &= ~CBB_INSERTING; 1176 1177 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1178 CB_SOCKET_EVENT); 1179 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1180 CB_SOCKET_STAT); 1181 1182 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1183 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1184 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1185 sc->sc_flags |= CBB_CARDEXIST; 1186 /* call pccard interrupt handler here */ 1187 if (sockstate & CB_SOCKET_STAT_16BIT) { 1188 /* 16-bit card found */ 1189 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1190 cardslot_event_throw(sc->sc_csc, 1191 CARDSLOT_EVENT_INSERTION_16); 1192 } else if (sockstate & CB_SOCKET_STAT_CB) { 1193 /* cardbus card found */ 1194 /* cardbus_attach_card(sc->sc_csc); */ 1195 cardslot_event_throw(sc->sc_csc, 1196 CARDSLOT_EVENT_INSERTION_CB); 1197 } else { 1198 /* who are you? */ 1199 } 1200 } else { 1201 callout_reset(&sc->sc_insert_ch, hz / 10, 1202 pci113x_insert, sc); 1203 } 1204 } 1205 1206 #define PCCBB_PCMCIA_OFFSET 0x800 1207 static u_int8_t 1208 pccbb_pcmcia_read(ph, reg) 1209 struct pcic_handle *ph; 1210 int reg; 1211 { 1212 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1213 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1214 1215 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1216 PCCBB_PCMCIA_OFFSET + reg); 1217 } 1218 1219 static void 1220 pccbb_pcmcia_write(ph, reg, val) 1221 struct pcic_handle *ph; 1222 int reg; 1223 u_int8_t val; 1224 { 1225 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1226 val); 1227 1228 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1229 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1230 } 1231 1232 /* 1233 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1234 */ 1235 STATIC int 1236 pccbb_ctrl(ct, command) 1237 cardbus_chipset_tag_t ct; 1238 int command; 1239 { 1240 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1241 1242 switch (command) { 1243 case CARDBUS_CD: 1244 if (2 == pccbb_detect_card(sc)) { 1245 int retval = 0; 1246 int status = cb_detect_voltage(sc); 1247 if (PCCARD_VCC_5V & status) { 1248 retval |= CARDBUS_5V_CARD; 1249 } 1250 if (PCCARD_VCC_3V & status) { 1251 retval |= CARDBUS_3V_CARD; 1252 } 1253 if (PCCARD_VCC_XV & status) { 1254 retval |= CARDBUS_XV_CARD; 1255 } 1256 if (PCCARD_VCC_YV & status) { 1257 retval |= CARDBUS_YV_CARD; 1258 } 1259 return retval; 1260 } else { 1261 return 0; 1262 } 1263 case CARDBUS_RESET: 1264 return cb_reset(sc); 1265 case CARDBUS_IO_ENABLE: /* fallthrough */ 1266 case CARDBUS_IO_DISABLE: /* fallthrough */ 1267 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1268 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1269 case CARDBUS_BM_ENABLE: /* fallthrough */ 1270 case CARDBUS_BM_DISABLE: /* fallthrough */ 1271 /* XXX: I think we don't need to call this function below. */ 1272 return pccbb_cardenable(sc, command); 1273 } 1274 1275 return 0; 1276 } 1277 1278 /* 1279 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1280 * This function returns true when it succeeds and returns false when 1281 * it fails. 1282 */ 1283 STATIC int 1284 pccbb_power(ct, command) 1285 cardbus_chipset_tag_t ct; 1286 int command; 1287 { 1288 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1289 u_int32_t status, sock_ctrl, reg_ctrl; 1290 bus_space_tag_t memt = sc->sc_base_memt; 1291 bus_space_handle_t memh = sc->sc_base_memh; 1292 int on = 0, pwrcycle; 1293 1294 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1295 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1296 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1297 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1298 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1299 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1300 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1301 "UNKNOWN", 1302 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1303 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1304 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1305 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1306 "UNKNOWN", command)); 1307 1308 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1309 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1310 1311 switch (command & CARDBUS_VCCMASK) { 1312 case CARDBUS_VCC_UC: 1313 break; 1314 case CARDBUS_VCC_5V: 1315 on++; 1316 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1317 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1318 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1319 } else { 1320 printf("%s: BAD voltage request: no 5 V card\n", 1321 sc->sc_dev.dv_xname); 1322 return 0; 1323 } 1324 break; 1325 case CARDBUS_VCC_3V: 1326 on++; 1327 if (CB_SOCKET_STAT_3VCARD & status) { 1328 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1329 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1330 } else { 1331 printf("%s: BAD voltage request: no 3.3 V card\n", 1332 sc->sc_dev.dv_xname); 1333 return 0; 1334 } 1335 break; 1336 case CARDBUS_VCC_0V: 1337 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1338 break; 1339 default: 1340 return 0; /* power NEVER changed */ 1341 } 1342 1343 switch (command & CARDBUS_VPPMASK) { 1344 case CARDBUS_VPP_UC: 1345 break; 1346 case CARDBUS_VPP_0V: 1347 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1348 break; 1349 case CARDBUS_VPP_VCC: 1350 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1351 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1352 break; 1353 case CARDBUS_VPP_12V: 1354 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1355 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1356 break; 1357 } 1358 1359 pwrcycle = sc->sc_pwrcycle; 1360 1361 #if 0 1362 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1363 #endif 1364 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1365 1366 if (on) { 1367 int s; 1368 struct timeval before, after, diff; 1369 1370 microtime(&before); 1371 s = splbio(); 1372 while (pwrcycle == sc->sc_pwrcycle) 1373 tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 0); 1374 splx(s); 1375 microtime(&after); 1376 timersub(&after, &before, &diff); 1377 printf("%s: wait took %ld.%06lds\n", sc->sc_dev.dv_xname, 1378 diff.tv_sec, diff.tv_usec); 1379 } 1380 1381 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1382 1383 if (on) { 1384 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1385 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1386 } 1387 1388 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1389 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1390 sc->sc_dev.dv_xname, sock_ctrl, status); 1391 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1392 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1393 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1394 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1395 status &= ~CB_SOCKET_STAT_BADVCC; 1396 bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1397 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1398 CB_SOCKET_STAT)); 1399 return 0; 1400 } 1401 1402 if (sc->sc_chipset == CB_TOPIC97) { 1403 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1404 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1405 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1406 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1407 else 1408 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1409 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1410 } 1411 1412 return 1; /* power changed correctly */ 1413 } 1414 1415 #if defined CB_PCMCIA_POLL 1416 struct cb_poll_str { 1417 void *arg; 1418 int (*func) __P((void *)); 1419 int level; 1420 pccard_chipset_tag_t ct; 1421 int count; 1422 struct callout poll_ch; 1423 }; 1424 1425 static struct cb_poll_str cb_poll[10]; 1426 static int cb_poll_n = 0; 1427 1428 static void cb_pcmcia_poll __P((void *arg)); 1429 1430 static void 1431 cb_pcmcia_poll(arg) 1432 void *arg; 1433 { 1434 struct cb_poll_str *poll = arg; 1435 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1436 struct pccbb_softc *sc = psc->cpc_parent; 1437 int s; 1438 u_int32_t spsr; /* socket present-state reg */ 1439 1440 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1441 switch (poll->level) { 1442 case IPL_NET: 1443 s = splnet(); 1444 break; 1445 case IPL_BIO: 1446 s = splbio(); 1447 break; 1448 case IPL_TTY: /* fallthrough */ 1449 default: 1450 s = spltty(); 1451 break; 1452 } 1453 1454 spsr = 1455 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1456 CB_SOCKET_STAT); 1457 1458 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1459 if (!(spsr & 0x40)) { /* CINT low */ 1460 #else 1461 if (1) { 1462 #endif 1463 if ((*poll->func) (poll->arg) == 1) { 1464 ++poll->count; 1465 printf("intr: reported from poller, 0x%x\n", spsr); 1466 #if defined LEVEL2 1467 } else { 1468 printf("intr: miss! 0x%x\n", spsr); 1469 #endif 1470 } 1471 } 1472 splx(s); 1473 } 1474 #endif /* defined CB_PCMCIA_POLL */ 1475 1476 /* 1477 * static int pccbb_detect_card(struct pccbb_softc *sc) 1478 * return value: 0 if no card exists. 1479 * 1 if 16-bit card exists. 1480 * 2 if cardbus card exists. 1481 */ 1482 static int 1483 pccbb_detect_card(sc) 1484 struct pccbb_softc *sc; 1485 { 1486 bus_space_handle_t base_memh = sc->sc_base_memh; 1487 bus_space_tag_t base_memt = sc->sc_base_memt; 1488 u_int32_t sockstat = 1489 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1490 int retval = 0; 1491 1492 /* CD1 and CD2 asserted */ 1493 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1494 /* card must be present */ 1495 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1496 /* NOTACARD DEASSERTED */ 1497 if (CB_SOCKET_STAT_CB & sockstat) { 1498 /* CardBus mode */ 1499 retval = 2; 1500 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1501 /* 16-bit mode */ 1502 retval = 1; 1503 } 1504 } 1505 } 1506 return retval; 1507 } 1508 1509 /* 1510 * STATIC int cb_reset(struct pccbb_softc *sc) 1511 * This function resets CardBus card. 1512 */ 1513 STATIC int 1514 cb_reset(sc) 1515 struct pccbb_softc *sc; 1516 { 1517 /* 1518 * Reset Assert at least 20 ms 1519 * Some machines request longer duration. 1520 */ 1521 int reset_duration = 1522 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1523 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1524 1525 /* Reset bit Assert (bit 6 at 0x3E) */ 1526 bcr |= CB_BCR_RESET_ENABLE; 1527 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1528 DELAY_MS(reset_duration, sc); 1529 1530 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1531 /* Reset bit Deassert (bit 6 at 0x3E) */ 1532 bcr &= ~CB_BCR_RESET_ENABLE; 1533 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1534 DELAY_MS(reset_duration, sc); 1535 } 1536 /* No card found on the slot. Keep Reset. */ 1537 return 1; 1538 } 1539 1540 /* 1541 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1542 * This function detect card Voltage. 1543 */ 1544 STATIC int 1545 cb_detect_voltage(sc) 1546 struct pccbb_softc *sc; 1547 { 1548 u_int32_t psr; /* socket present-state reg */ 1549 bus_space_tag_t iot = sc->sc_base_memt; 1550 bus_space_handle_t ioh = sc->sc_base_memh; 1551 int vol = PCCARD_VCC_UKN; /* set 0 */ 1552 1553 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1554 1555 if (0x400u & psr) { 1556 vol |= PCCARD_VCC_5V; 1557 } 1558 if (0x800u & psr) { 1559 vol |= PCCARD_VCC_3V; 1560 } 1561 1562 return vol; 1563 } 1564 1565 STATIC int 1566 cbbprint(aux, pcic) 1567 void *aux; 1568 const char *pcic; 1569 { 1570 /* 1571 struct cbslot_attach_args *cba = aux; 1572 1573 if (cba->cba_slot >= 0) { 1574 aprint_normal(" slot %d", cba->cba_slot); 1575 } 1576 */ 1577 return UNCONF; 1578 } 1579 1580 /* 1581 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1582 * This function enables and disables the card 1583 */ 1584 STATIC int 1585 pccbb_cardenable(sc, function) 1586 struct pccbb_softc *sc; 1587 int function; 1588 { 1589 u_int32_t command = 1590 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1591 1592 DPRINTF(("pccbb_cardenable:")); 1593 switch (function) { 1594 case CARDBUS_IO_ENABLE: 1595 command |= PCI_COMMAND_IO_ENABLE; 1596 break; 1597 case CARDBUS_IO_DISABLE: 1598 command &= ~PCI_COMMAND_IO_ENABLE; 1599 break; 1600 case CARDBUS_MEM_ENABLE: 1601 command |= PCI_COMMAND_MEM_ENABLE; 1602 break; 1603 case CARDBUS_MEM_DISABLE: 1604 command &= ~PCI_COMMAND_MEM_ENABLE; 1605 break; 1606 case CARDBUS_BM_ENABLE: 1607 command |= PCI_COMMAND_MASTER_ENABLE; 1608 break; 1609 case CARDBUS_BM_DISABLE: 1610 command &= ~PCI_COMMAND_MASTER_ENABLE; 1611 break; 1612 default: 1613 return 0; 1614 } 1615 1616 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1617 DPRINTF((" command reg 0x%x\n", command)); 1618 return 1; 1619 } 1620 1621 #if !rbus 1622 /* 1623 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1624 */ 1625 static int 1626 pccbb_io_open(ct, win, start, end) 1627 cardbus_chipset_tag_t ct; 1628 int win; 1629 u_int32_t start, end; 1630 { 1631 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1632 int basereg; 1633 int limitreg; 1634 1635 if ((win < 0) || (win > 2)) { 1636 #if defined DIAGNOSTIC 1637 printf("cardbus_io_open: window out of range %d\n", win); 1638 #endif 1639 return 0; 1640 } 1641 1642 basereg = win * 8 + 0x2c; 1643 limitreg = win * 8 + 0x30; 1644 1645 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1646 start, basereg, end, limitreg)); 1647 1648 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1649 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1650 return 1; 1651 } 1652 1653 /* 1654 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1655 */ 1656 static int 1657 pccbb_io_close(ct, win) 1658 cardbus_chipset_tag_t ct; 1659 int win; 1660 { 1661 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1662 int basereg; 1663 int limitreg; 1664 1665 if ((win < 0) || (win > 2)) { 1666 #if defined DIAGNOSTIC 1667 printf("cardbus_io_close: window out of range %d\n", win); 1668 #endif 1669 return 0; 1670 } 1671 1672 basereg = win * 8 + 0x2c; 1673 limitreg = win * 8 + 0x30; 1674 1675 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1676 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1677 return 1; 1678 } 1679 1680 /* 1681 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1682 */ 1683 static int 1684 pccbb_mem_open(ct, win, start, end) 1685 cardbus_chipset_tag_t ct; 1686 int win; 1687 u_int32_t start, end; 1688 { 1689 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1690 int basereg; 1691 int limitreg; 1692 1693 if ((win < 0) || (win > 2)) { 1694 #if defined DIAGNOSTIC 1695 printf("cardbus_mem_open: window out of range %d\n", win); 1696 #endif 1697 return 0; 1698 } 1699 1700 basereg = win * 8 + 0x1c; 1701 limitreg = win * 8 + 0x20; 1702 1703 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1704 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1705 return 1; 1706 } 1707 1708 /* 1709 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1710 */ 1711 static int 1712 pccbb_mem_close(ct, win) 1713 cardbus_chipset_tag_t ct; 1714 int win; 1715 { 1716 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1717 int basereg; 1718 int limitreg; 1719 1720 if ((win < 0) || (win > 2)) { 1721 #if defined DIAGNOSTIC 1722 printf("cardbus_mem_close: window out of range %d\n", win); 1723 #endif 1724 return 0; 1725 } 1726 1727 basereg = win * 8 + 0x1c; 1728 limitreg = win * 8 + 0x20; 1729 1730 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1731 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1732 return 1; 1733 } 1734 #endif 1735 1736 /* 1737 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1738 * int irq, 1739 * int level, 1740 * int (* func) __P((void *)), 1741 * void *arg) 1742 * 1743 * This function registers an interrupt handler at the bridge, in 1744 * order not to call the interrupt handlers of child devices when 1745 * a card-deletion interrupt occurs. 1746 * 1747 * The arguments irq and level are not used. 1748 */ 1749 static void * 1750 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1751 cardbus_chipset_tag_t ct; 1752 int irq, level; 1753 int (*func) __P((void *)); 1754 void *arg; 1755 { 1756 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1757 1758 return pccbb_intr_establish(sc, irq, level, func, arg); 1759 } 1760 1761 1762 /* 1763 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1764 * void *ih) 1765 * 1766 * This function removes an interrupt handler pointed by ih. 1767 */ 1768 static void 1769 pccbb_cb_intr_disestablish(ct, ih) 1770 cardbus_chipset_tag_t ct; 1771 void *ih; 1772 { 1773 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1774 1775 pccbb_intr_disestablish(sc, ih); 1776 } 1777 1778 1779 void 1780 pccbb_intr_route(sc) 1781 struct pccbb_softc *sc; 1782 { 1783 pcireg_t reg; 1784 1785 /* initialize bridge intr routing */ 1786 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1787 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1788 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1789 1790 switch (sc->sc_chipset) { 1791 case CB_TI113X: 1792 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1793 /* functional intr enabled */ 1794 reg |= PCI113X_CBCTRL_PCI_INTR; 1795 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1796 break; 1797 default: 1798 break; 1799 } 1800 } 1801 1802 /* 1803 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1804 * int irq, 1805 * int level, 1806 * int (* func) __P((void *)), 1807 * void *arg) 1808 * 1809 * This function registers an interrupt handler at the bridge, in 1810 * order not to call the interrupt handlers of child devices when 1811 * a card-deletion interrupt occurs. 1812 * 1813 * The arguments irq is not used because pccbb selects intr vector. 1814 */ 1815 static void * 1816 pccbb_intr_establish(sc, irq, level, func, arg) 1817 struct pccbb_softc *sc; 1818 int irq, level; 1819 int (*func) __P((void *)); 1820 void *arg; 1821 { 1822 struct pccbb_intrhand_list *pil, *newpil; 1823 1824 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1825 1826 if (LIST_EMPTY(&sc->sc_pil)) { 1827 pccbb_intr_route(sc); 1828 } 1829 1830 /* 1831 * Allocate a room for interrupt handler structure. 1832 */ 1833 if (NULL == (newpil = 1834 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1835 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1836 return NULL; 1837 } 1838 1839 newpil->pil_func = func; 1840 newpil->pil_arg = arg; 1841 newpil->pil_level = level; 1842 1843 if (LIST_EMPTY(&sc->sc_pil)) { 1844 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1845 } else { 1846 for (pil = LIST_FIRST(&sc->sc_pil); 1847 LIST_NEXT(pil, pil_next) != NULL; 1848 pil = LIST_NEXT(pil, pil_next)); 1849 LIST_INSERT_AFTER(pil, newpil, pil_next); 1850 } 1851 1852 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1853 LIST_FIRST(&sc->sc_pil))); 1854 1855 return newpil; 1856 } 1857 1858 /* 1859 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1860 * void *ih) 1861 * 1862 * This function removes an interrupt handler pointed by ih. ih 1863 * should be the value returned by cardbus_intr_establish() or 1864 * NULL. 1865 * 1866 * When ih is NULL, this function will do nothing. 1867 */ 1868 static void 1869 pccbb_intr_disestablish(sc, ih) 1870 struct pccbb_softc *sc; 1871 void *ih; 1872 { 1873 struct pccbb_intrhand_list *pil; 1874 pcireg_t reg; 1875 1876 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1877 LIST_FIRST(&sc->sc_pil))); 1878 1879 if (ih == NULL) { 1880 /* intr handler is not set */ 1881 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1882 return; 1883 } 1884 1885 #ifdef DIAGNOSTIC 1886 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1887 pil = LIST_NEXT(pil, pil_next)) { 1888 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1889 if (pil == ih) { 1890 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1891 break; 1892 } 1893 } 1894 if (pil == NULL) { 1895 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1896 sc->sc_dev.dv_xname, ih); 1897 } 1898 #endif 1899 1900 pil = (struct pccbb_intrhand_list *)ih; 1901 LIST_REMOVE(pil, pil_next); 1902 free(pil, M_DEVBUF); 1903 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1904 1905 if (LIST_EMPTY(&sc->sc_pil)) { 1906 /* No interrupt handlers */ 1907 1908 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1909 1910 /* stop routing PCI intr */ 1911 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1912 reg |= CB_BCR_INTR_IREQ_ENABLE; 1913 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1914 1915 switch (sc->sc_chipset) { 1916 case CB_TI113X: 1917 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1918 /* functional intr disabled */ 1919 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1920 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1921 break; 1922 default: 1923 break; 1924 } 1925 } 1926 } 1927 1928 #if defined SHOW_REGS 1929 static void 1930 cb_show_regs(pc, tag, memt, memh) 1931 pci_chipset_tag_t pc; 1932 pcitag_t tag; 1933 bus_space_tag_t memt; 1934 bus_space_handle_t memh; 1935 { 1936 int i; 1937 printf("PCI config regs:"); 1938 for (i = 0; i < 0x50; i += 4) { 1939 if (i % 16 == 0) { 1940 printf("\n 0x%02x:", i); 1941 } 1942 printf(" %08x", pci_conf_read(pc, tag, i)); 1943 } 1944 for (i = 0x80; i < 0xb0; i += 4) { 1945 if (i % 16 == 0) { 1946 printf("\n 0x%02x:", i); 1947 } 1948 printf(" %08x", pci_conf_read(pc, tag, i)); 1949 } 1950 1951 if (memh == 0) { 1952 printf("\n"); 1953 return; 1954 } 1955 1956 printf("\nsocket regs:"); 1957 for (i = 0; i <= 0x10; i += 0x04) { 1958 printf(" %08x", bus_space_read_4(memt, memh, i)); 1959 } 1960 printf("\nExCA regs:"); 1961 for (i = 0; i < 0x08; ++i) { 1962 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1963 } 1964 printf("\n"); 1965 return; 1966 } 1967 #endif 1968 1969 /* 1970 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1971 * int busno, int devno, int function) 1972 * This is the function to make a tag to access config space of 1973 * a CardBus Card. It works same as pci_conf_read. 1974 */ 1975 static cardbustag_t 1976 pccbb_make_tag(cc, busno, devno, function) 1977 cardbus_chipset_tag_t cc; 1978 int busno, devno, function; 1979 { 1980 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1981 1982 return pci_make_tag(sc->sc_pc, busno, devno, function); 1983 } 1984 1985 static void 1986 pccbb_free_tag(cc, tag) 1987 cardbus_chipset_tag_t cc; 1988 cardbustag_t tag; 1989 { 1990 } 1991 1992 /* 1993 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1994 * cardbustag_t tag, int offset) 1995 * This is the function to read the config space of a CardBus Card. 1996 * It works same as pci_conf_read. 1997 */ 1998 static cardbusreg_t 1999 pccbb_conf_read(cc, tag, offset) 2000 cardbus_chipset_tag_t cc; 2001 cardbustag_t tag; 2002 int offset; /* register offset */ 2003 { 2004 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2005 2006 return pci_conf_read(sc->sc_pc, tag, offset); 2007 } 2008 2009 /* 2010 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 2011 * int offs, cardbusreg_t val) 2012 * This is the function to write the config space of a CardBus Card. 2013 * It works same as pci_conf_write. 2014 */ 2015 static void 2016 pccbb_conf_write(cc, tag, reg, val) 2017 cardbus_chipset_tag_t cc; 2018 cardbustag_t tag; 2019 int reg; /* register offset */ 2020 cardbusreg_t val; 2021 { 2022 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2023 2024 pci_conf_write(sc->sc_pc, tag, reg, val); 2025 } 2026 2027 #if 0 2028 STATIC int 2029 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2030 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2031 int speed, int flags, 2032 bus_space_handle_t * iohp) 2033 #endif 2034 /* 2035 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2036 * bus_addr_t start, bus_size_t size, 2037 * bus_size_t align, 2038 * struct pcmcia_io_handle *pcihp 2039 * 2040 * This function only allocates I/O region for pccard. This function 2041 * never maps the allocated region to pccard I/O area. 2042 * 2043 * XXX: The interface of this function is not very good, I believe. 2044 */ 2045 STATIC int 2046 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2047 pcmcia_chipset_handle_t pch; 2048 bus_addr_t start; /* start address */ 2049 bus_size_t size; 2050 bus_size_t align; 2051 struct pcmcia_io_handle *pcihp; 2052 { 2053 struct pcic_handle *ph = (struct pcic_handle *)pch; 2054 bus_addr_t ioaddr; 2055 int flags = 0; 2056 bus_space_tag_t iot; 2057 bus_space_handle_t ioh; 2058 bus_addr_t mask; 2059 #if rbus 2060 rbus_tag_t rb; 2061 #endif 2062 if (align == 0) { 2063 align = size; /* XXX: funny??? */ 2064 } 2065 2066 if (start != 0) { 2067 /* XXX: assume all card decode lower 10 bits by its hardware */ 2068 mask = 0x3ff; 2069 /* enforce to use only masked address */ 2070 start &= mask; 2071 } else { 2072 /* 2073 * calculate mask: 2074 * 1. get the most significant bit of size (call it msb). 2075 * 2. compare msb with the value of size. 2076 * 3. if size is larger, shift msb left once. 2077 * 4. obtain mask value to decrement msb. 2078 */ 2079 bus_size_t size_tmp = size; 2080 int shifts = 0; 2081 2082 mask = 1; 2083 while (size_tmp) { 2084 ++shifts; 2085 size_tmp >>= 1; 2086 } 2087 mask = (1 << shifts); 2088 if (mask < size) { 2089 mask <<= 1; 2090 } 2091 --mask; 2092 } 2093 2094 /* 2095 * Allocate some arbitrary I/O space. 2096 */ 2097 2098 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2099 2100 #if rbus 2101 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2102 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2103 return 1; 2104 } 2105 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2106 (u_long) ioaddr, (u_long) size)); 2107 #else 2108 if (start) { 2109 ioaddr = start; 2110 if (bus_space_map(iot, start, size, 0, &ioh)) { 2111 return 1; 2112 } 2113 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2114 (u_long) ioaddr, (u_long) size)); 2115 } else { 2116 flags |= PCMCIA_IO_ALLOCATED; 2117 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2118 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2119 size, align, 0, 0, &ioaddr, &ioh)) { 2120 /* No room be able to be get. */ 2121 return 1; 2122 } 2123 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2124 (u_long) ioaddr, (u_long) size)); 2125 } 2126 #endif 2127 2128 pcihp->iot = iot; 2129 pcihp->ioh = ioh; 2130 pcihp->addr = ioaddr; 2131 pcihp->size = size; 2132 pcihp->flags = flags; 2133 2134 return 0; 2135 } 2136 2137 /* 2138 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2139 * struct pcmcia_io_handle *pcihp) 2140 * 2141 * This function only frees I/O region for pccard. 2142 * 2143 * XXX: The interface of this function is not very good, I believe. 2144 */ 2145 void 2146 pccbb_pcmcia_io_free(pch, pcihp) 2147 pcmcia_chipset_handle_t pch; 2148 struct pcmcia_io_handle *pcihp; 2149 { 2150 #if !rbus 2151 bus_space_tag_t iot = pcihp->iot; 2152 #endif 2153 bus_space_handle_t ioh = pcihp->ioh; 2154 bus_size_t size = pcihp->size; 2155 2156 #if rbus 2157 struct pccbb_softc *sc = 2158 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2159 rbus_tag_t rb = sc->sc_rbus_iot; 2160 2161 rbus_space_free(rb, ioh, size, NULL); 2162 #else 2163 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2164 bus_space_free(iot, ioh, size); 2165 else 2166 bus_space_unmap(iot, ioh, size); 2167 #endif 2168 } 2169 2170 /* 2171 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2172 * bus_addr_t offset, bus_size_t size, 2173 * struct pcmcia_io_handle *pcihp, 2174 * int *windowp) 2175 * 2176 * This function maps the allocated I/O region to pccard. This function 2177 * never allocates any I/O region for pccard I/O area. I don't 2178 * understand why the original authors of pcmciabus separated alloc and 2179 * map. I believe the two must be unite. 2180 * 2181 * XXX: no wait timing control? 2182 */ 2183 int 2184 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2185 pcmcia_chipset_handle_t pch; 2186 int width; 2187 bus_addr_t offset; 2188 bus_size_t size; 2189 struct pcmcia_io_handle *pcihp; 2190 int *windowp; 2191 { 2192 struct pcic_handle *ph = (struct pcic_handle *)pch; 2193 bus_addr_t ioaddr = pcihp->addr + offset; 2194 int i, win; 2195 #if defined CBB_DEBUG 2196 static char *width_names[] = { "dynamic", "io8", "io16" }; 2197 #endif 2198 2199 /* Sanity check I/O handle. */ 2200 2201 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2202 panic("pccbb_pcmcia_io_map iot is bogus"); 2203 } 2204 2205 /* XXX Sanity check offset/size. */ 2206 2207 win = -1; 2208 for (i = 0; i < PCIC_IO_WINS; i++) { 2209 if ((ph->ioalloc & (1 << i)) == 0) { 2210 win = i; 2211 ph->ioalloc |= (1 << i); 2212 break; 2213 } 2214 } 2215 2216 if (win == -1) { 2217 return 1; 2218 } 2219 2220 *windowp = win; 2221 2222 /* XXX this is pretty gross */ 2223 2224 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2225 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2226 2227 /* XXX wtf is this doing here? */ 2228 2229 #if 0 2230 printf(" port 0x%lx", (u_long) ioaddr); 2231 if (size > 1) { 2232 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2233 } 2234 #endif 2235 2236 ph->io[win].addr = ioaddr; 2237 ph->io[win].size = size; 2238 ph->io[win].width = width; 2239 2240 /* actual dirty register-value changing in the function below. */ 2241 pccbb_pcmcia_do_io_map(ph, win); 2242 2243 return 0; 2244 } 2245 2246 /* 2247 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2248 * 2249 * This function changes register-value to map I/O region for pccard. 2250 */ 2251 static void 2252 pccbb_pcmcia_do_io_map(ph, win) 2253 struct pcic_handle *ph; 2254 int win; 2255 { 2256 static u_int8_t pcic_iowidth[3] = { 2257 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2258 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2259 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2260 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2261 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2262 }; 2263 2264 #define PCIC_SIA_START_LOW 0 2265 #define PCIC_SIA_START_HIGH 1 2266 #define PCIC_SIA_STOP_LOW 2 2267 #define PCIC_SIA_STOP_HIGH 3 2268 2269 int regbase_win = 0x8 + win * 0x04; 2270 u_int8_t ioctl, enable; 2271 2272 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2273 "width %d\n", win, (unsigned long)ph->io[win].addr, 2274 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2275 2276 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2277 ph->io[win].addr & 0xff); 2278 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2279 (ph->io[win].addr >> 8) & 0xff); 2280 2281 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2282 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2283 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2284 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2285 2286 ioctl = Pcic_read(ph, PCIC_IOCTL); 2287 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2288 switch (win) { 2289 case 0: 2290 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2291 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2292 PCIC_IOCTL_IO0_DATASIZE_MASK); 2293 ioctl |= pcic_iowidth[ph->io[win].width]; 2294 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2295 break; 2296 case 1: 2297 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2298 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2299 PCIC_IOCTL_IO1_DATASIZE_MASK); 2300 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2301 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2302 break; 2303 } 2304 Pcic_write(ph, PCIC_IOCTL, ioctl); 2305 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2306 #if defined CBB_DEBUG 2307 { 2308 u_int8_t start_low = 2309 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2310 u_int8_t start_high = 2311 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2312 u_int8_t stop_low = 2313 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2314 u_int8_t stop_high = 2315 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2316 printf 2317 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2318 start_low, start_high, stop_low, stop_high, ioctl, enable); 2319 } 2320 #endif 2321 } 2322 2323 /* 2324 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2325 * 2326 * This function unmaps I/O region. No return value. 2327 */ 2328 STATIC void 2329 pccbb_pcmcia_io_unmap(pch, win) 2330 pcmcia_chipset_handle_t pch; 2331 int win; 2332 { 2333 struct pcic_handle *ph = (struct pcic_handle *)pch; 2334 int reg; 2335 2336 if (win >= PCIC_IO_WINS || win < 0) { 2337 panic("pccbb_pcmcia_io_unmap: window out of range"); 2338 } 2339 2340 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2341 switch (win) { 2342 case 0: 2343 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2344 break; 2345 case 1: 2346 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2347 break; 2348 } 2349 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2350 2351 ph->ioalloc &= ~(1 << win); 2352 } 2353 2354 static int 2355 pccbb_pcmcia_wait_ready(ph) 2356 struct pcic_handle *ph; 2357 { 2358 u_int8_t stat; 2359 int i; 2360 2361 /* wait an initial 10ms for quick cards */ 2362 stat = Pcic_read(ph, PCIC_IF_STATUS); 2363 if (stat & PCIC_IF_STATUS_READY) 2364 return (0); 2365 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2366 for (i = 0; i < 50; i++) { 2367 stat = Pcic_read(ph, PCIC_IF_STATUS); 2368 if (stat & PCIC_IF_STATUS_READY) 2369 return (0); 2370 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2371 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2372 return (ENXIO); 2373 /* wait .1s (100ms) each iteration now */ 2374 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2375 } 2376 2377 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2378 return (EWOULDBLOCK); 2379 } 2380 2381 /* 2382 * Perform long (msec order) delay. 2383 */ 2384 static void 2385 pccbb_pcmcia_delay(ph, timo, wmesg) 2386 struct pcic_handle *ph; 2387 int timo; /* in ms. must not be zero */ 2388 const char *wmesg; 2389 { 2390 2391 #ifdef DIAGNOSTIC 2392 if (timo <= 0) 2393 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2394 if (!curlwp) 2395 panic("pccbb_pcmcia_delay: called in interrupt context"); 2396 #if 0 2397 if (!ph->event_thread) 2398 panic("pccbb_pcmcia_delay: no event thread"); 2399 #endif 2400 #endif 2401 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2402 wmesg, ph->event_thread, timo)); 2403 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2404 } 2405 2406 /* 2407 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2408 * 2409 * This function enables the card. All information is stored in 2410 * the first argument, pcmcia_chipset_handle_t. 2411 */ 2412 STATIC void 2413 pccbb_pcmcia_socket_enable(pch) 2414 pcmcia_chipset_handle_t pch; 2415 { 2416 struct pcic_handle *ph = (struct pcic_handle *)pch; 2417 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2418 pcireg_t spsr; 2419 int voltage; 2420 int win; 2421 u_int8_t power, intr; 2422 #ifdef DIAGNOSTIC 2423 int reg; 2424 #endif 2425 2426 /* this bit is mostly stolen from pcic_attach_card */ 2427 2428 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2429 2430 /* get card Vcc info */ 2431 spsr = 2432 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2433 CB_SOCKET_STAT); 2434 if (spsr & CB_SOCKET_STAT_5VCARD) { 2435 DPRINTF(("5V card\n")); 2436 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2437 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2438 DPRINTF(("3V card\n")); 2439 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2440 } else { 2441 printf("?V card, 0x%x\n", spsr); /* XXX */ 2442 return; 2443 } 2444 2445 /* disable interrupts; assert RESET */ 2446 intr = Pcic_read(ph, PCIC_INTR); 2447 intr &= PCIC_INTR_ENABLE; 2448 Pcic_write(ph, PCIC_INTR, intr); 2449 2450 /* zero out the address windows */ 2451 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2452 2453 /* power down the socket to reset it, clear the card reset pin */ 2454 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2455 2456 /* power off; assert output enable bit */ 2457 power = PCIC_PWRCTL_OE; 2458 Pcic_write(ph, PCIC_PWRCTL, power); 2459 2460 /* power up the socket */ 2461 if (pccbb_power(sc, voltage) == 0) 2462 return; 2463 2464 /* negate RESET */ 2465 intr |= PCIC_INTR_RESET; 2466 Pcic_write(ph, PCIC_INTR, intr); 2467 2468 /* 2469 * RESET Setup Time (Tsu (RESET)) = 20ms 2470 */ 2471 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2472 2473 #ifdef DIAGNOSTIC 2474 reg = Pcic_read(ph, PCIC_IF_STATUS); 2475 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2476 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2477 #endif 2478 2479 /* wait for the chip to finish initializing */ 2480 if (pccbb_pcmcia_wait_ready(ph)) { 2481 /* XXX return a failure status?? */ 2482 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2483 Pcic_write(ph, PCIC_PWRCTL, 0); 2484 return; 2485 } 2486 2487 /* reinstall all the memory and io mappings */ 2488 for (win = 0; win < PCIC_MEM_WINS; ++win) 2489 if (ph->memalloc & (1 << win)) 2490 pccbb_pcmcia_do_mem_map(ph, win); 2491 for (win = 0; win < PCIC_IO_WINS; ++win) 2492 if (ph->ioalloc & (1 << win)) 2493 pccbb_pcmcia_do_io_map(ph, win); 2494 } 2495 2496 /* 2497 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2498 * 2499 * This function disables the card. All information is stored in 2500 * the first argument, pcmcia_chipset_handle_t. 2501 */ 2502 STATIC void 2503 pccbb_pcmcia_socket_disable(pch) 2504 pcmcia_chipset_handle_t pch; 2505 { 2506 struct pcic_handle *ph = (struct pcic_handle *)pch; 2507 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2508 u_int8_t intr; 2509 2510 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2511 2512 /* disable interrupts; assert RESET */ 2513 intr = Pcic_read(ph, PCIC_INTR); 2514 intr &= PCIC_INTR_ENABLE; 2515 Pcic_write(ph, PCIC_INTR, intr); 2516 2517 /* zero out the address windows */ 2518 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2519 2520 /* power down the socket to reset it, clear the card reset pin */ 2521 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2522 2523 /* disable socket: negate output enable bit and power off */ 2524 Pcic_write(ph, PCIC_PWRCTL, 0); 2525 2526 /* 2527 * Vcc Falling Time (Tpf) = 300ms 2528 */ 2529 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2530 } 2531 2532 STATIC void 2533 pccbb_pcmcia_socket_settype(pch, type) 2534 pcmcia_chipset_handle_t pch; 2535 int type; 2536 { 2537 struct pcic_handle *ph = (struct pcic_handle *)pch; 2538 u_int8_t intr; 2539 2540 /* set the card type */ 2541 2542 intr = Pcic_read(ph, PCIC_INTR); 2543 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2544 if (type == PCMCIA_IFTYPE_IO) 2545 intr |= PCIC_INTR_CARDTYPE_IO; 2546 else 2547 intr |= PCIC_INTR_CARDTYPE_MEM; 2548 Pcic_write(ph, PCIC_INTR, intr); 2549 2550 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2551 ph->ph_parent->dv_xname, ph->sock, 2552 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2553 } 2554 2555 /* 2556 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2557 * 2558 * This function detects whether a card is in the slot or not. 2559 * If a card is inserted, return 1. Otherwise, return 0. 2560 */ 2561 STATIC int 2562 pccbb_pcmcia_card_detect(pch) 2563 pcmcia_chipset_handle_t pch; 2564 { 2565 struct pcic_handle *ph = (struct pcic_handle *)pch; 2566 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2567 2568 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2569 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2570 } 2571 2572 #if 0 2573 STATIC int 2574 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2575 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2576 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2577 #endif 2578 /* 2579 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2580 * bus_size_t size, 2581 * struct pcmcia_mem_handle *pcmhp) 2582 * 2583 * This function only allocates memory region for pccard. This 2584 * function never maps the allocated region to pccard memory area. 2585 * 2586 * XXX: Why the argument of start address is not in? 2587 */ 2588 STATIC int 2589 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2590 pcmcia_chipset_handle_t pch; 2591 bus_size_t size; 2592 struct pcmcia_mem_handle *pcmhp; 2593 { 2594 struct pcic_handle *ph = (struct pcic_handle *)pch; 2595 bus_space_handle_t memh; 2596 bus_addr_t addr; 2597 bus_size_t sizepg; 2598 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2599 #if rbus 2600 rbus_tag_t rb; 2601 #endif 2602 2603 /* Check that the card is still there. */ 2604 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2605 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2606 return 1; 2607 2608 /* out of sc->memh, allocate as many pages as necessary */ 2609 2610 /* convert size to PCIC pages */ 2611 /* 2612 * This is not enough; when the requested region is on the page 2613 * boundaries, this may calculate wrong result. 2614 */ 2615 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2616 #if 0 2617 if (sizepg > PCIC_MAX_MEM_PAGES) { 2618 return 1; 2619 } 2620 #endif 2621 2622 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2623 return 1; 2624 } 2625 2626 addr = 0; /* XXX gcc -Wuninitialized */ 2627 2628 #if rbus 2629 rb = sc->sc_rbus_memt; 2630 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2631 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2632 &addr, &memh)) { 2633 return 1; 2634 } 2635 #else 2636 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2637 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2638 0, /* boundary */ 2639 0, /* flags */ 2640 &addr, &memh)) { 2641 return 1; 2642 } 2643 #endif 2644 2645 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2646 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2647 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2648 2649 pcmhp->memt = sc->sc_memt; 2650 pcmhp->memh = memh; 2651 pcmhp->addr = addr; 2652 pcmhp->size = size; 2653 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2654 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2655 pcmhp->mhandle = 0; 2656 /* No offset??? Funny. */ 2657 2658 return 0; 2659 } 2660 2661 /* 2662 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2663 * struct pcmcia_mem_handle *pcmhp) 2664 * 2665 * This function release the memory space allocated by the function 2666 * pccbb_pcmcia_mem_alloc(). 2667 */ 2668 STATIC void 2669 pccbb_pcmcia_mem_free(pch, pcmhp) 2670 pcmcia_chipset_handle_t pch; 2671 struct pcmcia_mem_handle *pcmhp; 2672 { 2673 #if rbus 2674 struct pcic_handle *ph = (struct pcic_handle *)pch; 2675 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2676 2677 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2678 #else 2679 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2680 #endif 2681 } 2682 2683 /* 2684 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2685 * 2686 * This function release the memory space allocated by the function 2687 * pccbb_pcmcia_mem_alloc(). 2688 */ 2689 STATIC void 2690 pccbb_pcmcia_do_mem_map(ph, win) 2691 struct pcic_handle *ph; 2692 int win; 2693 { 2694 int regbase_win; 2695 bus_addr_t phys_addr; 2696 bus_addr_t phys_end; 2697 2698 #define PCIC_SMM_START_LOW 0 2699 #define PCIC_SMM_START_HIGH 1 2700 #define PCIC_SMM_STOP_LOW 2 2701 #define PCIC_SMM_STOP_HIGH 3 2702 #define PCIC_CMA_LOW 4 2703 #define PCIC_CMA_HIGH 5 2704 2705 u_int8_t start_low, start_high = 0; 2706 u_int8_t stop_low, stop_high; 2707 u_int8_t off_low, off_high; 2708 u_int8_t mem_window; 2709 int reg; 2710 2711 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2712 int mem8 = 2713 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2714 || (kind == PCMCIA_MEM_ATTR); 2715 2716 regbase_win = 0x10 + win * 0x08; 2717 2718 phys_addr = ph->mem[win].addr; 2719 phys_end = phys_addr + ph->mem[win].size; 2720 2721 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2722 (unsigned long)phys_addr, (unsigned long)phys_end, 2723 (unsigned long)ph->mem[win].offset)); 2724 2725 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2726 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2727 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2728 2729 /* bit 19:12 */ 2730 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2731 /* bit 23:20 and bit 7 on */ 2732 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2733 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2734 /* bit 31:24, for 32-bit address */ 2735 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2736 2737 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2738 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2739 2740 if (((struct pccbb_softc *)ph-> 2741 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2742 Pcic_write(ph, 0x40 + win, mem_window); 2743 } 2744 2745 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2746 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2747 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2748 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2749 2750 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2751 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2752 2753 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2754 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2755 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2756 | ((kind == PCMCIA_MEM_ATTR) ? 2757 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2758 2759 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2760 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2761 2762 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2763 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2764 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2765 2766 #if defined CBB_DEBUG 2767 { 2768 int r1, r2, r3, r4, r5, r6, r7 = 0; 2769 2770 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2771 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2772 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2773 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2774 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2775 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2776 if (((struct pccbb_softc *)(ph-> 2777 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2778 r7 = Pcic_read(ph, 0x40 + win); 2779 } 2780 2781 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2782 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2783 if (((struct pccbb_softc *)(ph-> 2784 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2785 DPRINTF((" %02x", r7)); 2786 } 2787 DPRINTF(("\n")); 2788 } 2789 #endif 2790 } 2791 2792 /* 2793 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2794 * bus_addr_t card_addr, bus_size_t size, 2795 * struct pcmcia_mem_handle *pcmhp, 2796 * bus_addr_t *offsetp, int *windowp) 2797 * 2798 * This function maps memory space allocated by the function 2799 * pccbb_pcmcia_mem_alloc(). 2800 */ 2801 STATIC int 2802 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2803 pcmcia_chipset_handle_t pch; 2804 int kind; 2805 bus_addr_t card_addr; 2806 bus_size_t size; 2807 struct pcmcia_mem_handle *pcmhp; 2808 bus_addr_t *offsetp; 2809 int *windowp; 2810 { 2811 struct pcic_handle *ph = (struct pcic_handle *)pch; 2812 bus_addr_t busaddr; 2813 long card_offset; 2814 int win; 2815 2816 /* Check that the card is still there. */ 2817 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2818 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2819 return 1; 2820 2821 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2822 if ((ph->memalloc & (1 << win)) == 0) { 2823 ph->memalloc |= (1 << win); 2824 break; 2825 } 2826 } 2827 2828 if (win == PCIC_MEM_WINS) { 2829 return 1; 2830 } 2831 2832 *windowp = win; 2833 2834 /* XXX this is pretty gross */ 2835 2836 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2837 panic("pccbb_pcmcia_mem_map memt is bogus"); 2838 } 2839 2840 busaddr = pcmhp->addr; 2841 2842 /* 2843 * compute the address offset to the pcmcia address space for the 2844 * pcic. this is intentionally signed. The masks and shifts below 2845 * will cause TRT to happen in the pcic registers. Deal with making 2846 * sure the address is aligned, and return the alignment offset. 2847 */ 2848 2849 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2850 card_addr -= *offsetp; 2851 2852 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2853 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2854 (u_long) card_addr)); 2855 2856 /* 2857 * include the offset in the size, and decrement size by one, since 2858 * the hw wants start/stop 2859 */ 2860 size += *offsetp - 1; 2861 2862 card_offset = (((long)card_addr) - ((long)busaddr)); 2863 2864 ph->mem[win].addr = busaddr; 2865 ph->mem[win].size = size; 2866 ph->mem[win].offset = card_offset; 2867 ph->mem[win].kind = kind; 2868 2869 pccbb_pcmcia_do_mem_map(ph, win); 2870 2871 return 0; 2872 } 2873 2874 /* 2875 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2876 * int window) 2877 * 2878 * This function unmaps memory space which mapped by the function 2879 * pccbb_pcmcia_mem_map(). 2880 */ 2881 STATIC void 2882 pccbb_pcmcia_mem_unmap(pch, window) 2883 pcmcia_chipset_handle_t pch; 2884 int window; 2885 { 2886 struct pcic_handle *ph = (struct pcic_handle *)pch; 2887 int reg; 2888 2889 if (window >= PCIC_MEM_WINS) { 2890 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2891 } 2892 2893 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2894 reg &= ~(1 << window); 2895 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2896 2897 ph->memalloc &= ~(1 << window); 2898 } 2899 2900 #if defined PCCBB_PCMCIA_POLL 2901 struct pccbb_poll_str { 2902 void *arg; 2903 int (*func) __P((void *)); 2904 int level; 2905 struct pcic_handle *ph; 2906 int count; 2907 int num; 2908 struct callout poll_ch; 2909 }; 2910 2911 static struct pccbb_poll_str pccbb_poll[10]; 2912 static int pccbb_poll_n = 0; 2913 2914 static void pccbb_pcmcia_poll __P((void *arg)); 2915 2916 static void 2917 pccbb_pcmcia_poll(arg) 2918 void *arg; 2919 { 2920 struct pccbb_poll_str *poll = arg; 2921 struct pcic_handle *ph = poll->ph; 2922 struct pccbb_softc *sc = ph->sc; 2923 int s; 2924 u_int32_t spsr; /* socket present-state reg */ 2925 2926 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2927 switch (poll->level) { 2928 case IPL_NET: 2929 s = splnet(); 2930 break; 2931 case IPL_BIO: 2932 s = splbio(); 2933 break; 2934 case IPL_TTY: /* fallthrough */ 2935 default: 2936 s = spltty(); 2937 break; 2938 } 2939 2940 spsr = 2941 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2942 CB_SOCKET_STAT); 2943 2944 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2945 if (!(spsr & 0x40)) /* CINT low */ 2946 #else 2947 if (1) 2948 #endif 2949 { 2950 if ((*poll->func) (poll->arg) > 0) { 2951 ++poll->count; 2952 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2953 #if defined LEVEL2 2954 } else { 2955 printf("intr: miss! 0x%x\n", spsr); 2956 #endif 2957 } 2958 } 2959 splx(s); 2960 } 2961 #endif /* defined CB_PCMCIA_POLL */ 2962 2963 /* 2964 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2965 * struct pcmcia_function *pf, 2966 * int ipl, 2967 * int (*func)(void *), 2968 * void *arg); 2969 * 2970 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2971 */ 2972 STATIC void * 2973 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2974 pcmcia_chipset_handle_t pch; 2975 struct pcmcia_function *pf; 2976 int ipl; 2977 int (*func) __P((void *)); 2978 void *arg; 2979 { 2980 struct pcic_handle *ph = (struct pcic_handle *)pch; 2981 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2982 2983 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2984 /* what should I do? */ 2985 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2986 DPRINTF(("%s does not provide edge nor pulse " 2987 "interrupt\n", sc->sc_dev.dv_xname)); 2988 return NULL; 2989 } 2990 /* 2991 * XXX Noooooo! The interrupt flag must set properly!! 2992 * dumb pcmcia driver!! 2993 */ 2994 } 2995 2996 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2997 } 2998 2999 /* 3000 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 3001 * void *ih) 3002 * 3003 * This function disables PC-Card interrupt. 3004 */ 3005 STATIC void 3006 pccbb_pcmcia_intr_disestablish(pch, ih) 3007 pcmcia_chipset_handle_t pch; 3008 void *ih; 3009 { 3010 struct pcic_handle *ph = (struct pcic_handle *)pch; 3011 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3012 3013 pccbb_intr_disestablish(sc, ih); 3014 } 3015 3016 #if rbus 3017 /* 3018 * static int 3019 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3020 * bus_addr_t addr, bus_size_t size, 3021 * bus_addr_t mask, bus_size_t align, 3022 * int flags, bus_addr_t *addrp; 3023 * bus_space_handle_t *bshp) 3024 * 3025 * This function allocates a portion of memory or io space for 3026 * clients. This function is called from CardBus card drivers. 3027 */ 3028 static int 3029 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3030 cardbus_chipset_tag_t ct; 3031 rbus_tag_t rb; 3032 bus_addr_t addr; 3033 bus_size_t size; 3034 bus_addr_t mask; 3035 bus_size_t align; 3036 int flags; 3037 bus_addr_t *addrp; 3038 bus_space_handle_t *bshp; 3039 { 3040 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3041 3042 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3043 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3044 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3045 3046 if (align == 0) { 3047 align = size; 3048 } 3049 3050 if (rb->rb_bt == sc->sc_memt) { 3051 if (align < 16) { 3052 return 1; 3053 } 3054 /* 3055 * XXX: align more than 0x1000 to avoid overwrapping 3056 * memory windows for two or more devices. 0x1000 3057 * means memory window's granularity. 3058 * 3059 * Two or more devices should be able to share same 3060 * memory window region. However, overrapping memory 3061 * window is not good because some devices, such as 3062 * 3Com 3C575[BC], have a broken address decoder and 3063 * intrude other's memory region. 3064 */ 3065 if (align < 0x1000) { 3066 align = 0x1000; 3067 } 3068 } else if (rb->rb_bt == sc->sc_iot) { 3069 if (align < 4) { 3070 return 1; 3071 } 3072 /* XXX: hack for avoiding ISA image */ 3073 if (mask < 0x0100) { 3074 mask = 0x3ff; 3075 addr = 0x300; 3076 } 3077 3078 } else { 3079 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3080 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3081 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3082 (unsigned long)sc->sc_memt)); 3083 return 1; 3084 /* XXX: panic here? */ 3085 } 3086 3087 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3088 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3089 return 1; 3090 } 3091 3092 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3093 3094 return 0; 3095 } 3096 3097 /* 3098 * static int 3099 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3100 * bus_space_handle_t *bshp, bus_size_t size); 3101 * 3102 * This function is called from CardBus card drivers. 3103 */ 3104 static int 3105 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3106 cardbus_chipset_tag_t ct; 3107 rbus_tag_t rb; 3108 bus_space_handle_t bsh; 3109 bus_size_t size; 3110 { 3111 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3112 bus_space_tag_t bt = rb->rb_bt; 3113 3114 pccbb_close_win(sc, bt, bsh, size); 3115 3116 if (bt == sc->sc_memt) { 3117 } else if (bt == sc->sc_iot) { 3118 } else { 3119 return 1; 3120 /* XXX: panic here? */ 3121 } 3122 3123 return rbus_space_free(rb, bsh, size, NULL); 3124 } 3125 #endif /* rbus */ 3126 3127 #if rbus 3128 3129 static int 3130 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3131 struct pccbb_softc *sc; 3132 bus_space_tag_t bst; 3133 bus_addr_t addr; 3134 bus_size_t size; 3135 bus_space_handle_t bsh; 3136 int flags; 3137 { 3138 struct pccbb_win_chain_head *head; 3139 bus_addr_t align; 3140 3141 head = &sc->sc_iowindow; 3142 align = 0x04; 3143 if (sc->sc_memt == bst) { 3144 head = &sc->sc_memwindow; 3145 align = 0x1000; 3146 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3147 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3148 (unsigned long)bst)); 3149 } 3150 3151 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3152 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3153 sc->sc_dev.dv_xname, 3154 (head == &sc->sc_memwindow) ? "mem" : "io"); 3155 } 3156 pccbb_winset(align, sc, bst); 3157 3158 return 0; 3159 } 3160 3161 static int 3162 pccbb_close_win(sc, bst, bsh, size) 3163 struct pccbb_softc *sc; 3164 bus_space_tag_t bst; 3165 bus_space_handle_t bsh; 3166 bus_size_t size; 3167 { 3168 struct pccbb_win_chain_head *head; 3169 bus_addr_t align; 3170 3171 head = &sc->sc_iowindow; 3172 align = 0x04; 3173 if (sc->sc_memt == bst) { 3174 head = &sc->sc_memwindow; 3175 align = 0x1000; 3176 } 3177 3178 if (pccbb_winlist_delete(head, bsh, size)) { 3179 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3180 sc->sc_dev.dv_xname, 3181 (head == &sc->sc_memwindow) ? "mem" : "io"); 3182 } 3183 pccbb_winset(align, sc, bst); 3184 3185 return 0; 3186 } 3187 3188 static int 3189 pccbb_winlist_insert(head, start, size, bsh, flags) 3190 struct pccbb_win_chain_head *head; 3191 bus_addr_t start; 3192 bus_size_t size; 3193 bus_space_handle_t bsh; 3194 int flags; 3195 { 3196 struct pccbb_win_chain *chainp, *elem; 3197 3198 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3199 M_NOWAIT)) == NULL) 3200 return (1); /* fail */ 3201 3202 elem->wc_start = start; 3203 elem->wc_end = start + (size - 1); 3204 elem->wc_handle = bsh; 3205 elem->wc_flags = flags; 3206 3207 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3208 chainp = TAILQ_NEXT(chainp, wc_list)) { 3209 if (chainp->wc_end < start) 3210 continue; 3211 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3212 return (0); 3213 } 3214 3215 TAILQ_INSERT_TAIL(head, elem, wc_list); 3216 return (0); 3217 } 3218 3219 static int 3220 pccbb_winlist_delete(head, bsh, size) 3221 struct pccbb_win_chain_head *head; 3222 bus_space_handle_t bsh; 3223 bus_size_t size; 3224 { 3225 struct pccbb_win_chain *chainp; 3226 3227 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3228 chainp = TAILQ_NEXT(chainp, wc_list)) { 3229 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3230 continue; 3231 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3232 printf("pccbb_winlist_delete: window 0x%lx size " 3233 "inconsistent: 0x%lx, 0x%lx\n", 3234 (unsigned long)chainp->wc_start, 3235 (unsigned long)(chainp->wc_end - chainp->wc_start), 3236 (unsigned long)(size - 1)); 3237 return 1; 3238 } 3239 3240 TAILQ_REMOVE(head, chainp, wc_list); 3241 free(chainp, M_DEVBUF); 3242 3243 return 0; 3244 } 3245 3246 return 1; /* fail: no candidate to remove */ 3247 } 3248 3249 static void 3250 pccbb_winset(align, sc, bst) 3251 bus_addr_t align; 3252 struct pccbb_softc *sc; 3253 bus_space_tag_t bst; 3254 { 3255 pci_chipset_tag_t pc; 3256 pcitag_t tag; 3257 bus_addr_t mask = ~(align - 1); 3258 struct { 3259 cardbusreg_t win_start; 3260 cardbusreg_t win_limit; 3261 int win_flags; 3262 } win[2]; 3263 struct pccbb_win_chain *chainp; 3264 int offs; 3265 3266 win[0].win_start = win[1].win_start = 0xffffffff; 3267 win[0].win_limit = win[1].win_limit = 0; 3268 win[0].win_flags = win[1].win_flags = 0; 3269 3270 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3271 offs = 0x2c; 3272 if (sc->sc_memt == bst) { 3273 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3274 offs = 0x1c; 3275 } 3276 3277 if (chainp != NULL) { 3278 win[0].win_start = chainp->wc_start & mask; 3279 win[0].win_limit = chainp->wc_end & mask; 3280 win[0].win_flags = chainp->wc_flags; 3281 chainp = TAILQ_NEXT(chainp, wc_list); 3282 } 3283 3284 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3285 if (win[1].win_start == 0xffffffff) { 3286 /* window 1 is not used */ 3287 if ((win[0].win_flags == chainp->wc_flags) && 3288 (win[0].win_limit + align >= 3289 (chainp->wc_start & mask))) { 3290 /* concatenate */ 3291 win[0].win_limit = chainp->wc_end & mask; 3292 } else { 3293 /* make new window */ 3294 win[1].win_start = chainp->wc_start & mask; 3295 win[1].win_limit = chainp->wc_end & mask; 3296 win[1].win_flags = chainp->wc_flags; 3297 } 3298 continue; 3299 } 3300 3301 /* Both windows are engaged. */ 3302 if (win[0].win_flags == win[1].win_flags) { 3303 /* same flags */ 3304 if (win[0].win_flags == chainp->wc_flags) { 3305 if (win[1].win_start - (win[0].win_limit + 3306 align) < 3307 (chainp->wc_start & mask) - 3308 ((chainp->wc_end & mask) + align)) { 3309 /* 3310 * merge window 0 and 1, and set win1 3311 * to chainp 3312 */ 3313 win[0].win_limit = win[1].win_limit; 3314 win[1].win_start = 3315 chainp->wc_start & mask; 3316 win[1].win_limit = 3317 chainp->wc_end & mask; 3318 } else { 3319 win[1].win_limit = 3320 chainp->wc_end & mask; 3321 } 3322 } else { 3323 /* different flags */ 3324 3325 /* concatenate win0 and win1 */ 3326 win[0].win_limit = win[1].win_limit; 3327 /* allocate win[1] to new space */ 3328 win[1].win_start = chainp->wc_start & mask; 3329 win[1].win_limit = chainp->wc_end & mask; 3330 win[1].win_flags = chainp->wc_flags; 3331 } 3332 } else { 3333 /* the flags of win[0] and win[1] is different */ 3334 if (win[0].win_flags == chainp->wc_flags) { 3335 win[0].win_limit = chainp->wc_end & mask; 3336 /* 3337 * XXX this creates overlapping windows, so 3338 * what should the poor bridge do if one is 3339 * cachable, and the other is not? 3340 */ 3341 printf("%s: overlapping windows\n", 3342 sc->sc_dev.dv_xname); 3343 } else { 3344 win[1].win_limit = chainp->wc_end & mask; 3345 } 3346 } 3347 } 3348 3349 pc = sc->sc_pc; 3350 tag = sc->sc_tag; 3351 pci_conf_write(pc, tag, offs, win[0].win_start); 3352 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3353 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3354 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3355 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3356 (unsigned long)pci_conf_read(pc, tag, offs), 3357 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3358 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3359 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3360 3361 if (bst == sc->sc_memt) { 3362 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3363 3364 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3365 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3366 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3367 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3368 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3369 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3370 } 3371 } 3372 3373 #endif /* rbus */ 3374 3375 static void 3376 pccbb_powerhook(why, arg) 3377 int why; 3378 void *arg; 3379 { 3380 struct pccbb_softc *sc = arg; 3381 pcireg_t reg; 3382 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3383 bus_space_handle_t base_memh = sc->sc_base_memh; 3384 3385 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3386 3387 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3388 DPRINTF(("%s: power: why %d stopping intr\n", 3389 sc->sc_dev.dv_xname, why)); 3390 if (sc->sc_pil_intr_enable) { 3391 (void)pccbbintr_function(sc); 3392 } 3393 sc->sc_pil_intr_enable = 0; 3394 3395 /* ToDo: deactivate or suspend child devices */ 3396 3397 } 3398 3399 if (why == PWR_RESUME) { 3400 if (sc->sc_pwrmgt_offs != 0) { 3401 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3402 sc->sc_pwrmgt_offs + 4); 3403 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3404 reg & 0x100) { 3405 /* powrstate != D0 */ 3406 3407 printf("%s going back to D0 mode\n", 3408 sc->sc_dev.dv_xname); 3409 reg &= ~PCI_PMCSR_STATE_MASK; 3410 reg |= PCI_PMCSR_STATE_D0; 3411 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3412 pci_conf_write(sc->sc_pc, sc->sc_tag, 3413 sc->sc_pwrmgt_offs + 4, reg); 3414 3415 pci_conf_write(sc->sc_pc, sc->sc_tag, 3416 PCI_SOCKBASE, sc->sc_sockbase); 3417 pci_conf_write(sc->sc_pc, sc->sc_tag, 3418 PCI_BUSNUM, sc->sc_busnum); 3419 pccbb_chipinit(sc); 3420 /* setup memory and io space window for CB */ 3421 pccbb_winset(0x1000, sc, sc->sc_memt); 3422 pccbb_winset(0x04, sc, sc->sc_iot); 3423 } 3424 } 3425 3426 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3427 /* BIOS did not recover this register */ 3428 pci_conf_write (sc->sc_pc, sc->sc_tag, 3429 PCI_SOCKBASE, sc->sc_sockbase); 3430 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3431 /* BIOS did not recover this register */ 3432 pci_conf_write (sc->sc_pc, sc->sc_tag, 3433 PCI_BUSNUM, sc->sc_busnum); 3434 /* CSC Interrupt: Card detect interrupt on */ 3435 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3436 /* Card detect intr is turned on. */ 3437 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3438 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3439 /* reset interrupt */ 3440 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3441 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3442 3443 /* 3444 * check for card insertion or removal during suspend period. 3445 * XXX: the code can't cope with card swap (remove then 3446 * insert). how can we detect such situation? 3447 */ 3448 (void)pccbbintr(sc); 3449 3450 sc->sc_pil_intr_enable = 1; 3451 DPRINTF(("%s: power: RESUME enabling intr\n", 3452 sc->sc_dev.dv_xname)); 3453 3454 /* ToDo: activate or wakeup child devices */ 3455 } 3456 } 3457
Indexes created Thu Sep 25 16:09:42 GMT 2025