pccbb.c revision 1.116
1 /* $NetBSD: pccbb.c,v 1.116 2005/02/04 02:10:45 perry Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.116 2005/02/04 02:10:45 perry Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch(struct device *, struct cfdata *, void *); 115 void pccbbattach(struct device *, struct device *, void *); 116 int pccbbintr(void *); 117 static void pci113x_insert(void *); 118 static int pccbbintr_function(struct pccbb_softc *); 119 120 static int pccbb_detect_card(struct pccbb_softc *); 121 122 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 123 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset(struct pccbb_softc *); 128 STATIC int cb_detect_voltage(struct pccbb_softc *); 129 STATIC int cbbprint(void *, const char *); 130 131 static int cb_chipset(u_int32_t, int *); 132 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 133 struct pcmciabus_attach_args *); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 136 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 137 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 138 #endif 139 140 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 141 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 142 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 143 #if !rbus 144 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 145 static int pccbb_io_close(cardbus_chipset_tag_t, int); 146 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 147 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc); 151 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 152 153 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc); 155 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 156 157 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int, int); 158 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 159 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 160 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 161 cardbusreg_t); 162 static void pccbb_chipinit(struct pccbb_softc *); 163 164 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 165 struct pcmcia_mem_handle *); 166 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 167 struct pcmcia_mem_handle *); 168 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 170 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 171 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 172 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 173 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 174 struct pcmcia_io_handle *); 175 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 176 bus_size_t, struct pcmcia_io_handle *, int *); 177 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 178 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 179 struct pcmcia_function *, int, int (*)(void *), void *); 180 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 181 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 182 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 183 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 184 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 185 186 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 187 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 188 189 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 190 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 191 static void pccbb_powerhook(int, void *); 192 193 /* bus-space allocation and deallocation functions */ 194 #if rbus 195 196 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 198 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 199 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 200 bus_space_handle_t, bus_size_t); 201 202 #endif /* rbus */ 203 204 #if rbus 205 206 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 207 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 208 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 209 bus_space_handle_t, bus_size_t); 210 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 211 bus_size_t, bus_space_handle_t, int); 212 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 213 bus_space_handle_t, bus_size_t); 214 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 215 bus_space_tag_t); 216 void pccbb_winlist_show(struct pccbb_win_chain *); 217 218 #endif /* rbus */ 219 220 /* for config_defer */ 221 static void pccbb_pci_callback(struct device *); 222 223 #if defined SHOW_REGS 224 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 225 bus_space_tag_t memt, bus_space_handle_t memh); 226 #endif 227 228 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 229 pcicbbmatch, pccbbattach, NULL, NULL); 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_socket_settype, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(parent, match, aux) 279 struct device *parent; 280 struct cfdata *match; 281 void *aux; 282 { 283 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 284 285 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 286 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 287 PCI_INTERFACE(pa->pa_class) == 0) { 288 return 1; 289 } 290 291 return 0; 292 } 293 294 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 295 | ((prod) << PCI_PRODUCT_SHIFT)) 296 297 const struct yenta_chipinfo { 298 pcireg_t yc_id; /* vendor tag | product tag */ 299 int yc_chiptype; 300 int yc_flags; 301 } yc_chipsets[] = { 302 /* Texas Instruments chips */ 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 332 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 334 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 335 336 /* Ricoh chips */ 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 344 PCCBB_PCMCIA_MEM_32}, 345 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 346 PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 348 PCCBB_PCMCIA_MEM_32}, 349 350 /* Toshiba products */ 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 352 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 354 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 355 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 356 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 358 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 359 360 /* Cirrus Logic products */ 361 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 362 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 363 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 364 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 365 366 /* sentinel, or Generic chip */ 367 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 368 }; 369 370 static int 371 cb_chipset(pci_id, flagp) 372 u_int32_t pci_id; 373 int *flagp; 374 { 375 const struct yenta_chipinfo *yc; 376 377 /* Loop over except the last default entry. */ 378 for (yc = yc_chipsets; yc < yc_chipsets + 379 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 380 if (pci_id == yc->yc_id) 381 break; 382 383 if (flagp != NULL) 384 *flagp = yc->yc_flags; 385 386 return (yc->yc_chiptype); 387 } 388 389 static void 390 pccbb_shutdown(void *arg) 391 { 392 struct pccbb_softc *sc = arg; 393 pcireg_t command; 394 395 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 396 397 /* 398 * turn off power 399 * 400 * XXX - do not turn off power if chipset is TI 113X because 401 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 402 */ 403 if (sc->sc_chipset != CB_TI113X) { 404 pccbb_power((cardbus_chipset_tag_t)sc, 405 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 406 } 407 408 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 409 0); 410 411 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 412 413 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 414 PCI_COMMAND_MASTER_ENABLE); 415 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 416 417 } 418 419 void 420 pccbbattach(parent, self, aux) 421 struct device *parent; 422 struct device *self; 423 void *aux; 424 { 425 struct pccbb_softc *sc = (void *)self; 426 struct pci_attach_args *pa = aux; 427 pci_chipset_tag_t pc = pa->pa_pc; 428 pcireg_t busreg, reg, sock_base; 429 bus_addr_t sockbase; 430 char devinfo[256]; 431 int flags; 432 int pwrmgt_offs; 433 434 #ifdef __HAVE_PCCBB_ATTACH_HOOK 435 pccbb_attach_hook(parent, self, pa); 436 #endif 437 438 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 439 440 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 441 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 442 #ifdef CBB_DEBUG 443 printf(" (chipflags %x)", flags); 444 #endif 445 printf("\n"); 446 447 TAILQ_INIT(&sc->sc_memwindow); 448 TAILQ_INIT(&sc->sc_iowindow); 449 450 #if rbus 451 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 452 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 453 454 #if 0 455 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 456 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 457 #endif 458 #endif /* rbus */ 459 460 sc->sc_flags &= ~CBB_MEMHMAPPED; 461 462 /* power management: set D0 state */ 463 sc->sc_pwrmgt_offs = 0; 464 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 465 &pwrmgt_offs, 0)) { 466 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 467 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 468 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 469 reg &= ~PCI_PMCSR_STATE_MASK; 470 reg |= PCI_PMCSR_STATE_D0; 471 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 472 pci_conf_write(pc, pa->pa_tag, 473 pwrmgt_offs + PCI_PMCSR, reg); 474 } 475 476 sc->sc_pwrmgt_offs = pwrmgt_offs; 477 } 478 479 /* 480 * MAP socket registers and ExCA registers on memory-space 481 * When no valid address is set on socket base registers (on pci 482 * config space), get it not polite way. 483 */ 484 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 485 486 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 487 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 488 /* The address must be valid. */ 489 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 490 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 491 printf("%s: can't map socket base address 0x%lx\n", 492 sc->sc_dev.dv_xname, (unsigned long)sock_base); 493 /* 494 * I think it's funny: socket base registers must be 495 * mapped on memory space, but ... 496 */ 497 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 498 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 499 NULL)) { 500 printf("%s: can't map socket base address" 501 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 502 (unsigned long)sockbase); 503 /* give up... allocate reg space via rbus. */ 504 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 505 } else 506 sc->sc_flags |= CBB_MEMHMAPPED; 507 } else { 508 DPRINTF(("%s: socket base address 0x%lx\n", 509 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 510 sc->sc_flags |= CBB_MEMHMAPPED; 511 } 512 } 513 514 sc->sc_mem_start = 0; /* XXX */ 515 sc->sc_mem_end = 0xffffffff; /* XXX */ 516 517 /* 518 * When interrupt isn't routed correctly, give up probing cbb and do 519 * not kill pcic-compatible port. 520 */ 521 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 522 printf("%s: NOT USED because of unconfigured interrupt\n", 523 sc->sc_dev.dv_xname); 524 return; 525 } 526 527 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 528 529 /* pccbb_machdep.c end */ 530 531 #if defined CBB_DEBUG 532 { 533 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 534 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 535 intrname[pa->pa_intrpin], pa->pa_intrline); 536 } 537 #endif 538 539 /* setup softc */ 540 sc->sc_pc = pc; 541 sc->sc_iot = pa->pa_iot; 542 sc->sc_memt = pa->pa_memt; 543 sc->sc_dmat = pa->pa_dmat; 544 sc->sc_tag = pa->pa_tag; 545 sc->sc_function = pa->pa_function; 546 sc->sc_sockbase = sock_base; 547 sc->sc_busnum = busreg; 548 549 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 550 551 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 552 553 shutdownhook_establish(pccbb_shutdown, sc); 554 555 /* Disable legacy register mapping. */ 556 switch (sc->sc_chipset) { 557 case CB_RX5C46X: /* fallthrough */ 558 #if 0 559 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 560 case CB_RX5C47X: 561 #endif 562 /* 563 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 564 * cannot be disabled by substituting 0 into PCI_LEGACY 565 * register. Ricoh CardBus bridges have special bits on Bridge 566 * control reg (addr 0x3e on PCI config space). 567 */ 568 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 569 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 570 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 571 break; 572 573 default: 574 /* XXX I don't know proper way to kill legacy I/O. */ 575 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 576 break; 577 } 578 579 config_defer(self, pccbb_pci_callback); 580 } 581 582 583 584 585 /* 586 * static void pccbb_pci_callback(struct device *self) 587 * 588 * The actual attach routine: get memory space for YENTA register 589 * space, setup YENTA register and route interrupt. 590 * 591 * This function should be deferred because this device may obtain 592 * memory space dynamically. This function must avoid obtaining 593 * memory area which has already kept for another device. 594 */ 595 static void 596 pccbb_pci_callback(self) 597 struct device *self; 598 { 599 struct pccbb_softc *sc = (void *)self; 600 pci_chipset_tag_t pc = sc->sc_pc; 601 pci_intr_handle_t ih; 602 const char *intrstr = NULL; 603 bus_addr_t sockbase; 604 struct cbslot_attach_args cba; 605 struct pcmciabus_attach_args paa; 606 struct cardslot_attach_args caa; 607 struct cardslot_softc *csc; 608 609 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 610 /* The socket registers aren't mapped correctly. */ 611 #if rbus 612 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 613 (sc->sc_chipset == CB_RX5C47X 614 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 615 0, &sockbase, &sc->sc_base_memh)) { 616 return; 617 } 618 sc->sc_base_memt = sc->sc_memt; 619 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 620 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 621 sc->sc_dev.dv_xname, (unsigned long)sockbase, 622 (unsigned long)pci_conf_read(pc, sc->sc_tag, 623 PCI_SOCKBASE))); 624 #else 625 sc->sc_base_memt = sc->sc_memt; 626 #if !defined CBB_PCI_BASE 627 #define CBB_PCI_BASE 0x20000000 628 #endif 629 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 630 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 631 /* cannot allocate memory space */ 632 return; 633 } 634 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 635 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 636 sc->sc_dev.dv_xname, (unsigned long)sock_base, 637 (unsigned long)pci_conf_read(pc, 638 sc->sc_tag, PCI_SOCKBASE))); 639 sc->sc_sockbase = sockbase; 640 #endif 641 sc->sc_flags |= CBB_MEMHMAPPED; 642 } 643 644 /* bus bridge initialization */ 645 pccbb_chipinit(sc); 646 647 /* clear data structure for child device interrupt handlers */ 648 LIST_INIT(&sc->sc_pil); 649 sc->sc_pil_intr_enable = 1; 650 651 /* Map and establish the interrupt. */ 652 if (pci_intr_map(&sc->sc_pa, &ih)) { 653 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 654 return; 655 } 656 intrstr = pci_intr_string(pc, ih); 657 658 /* 659 * XXX pccbbintr should be called under the priority lower 660 * than any other hard interrputs. 661 */ 662 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 663 664 if (sc->sc_ih == NULL) { 665 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 666 if (intrstr != NULL) { 667 printf(" at %s", intrstr); 668 } 669 printf("\n"); 670 return; 671 } 672 673 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 674 powerhook_establish(pccbb_powerhook, sc); 675 676 { 677 u_int32_t sockstat; 678 679 sockstat = bus_space_read_4(sc->sc_base_memt, 680 sc->sc_base_memh, CB_SOCKET_STAT); 681 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 682 sc->sc_flags |= CBB_CARDEXIST; 683 } 684 } 685 686 /* 687 * attach cardbus 688 */ 689 { 690 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 691 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 692 693 /* initialize cbslot_attach */ 694 cba.cba_busname = "cardbus"; 695 cba.cba_iot = sc->sc_iot; 696 cba.cba_memt = sc->sc_memt; 697 cba.cba_dmat = sc->sc_dmat; 698 cba.cba_bus = (busreg >> 8) & 0x0ff; 699 cba.cba_cc = (void *)sc; 700 cba.cba_cf = &pccbb_funcs; 701 cba.cba_intrline = sc->sc_pa.pa_intrline; 702 703 #if rbus 704 cba.cba_rbus_iot = sc->sc_rbus_iot; 705 cba.cba_rbus_memt = sc->sc_rbus_memt; 706 #endif 707 708 cba.cba_cacheline = PCI_CACHELINE(bhlc); 709 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 710 711 if (bootverbose) { 712 printf("%s: cacheline 0x%x lattimer 0x%x\n", 713 sc->sc_dev.dv_xname, cba.cba_cacheline, 714 cba.cba_lattimer); 715 printf("%s: bhlc 0x%x lscp 0x%x\n", 716 sc->sc_dev.dv_xname, bhlc, busreg); 717 } 718 #if defined SHOW_REGS 719 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 720 sc->sc_base_memh); 721 #endif 722 } 723 724 pccbb_pcmcia_attach_setup(sc, &paa); 725 caa.caa_cb_attach = NULL; 726 if (cba.cba_bus == 0) 727 printf("%s: secondary bus number uninitialized; try PCIBIOS_BUS_FIXUP\n", sc->sc_dev.dv_xname); 728 else 729 caa.caa_cb_attach = &cba; 730 caa.caa_16_attach = &paa; 731 caa.caa_ph = &sc->sc_pcmcia_h; 732 733 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 734 DPRINTF(("pccbbattach: found cardslot\n")); 735 sc->sc_csc = csc; 736 } 737 738 return; 739 } 740 741 742 743 744 745 /* 746 * static void pccbb_chipinit(struct pccbb_softc *sc) 747 * 748 * This function initialize YENTA chip registers listed below: 749 * 1) PCI command reg, 750 * 2) PCI and CardBus latency timer, 751 * 3) route PCI interrupt, 752 * 4) close all memory and io windows. 753 * 5) turn off bus power. 754 * 6) card detect interrupt on. 755 * 7) clear interrupt 756 */ 757 static void 758 pccbb_chipinit(sc) 759 struct pccbb_softc *sc; 760 { 761 pci_chipset_tag_t pc = sc->sc_pc; 762 pcitag_t tag = sc->sc_tag; 763 bus_space_tag_t bmt = sc->sc_base_memt; 764 bus_space_handle_t bmh = sc->sc_base_memh; 765 pcireg_t reg; 766 767 /* 768 * Set PCI command reg. 769 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 770 */ 771 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 772 /* I believe it is harmless. */ 773 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 774 PCI_COMMAND_MASTER_ENABLE); 775 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 776 777 /* 778 * Set CardBus latency timer. 779 */ 780 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 781 if (PCI_CB_LATENCY(reg) < 0x20) { 782 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 783 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 784 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 785 } 786 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 787 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 788 789 /* 790 * Set PCI latency timer. 791 */ 792 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 793 if (PCI_LATTIMER(reg) < 0x10) { 794 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 795 reg |= (0x10 << PCI_LATTIMER_SHIFT); 796 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 797 } 798 DPRINTF(("PCI latency timer 0x%x (%x)\n", 799 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 800 801 802 /* Route functional interrupts to PCI. */ 803 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 804 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 805 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 806 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 807 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 808 809 switch (sc->sc_chipset) { 810 case CB_TI113X: 811 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 812 /* This bit is shared, but may read as 0 on some chips, so set 813 it explicitly on both functions. */ 814 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 815 /* CSC intr enable */ 816 reg |= PCI113X_CBCTRL_PCI_CSC; 817 /* functional intr prohibit | prohibit ISA routing */ 818 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 819 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 820 break; 821 822 case CB_TI12XX: 823 /* 824 * Some TI 12xx (and [14][45]xx) based pci cards 825 * sometimes have issues with the MFUNC register not 826 * being initialized due to a bad EEPROM on board. 827 * Laptops that this matters on have this register 828 * properly initialized. 829 * 830 * The TI125X parts have a different register. 831 */ 832 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 833 if (reg == 0) { 834 reg &= ~PCI12XX_MFUNC_PIN0; 835 reg |= PCI12XX_MFUNC_PIN0_INTA; 836 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 837 PCI12XX_SYSCTRL_INTRTIE) == 0) { 838 reg &= ~PCI12XX_MFUNC_PIN1; 839 reg |= PCI12XX_MFUNC_PIN1_INTB; 840 } 841 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 842 } 843 /* fallthrough */ 844 845 case CB_TI125X: 846 /* 847 * Disable zoom video. Some machines initialize this 848 * improperly and experience has shown that this helps 849 * prevent strange behavior. 850 */ 851 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 852 853 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 854 reg |= PCI12XX_SYSCTRL_VCCPROT; 855 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 856 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 857 reg |= PCI12XX_CBCTRL_CSC; 858 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 859 break; 860 861 case CB_TOPIC95B: 862 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 863 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 864 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 865 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 866 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 867 sc->sc_dev.dv_xname, reg)); 868 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 869 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 870 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 871 DPRINTF(("0x%x\n", reg)); 872 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 873 break; 874 875 case CB_TOPIC97: 876 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 877 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 878 sc->sc_dev.dv_xname, reg)); 879 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 880 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 881 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 882 reg |= TOPIC97_SLOT_CTRL_PCIINT; 883 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 884 DPRINTF(("0x%x\n", reg)); 885 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 886 /* make sure to assert LV card support bits */ 887 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 888 0x800 + 0x3e, 889 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 890 0x800 + 0x3e) | 0x03); 891 break; 892 } 893 894 /* Close all memory and I/O windows. */ 895 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 896 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 897 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 898 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 899 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 900 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 901 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 902 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 903 904 /* reset 16-bit pcmcia bus */ 905 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 906 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 907 908 /* turn off power */ 909 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 910 911 /* CSC Interrupt: Card detect interrupt on */ 912 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 913 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; /* Card detect intr is turned on. */ 914 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 915 /* reset interrupt */ 916 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 917 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 918 } 919 920 921 922 923 /* 924 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 925 * struct pcmciabus_attach_args *paa) 926 * 927 * This function attaches 16-bit PCcard bus. 928 */ 929 STATIC void 930 pccbb_pcmcia_attach_setup(sc, paa) 931 struct pccbb_softc *sc; 932 struct pcmciabus_attach_args *paa; 933 { 934 struct pcic_handle *ph = &sc->sc_pcmcia_h; 935 #if rbus 936 rbus_tag_t rb; 937 #endif 938 939 /* initialize pcmcia part in pccbb_softc */ 940 ph->ph_parent = (struct device *)sc; 941 ph->sock = sc->sc_function; 942 ph->flags = 0; 943 ph->shutdown = 0; 944 ph->ih_irq = sc->sc_pa.pa_intrline; 945 ph->ph_bus_t = sc->sc_base_memt; 946 ph->ph_bus_h = sc->sc_base_memh; 947 ph->ph_read = pccbb_pcmcia_read; 948 ph->ph_write = pccbb_pcmcia_write; 949 sc->sc_pct = &pccbb_pcmcia_funcs; 950 951 /* 952 * We need to do a few things here: 953 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 954 * setting the IRQ numbers to 0. 955 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 956 * routing of CSC interrupts (e.g. card removal) to PCI while in 957 * PCMCIA mode. We just leave this set all the time. 958 * 3) Enable card insertion/removal interrupts in case the chip also 959 * needs that while in PCMCIA mode. 960 * 4) Clear any pending CSC interrupt. 961 */ 962 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 963 if (sc->sc_chipset == CB_TI113X) { 964 Pcic_write(ph, PCIC_CSC_INTR, 0); 965 } else { 966 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 967 Pcic_read(ph, PCIC_CSC); 968 } 969 970 /* initialize pcmcia bus attachment */ 971 paa->paa_busname = "pcmcia"; 972 paa->pct = sc->sc_pct; 973 paa->pch = ph; 974 paa->iobase = 0; /* I don't use them */ 975 paa->iosize = 0; 976 #if rbus 977 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 978 paa->iobase = rb->rb_start + rb->rb_offset; 979 paa->iosize = rb->rb_end - rb->rb_start; 980 #endif 981 982 return; 983 } 984 985 #if 0 986 STATIC void 987 pccbb_pcmcia_attach_card(ph) 988 struct pcic_handle *ph; 989 { 990 if (ph->flags & PCIC_FLAG_CARDP) { 991 panic("pccbb_pcmcia_attach_card: already attached"); 992 } 993 994 /* call the MI attach function */ 995 pcmcia_card_attach(ph->pcmcia); 996 997 ph->flags |= PCIC_FLAG_CARDP; 998 } 999 1000 STATIC void 1001 pccbb_pcmcia_detach_card(ph, flags) 1002 struct pcic_handle *ph; 1003 int flags; 1004 { 1005 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1006 panic("pccbb_pcmcia_detach_card: already detached"); 1007 } 1008 1009 ph->flags &= ~PCIC_FLAG_CARDP; 1010 1011 /* call the MI detach function */ 1012 pcmcia_card_detach(ph->pcmcia, flags); 1013 } 1014 #endif 1015 1016 /* 1017 * int pccbbintr(arg) 1018 * void *arg; 1019 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1020 * itself. 1021 */ 1022 int 1023 pccbbintr(arg) 1024 void *arg; 1025 { 1026 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1027 u_int32_t sockevent, sockstate; 1028 bus_space_tag_t memt = sc->sc_base_memt; 1029 bus_space_handle_t memh = sc->sc_base_memh; 1030 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1031 1032 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1033 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1034 Pcic_read(ph, PCIC_CSC); 1035 1036 if (sockevent == 0) { 1037 /* This intr is not for me: it may be for my child devices. */ 1038 if (sc->sc_pil_intr_enable) { 1039 return pccbbintr_function(sc); 1040 } else { 1041 return 0; 1042 } 1043 } 1044 1045 if (sockevent & CB_SOCKET_EVENT_CD) { 1046 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1047 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1048 /* A card should be removed. */ 1049 if (sc->sc_flags & CBB_CARDEXIST) { 1050 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1051 sockevent)); 1052 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1053 sc->sc_flags &= ~CBB_CARDEXIST; 1054 if (sc->sc_csc->sc_status & 1055 CARDSLOT_STATUS_CARD_16) { 1056 #if 0 1057 struct pcic_handle *ph = 1058 &sc->sc_pcmcia_h; 1059 1060 pcmcia_card_deactivate(ph->pcmcia); 1061 pccbb_pcmcia_socket_disable(ph); 1062 pccbb_pcmcia_detach_card(ph, 1063 DETACH_FORCE); 1064 #endif 1065 cardslot_event_throw(sc->sc_csc, 1066 CARDSLOT_EVENT_REMOVAL_16); 1067 } else if (sc->sc_csc->sc_status & 1068 CARDSLOT_STATUS_CARD_CB) { 1069 /* Cardbus intr removed */ 1070 cardslot_event_throw(sc->sc_csc, 1071 CARDSLOT_EVENT_REMOVAL_CB); 1072 } 1073 } else if (sc->sc_flags & CBB_INSERTING) { 1074 sc->sc_flags &= ~CBB_INSERTING; 1075 callout_stop(&sc->sc_insert_ch); 1076 } 1077 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1078 /* 1079 * The pccbbintr may called from powerdown hook when 1080 * the system resumed, to detect the card 1081 * insertion/removal during suspension. 1082 */ 1083 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1084 if (sc->sc_flags & CBB_INSERTING) { 1085 callout_stop(&sc->sc_insert_ch); 1086 } 1087 callout_reset(&sc->sc_insert_ch, hz / 5, 1088 pci113x_insert, sc); 1089 sc->sc_flags |= CBB_INSERTING; 1090 } 1091 } 1092 1093 if (sockevent & CB_SOCKET_EVENT_POWER) { 1094 sc->sc_pwrcycle++; 1095 wakeup(&sc->sc_pwrcycle); 1096 } 1097 1098 return (1); 1099 } 1100 1101 /* 1102 * static int pccbbintr_function(struct pccbb_softc *sc) 1103 * 1104 * This function calls each interrupt handler registered at the 1105 * bridge. The interrupt handlers are called in registered order. 1106 */ 1107 static int 1108 pccbbintr_function(sc) 1109 struct pccbb_softc *sc; 1110 { 1111 int retval = 0, val; 1112 struct pccbb_intrhand_list *pil; 1113 int s, splchanged; 1114 1115 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1116 pil = LIST_NEXT(pil, pil_next)) { 1117 /* 1118 * XXX priority change. gross. I use if-else 1119 * sentense instead of switch-case sentense because of 1120 * avoiding duplicate case value error. More than one 1121 * IPL_XXX use same value. It depends on 1122 * implimentation. 1123 */ 1124 splchanged = 1; 1125 if (pil->pil_level == IPL_SERIAL) { 1126 s = splserial(); 1127 } else if (pil->pil_level == IPL_HIGH) { 1128 s = splhigh(); 1129 } else if (pil->pil_level == IPL_CLOCK) { 1130 s = splclock(); 1131 } else if (pil->pil_level == IPL_AUDIO) { 1132 s = splaudio(); 1133 } else if (pil->pil_level == IPL_VM) { 1134 s = splvm(); 1135 } else if (pil->pil_level == IPL_TTY) { 1136 s = spltty(); 1137 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1138 s = splsoftserial(); 1139 } else if (pil->pil_level == IPL_NET) { 1140 s = splnet(); 1141 } else { 1142 s = 0; /* XXX: gcc */ 1143 splchanged = 0; 1144 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1145 } 1146 1147 val = (*pil->pil_func)(pil->pil_arg); 1148 1149 if (splchanged != 0) { 1150 splx(s); 1151 } 1152 1153 retval = retval == 1 ? 1 : 1154 retval == 0 ? val : val != 0 ? val : retval; 1155 } 1156 1157 return retval; 1158 } 1159 1160 static void 1161 pci113x_insert(arg) 1162 void *arg; 1163 { 1164 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1165 u_int32_t sockevent, sockstate; 1166 1167 if (!(sc->sc_flags & CBB_INSERTING)) { 1168 /* We add a card only under inserting state. */ 1169 return; 1170 } 1171 sc->sc_flags &= ~CBB_INSERTING; 1172 1173 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1174 CB_SOCKET_EVENT); 1175 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1176 CB_SOCKET_STAT); 1177 1178 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1179 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1180 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1181 sc->sc_flags |= CBB_CARDEXIST; 1182 /* call pccard interrupt handler here */ 1183 if (sockstate & CB_SOCKET_STAT_16BIT) { 1184 /* 16-bit card found */ 1185 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1186 cardslot_event_throw(sc->sc_csc, 1187 CARDSLOT_EVENT_INSERTION_16); 1188 } else if (sockstate & CB_SOCKET_STAT_CB) { 1189 /* cardbus card found */ 1190 /* cardbus_attach_card(sc->sc_csc); */ 1191 cardslot_event_throw(sc->sc_csc, 1192 CARDSLOT_EVENT_INSERTION_CB); 1193 } else { 1194 /* who are you? */ 1195 } 1196 } else { 1197 callout_reset(&sc->sc_insert_ch, hz / 10, 1198 pci113x_insert, sc); 1199 } 1200 } 1201 1202 #define PCCBB_PCMCIA_OFFSET 0x800 1203 static u_int8_t 1204 pccbb_pcmcia_read(ph, reg) 1205 struct pcic_handle *ph; 1206 int reg; 1207 { 1208 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1209 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1210 1211 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1212 PCCBB_PCMCIA_OFFSET + reg); 1213 } 1214 1215 static void 1216 pccbb_pcmcia_write(ph, reg, val) 1217 struct pcic_handle *ph; 1218 int reg; 1219 u_int8_t val; 1220 { 1221 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1222 val); 1223 1224 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1225 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1226 } 1227 1228 /* 1229 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1230 */ 1231 STATIC int 1232 pccbb_ctrl(ct, command) 1233 cardbus_chipset_tag_t ct; 1234 int command; 1235 { 1236 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1237 1238 switch (command) { 1239 case CARDBUS_CD: 1240 if (2 == pccbb_detect_card(sc)) { 1241 int retval = 0; 1242 int status = cb_detect_voltage(sc); 1243 if (PCCARD_VCC_5V & status) { 1244 retval |= CARDBUS_5V_CARD; 1245 } 1246 if (PCCARD_VCC_3V & status) { 1247 retval |= CARDBUS_3V_CARD; 1248 } 1249 if (PCCARD_VCC_XV & status) { 1250 retval |= CARDBUS_XV_CARD; 1251 } 1252 if (PCCARD_VCC_YV & status) { 1253 retval |= CARDBUS_YV_CARD; 1254 } 1255 return retval; 1256 } else { 1257 return 0; 1258 } 1259 case CARDBUS_RESET: 1260 return cb_reset(sc); 1261 case CARDBUS_IO_ENABLE: /* fallthrough */ 1262 case CARDBUS_IO_DISABLE: /* fallthrough */ 1263 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1264 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1265 case CARDBUS_BM_ENABLE: /* fallthrough */ 1266 case CARDBUS_BM_DISABLE: /* fallthrough */ 1267 /* XXX: I think we don't need to call this function below. */ 1268 return pccbb_cardenable(sc, command); 1269 } 1270 1271 return 0; 1272 } 1273 1274 /* 1275 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1276 * This function returns true when it succeeds and returns false when 1277 * it fails. 1278 */ 1279 STATIC int 1280 pccbb_power(ct, command) 1281 cardbus_chipset_tag_t ct; 1282 int command; 1283 { 1284 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1285 u_int32_t status, sock_ctrl, reg_ctrl; 1286 bus_space_tag_t memt = sc->sc_base_memt; 1287 bus_space_handle_t memh = sc->sc_base_memh; 1288 int on = 0, pwrcycle; 1289 1290 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1291 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1292 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1293 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1294 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1295 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1296 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1297 "UNKNOWN", 1298 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1299 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1300 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1301 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1302 "UNKNOWN", command)); 1303 1304 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1305 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1306 1307 switch (command & CARDBUS_VCCMASK) { 1308 case CARDBUS_VCC_UC: 1309 break; 1310 case CARDBUS_VCC_5V: 1311 on++; 1312 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1313 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1314 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1315 } else { 1316 printf("%s: BAD voltage request: no 5 V card\n", 1317 sc->sc_dev.dv_xname); 1318 return 0; 1319 } 1320 break; 1321 case CARDBUS_VCC_3V: 1322 on++; 1323 if (CB_SOCKET_STAT_3VCARD & status) { 1324 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1325 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1326 } else { 1327 printf("%s: BAD voltage request: no 3.3 V card\n", 1328 sc->sc_dev.dv_xname); 1329 return 0; 1330 } 1331 break; 1332 case CARDBUS_VCC_0V: 1333 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1334 break; 1335 default: 1336 return 0; /* power NEVER changed */ 1337 } 1338 1339 switch (command & CARDBUS_VPPMASK) { 1340 case CARDBUS_VPP_UC: 1341 break; 1342 case CARDBUS_VPP_0V: 1343 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1344 break; 1345 case CARDBUS_VPP_VCC: 1346 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1347 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1348 break; 1349 case CARDBUS_VPP_12V: 1350 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1351 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1352 break; 1353 } 1354 1355 pwrcycle = sc->sc_pwrcycle; 1356 1357 #if 0 1358 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1359 #endif 1360 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1361 1362 if (on) { 1363 int s; 1364 struct timeval before, after, diff; 1365 1366 microtime(&before); 1367 s = splbio(); 1368 while (pwrcycle == sc->sc_pwrcycle) 1369 tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 0); 1370 splx(s); 1371 microtime(&after); 1372 timersub(&after, &before, &diff); 1373 printf("%s: wait took %ld.%06lds\n", sc->sc_dev.dv_xname, 1374 diff.tv_sec, diff.tv_usec); 1375 } 1376 1377 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1378 1379 if (on) { 1380 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1381 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1382 } 1383 1384 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1385 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1386 sc->sc_dev.dv_xname, sock_ctrl, status); 1387 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1388 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1389 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1390 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1391 status &= ~CB_SOCKET_STAT_BADVCC; 1392 bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1393 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1394 CB_SOCKET_STAT)); 1395 return 0; 1396 } 1397 1398 if (sc->sc_chipset == CB_TOPIC97) { 1399 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1400 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1401 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1402 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1403 else 1404 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1405 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1406 } 1407 1408 return 1; /* power changed correctly */ 1409 } 1410 1411 #if defined CB_PCMCIA_POLL 1412 struct cb_poll_str { 1413 void *arg; 1414 int (*func)(void *); 1415 int level; 1416 pccard_chipset_tag_t ct; 1417 int count; 1418 struct callout poll_ch; 1419 }; 1420 1421 static struct cb_poll_str cb_poll[10]; 1422 static int cb_poll_n = 0; 1423 1424 static void cb_pcmcia_poll(void *arg); 1425 1426 static void 1427 cb_pcmcia_poll(arg) 1428 void *arg; 1429 { 1430 struct cb_poll_str *poll = arg; 1431 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1432 struct pccbb_softc *sc = psc->cpc_parent; 1433 int s; 1434 u_int32_t spsr; /* socket present-state reg */ 1435 1436 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1437 switch (poll->level) { 1438 case IPL_NET: 1439 s = splnet(); 1440 break; 1441 case IPL_BIO: 1442 s = splbio(); 1443 break; 1444 case IPL_TTY: /* fallthrough */ 1445 default: 1446 s = spltty(); 1447 break; 1448 } 1449 1450 spsr = 1451 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1452 CB_SOCKET_STAT); 1453 1454 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1455 if (!(spsr & 0x40)) { /* CINT low */ 1456 #else 1457 if (1) { 1458 #endif 1459 if ((*poll->func) (poll->arg) == 1) { 1460 ++poll->count; 1461 printf("intr: reported from poller, 0x%x\n", spsr); 1462 #if defined LEVEL2 1463 } else { 1464 printf("intr: miss! 0x%x\n", spsr); 1465 #endif 1466 } 1467 } 1468 splx(s); 1469 } 1470 #endif /* defined CB_PCMCIA_POLL */ 1471 1472 /* 1473 * static int pccbb_detect_card(struct pccbb_softc *sc) 1474 * return value: 0 if no card exists. 1475 * 1 if 16-bit card exists. 1476 * 2 if cardbus card exists. 1477 */ 1478 static int 1479 pccbb_detect_card(sc) 1480 struct pccbb_softc *sc; 1481 { 1482 bus_space_handle_t base_memh = sc->sc_base_memh; 1483 bus_space_tag_t base_memt = sc->sc_base_memt; 1484 u_int32_t sockstat = 1485 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1486 int retval = 0; 1487 1488 /* CD1 and CD2 asserted */ 1489 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1490 /* card must be present */ 1491 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1492 /* NOTACARD DEASSERTED */ 1493 if (CB_SOCKET_STAT_CB & sockstat) { 1494 /* CardBus mode */ 1495 retval = 2; 1496 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1497 /* 16-bit mode */ 1498 retval = 1; 1499 } 1500 } 1501 } 1502 return retval; 1503 } 1504 1505 /* 1506 * STATIC int cb_reset(struct pccbb_softc *sc) 1507 * This function resets CardBus card. 1508 */ 1509 STATIC int 1510 cb_reset(sc) 1511 struct pccbb_softc *sc; 1512 { 1513 /* 1514 * Reset Assert at least 20 ms 1515 * Some machines request longer duration. 1516 */ 1517 int reset_duration = 1518 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1519 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1520 1521 /* Reset bit Assert (bit 6 at 0x3E) */ 1522 bcr |= CB_BCR_RESET_ENABLE; 1523 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1524 DELAY_MS(reset_duration, sc); 1525 1526 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1527 /* Reset bit Deassert (bit 6 at 0x3E) */ 1528 bcr &= ~CB_BCR_RESET_ENABLE; 1529 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1530 DELAY_MS(reset_duration, sc); 1531 } 1532 /* No card found on the slot. Keep Reset. */ 1533 return 1; 1534 } 1535 1536 /* 1537 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1538 * This function detect card Voltage. 1539 */ 1540 STATIC int 1541 cb_detect_voltage(sc) 1542 struct pccbb_softc *sc; 1543 { 1544 u_int32_t psr; /* socket present-state reg */ 1545 bus_space_tag_t iot = sc->sc_base_memt; 1546 bus_space_handle_t ioh = sc->sc_base_memh; 1547 int vol = PCCARD_VCC_UKN; /* set 0 */ 1548 1549 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1550 1551 if (0x400u & psr) { 1552 vol |= PCCARD_VCC_5V; 1553 } 1554 if (0x800u & psr) { 1555 vol |= PCCARD_VCC_3V; 1556 } 1557 1558 return vol; 1559 } 1560 1561 STATIC int 1562 cbbprint(aux, pcic) 1563 void *aux; 1564 const char *pcic; 1565 { 1566 /* 1567 struct cbslot_attach_args *cba = aux; 1568 1569 if (cba->cba_slot >= 0) { 1570 aprint_normal(" slot %d", cba->cba_slot); 1571 } 1572 */ 1573 return UNCONF; 1574 } 1575 1576 /* 1577 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1578 * This function enables and disables the card 1579 */ 1580 STATIC int 1581 pccbb_cardenable(sc, function) 1582 struct pccbb_softc *sc; 1583 int function; 1584 { 1585 u_int32_t command = 1586 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1587 1588 DPRINTF(("pccbb_cardenable:")); 1589 switch (function) { 1590 case CARDBUS_IO_ENABLE: 1591 command |= PCI_COMMAND_IO_ENABLE; 1592 break; 1593 case CARDBUS_IO_DISABLE: 1594 command &= ~PCI_COMMAND_IO_ENABLE; 1595 break; 1596 case CARDBUS_MEM_ENABLE: 1597 command |= PCI_COMMAND_MEM_ENABLE; 1598 break; 1599 case CARDBUS_MEM_DISABLE: 1600 command &= ~PCI_COMMAND_MEM_ENABLE; 1601 break; 1602 case CARDBUS_BM_ENABLE: 1603 command |= PCI_COMMAND_MASTER_ENABLE; 1604 break; 1605 case CARDBUS_BM_DISABLE: 1606 command &= ~PCI_COMMAND_MASTER_ENABLE; 1607 break; 1608 default: 1609 return 0; 1610 } 1611 1612 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1613 DPRINTF((" command reg 0x%x\n", command)); 1614 return 1; 1615 } 1616 1617 #if !rbus 1618 /* 1619 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1620 */ 1621 static int 1622 pccbb_io_open(ct, win, start, end) 1623 cardbus_chipset_tag_t ct; 1624 int win; 1625 u_int32_t start, end; 1626 { 1627 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1628 int basereg; 1629 int limitreg; 1630 1631 if ((win < 0) || (win > 2)) { 1632 #if defined DIAGNOSTIC 1633 printf("cardbus_io_open: window out of range %d\n", win); 1634 #endif 1635 return 0; 1636 } 1637 1638 basereg = win * 8 + 0x2c; 1639 limitreg = win * 8 + 0x30; 1640 1641 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1642 start, basereg, end, limitreg)); 1643 1644 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1645 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1646 return 1; 1647 } 1648 1649 /* 1650 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1651 */ 1652 static int 1653 pccbb_io_close(ct, win) 1654 cardbus_chipset_tag_t ct; 1655 int win; 1656 { 1657 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1658 int basereg; 1659 int limitreg; 1660 1661 if ((win < 0) || (win > 2)) { 1662 #if defined DIAGNOSTIC 1663 printf("cardbus_io_close: window out of range %d\n", win); 1664 #endif 1665 return 0; 1666 } 1667 1668 basereg = win * 8 + 0x2c; 1669 limitreg = win * 8 + 0x30; 1670 1671 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1672 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1673 return 1; 1674 } 1675 1676 /* 1677 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1678 */ 1679 static int 1680 pccbb_mem_open(ct, win, start, end) 1681 cardbus_chipset_tag_t ct; 1682 int win; 1683 u_int32_t start, end; 1684 { 1685 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1686 int basereg; 1687 int limitreg; 1688 1689 if ((win < 0) || (win > 2)) { 1690 #if defined DIAGNOSTIC 1691 printf("cardbus_mem_open: window out of range %d\n", win); 1692 #endif 1693 return 0; 1694 } 1695 1696 basereg = win * 8 + 0x1c; 1697 limitreg = win * 8 + 0x20; 1698 1699 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1700 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1701 return 1; 1702 } 1703 1704 /* 1705 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1706 */ 1707 static int 1708 pccbb_mem_close(ct, win) 1709 cardbus_chipset_tag_t ct; 1710 int win; 1711 { 1712 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1713 int basereg; 1714 int limitreg; 1715 1716 if ((win < 0) || (win > 2)) { 1717 #if defined DIAGNOSTIC 1718 printf("cardbus_mem_close: window out of range %d\n", win); 1719 #endif 1720 return 0; 1721 } 1722 1723 basereg = win * 8 + 0x1c; 1724 limitreg = win * 8 + 0x20; 1725 1726 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1727 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1728 return 1; 1729 } 1730 #endif 1731 1732 /* 1733 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1734 * int irq, 1735 * int level, 1736 * int (* func)(void *), 1737 * void *arg) 1738 * 1739 * This function registers an interrupt handler at the bridge, in 1740 * order not to call the interrupt handlers of child devices when 1741 * a card-deletion interrupt occurs. 1742 * 1743 * The arguments irq and level are not used. 1744 */ 1745 static void * 1746 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1747 cardbus_chipset_tag_t ct; 1748 int irq, level; 1749 int (*func)(void *); 1750 void *arg; 1751 { 1752 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1753 1754 return pccbb_intr_establish(sc, irq, level, func, arg); 1755 } 1756 1757 1758 /* 1759 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1760 * void *ih) 1761 * 1762 * This function removes an interrupt handler pointed by ih. 1763 */ 1764 static void 1765 pccbb_cb_intr_disestablish(ct, ih) 1766 cardbus_chipset_tag_t ct; 1767 void *ih; 1768 { 1769 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1770 1771 pccbb_intr_disestablish(sc, ih); 1772 } 1773 1774 1775 void 1776 pccbb_intr_route(sc) 1777 struct pccbb_softc *sc; 1778 { 1779 pcireg_t reg; 1780 1781 /* initialize bridge intr routing */ 1782 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1783 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1784 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1785 1786 switch (sc->sc_chipset) { 1787 case CB_TI113X: 1788 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1789 /* functional intr enabled */ 1790 reg |= PCI113X_CBCTRL_PCI_INTR; 1791 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1792 break; 1793 default: 1794 break; 1795 } 1796 } 1797 1798 /* 1799 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1800 * int irq, 1801 * int level, 1802 * int (* func)(void *), 1803 * void *arg) 1804 * 1805 * This function registers an interrupt handler at the bridge, in 1806 * order not to call the interrupt handlers of child devices when 1807 * a card-deletion interrupt occurs. 1808 * 1809 * The arguments irq is not used because pccbb selects intr vector. 1810 */ 1811 static void * 1812 pccbb_intr_establish(sc, irq, level, func, arg) 1813 struct pccbb_softc *sc; 1814 int irq, level; 1815 int (*func)(void *); 1816 void *arg; 1817 { 1818 struct pccbb_intrhand_list *pil, *newpil; 1819 1820 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1821 1822 if (LIST_EMPTY(&sc->sc_pil)) { 1823 pccbb_intr_route(sc); 1824 } 1825 1826 /* 1827 * Allocate a room for interrupt handler structure. 1828 */ 1829 if (NULL == (newpil = 1830 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1831 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1832 return NULL; 1833 } 1834 1835 newpil->pil_func = func; 1836 newpil->pil_arg = arg; 1837 newpil->pil_level = level; 1838 1839 if (LIST_EMPTY(&sc->sc_pil)) { 1840 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1841 } else { 1842 for (pil = LIST_FIRST(&sc->sc_pil); 1843 LIST_NEXT(pil, pil_next) != NULL; 1844 pil = LIST_NEXT(pil, pil_next)); 1845 LIST_INSERT_AFTER(pil, newpil, pil_next); 1846 } 1847 1848 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1849 LIST_FIRST(&sc->sc_pil))); 1850 1851 return newpil; 1852 } 1853 1854 /* 1855 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1856 * void *ih) 1857 * 1858 * This function removes an interrupt handler pointed by ih. ih 1859 * should be the value returned by cardbus_intr_establish() or 1860 * NULL. 1861 * 1862 * When ih is NULL, this function will do nothing. 1863 */ 1864 static void 1865 pccbb_intr_disestablish(sc, ih) 1866 struct pccbb_softc *sc; 1867 void *ih; 1868 { 1869 struct pccbb_intrhand_list *pil; 1870 pcireg_t reg; 1871 1872 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1873 LIST_FIRST(&sc->sc_pil))); 1874 1875 if (ih == NULL) { 1876 /* intr handler is not set */ 1877 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1878 return; 1879 } 1880 1881 #ifdef DIAGNOSTIC 1882 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1883 pil = LIST_NEXT(pil, pil_next)) { 1884 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1885 if (pil == ih) { 1886 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1887 break; 1888 } 1889 } 1890 if (pil == NULL) { 1891 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1892 sc->sc_dev.dv_xname, ih); 1893 } 1894 #endif 1895 1896 pil = (struct pccbb_intrhand_list *)ih; 1897 LIST_REMOVE(pil, pil_next); 1898 free(pil, M_DEVBUF); 1899 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1900 1901 if (LIST_EMPTY(&sc->sc_pil)) { 1902 /* No interrupt handlers */ 1903 1904 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1905 1906 /* stop routing PCI intr */ 1907 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1908 reg |= CB_BCR_INTR_IREQ_ENABLE; 1909 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1910 1911 switch (sc->sc_chipset) { 1912 case CB_TI113X: 1913 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1914 /* functional intr disabled */ 1915 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1916 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1917 break; 1918 default: 1919 break; 1920 } 1921 } 1922 } 1923 1924 #if defined SHOW_REGS 1925 static void 1926 cb_show_regs(pc, tag, memt, memh) 1927 pci_chipset_tag_t pc; 1928 pcitag_t tag; 1929 bus_space_tag_t memt; 1930 bus_space_handle_t memh; 1931 { 1932 int i; 1933 printf("PCI config regs:"); 1934 for (i = 0; i < 0x50; i += 4) { 1935 if (i % 16 == 0) { 1936 printf("\n 0x%02x:", i); 1937 } 1938 printf(" %08x", pci_conf_read(pc, tag, i)); 1939 } 1940 for (i = 0x80; i < 0xb0; i += 4) { 1941 if (i % 16 == 0) { 1942 printf("\n 0x%02x:", i); 1943 } 1944 printf(" %08x", pci_conf_read(pc, tag, i)); 1945 } 1946 1947 if (memh == 0) { 1948 printf("\n"); 1949 return; 1950 } 1951 1952 printf("\nsocket regs:"); 1953 for (i = 0; i <= 0x10; i += 0x04) { 1954 printf(" %08x", bus_space_read_4(memt, memh, i)); 1955 } 1956 printf("\nExCA regs:"); 1957 for (i = 0; i < 0x08; ++i) { 1958 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1959 } 1960 printf("\n"); 1961 return; 1962 } 1963 #endif 1964 1965 /* 1966 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1967 * int busno, int devno, int function) 1968 * This is the function to make a tag to access config space of 1969 * a CardBus Card. It works same as pci_conf_read. 1970 */ 1971 static cardbustag_t 1972 pccbb_make_tag(cc, busno, devno, function) 1973 cardbus_chipset_tag_t cc; 1974 int busno, devno, function; 1975 { 1976 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1977 1978 return pci_make_tag(sc->sc_pc, busno, devno, function); 1979 } 1980 1981 static void 1982 pccbb_free_tag(cc, tag) 1983 cardbus_chipset_tag_t cc; 1984 cardbustag_t tag; 1985 { 1986 } 1987 1988 /* 1989 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1990 * cardbustag_t tag, int offset) 1991 * This is the function to read the config space of a CardBus Card. 1992 * It works same as pci_conf_read. 1993 */ 1994 static cardbusreg_t 1995 pccbb_conf_read(cc, tag, offset) 1996 cardbus_chipset_tag_t cc; 1997 cardbustag_t tag; 1998 int offset; /* register offset */ 1999 { 2000 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2001 2002 return pci_conf_read(sc->sc_pc, tag, offset); 2003 } 2004 2005 /* 2006 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 2007 * int offs, cardbusreg_t val) 2008 * This is the function to write the config space of a CardBus Card. 2009 * It works same as pci_conf_write. 2010 */ 2011 static void 2012 pccbb_conf_write(cc, tag, reg, val) 2013 cardbus_chipset_tag_t cc; 2014 cardbustag_t tag; 2015 int reg; /* register offset */ 2016 cardbusreg_t val; 2017 { 2018 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2019 2020 pci_conf_write(sc->sc_pc, tag, reg, val); 2021 } 2022 2023 #if 0 2024 STATIC int 2025 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2026 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2027 int speed, int flags, 2028 bus_space_handle_t * iohp) 2029 #endif 2030 /* 2031 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2032 * bus_addr_t start, bus_size_t size, 2033 * bus_size_t align, 2034 * struct pcmcia_io_handle *pcihp 2035 * 2036 * This function only allocates I/O region for pccard. This function 2037 * never maps the allocated region to pccard I/O area. 2038 * 2039 * XXX: The interface of this function is not very good, I believe. 2040 */ 2041 STATIC int 2042 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2043 pcmcia_chipset_handle_t pch; 2044 bus_addr_t start; /* start address */ 2045 bus_size_t size; 2046 bus_size_t align; 2047 struct pcmcia_io_handle *pcihp; 2048 { 2049 struct pcic_handle *ph = (struct pcic_handle *)pch; 2050 bus_addr_t ioaddr; 2051 int flags = 0; 2052 bus_space_tag_t iot; 2053 bus_space_handle_t ioh; 2054 bus_addr_t mask; 2055 #if rbus 2056 rbus_tag_t rb; 2057 #endif 2058 if (align == 0) { 2059 align = size; /* XXX: funny??? */ 2060 } 2061 2062 if (start != 0) { 2063 /* XXX: assume all card decode lower 10 bits by its hardware */ 2064 mask = 0x3ff; 2065 /* enforce to use only masked address */ 2066 start &= mask; 2067 } else { 2068 /* 2069 * calculate mask: 2070 * 1. get the most significant bit of size (call it msb). 2071 * 2. compare msb with the value of size. 2072 * 3. if size is larger, shift msb left once. 2073 * 4. obtain mask value to decrement msb. 2074 */ 2075 bus_size_t size_tmp = size; 2076 int shifts = 0; 2077 2078 mask = 1; 2079 while (size_tmp) { 2080 ++shifts; 2081 size_tmp >>= 1; 2082 } 2083 mask = (1 << shifts); 2084 if (mask < size) { 2085 mask <<= 1; 2086 } 2087 --mask; 2088 } 2089 2090 /* 2091 * Allocate some arbitrary I/O space. 2092 */ 2093 2094 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2095 2096 #if rbus 2097 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2098 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2099 return 1; 2100 } 2101 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2102 (u_long) ioaddr, (u_long) size)); 2103 #else 2104 if (start) { 2105 ioaddr = start; 2106 if (bus_space_map(iot, start, size, 0, &ioh)) { 2107 return 1; 2108 } 2109 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2110 (u_long) ioaddr, (u_long) size)); 2111 } else { 2112 flags |= PCMCIA_IO_ALLOCATED; 2113 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2114 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2115 size, align, 0, 0, &ioaddr, &ioh)) { 2116 /* No room be able to be get. */ 2117 return 1; 2118 } 2119 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2120 (u_long) ioaddr, (u_long) size)); 2121 } 2122 #endif 2123 2124 pcihp->iot = iot; 2125 pcihp->ioh = ioh; 2126 pcihp->addr = ioaddr; 2127 pcihp->size = size; 2128 pcihp->flags = flags; 2129 2130 return 0; 2131 } 2132 2133 /* 2134 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2135 * struct pcmcia_io_handle *pcihp) 2136 * 2137 * This function only frees I/O region for pccard. 2138 * 2139 * XXX: The interface of this function is not very good, I believe. 2140 */ 2141 void 2142 pccbb_pcmcia_io_free(pch, pcihp) 2143 pcmcia_chipset_handle_t pch; 2144 struct pcmcia_io_handle *pcihp; 2145 { 2146 #if !rbus 2147 bus_space_tag_t iot = pcihp->iot; 2148 #endif 2149 bus_space_handle_t ioh = pcihp->ioh; 2150 bus_size_t size = pcihp->size; 2151 2152 #if rbus 2153 struct pccbb_softc *sc = 2154 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2155 rbus_tag_t rb = sc->sc_rbus_iot; 2156 2157 rbus_space_free(rb, ioh, size, NULL); 2158 #else 2159 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2160 bus_space_free(iot, ioh, size); 2161 else 2162 bus_space_unmap(iot, ioh, size); 2163 #endif 2164 } 2165 2166 /* 2167 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2168 * bus_addr_t offset, bus_size_t size, 2169 * struct pcmcia_io_handle *pcihp, 2170 * int *windowp) 2171 * 2172 * This function maps the allocated I/O region to pccard. This function 2173 * never allocates any I/O region for pccard I/O area. I don't 2174 * understand why the original authors of pcmciabus separated alloc and 2175 * map. I believe the two must be unite. 2176 * 2177 * XXX: no wait timing control? 2178 */ 2179 int 2180 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2181 pcmcia_chipset_handle_t pch; 2182 int width; 2183 bus_addr_t offset; 2184 bus_size_t size; 2185 struct pcmcia_io_handle *pcihp; 2186 int *windowp; 2187 { 2188 struct pcic_handle *ph = (struct pcic_handle *)pch; 2189 bus_addr_t ioaddr = pcihp->addr + offset; 2190 int i, win; 2191 #if defined CBB_DEBUG 2192 static char *width_names[] = { "dynamic", "io8", "io16" }; 2193 #endif 2194 2195 /* Sanity check I/O handle. */ 2196 2197 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2198 panic("pccbb_pcmcia_io_map iot is bogus"); 2199 } 2200 2201 /* XXX Sanity check offset/size. */ 2202 2203 win = -1; 2204 for (i = 0; i < PCIC_IO_WINS; i++) { 2205 if ((ph->ioalloc & (1 << i)) == 0) { 2206 win = i; 2207 ph->ioalloc |= (1 << i); 2208 break; 2209 } 2210 } 2211 2212 if (win == -1) { 2213 return 1; 2214 } 2215 2216 *windowp = win; 2217 2218 /* XXX this is pretty gross */ 2219 2220 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2221 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2222 2223 /* XXX wtf is this doing here? */ 2224 2225 #if 0 2226 printf(" port 0x%lx", (u_long) ioaddr); 2227 if (size > 1) { 2228 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2229 } 2230 #endif 2231 2232 ph->io[win].addr = ioaddr; 2233 ph->io[win].size = size; 2234 ph->io[win].width = width; 2235 2236 /* actual dirty register-value changing in the function below. */ 2237 pccbb_pcmcia_do_io_map(ph, win); 2238 2239 return 0; 2240 } 2241 2242 /* 2243 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2244 * 2245 * This function changes register-value to map I/O region for pccard. 2246 */ 2247 static void 2248 pccbb_pcmcia_do_io_map(ph, win) 2249 struct pcic_handle *ph; 2250 int win; 2251 { 2252 static u_int8_t pcic_iowidth[3] = { 2253 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2254 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2255 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2256 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2257 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2258 }; 2259 2260 #define PCIC_SIA_START_LOW 0 2261 #define PCIC_SIA_START_HIGH 1 2262 #define PCIC_SIA_STOP_LOW 2 2263 #define PCIC_SIA_STOP_HIGH 3 2264 2265 int regbase_win = 0x8 + win * 0x04; 2266 u_int8_t ioctl, enable; 2267 2268 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2269 "width %d\n", win, (unsigned long)ph->io[win].addr, 2270 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2271 2272 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2273 ph->io[win].addr & 0xff); 2274 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2275 (ph->io[win].addr >> 8) & 0xff); 2276 2277 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2278 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2279 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2280 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2281 2282 ioctl = Pcic_read(ph, PCIC_IOCTL); 2283 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2284 switch (win) { 2285 case 0: 2286 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2287 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2288 PCIC_IOCTL_IO0_DATASIZE_MASK); 2289 ioctl |= pcic_iowidth[ph->io[win].width]; 2290 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2291 break; 2292 case 1: 2293 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2294 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2295 PCIC_IOCTL_IO1_DATASIZE_MASK); 2296 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2297 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2298 break; 2299 } 2300 Pcic_write(ph, PCIC_IOCTL, ioctl); 2301 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2302 #if defined CBB_DEBUG 2303 { 2304 u_int8_t start_low = 2305 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2306 u_int8_t start_high = 2307 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2308 u_int8_t stop_low = 2309 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2310 u_int8_t stop_high = 2311 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2312 printf 2313 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2314 start_low, start_high, stop_low, stop_high, ioctl, enable); 2315 } 2316 #endif 2317 } 2318 2319 /* 2320 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2321 * 2322 * This function unmaps I/O region. No return value. 2323 */ 2324 STATIC void 2325 pccbb_pcmcia_io_unmap(pch, win) 2326 pcmcia_chipset_handle_t pch; 2327 int win; 2328 { 2329 struct pcic_handle *ph = (struct pcic_handle *)pch; 2330 int reg; 2331 2332 if (win >= PCIC_IO_WINS || win < 0) { 2333 panic("pccbb_pcmcia_io_unmap: window out of range"); 2334 } 2335 2336 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2337 switch (win) { 2338 case 0: 2339 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2340 break; 2341 case 1: 2342 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2343 break; 2344 } 2345 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2346 2347 ph->ioalloc &= ~(1 << win); 2348 } 2349 2350 static int 2351 pccbb_pcmcia_wait_ready(ph) 2352 struct pcic_handle *ph; 2353 { 2354 u_int8_t stat; 2355 int i; 2356 2357 /* wait an initial 10ms for quick cards */ 2358 stat = Pcic_read(ph, PCIC_IF_STATUS); 2359 if (stat & PCIC_IF_STATUS_READY) 2360 return (0); 2361 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2362 for (i = 0; i < 50; i++) { 2363 stat = Pcic_read(ph, PCIC_IF_STATUS); 2364 if (stat & PCIC_IF_STATUS_READY) 2365 return (0); 2366 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2367 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2368 return (ENXIO); 2369 /* wait .1s (100ms) each iteration now */ 2370 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2371 } 2372 2373 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2374 return (EWOULDBLOCK); 2375 } 2376 2377 /* 2378 * Perform long (msec order) delay. 2379 */ 2380 static void 2381 pccbb_pcmcia_delay(ph, timo, wmesg) 2382 struct pcic_handle *ph; 2383 int timo; /* in ms. must not be zero */ 2384 const char *wmesg; 2385 { 2386 2387 #ifdef DIAGNOSTIC 2388 if (timo <= 0) 2389 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2390 if (!curlwp) 2391 panic("pccbb_pcmcia_delay: called in interrupt context"); 2392 #if 0 2393 if (!ph->event_thread) 2394 panic("pccbb_pcmcia_delay: no event thread"); 2395 #endif 2396 #endif 2397 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2398 wmesg, ph->event_thread, timo)); 2399 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2400 } 2401 2402 /* 2403 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2404 * 2405 * This function enables the card. All information is stored in 2406 * the first argument, pcmcia_chipset_handle_t. 2407 */ 2408 STATIC void 2409 pccbb_pcmcia_socket_enable(pch) 2410 pcmcia_chipset_handle_t pch; 2411 { 2412 struct pcic_handle *ph = (struct pcic_handle *)pch; 2413 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2414 pcireg_t spsr; 2415 int voltage; 2416 int win; 2417 u_int8_t power, intr; 2418 #ifdef DIAGNOSTIC 2419 int reg; 2420 #endif 2421 2422 /* this bit is mostly stolen from pcic_attach_card */ 2423 2424 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2425 2426 /* get card Vcc info */ 2427 spsr = 2428 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2429 CB_SOCKET_STAT); 2430 if (spsr & CB_SOCKET_STAT_5VCARD) { 2431 DPRINTF(("5V card\n")); 2432 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2433 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2434 DPRINTF(("3V card\n")); 2435 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2436 } else { 2437 printf("?V card, 0x%x\n", spsr); /* XXX */ 2438 return; 2439 } 2440 2441 /* disable interrupts; assert RESET */ 2442 intr = Pcic_read(ph, PCIC_INTR); 2443 intr &= PCIC_INTR_ENABLE; 2444 Pcic_write(ph, PCIC_INTR, intr); 2445 2446 /* zero out the address windows */ 2447 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2448 2449 /* power down the socket to reset it, clear the card reset pin */ 2450 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2451 2452 /* power off; assert output enable bit */ 2453 power = PCIC_PWRCTL_OE; 2454 Pcic_write(ph, PCIC_PWRCTL, power); 2455 2456 /* power up the socket */ 2457 if (pccbb_power(sc, voltage) == 0) 2458 return; 2459 2460 /* 2461 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2462 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2463 * RESET Width (Th (Hi-z RESET)) = 1ms 2464 * RESET Width (Tw (RESET)) = 10us 2465 */ 2466 pccbb_pcmcia_delay(ph, 1, "pccen1"); 2467 2468 /* negate RESET */ 2469 intr |= PCIC_INTR_RESET; 2470 Pcic_write(ph, PCIC_INTR, intr); 2471 2472 /* 2473 * RESET Setup Time (Tsu (RESET)) = 20ms 2474 */ 2475 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2476 2477 #ifdef DIAGNOSTIC 2478 reg = Pcic_read(ph, PCIC_IF_STATUS); 2479 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2480 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2481 #endif 2482 2483 /* wait for the chip to finish initializing */ 2484 if (pccbb_pcmcia_wait_ready(ph)) { 2485 /* XXX return a failure status?? */ 2486 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2487 Pcic_write(ph, PCIC_PWRCTL, 0); 2488 return; 2489 } 2490 2491 /* reinstall all the memory and io mappings */ 2492 for (win = 0; win < PCIC_MEM_WINS; ++win) 2493 if (ph->memalloc & (1 << win)) 2494 pccbb_pcmcia_do_mem_map(ph, win); 2495 for (win = 0; win < PCIC_IO_WINS; ++win) 2496 if (ph->ioalloc & (1 << win)) 2497 pccbb_pcmcia_do_io_map(ph, win); 2498 } 2499 2500 /* 2501 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2502 * 2503 * This function disables the card. All information is stored in 2504 * the first argument, pcmcia_chipset_handle_t. 2505 */ 2506 STATIC void 2507 pccbb_pcmcia_socket_disable(pch) 2508 pcmcia_chipset_handle_t pch; 2509 { 2510 struct pcic_handle *ph = (struct pcic_handle *)pch; 2511 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2512 u_int8_t intr; 2513 2514 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2515 2516 /* disable interrupts; assert RESET */ 2517 intr = Pcic_read(ph, PCIC_INTR); 2518 intr &= PCIC_INTR_ENABLE; 2519 Pcic_write(ph, PCIC_INTR, intr); 2520 2521 /* zero out the address windows */ 2522 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2523 2524 /* power down the socket to reset it, clear the card reset pin */ 2525 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2526 2527 /* disable socket: negate output enable bit and power off */ 2528 Pcic_write(ph, PCIC_PWRCTL, 0); 2529 2530 /* 2531 * Vcc Falling Time (Tpf) = 300ms 2532 */ 2533 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2534 } 2535 2536 STATIC void 2537 pccbb_pcmcia_socket_settype(pch, type) 2538 pcmcia_chipset_handle_t pch; 2539 int type; 2540 { 2541 struct pcic_handle *ph = (struct pcic_handle *)pch; 2542 u_int8_t intr; 2543 2544 /* set the card type */ 2545 2546 intr = Pcic_read(ph, PCIC_INTR); 2547 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2548 if (type == PCMCIA_IFTYPE_IO) 2549 intr |= PCIC_INTR_CARDTYPE_IO; 2550 else 2551 intr |= PCIC_INTR_CARDTYPE_MEM; 2552 Pcic_write(ph, PCIC_INTR, intr); 2553 2554 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2555 ph->ph_parent->dv_xname, ph->sock, 2556 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2557 } 2558 2559 /* 2560 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2561 * 2562 * This function detects whether a card is in the slot or not. 2563 * If a card is inserted, return 1. Otherwise, return 0. 2564 */ 2565 STATIC int 2566 pccbb_pcmcia_card_detect(pch) 2567 pcmcia_chipset_handle_t pch; 2568 { 2569 struct pcic_handle *ph = (struct pcic_handle *)pch; 2570 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2571 2572 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2573 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2574 } 2575 2576 #if 0 2577 STATIC int 2578 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2579 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2580 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2581 #endif 2582 /* 2583 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2584 * bus_size_t size, 2585 * struct pcmcia_mem_handle *pcmhp) 2586 * 2587 * This function only allocates memory region for pccard. This 2588 * function never maps the allocated region to pccard memory area. 2589 * 2590 * XXX: Why the argument of start address is not in? 2591 */ 2592 STATIC int 2593 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2594 pcmcia_chipset_handle_t pch; 2595 bus_size_t size; 2596 struct pcmcia_mem_handle *pcmhp; 2597 { 2598 struct pcic_handle *ph = (struct pcic_handle *)pch; 2599 bus_space_handle_t memh; 2600 bus_addr_t addr; 2601 bus_size_t sizepg; 2602 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2603 #if rbus 2604 rbus_tag_t rb; 2605 #endif 2606 2607 /* Check that the card is still there. */ 2608 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2609 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2610 return 1; 2611 2612 /* out of sc->memh, allocate as many pages as necessary */ 2613 2614 /* convert size to PCIC pages */ 2615 /* 2616 * This is not enough; when the requested region is on the page 2617 * boundaries, this may calculate wrong result. 2618 */ 2619 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2620 #if 0 2621 if (sizepg > PCIC_MAX_MEM_PAGES) { 2622 return 1; 2623 } 2624 #endif 2625 2626 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2627 return 1; 2628 } 2629 2630 addr = 0; /* XXX gcc -Wuninitialized */ 2631 2632 #if rbus 2633 rb = sc->sc_rbus_memt; 2634 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2635 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2636 &addr, &memh)) { 2637 return 1; 2638 } 2639 #else 2640 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2641 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2642 0, /* boundary */ 2643 0, /* flags */ 2644 &addr, &memh)) { 2645 return 1; 2646 } 2647 #endif 2648 2649 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2650 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2651 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2652 2653 pcmhp->memt = sc->sc_memt; 2654 pcmhp->memh = memh; 2655 pcmhp->addr = addr; 2656 pcmhp->size = size; 2657 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2658 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2659 pcmhp->mhandle = 0; 2660 /* No offset??? Funny. */ 2661 2662 return 0; 2663 } 2664 2665 /* 2666 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2667 * struct pcmcia_mem_handle *pcmhp) 2668 * 2669 * This function release the memory space allocated by the function 2670 * pccbb_pcmcia_mem_alloc(). 2671 */ 2672 STATIC void 2673 pccbb_pcmcia_mem_free(pch, pcmhp) 2674 pcmcia_chipset_handle_t pch; 2675 struct pcmcia_mem_handle *pcmhp; 2676 { 2677 #if rbus 2678 struct pcic_handle *ph = (struct pcic_handle *)pch; 2679 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2680 2681 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2682 #else 2683 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2684 #endif 2685 } 2686 2687 /* 2688 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2689 * 2690 * This function release the memory space allocated by the function 2691 * pccbb_pcmcia_mem_alloc(). 2692 */ 2693 STATIC void 2694 pccbb_pcmcia_do_mem_map(ph, win) 2695 struct pcic_handle *ph; 2696 int win; 2697 { 2698 int regbase_win; 2699 bus_addr_t phys_addr; 2700 bus_addr_t phys_end; 2701 2702 #define PCIC_SMM_START_LOW 0 2703 #define PCIC_SMM_START_HIGH 1 2704 #define PCIC_SMM_STOP_LOW 2 2705 #define PCIC_SMM_STOP_HIGH 3 2706 #define PCIC_CMA_LOW 4 2707 #define PCIC_CMA_HIGH 5 2708 2709 u_int8_t start_low, start_high = 0; 2710 u_int8_t stop_low, stop_high; 2711 u_int8_t off_low, off_high; 2712 u_int8_t mem_window; 2713 int reg; 2714 2715 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2716 int mem8 = 2717 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2718 || (kind == PCMCIA_MEM_ATTR); 2719 2720 regbase_win = 0x10 + win * 0x08; 2721 2722 phys_addr = ph->mem[win].addr; 2723 phys_end = phys_addr + ph->mem[win].size; 2724 2725 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2726 (unsigned long)phys_addr, (unsigned long)phys_end, 2727 (unsigned long)ph->mem[win].offset)); 2728 2729 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2730 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2731 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2732 2733 /* bit 19:12 */ 2734 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2735 /* bit 23:20 and bit 7 on */ 2736 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2737 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2738 /* bit 31:24, for 32-bit address */ 2739 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2740 2741 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2742 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2743 2744 if (((struct pccbb_softc *)ph-> 2745 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2746 Pcic_write(ph, 0x40 + win, mem_window); 2747 } 2748 2749 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2750 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2751 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2752 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2753 2754 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2755 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2756 2757 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2758 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2759 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2760 | ((kind == PCMCIA_MEM_ATTR) ? 2761 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2762 2763 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2764 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2765 2766 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2767 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2768 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2769 2770 #if defined CBB_DEBUG 2771 { 2772 int r1, r2, r3, r4, r5, r6, r7 = 0; 2773 2774 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2775 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2776 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2777 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2778 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2779 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2780 if (((struct pccbb_softc *)(ph-> 2781 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2782 r7 = Pcic_read(ph, 0x40 + win); 2783 } 2784 2785 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2786 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2787 if (((struct pccbb_softc *)(ph-> 2788 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2789 DPRINTF((" %02x", r7)); 2790 } 2791 DPRINTF(("\n")); 2792 } 2793 #endif 2794 } 2795 2796 /* 2797 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2798 * bus_addr_t card_addr, bus_size_t size, 2799 * struct pcmcia_mem_handle *pcmhp, 2800 * bus_addr_t *offsetp, int *windowp) 2801 * 2802 * This function maps memory space allocated by the function 2803 * pccbb_pcmcia_mem_alloc(). 2804 */ 2805 STATIC int 2806 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2807 pcmcia_chipset_handle_t pch; 2808 int kind; 2809 bus_addr_t card_addr; 2810 bus_size_t size; 2811 struct pcmcia_mem_handle *pcmhp; 2812 bus_addr_t *offsetp; 2813 int *windowp; 2814 { 2815 struct pcic_handle *ph = (struct pcic_handle *)pch; 2816 bus_addr_t busaddr; 2817 long card_offset; 2818 int win; 2819 2820 /* Check that the card is still there. */ 2821 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2822 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2823 return 1; 2824 2825 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2826 if ((ph->memalloc & (1 << win)) == 0) { 2827 ph->memalloc |= (1 << win); 2828 break; 2829 } 2830 } 2831 2832 if (win == PCIC_MEM_WINS) { 2833 return 1; 2834 } 2835 2836 *windowp = win; 2837 2838 /* XXX this is pretty gross */ 2839 2840 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2841 panic("pccbb_pcmcia_mem_map memt is bogus"); 2842 } 2843 2844 busaddr = pcmhp->addr; 2845 2846 /* 2847 * compute the address offset to the pcmcia address space for the 2848 * pcic. this is intentionally signed. The masks and shifts below 2849 * will cause TRT to happen in the pcic registers. Deal with making 2850 * sure the address is aligned, and return the alignment offset. 2851 */ 2852 2853 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2854 card_addr -= *offsetp; 2855 2856 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2857 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2858 (u_long) card_addr)); 2859 2860 /* 2861 * include the offset in the size, and decrement size by one, since 2862 * the hw wants start/stop 2863 */ 2864 size += *offsetp - 1; 2865 2866 card_offset = (((long)card_addr) - ((long)busaddr)); 2867 2868 ph->mem[win].addr = busaddr; 2869 ph->mem[win].size = size; 2870 ph->mem[win].offset = card_offset; 2871 ph->mem[win].kind = kind; 2872 2873 pccbb_pcmcia_do_mem_map(ph, win); 2874 2875 return 0; 2876 } 2877 2878 /* 2879 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2880 * int window) 2881 * 2882 * This function unmaps memory space which mapped by the function 2883 * pccbb_pcmcia_mem_map(). 2884 */ 2885 STATIC void 2886 pccbb_pcmcia_mem_unmap(pch, window) 2887 pcmcia_chipset_handle_t pch; 2888 int window; 2889 { 2890 struct pcic_handle *ph = (struct pcic_handle *)pch; 2891 int reg; 2892 2893 if (window >= PCIC_MEM_WINS) { 2894 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2895 } 2896 2897 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2898 reg &= ~(1 << window); 2899 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2900 2901 ph->memalloc &= ~(1 << window); 2902 } 2903 2904 #if defined PCCBB_PCMCIA_POLL 2905 struct pccbb_poll_str { 2906 void *arg; 2907 int (*func)(void *); 2908 int level; 2909 struct pcic_handle *ph; 2910 int count; 2911 int num; 2912 struct callout poll_ch; 2913 }; 2914 2915 static struct pccbb_poll_str pccbb_poll[10]; 2916 static int pccbb_poll_n = 0; 2917 2918 static void pccbb_pcmcia_poll(void *arg); 2919 2920 static void 2921 pccbb_pcmcia_poll(arg) 2922 void *arg; 2923 { 2924 struct pccbb_poll_str *poll = arg; 2925 struct pcic_handle *ph = poll->ph; 2926 struct pccbb_softc *sc = ph->sc; 2927 int s; 2928 u_int32_t spsr; /* socket present-state reg */ 2929 2930 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2931 switch (poll->level) { 2932 case IPL_NET: 2933 s = splnet(); 2934 break; 2935 case IPL_BIO: 2936 s = splbio(); 2937 break; 2938 case IPL_TTY: /* fallthrough */ 2939 default: 2940 s = spltty(); 2941 break; 2942 } 2943 2944 spsr = 2945 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2946 CB_SOCKET_STAT); 2947 2948 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2949 if (!(spsr & 0x40)) /* CINT low */ 2950 #else 2951 if (1) 2952 #endif 2953 { 2954 if ((*poll->func) (poll->arg) > 0) { 2955 ++poll->count; 2956 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2957 #if defined LEVEL2 2958 } else { 2959 printf("intr: miss! 0x%x\n", spsr); 2960 #endif 2961 } 2962 } 2963 splx(s); 2964 } 2965 #endif /* defined CB_PCMCIA_POLL */ 2966 2967 /* 2968 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2969 * struct pcmcia_function *pf, 2970 * int ipl, 2971 * int (*func)(void *), 2972 * void *arg); 2973 * 2974 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2975 */ 2976 STATIC void * 2977 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2978 pcmcia_chipset_handle_t pch; 2979 struct pcmcia_function *pf; 2980 int ipl; 2981 int (*func)(void *); 2982 void *arg; 2983 { 2984 struct pcic_handle *ph = (struct pcic_handle *)pch; 2985 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2986 2987 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2988 /* what should I do? */ 2989 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2990 DPRINTF(("%s does not provide edge nor pulse " 2991 "interrupt\n", sc->sc_dev.dv_xname)); 2992 return NULL; 2993 } 2994 /* 2995 * XXX Noooooo! The interrupt flag must set properly!! 2996 * dumb pcmcia driver!! 2997 */ 2998 } 2999 3000 return pccbb_intr_establish(sc, 0, ipl, func, arg); 3001 } 3002 3003 /* 3004 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 3005 * void *ih) 3006 * 3007 * This function disables PC-Card interrupt. 3008 */ 3009 STATIC void 3010 pccbb_pcmcia_intr_disestablish(pch, ih) 3011 pcmcia_chipset_handle_t pch; 3012 void *ih; 3013 { 3014 struct pcic_handle *ph = (struct pcic_handle *)pch; 3015 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3016 3017 pccbb_intr_disestablish(sc, ih); 3018 } 3019 3020 #if rbus 3021 /* 3022 * static int 3023 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3024 * bus_addr_t addr, bus_size_t size, 3025 * bus_addr_t mask, bus_size_t align, 3026 * int flags, bus_addr_t *addrp; 3027 * bus_space_handle_t *bshp) 3028 * 3029 * This function allocates a portion of memory or io space for 3030 * clients. This function is called from CardBus card drivers. 3031 */ 3032 static int 3033 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3034 cardbus_chipset_tag_t ct; 3035 rbus_tag_t rb; 3036 bus_addr_t addr; 3037 bus_size_t size; 3038 bus_addr_t mask; 3039 bus_size_t align; 3040 int flags; 3041 bus_addr_t *addrp; 3042 bus_space_handle_t *bshp; 3043 { 3044 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3045 3046 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3047 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3048 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3049 3050 if (align == 0) { 3051 align = size; 3052 } 3053 3054 if (rb->rb_bt == sc->sc_memt) { 3055 if (align < 16) { 3056 return 1; 3057 } 3058 /* 3059 * XXX: align more than 0x1000 to avoid overwrapping 3060 * memory windows for two or more devices. 0x1000 3061 * means memory window's granularity. 3062 * 3063 * Two or more devices should be able to share same 3064 * memory window region. However, overrapping memory 3065 * window is not good because some devices, such as 3066 * 3Com 3C575[BC], have a broken address decoder and 3067 * intrude other's memory region. 3068 */ 3069 if (align < 0x1000) { 3070 align = 0x1000; 3071 } 3072 } else if (rb->rb_bt == sc->sc_iot) { 3073 if (align < 4) { 3074 return 1; 3075 } 3076 /* XXX: hack for avoiding ISA image */ 3077 if (mask < 0x0100) { 3078 mask = 0x3ff; 3079 addr = 0x300; 3080 } 3081 3082 } else { 3083 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3084 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3085 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3086 (unsigned long)sc->sc_memt)); 3087 return 1; 3088 /* XXX: panic here? */ 3089 } 3090 3091 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3092 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3093 return 1; 3094 } 3095 3096 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3097 3098 return 0; 3099 } 3100 3101 /* 3102 * static int 3103 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3104 * bus_space_handle_t *bshp, bus_size_t size); 3105 * 3106 * This function is called from CardBus card drivers. 3107 */ 3108 static int 3109 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3110 cardbus_chipset_tag_t ct; 3111 rbus_tag_t rb; 3112 bus_space_handle_t bsh; 3113 bus_size_t size; 3114 { 3115 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3116 bus_space_tag_t bt = rb->rb_bt; 3117 3118 pccbb_close_win(sc, bt, bsh, size); 3119 3120 if (bt == sc->sc_memt) { 3121 } else if (bt == sc->sc_iot) { 3122 } else { 3123 return 1; 3124 /* XXX: panic here? */ 3125 } 3126 3127 return rbus_space_free(rb, bsh, size, NULL); 3128 } 3129 #endif /* rbus */ 3130 3131 #if rbus 3132 3133 static int 3134 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3135 struct pccbb_softc *sc; 3136 bus_space_tag_t bst; 3137 bus_addr_t addr; 3138 bus_size_t size; 3139 bus_space_handle_t bsh; 3140 int flags; 3141 { 3142 struct pccbb_win_chain_head *head; 3143 bus_addr_t align; 3144 3145 head = &sc->sc_iowindow; 3146 align = 0x04; 3147 if (sc->sc_memt == bst) { 3148 head = &sc->sc_memwindow; 3149 align = 0x1000; 3150 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3151 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3152 (unsigned long)bst)); 3153 } 3154 3155 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3156 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3157 sc->sc_dev.dv_xname, 3158 (head == &sc->sc_memwindow) ? "mem" : "io"); 3159 } 3160 pccbb_winset(align, sc, bst); 3161 3162 return 0; 3163 } 3164 3165 static int 3166 pccbb_close_win(sc, bst, bsh, size) 3167 struct pccbb_softc *sc; 3168 bus_space_tag_t bst; 3169 bus_space_handle_t bsh; 3170 bus_size_t size; 3171 { 3172 struct pccbb_win_chain_head *head; 3173 bus_addr_t align; 3174 3175 head = &sc->sc_iowindow; 3176 align = 0x04; 3177 if (sc->sc_memt == bst) { 3178 head = &sc->sc_memwindow; 3179 align = 0x1000; 3180 } 3181 3182 if (pccbb_winlist_delete(head, bsh, size)) { 3183 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3184 sc->sc_dev.dv_xname, 3185 (head == &sc->sc_memwindow) ? "mem" : "io"); 3186 } 3187 pccbb_winset(align, sc, bst); 3188 3189 return 0; 3190 } 3191 3192 static int 3193 pccbb_winlist_insert(head, start, size, bsh, flags) 3194 struct pccbb_win_chain_head *head; 3195 bus_addr_t start; 3196 bus_size_t size; 3197 bus_space_handle_t bsh; 3198 int flags; 3199 { 3200 struct pccbb_win_chain *chainp, *elem; 3201 3202 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3203 M_NOWAIT)) == NULL) 3204 return (1); /* fail */ 3205 3206 elem->wc_start = start; 3207 elem->wc_end = start + (size - 1); 3208 elem->wc_handle = bsh; 3209 elem->wc_flags = flags; 3210 3211 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3212 chainp = TAILQ_NEXT(chainp, wc_list)) { 3213 if (chainp->wc_end < start) 3214 continue; 3215 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3216 return (0); 3217 } 3218 3219 TAILQ_INSERT_TAIL(head, elem, wc_list); 3220 return (0); 3221 } 3222 3223 static int 3224 pccbb_winlist_delete(head, bsh, size) 3225 struct pccbb_win_chain_head *head; 3226 bus_space_handle_t bsh; 3227 bus_size_t size; 3228 { 3229 struct pccbb_win_chain *chainp; 3230 3231 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3232 chainp = TAILQ_NEXT(chainp, wc_list)) { 3233 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3234 continue; 3235 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3236 printf("pccbb_winlist_delete: window 0x%lx size " 3237 "inconsistent: 0x%lx, 0x%lx\n", 3238 (unsigned long)chainp->wc_start, 3239 (unsigned long)(chainp->wc_end - chainp->wc_start), 3240 (unsigned long)(size - 1)); 3241 return 1; 3242 } 3243 3244 TAILQ_REMOVE(head, chainp, wc_list); 3245 free(chainp, M_DEVBUF); 3246 3247 return 0; 3248 } 3249 3250 return 1; /* fail: no candidate to remove */ 3251 } 3252 3253 static void 3254 pccbb_winset(align, sc, bst) 3255 bus_addr_t align; 3256 struct pccbb_softc *sc; 3257 bus_space_tag_t bst; 3258 { 3259 pci_chipset_tag_t pc; 3260 pcitag_t tag; 3261 bus_addr_t mask = ~(align - 1); 3262 struct { 3263 cardbusreg_t win_start; 3264 cardbusreg_t win_limit; 3265 int win_flags; 3266 } win[2]; 3267 struct pccbb_win_chain *chainp; 3268 int offs; 3269 3270 win[0].win_start = win[1].win_start = 0xffffffff; 3271 win[0].win_limit = win[1].win_limit = 0; 3272 win[0].win_flags = win[1].win_flags = 0; 3273 3274 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3275 offs = 0x2c; 3276 if (sc->sc_memt == bst) { 3277 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3278 offs = 0x1c; 3279 } 3280 3281 if (chainp != NULL) { 3282 win[0].win_start = chainp->wc_start & mask; 3283 win[0].win_limit = chainp->wc_end & mask; 3284 win[0].win_flags = chainp->wc_flags; 3285 chainp = TAILQ_NEXT(chainp, wc_list); 3286 } 3287 3288 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3289 if (win[1].win_start == 0xffffffff) { 3290 /* window 1 is not used */ 3291 if ((win[0].win_flags == chainp->wc_flags) && 3292 (win[0].win_limit + align >= 3293 (chainp->wc_start & mask))) { 3294 /* concatenate */ 3295 win[0].win_limit = chainp->wc_end & mask; 3296 } else { 3297 /* make new window */ 3298 win[1].win_start = chainp->wc_start & mask; 3299 win[1].win_limit = chainp->wc_end & mask; 3300 win[1].win_flags = chainp->wc_flags; 3301 } 3302 continue; 3303 } 3304 3305 /* Both windows are engaged. */ 3306 if (win[0].win_flags == win[1].win_flags) { 3307 /* same flags */ 3308 if (win[0].win_flags == chainp->wc_flags) { 3309 if (win[1].win_start - (win[0].win_limit + 3310 align) < 3311 (chainp->wc_start & mask) - 3312 ((chainp->wc_end & mask) + align)) { 3313 /* 3314 * merge window 0 and 1, and set win1 3315 * to chainp 3316 */ 3317 win[0].win_limit = win[1].win_limit; 3318 win[1].win_start = 3319 chainp->wc_start & mask; 3320 win[1].win_limit = 3321 chainp->wc_end & mask; 3322 } else { 3323 win[1].win_limit = 3324 chainp->wc_end & mask; 3325 } 3326 } else { 3327 /* different flags */ 3328 3329 /* concatenate win0 and win1 */ 3330 win[0].win_limit = win[1].win_limit; 3331 /* allocate win[1] to new space */ 3332 win[1].win_start = chainp->wc_start & mask; 3333 win[1].win_limit = chainp->wc_end & mask; 3334 win[1].win_flags = chainp->wc_flags; 3335 } 3336 } else { 3337 /* the flags of win[0] and win[1] is different */ 3338 if (win[0].win_flags == chainp->wc_flags) { 3339 win[0].win_limit = chainp->wc_end & mask; 3340 /* 3341 * XXX this creates overlapping windows, so 3342 * what should the poor bridge do if one is 3343 * cachable, and the other is not? 3344 */ 3345 printf("%s: overlapping windows\n", 3346 sc->sc_dev.dv_xname); 3347 } else { 3348 win[1].win_limit = chainp->wc_end & mask; 3349 } 3350 } 3351 } 3352 3353 pc = sc->sc_pc; 3354 tag = sc->sc_tag; 3355 pci_conf_write(pc, tag, offs, win[0].win_start); 3356 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3357 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3358 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3359 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3360 (unsigned long)pci_conf_read(pc, tag, offs), 3361 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3362 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3363 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3364 3365 if (bst == sc->sc_memt) { 3366 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3367 3368 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3369 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3370 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3371 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3372 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3373 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3374 } 3375 } 3376 3377 #endif /* rbus */ 3378 3379 static void 3380 pccbb_powerhook(why, arg) 3381 int why; 3382 void *arg; 3383 { 3384 struct pccbb_softc *sc = arg; 3385 pcireg_t reg; 3386 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3387 bus_space_handle_t base_memh = sc->sc_base_memh; 3388 3389 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3390 3391 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3392 DPRINTF(("%s: power: why %d stopping intr\n", 3393 sc->sc_dev.dv_xname, why)); 3394 if (sc->sc_pil_intr_enable) { 3395 (void)pccbbintr_function(sc); 3396 } 3397 sc->sc_pil_intr_enable = 0; 3398 3399 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3400 3401 /* ToDo: deactivate or suspend child devices */ 3402 3403 } 3404 3405 if (why == PWR_RESUME) { 3406 if (sc->sc_pwrmgt_offs != 0) { 3407 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3408 sc->sc_pwrmgt_offs + 4); 3409 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3410 reg & 0x100) { 3411 /* powrstate != D0 */ 3412 3413 printf("%s going back to D0 mode\n", 3414 sc->sc_dev.dv_xname); 3415 reg &= ~PCI_PMCSR_STATE_MASK; 3416 reg |= PCI_PMCSR_STATE_D0; 3417 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3418 pci_conf_write(sc->sc_pc, sc->sc_tag, 3419 sc->sc_pwrmgt_offs + 4, reg); 3420 3421 pci_conf_write(sc->sc_pc, sc->sc_tag, 3422 PCI_SOCKBASE, sc->sc_sockbase); 3423 pci_conf_write(sc->sc_pc, sc->sc_tag, 3424 PCI_BUSNUM, sc->sc_busnum); 3425 pccbb_chipinit(sc); 3426 /* setup memory and io space window for CB */ 3427 pccbb_winset(0x1000, sc, sc->sc_memt); 3428 pccbb_winset(0x04, sc, sc->sc_iot); 3429 goto norestore; 3430 } 3431 } 3432 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3433 norestore: 3434 3435 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3436 /* BIOS did not recover this register */ 3437 pci_conf_write (sc->sc_pc, sc->sc_tag, 3438 PCI_SOCKBASE, sc->sc_sockbase); 3439 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3440 /* BIOS did not recover this register */ 3441 pci_conf_write (sc->sc_pc, sc->sc_tag, 3442 PCI_BUSNUM, sc->sc_busnum); 3443 /* CSC Interrupt: Card detect interrupt on */ 3444 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3445 /* Card detect intr is turned on. */ 3446 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3447 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3448 /* reset interrupt */ 3449 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3450 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3451 3452 /* 3453 * check for card insertion or removal during suspend period. 3454 * XXX: the code can't cope with card swap (remove then 3455 * insert). how can we detect such situation? 3456 */ 3457 (void)pccbbintr(sc); 3458 3459 sc->sc_pil_intr_enable = 1; 3460 DPRINTF(("%s: power: RESUME enabling intr\n", 3461 sc->sc_dev.dv_xname)); 3462 3463 /* ToDo: activate or wakeup child devices */ 3464 } 3465 } 3466
Indexes created Thu Sep 25 16:09:42 GMT 2025