pccbb.c revision 1.120
1 /* $NetBSD: pccbb.c,v 1.120 2005/06/01 08:39:32 sekiya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.120 2005/06/01 08:39:32 sekiya Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int xtick = (hz*(time))/1000; \ 104 \ 105 if (xtick <= 1) { \ 106 xtick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", xtick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (/*CONSTCOND*/0) 113 114 int pcicbbmatch(struct device *, struct cfdata *, void *); 115 void pccbbattach(struct device *, struct device *, void *); 116 int pccbbintr(void *); 117 static void pci113x_insert(void *); 118 static int pccbbintr_function(struct pccbb_softc *); 119 120 static int pccbb_detect_card(struct pccbb_softc *); 121 122 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 123 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset(struct pccbb_softc *); 128 STATIC int cb_detect_voltage(struct pccbb_softc *); 129 STATIC int cbbprint(void *, const char *); 130 131 static int cb_chipset(u_int32_t, int *); 132 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 133 struct pcmciabus_attach_args *); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 136 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 137 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 138 #endif 139 140 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 141 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 142 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 143 #if !rbus 144 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 145 static int pccbb_io_close(cardbus_chipset_tag_t, int); 146 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 147 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc); 151 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 152 153 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc); 155 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 156 157 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int, int); 158 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 159 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 160 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 161 cardbusreg_t); 162 static void pccbb_chipinit(struct pccbb_softc *); 163 164 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 165 struct pcmcia_mem_handle *); 166 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 167 struct pcmcia_mem_handle *); 168 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 170 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 171 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 172 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 173 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 174 struct pcmcia_io_handle *); 175 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 176 bus_size_t, struct pcmcia_io_handle *, int *); 177 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 178 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 179 struct pcmcia_function *, int, int (*)(void *), void *); 180 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 181 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 182 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 183 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 184 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 185 186 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 187 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 188 189 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 190 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 191 static void pccbb_powerhook(int, void *); 192 193 /* bus-space allocation and deallocation functions */ 194 #if rbus 195 196 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 198 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 199 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 200 bus_space_handle_t, bus_size_t); 201 202 #endif /* rbus */ 203 204 #if rbus 205 206 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 207 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 208 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 209 bus_space_handle_t, bus_size_t); 210 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 211 bus_size_t, bus_space_handle_t, int); 212 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 213 bus_space_handle_t, bus_size_t); 214 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 215 bus_space_tag_t); 216 void pccbb_winlist_show(struct pccbb_win_chain *); 217 218 #endif /* rbus */ 219 220 /* for config_defer */ 221 static void pccbb_pci_callback(struct device *); 222 223 #if defined SHOW_REGS 224 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 225 bus_space_tag_t memt, bus_space_handle_t memh); 226 #endif 227 228 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 229 pcicbbmatch, pccbbattach, NULL, NULL); 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_socket_settype, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(parent, match, aux) 279 struct device *parent; 280 struct cfdata *match; 281 void *aux; 282 { 283 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 284 285 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 286 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 287 PCI_INTERFACE(pa->pa_class) == 0) { 288 return 1; 289 } 290 291 return 0; 292 } 293 294 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 295 | ((prod) << PCI_PRODUCT_SHIFT)) 296 297 const struct yenta_chipinfo { 298 pcireg_t yc_id; /* vendor tag | product tag */ 299 int yc_chiptype; 300 int yc_flags; 301 } yc_chipsets[] = { 302 /* Texas Instruments chips */ 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 332 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 334 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 335 336 /* Ricoh chips */ 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 344 PCCBB_PCMCIA_MEM_32}, 345 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 346 PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 348 PCCBB_PCMCIA_MEM_32}, 349 350 /* Toshiba products */ 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 352 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 354 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 355 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 356 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 358 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 359 360 /* Cirrus Logic products */ 361 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 362 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 363 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 364 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 365 366 /* sentinel, or Generic chip */ 367 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 368 }; 369 370 static int 371 cb_chipset(pci_id, flagp) 372 u_int32_t pci_id; 373 int *flagp; 374 { 375 const struct yenta_chipinfo *yc; 376 377 /* Loop over except the last default entry. */ 378 for (yc = yc_chipsets; yc < yc_chipsets + 379 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 380 if (pci_id == yc->yc_id) 381 break; 382 383 if (flagp != NULL) 384 *flagp = yc->yc_flags; 385 386 return (yc->yc_chiptype); 387 } 388 389 static void 390 pccbb_shutdown(void *arg) 391 { 392 struct pccbb_softc *sc = arg; 393 pcireg_t command; 394 395 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 396 397 /* 398 * turn off power 399 * 400 * XXX - do not turn off power if chipset is TI 113X because 401 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 402 */ 403 if (sc->sc_chipset != CB_TI113X) { 404 pccbb_power((cardbus_chipset_tag_t)sc, 405 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 406 } 407 408 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 409 0); 410 411 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 412 413 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 414 PCI_COMMAND_MASTER_ENABLE); 415 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 416 417 } 418 419 void 420 pccbbattach(parent, self, aux) 421 struct device *parent; 422 struct device *self; 423 void *aux; 424 { 425 struct pccbb_softc *sc = (void *)self; 426 struct pci_attach_args *pa = aux; 427 pci_chipset_tag_t pc = pa->pa_pc; 428 pcireg_t busreg, reg, sock_base; 429 bus_addr_t sockbase; 430 char devinfo[256]; 431 int flags; 432 int pwrmgt_offs; 433 434 #ifdef __HAVE_PCCBB_ATTACH_HOOK 435 pccbb_attach_hook(parent, self, pa); 436 #endif 437 438 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 439 440 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 441 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 442 #ifdef CBB_DEBUG 443 printf(" (chipflags %x)", flags); 444 #endif 445 printf("\n"); 446 447 TAILQ_INIT(&sc->sc_memwindow); 448 TAILQ_INIT(&sc->sc_iowindow); 449 450 #if rbus 451 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 452 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 453 454 #if 0 455 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 456 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 457 #endif 458 #endif /* rbus */ 459 460 sc->sc_flags &= ~CBB_MEMHMAPPED; 461 462 /* power management: set D0 state */ 463 sc->sc_pwrmgt_offs = 0; 464 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 465 &pwrmgt_offs, 0)) { 466 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 467 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 468 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 469 reg &= ~PCI_PMCSR_STATE_MASK; 470 reg |= PCI_PMCSR_STATE_D0; 471 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 472 pci_conf_write(pc, pa->pa_tag, 473 pwrmgt_offs + PCI_PMCSR, reg); 474 } 475 476 sc->sc_pwrmgt_offs = pwrmgt_offs; 477 } 478 479 /* 480 * MAP socket registers and ExCA registers on memory-space 481 * When no valid address is set on socket base registers (on pci 482 * config space), get it not polite way. 483 */ 484 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 485 486 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 487 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 488 /* The address must be valid. */ 489 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 490 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 491 printf("%s: can't map socket base address 0x%lx\n", 492 sc->sc_dev.dv_xname, (unsigned long)sock_base); 493 /* 494 * I think it's funny: socket base registers must be 495 * mapped on memory space, but ... 496 */ 497 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 498 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 499 NULL)) { 500 printf("%s: can't map socket base address" 501 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 502 (unsigned long)sockbase); 503 /* give up... allocate reg space via rbus. */ 504 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 505 } else 506 sc->sc_flags |= CBB_MEMHMAPPED; 507 } else { 508 DPRINTF(("%s: socket base address 0x%lx\n", 509 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 510 sc->sc_flags |= CBB_MEMHMAPPED; 511 } 512 } 513 514 sc->sc_mem_start = 0; /* XXX */ 515 sc->sc_mem_end = 0xffffffff; /* XXX */ 516 517 /* 518 * When interrupt isn't routed correctly, give up probing cbb and do 519 * not kill pcic-compatible port. 520 */ 521 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 522 printf("%s: NOT USED because of unconfigured interrupt\n", 523 sc->sc_dev.dv_xname); 524 return; 525 } 526 527 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 528 529 /* pccbb_machdep.c end */ 530 531 #if defined CBB_DEBUG 532 { 533 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 534 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 535 intrname[pa->pa_intrpin], pa->pa_intrline); 536 } 537 #endif 538 539 /* setup softc */ 540 sc->sc_pc = pc; 541 sc->sc_iot = pa->pa_iot; 542 sc->sc_memt = pa->pa_memt; 543 sc->sc_dmat = pa->pa_dmat; 544 sc->sc_tag = pa->pa_tag; 545 sc->sc_function = pa->pa_function; 546 sc->sc_sockbase = sock_base; 547 sc->sc_busnum = busreg; 548 549 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 550 551 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 552 553 shutdownhook_establish(pccbb_shutdown, sc); 554 555 /* Disable legacy register mapping. */ 556 switch (sc->sc_chipset) { 557 case CB_RX5C46X: /* fallthrough */ 558 #if 0 559 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 560 case CB_RX5C47X: 561 #endif 562 /* 563 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 564 * cannot be disabled by substituting 0 into PCI_LEGACY 565 * register. Ricoh CardBus bridges have special bits on Bridge 566 * control reg (addr 0x3e on PCI config space). 567 */ 568 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 569 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 570 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 571 break; 572 573 default: 574 /* XXX I don't know proper way to kill legacy I/O. */ 575 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 576 break; 577 } 578 579 config_defer(self, pccbb_pci_callback); 580 } 581 582 583 584 585 /* 586 * static void pccbb_pci_callback(struct device *self) 587 * 588 * The actual attach routine: get memory space for YENTA register 589 * space, setup YENTA register and route interrupt. 590 * 591 * This function should be deferred because this device may obtain 592 * memory space dynamically. This function must avoid obtaining 593 * memory area which has already kept for another device. 594 */ 595 static void 596 pccbb_pci_callback(self) 597 struct device *self; 598 { 599 struct pccbb_softc *sc = (void *)self; 600 pci_chipset_tag_t pc = sc->sc_pc; 601 pci_intr_handle_t ih; 602 const char *intrstr = NULL; 603 bus_addr_t sockbase; 604 struct cbslot_attach_args cba; 605 struct pcmciabus_attach_args paa; 606 struct cardslot_attach_args caa; 607 struct cardslot_softc *csc; 608 609 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 610 /* The socket registers aren't mapped correctly. */ 611 #if rbus 612 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 613 (sc->sc_chipset == CB_RX5C47X 614 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 615 0, &sockbase, &sc->sc_base_memh)) { 616 return; 617 } 618 sc->sc_base_memt = sc->sc_memt; 619 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 620 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 621 sc->sc_dev.dv_xname, (unsigned long)sockbase, 622 (unsigned long)pci_conf_read(pc, sc->sc_tag, 623 PCI_SOCKBASE))); 624 #else 625 sc->sc_base_memt = sc->sc_memt; 626 #if !defined CBB_PCI_BASE 627 #define CBB_PCI_BASE 0x20000000 628 #endif 629 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 630 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 631 /* cannot allocate memory space */ 632 return; 633 } 634 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 635 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 636 sc->sc_dev.dv_xname, (unsigned long)sock_base, 637 (unsigned long)pci_conf_read(pc, 638 sc->sc_tag, PCI_SOCKBASE))); 639 sc->sc_sockbase = sockbase; 640 #endif 641 sc->sc_flags |= CBB_MEMHMAPPED; 642 } 643 644 /* bus bridge initialization */ 645 pccbb_chipinit(sc); 646 647 /* clear data structure for child device interrupt handlers */ 648 LIST_INIT(&sc->sc_pil); 649 sc->sc_pil_intr_enable = 1; 650 651 /* Map and establish the interrupt. */ 652 if (pci_intr_map(&sc->sc_pa, &ih)) { 653 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 654 return; 655 } 656 intrstr = pci_intr_string(pc, ih); 657 658 /* 659 * XXX pccbbintr should be called under the priority lower 660 * than any other hard interupts. 661 */ 662 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 663 664 if (sc->sc_ih == NULL) { 665 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 666 if (intrstr != NULL) { 667 printf(" at %s", intrstr); 668 } 669 printf("\n"); 670 return; 671 } 672 673 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 674 powerhook_establish(pccbb_powerhook, sc); 675 676 { 677 u_int32_t sockstat; 678 679 sockstat = bus_space_read_4(sc->sc_base_memt, 680 sc->sc_base_memh, CB_SOCKET_STAT); 681 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 682 sc->sc_flags |= CBB_CARDEXIST; 683 } 684 } 685 686 /* 687 * attach cardbus 688 */ 689 { 690 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 691 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 692 693 /* initialize cbslot_attach */ 694 cba.cba_busname = "cardbus"; 695 cba.cba_iot = sc->sc_iot; 696 cba.cba_memt = sc->sc_memt; 697 cba.cba_dmat = sc->sc_dmat; 698 cba.cba_bus = (busreg >> 8) & 0x0ff; 699 cba.cba_cc = (void *)sc; 700 cba.cba_cf = &pccbb_funcs; 701 cba.cba_intrline = sc->sc_pa.pa_intrline; 702 703 #if rbus 704 cba.cba_rbus_iot = sc->sc_rbus_iot; 705 cba.cba_rbus_memt = sc->sc_rbus_memt; 706 #endif 707 708 cba.cba_cacheline = PCI_CACHELINE(bhlc); 709 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 710 711 if (bootverbose) { 712 printf("%s: cacheline 0x%x lattimer 0x%x\n", 713 sc->sc_dev.dv_xname, cba.cba_cacheline, 714 cba.cba_lattimer); 715 printf("%s: bhlc 0x%x lscp 0x%x\n", 716 sc->sc_dev.dv_xname, bhlc, busreg); 717 } 718 #if defined SHOW_REGS 719 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 720 sc->sc_base_memh); 721 #endif 722 } 723 724 pccbb_pcmcia_attach_setup(sc, &paa); 725 caa.caa_cb_attach = NULL; 726 if (cba.cba_bus == 0) 727 printf("%s: secondary bus number uninitialized; try PCIBIOS_BUS_FIXUP\n", sc->sc_dev.dv_xname); 728 else 729 caa.caa_cb_attach = &cba; 730 caa.caa_16_attach = &paa; 731 caa.caa_ph = &sc->sc_pcmcia_h; 732 733 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 734 DPRINTF(("pccbbattach: found cardslot\n")); 735 sc->sc_csc = csc; 736 } 737 738 return; 739 } 740 741 742 743 744 745 /* 746 * static void pccbb_chipinit(struct pccbb_softc *sc) 747 * 748 * This function initialize YENTA chip registers listed below: 749 * 1) PCI command reg, 750 * 2) PCI and CardBus latency timer, 751 * 3) route PCI interrupt, 752 * 4) close all memory and io windows. 753 * 5) turn off bus power. 754 * 6) card detect and power cycle interrupts on. 755 * 7) clear interrupt 756 */ 757 static void 758 pccbb_chipinit(sc) 759 struct pccbb_softc *sc; 760 { 761 pci_chipset_tag_t pc = sc->sc_pc; 762 pcitag_t tag = sc->sc_tag; 763 bus_space_tag_t bmt = sc->sc_base_memt; 764 bus_space_handle_t bmh = sc->sc_base_memh; 765 pcireg_t reg; 766 767 /* 768 * Set PCI command reg. 769 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 770 */ 771 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 772 /* I believe it is harmless. */ 773 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 774 PCI_COMMAND_MASTER_ENABLE); 775 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 776 777 /* 778 * Set CardBus latency timer. 779 */ 780 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 781 if (PCI_CB_LATENCY(reg) < 0x20) { 782 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 783 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 784 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 785 } 786 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 787 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 788 789 /* 790 * Set PCI latency timer. 791 */ 792 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 793 if (PCI_LATTIMER(reg) < 0x10) { 794 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 795 reg |= (0x10 << PCI_LATTIMER_SHIFT); 796 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 797 } 798 DPRINTF(("PCI latency timer 0x%x (%x)\n", 799 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 800 801 802 /* Route functional interrupts to PCI. */ 803 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 804 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 805 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 806 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 807 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 808 809 switch (sc->sc_chipset) { 810 case CB_TI113X: 811 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 812 /* This bit is shared, but may read as 0 on some chips, so set 813 it explicitly on both functions. */ 814 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 815 /* CSC intr enable */ 816 reg |= PCI113X_CBCTRL_PCI_CSC; 817 /* functional intr prohibit | prohibit ISA routing */ 818 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 819 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 820 break; 821 822 case CB_TI12XX: 823 /* 824 * Some TI 12xx (and [14][45]xx) based pci cards 825 * sometimes have issues with the MFUNC register not 826 * being initialized due to a bad EEPROM on board. 827 * Laptops that this matters on have this register 828 * properly initialized. 829 * 830 * The TI125X parts have a different register. 831 */ 832 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 833 if (reg == 0) { 834 reg &= ~PCI12XX_MFUNC_PIN0; 835 reg |= PCI12XX_MFUNC_PIN0_INTA; 836 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 837 PCI12XX_SYSCTRL_INTRTIE) == 0) { 838 reg &= ~PCI12XX_MFUNC_PIN1; 839 reg |= PCI12XX_MFUNC_PIN1_INTB; 840 } 841 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 842 } 843 /* fallthrough */ 844 845 case CB_TI125X: 846 /* 847 * Disable zoom video. Some machines initialize this 848 * improperly and experience has shown that this helps 849 * prevent strange behavior. 850 */ 851 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 852 853 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 854 reg |= PCI12XX_SYSCTRL_VCCPROT; 855 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 856 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 857 reg |= PCI12XX_CBCTRL_CSC; 858 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 859 break; 860 861 case CB_TOPIC95B: 862 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 863 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 864 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 865 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 866 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 867 sc->sc_dev.dv_xname, reg)); 868 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 869 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 870 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 871 DPRINTF(("0x%x\n", reg)); 872 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 873 break; 874 875 case CB_TOPIC97: 876 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 877 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 878 sc->sc_dev.dv_xname, reg)); 879 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 880 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 881 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 882 reg |= TOPIC97_SLOT_CTRL_PCIINT; 883 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 884 DPRINTF(("0x%x\n", reg)); 885 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 886 /* make sure to assert LV card support bits */ 887 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 888 0x800 + 0x3e, 889 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 890 0x800 + 0x3e) | 0x03); 891 break; 892 } 893 894 /* Close all memory and I/O windows. */ 895 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 896 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 897 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 898 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 899 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 900 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 901 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 902 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 903 904 /* reset 16-bit pcmcia bus */ 905 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 906 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 907 908 /* turn off power */ 909 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 910 911 /* CSC Interrupt: Card detect and power cycle interrupts on */ 912 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 913 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 914 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 915 /* reset interrupt */ 916 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 917 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 918 } 919 920 921 922 923 /* 924 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 925 * struct pcmciabus_attach_args *paa) 926 * 927 * This function attaches 16-bit PCcard bus. 928 */ 929 STATIC void 930 pccbb_pcmcia_attach_setup(sc, paa) 931 struct pccbb_softc *sc; 932 struct pcmciabus_attach_args *paa; 933 { 934 struct pcic_handle *ph = &sc->sc_pcmcia_h; 935 #if rbus 936 rbus_tag_t rb; 937 #endif 938 939 /* initialize pcmcia part in pccbb_softc */ 940 ph->ph_parent = (struct device *)sc; 941 ph->sock = sc->sc_function; 942 ph->flags = 0; 943 ph->shutdown = 0; 944 ph->ih_irq = sc->sc_pa.pa_intrline; 945 ph->ph_bus_t = sc->sc_base_memt; 946 ph->ph_bus_h = sc->sc_base_memh; 947 ph->ph_read = pccbb_pcmcia_read; 948 ph->ph_write = pccbb_pcmcia_write; 949 sc->sc_pct = &pccbb_pcmcia_funcs; 950 951 /* 952 * We need to do a few things here: 953 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 954 * setting the IRQ numbers to 0. 955 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 956 * routing of CSC interrupts (e.g. card removal) to PCI while in 957 * PCMCIA mode. We just leave this set all the time. 958 * 3) Enable card insertion/removal interrupts in case the chip also 959 * needs that while in PCMCIA mode. 960 * 4) Clear any pending CSC interrupt. 961 */ 962 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 963 if (sc->sc_chipset == CB_TI113X) { 964 Pcic_write(ph, PCIC_CSC_INTR, 0); 965 } else { 966 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 967 Pcic_read(ph, PCIC_CSC); 968 } 969 970 /* initialize pcmcia bus attachment */ 971 paa->paa_busname = "pcmcia"; 972 paa->pct = sc->sc_pct; 973 paa->pch = ph; 974 paa->iobase = 0; /* I don't use them */ 975 paa->iosize = 0; 976 #if rbus 977 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 978 paa->iobase = rb->rb_start + rb->rb_offset; 979 paa->iosize = rb->rb_end - rb->rb_start; 980 #endif 981 982 return; 983 } 984 985 #if 0 986 STATIC void 987 pccbb_pcmcia_attach_card(ph) 988 struct pcic_handle *ph; 989 { 990 if (ph->flags & PCIC_FLAG_CARDP) { 991 panic("pccbb_pcmcia_attach_card: already attached"); 992 } 993 994 /* call the MI attach function */ 995 pcmcia_card_attach(ph->pcmcia); 996 997 ph->flags |= PCIC_FLAG_CARDP; 998 } 999 1000 STATIC void 1001 pccbb_pcmcia_detach_card(ph, flags) 1002 struct pcic_handle *ph; 1003 int flags; 1004 { 1005 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1006 panic("pccbb_pcmcia_detach_card: already detached"); 1007 } 1008 1009 ph->flags &= ~PCIC_FLAG_CARDP; 1010 1011 /* call the MI detach function */ 1012 pcmcia_card_detach(ph->pcmcia, flags); 1013 } 1014 #endif 1015 1016 /* 1017 * int pccbbintr(arg) 1018 * void *arg; 1019 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1020 * itself. 1021 */ 1022 int 1023 pccbbintr(arg) 1024 void *arg; 1025 { 1026 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1027 u_int32_t sockevent, sockstate; 1028 bus_space_tag_t memt = sc->sc_base_memt; 1029 bus_space_handle_t memh = sc->sc_base_memh; 1030 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1031 1032 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1033 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1034 Pcic_read(ph, PCIC_CSC); 1035 1036 if (sockevent == 0) { 1037 /* This intr is not for me: it may be for my child devices. */ 1038 if (sc->sc_pil_intr_enable) { 1039 return pccbbintr_function(sc); 1040 } else { 1041 return 0; 1042 } 1043 } 1044 1045 if (sockevent & CB_SOCKET_EVENT_CD) { 1046 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1047 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1048 /* A card should be removed. */ 1049 if (sc->sc_flags & CBB_CARDEXIST) { 1050 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1051 sockevent)); 1052 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1053 sc->sc_flags &= ~CBB_CARDEXIST; 1054 if (sc->sc_csc->sc_status & 1055 CARDSLOT_STATUS_CARD_16) { 1056 #if 0 1057 struct pcic_handle *ph = 1058 &sc->sc_pcmcia_h; 1059 1060 pcmcia_card_deactivate(ph->pcmcia); 1061 pccbb_pcmcia_socket_disable(ph); 1062 pccbb_pcmcia_detach_card(ph, 1063 DETACH_FORCE); 1064 #endif 1065 cardslot_event_throw(sc->sc_csc, 1066 CARDSLOT_EVENT_REMOVAL_16); 1067 } else if (sc->sc_csc->sc_status & 1068 CARDSLOT_STATUS_CARD_CB) { 1069 /* Cardbus intr removed */ 1070 cardslot_event_throw(sc->sc_csc, 1071 CARDSLOT_EVENT_REMOVAL_CB); 1072 } 1073 } else if (sc->sc_flags & CBB_INSERTING) { 1074 sc->sc_flags &= ~CBB_INSERTING; 1075 callout_stop(&sc->sc_insert_ch); 1076 } 1077 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1078 /* 1079 * The pccbbintr may called from powerdown hook when 1080 * the system resumed, to detect the card 1081 * insertion/removal during suspension. 1082 */ 1083 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1084 if (sc->sc_flags & CBB_INSERTING) { 1085 callout_stop(&sc->sc_insert_ch); 1086 } 1087 callout_reset(&sc->sc_insert_ch, hz / 5, 1088 pci113x_insert, sc); 1089 sc->sc_flags |= CBB_INSERTING; 1090 } 1091 } 1092 1093 if (sockevent & CB_SOCKET_EVENT_POWER) { 1094 /* XXX: Does not happen when attaching a 16-bit card */ 1095 sc->sc_pwrcycle++; 1096 wakeup(&sc->sc_pwrcycle); 1097 } 1098 1099 return (1); 1100 } 1101 1102 /* 1103 * static int pccbbintr_function(struct pccbb_softc *sc) 1104 * 1105 * This function calls each interrupt handler registered at the 1106 * bridge. The interrupt handlers are called in registered order. 1107 */ 1108 static int 1109 pccbbintr_function(sc) 1110 struct pccbb_softc *sc; 1111 { 1112 int retval = 0, val; 1113 struct pccbb_intrhand_list *pil; 1114 int s, splchanged; 1115 1116 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1117 pil = LIST_NEXT(pil, pil_next)) { 1118 /* 1119 * XXX priority change. gross. I use if-else 1120 * sentense instead of switch-case sentense because of 1121 * avoiding duplicate case value error. More than one 1122 * IPL_XXX use same value. It depends on 1123 * implimentation. 1124 */ 1125 splchanged = 1; 1126 if (pil->pil_level == IPL_SERIAL) { 1127 s = splserial(); 1128 } else if (pil->pil_level == IPL_HIGH) { 1129 s = splhigh(); 1130 } else if (pil->pil_level == IPL_CLOCK) { 1131 s = splclock(); 1132 } else if (pil->pil_level == IPL_AUDIO) { 1133 s = splaudio(); 1134 } else if (pil->pil_level == IPL_VM) { 1135 s = splvm(); 1136 } else if (pil->pil_level == IPL_TTY) { 1137 s = spltty(); 1138 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1139 s = splsoftserial(); 1140 } else if (pil->pil_level == IPL_NET) { 1141 s = splnet(); 1142 } else { 1143 s = 0; /* XXX: gcc */ 1144 splchanged = 0; 1145 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1146 } 1147 1148 val = (*pil->pil_func)(pil->pil_arg); 1149 1150 if (splchanged != 0) { 1151 splx(s); 1152 } 1153 1154 retval = retval == 1 ? 1 : 1155 retval == 0 ? val : val != 0 ? val : retval; 1156 } 1157 1158 return retval; 1159 } 1160 1161 static void 1162 pci113x_insert(arg) 1163 void *arg; 1164 { 1165 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1166 u_int32_t sockevent, sockstate; 1167 1168 if (!(sc->sc_flags & CBB_INSERTING)) { 1169 /* We add a card only under inserting state. */ 1170 return; 1171 } 1172 sc->sc_flags &= ~CBB_INSERTING; 1173 1174 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1175 CB_SOCKET_EVENT); 1176 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1177 CB_SOCKET_STAT); 1178 1179 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1180 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1181 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1182 sc->sc_flags |= CBB_CARDEXIST; 1183 /* call pccard interrupt handler here */ 1184 if (sockstate & CB_SOCKET_STAT_16BIT) { 1185 /* 16-bit card found */ 1186 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1187 cardslot_event_throw(sc->sc_csc, 1188 CARDSLOT_EVENT_INSERTION_16); 1189 } else if (sockstate & CB_SOCKET_STAT_CB) { 1190 /* cardbus card found */ 1191 /* cardbus_attach_card(sc->sc_csc); */ 1192 cardslot_event_throw(sc->sc_csc, 1193 CARDSLOT_EVENT_INSERTION_CB); 1194 } else { 1195 /* who are you? */ 1196 } 1197 } else { 1198 callout_reset(&sc->sc_insert_ch, hz / 10, 1199 pci113x_insert, sc); 1200 } 1201 } 1202 1203 #define PCCBB_PCMCIA_OFFSET 0x800 1204 static u_int8_t 1205 pccbb_pcmcia_read(ph, reg) 1206 struct pcic_handle *ph; 1207 int reg; 1208 { 1209 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1210 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1211 1212 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1213 PCCBB_PCMCIA_OFFSET + reg); 1214 } 1215 1216 static void 1217 pccbb_pcmcia_write(ph, reg, val) 1218 struct pcic_handle *ph; 1219 int reg; 1220 u_int8_t val; 1221 { 1222 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1223 val); 1224 1225 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1226 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1227 } 1228 1229 /* 1230 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1231 */ 1232 STATIC int 1233 pccbb_ctrl(ct, command) 1234 cardbus_chipset_tag_t ct; 1235 int command; 1236 { 1237 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1238 1239 switch (command) { 1240 case CARDBUS_CD: 1241 if (2 == pccbb_detect_card(sc)) { 1242 int retval = 0; 1243 int status = cb_detect_voltage(sc); 1244 if (PCCARD_VCC_5V & status) { 1245 retval |= CARDBUS_5V_CARD; 1246 } 1247 if (PCCARD_VCC_3V & status) { 1248 retval |= CARDBUS_3V_CARD; 1249 } 1250 if (PCCARD_VCC_XV & status) { 1251 retval |= CARDBUS_XV_CARD; 1252 } 1253 if (PCCARD_VCC_YV & status) { 1254 retval |= CARDBUS_YV_CARD; 1255 } 1256 return retval; 1257 } else { 1258 return 0; 1259 } 1260 case CARDBUS_RESET: 1261 return cb_reset(sc); 1262 case CARDBUS_IO_ENABLE: /* fallthrough */ 1263 case CARDBUS_IO_DISABLE: /* fallthrough */ 1264 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1265 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1266 case CARDBUS_BM_ENABLE: /* fallthrough */ 1267 case CARDBUS_BM_DISABLE: /* fallthrough */ 1268 /* XXX: I think we don't need to call this function below. */ 1269 return pccbb_cardenable(sc, command); 1270 } 1271 1272 return 0; 1273 } 1274 1275 /* 1276 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1277 * This function returns true when it succeeds and returns false when 1278 * it fails. 1279 */ 1280 STATIC int 1281 pccbb_power(ct, command) 1282 cardbus_chipset_tag_t ct; 1283 int command; 1284 { 1285 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1286 u_int32_t status, sock_ctrl, reg_ctrl; 1287 bus_space_tag_t memt = sc->sc_base_memt; 1288 bus_space_handle_t memh = sc->sc_base_memh; 1289 int on = 0, pwrcycle; 1290 1291 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1292 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1293 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1294 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1295 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1296 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1297 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1298 "UNKNOWN", 1299 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1300 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1301 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1302 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1303 "UNKNOWN", command)); 1304 1305 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1306 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1307 1308 switch (command & CARDBUS_VCCMASK) { 1309 case CARDBUS_VCC_UC: 1310 break; 1311 case CARDBUS_VCC_5V: 1312 on++; 1313 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1314 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1315 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1316 } else { 1317 printf("%s: BAD voltage request: no 5 V card\n", 1318 sc->sc_dev.dv_xname); 1319 return 0; 1320 } 1321 break; 1322 case CARDBUS_VCC_3V: 1323 on++; 1324 if (CB_SOCKET_STAT_3VCARD & status) { 1325 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1326 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1327 } else { 1328 printf("%s: BAD voltage request: no 3.3 V card\n", 1329 sc->sc_dev.dv_xname); 1330 return 0; 1331 } 1332 break; 1333 case CARDBUS_VCC_0V: 1334 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1335 break; 1336 default: 1337 return 0; /* power NEVER changed */ 1338 } 1339 1340 switch (command & CARDBUS_VPPMASK) { 1341 case CARDBUS_VPP_UC: 1342 break; 1343 case CARDBUS_VPP_0V: 1344 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1345 break; 1346 case CARDBUS_VPP_VCC: 1347 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1348 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1349 break; 1350 case CARDBUS_VPP_12V: 1351 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1352 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1353 break; 1354 } 1355 1356 pwrcycle = sc->sc_pwrcycle; 1357 1358 #if 0 1359 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1360 #endif 1361 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1362 1363 if (on) { 1364 int s, error = 0; 1365 struct timeval before, after, diff; 1366 1367 microtime(&before); 1368 s = splbio(); 1369 while (pwrcycle == sc->sc_pwrcycle) { 1370 /* 1371 * XXX: Set timeout to 200ms because power cycle event 1372 * will be never happen when attaching a 16-bit card. 1373 */ 1374 if ((error = tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1375 hz / 5)) == EWOULDBLOCK) 1376 break; 1377 } 1378 splx(s); 1379 microtime(&after); 1380 timersub(&after, &before, &diff); 1381 printf("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1382 error == EWOULDBLOCK ? " too long" : "", 1383 diff.tv_sec, diff.tv_usec); 1384 } 1385 1386 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1387 1388 if (on) { 1389 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1390 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1391 } 1392 1393 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1394 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1395 sc->sc_dev.dv_xname, sock_ctrl, status); 1396 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1397 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1398 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1399 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1400 status &= ~CB_SOCKET_STAT_BADVCC; 1401 bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1402 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1403 CB_SOCKET_STAT)); 1404 return 0; 1405 } 1406 1407 if (sc->sc_chipset == CB_TOPIC97) { 1408 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1409 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1410 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1411 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1412 else 1413 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1414 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1415 } 1416 1417 return 1; /* power changed correctly */ 1418 } 1419 1420 #if defined CB_PCMCIA_POLL 1421 struct cb_poll_str { 1422 void *arg; 1423 int (*func)(void *); 1424 int level; 1425 pccard_chipset_tag_t ct; 1426 int count; 1427 struct callout poll_ch; 1428 }; 1429 1430 static struct cb_poll_str cb_poll[10]; 1431 static int cb_poll_n = 0; 1432 1433 static void cb_pcmcia_poll(void *arg); 1434 1435 static void 1436 cb_pcmcia_poll(arg) 1437 void *arg; 1438 { 1439 struct cb_poll_str *poll = arg; 1440 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1441 struct pccbb_softc *sc = psc->cpc_parent; 1442 int s; 1443 u_int32_t spsr; /* socket present-state reg */ 1444 1445 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1446 switch (poll->level) { 1447 case IPL_NET: 1448 s = splnet(); 1449 break; 1450 case IPL_BIO: 1451 s = splbio(); 1452 break; 1453 case IPL_TTY: /* fallthrough */ 1454 default: 1455 s = spltty(); 1456 break; 1457 } 1458 1459 spsr = 1460 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1461 CB_SOCKET_STAT); 1462 1463 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1464 if (!(spsr & 0x40)) { /* CINT low */ 1465 #else 1466 if (1) { 1467 #endif 1468 if ((*poll->func) (poll->arg) == 1) { 1469 ++poll->count; 1470 printf("intr: reported from poller, 0x%x\n", spsr); 1471 #if defined LEVEL2 1472 } else { 1473 printf("intr: miss! 0x%x\n", spsr); 1474 #endif 1475 } 1476 } 1477 splx(s); 1478 } 1479 #endif /* defined CB_PCMCIA_POLL */ 1480 1481 /* 1482 * static int pccbb_detect_card(struct pccbb_softc *sc) 1483 * return value: 0 if no card exists. 1484 * 1 if 16-bit card exists. 1485 * 2 if cardbus card exists. 1486 */ 1487 static int 1488 pccbb_detect_card(sc) 1489 struct pccbb_softc *sc; 1490 { 1491 bus_space_handle_t base_memh = sc->sc_base_memh; 1492 bus_space_tag_t base_memt = sc->sc_base_memt; 1493 u_int32_t sockstat = 1494 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1495 int retval = 0; 1496 1497 /* CD1 and CD2 asserted */ 1498 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1499 /* card must be present */ 1500 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1501 /* NOTACARD DEASSERTED */ 1502 if (CB_SOCKET_STAT_CB & sockstat) { 1503 /* CardBus mode */ 1504 retval = 2; 1505 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1506 /* 16-bit mode */ 1507 retval = 1; 1508 } 1509 } 1510 } 1511 return retval; 1512 } 1513 1514 /* 1515 * STATIC int cb_reset(struct pccbb_softc *sc) 1516 * This function resets CardBus card. 1517 */ 1518 STATIC int 1519 cb_reset(sc) 1520 struct pccbb_softc *sc; 1521 { 1522 /* 1523 * Reset Assert at least 20 ms 1524 * Some machines request longer duration. 1525 */ 1526 int reset_duration = 1527 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1528 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1529 1530 /* Reset bit Assert (bit 6 at 0x3E) */ 1531 bcr |= CB_BCR_RESET_ENABLE; 1532 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1533 DELAY_MS(reset_duration, sc); 1534 1535 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1536 /* Reset bit Deassert (bit 6 at 0x3E) */ 1537 bcr &= ~CB_BCR_RESET_ENABLE; 1538 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1539 DELAY_MS(reset_duration, sc); 1540 } 1541 /* No card found on the slot. Keep Reset. */ 1542 return 1; 1543 } 1544 1545 /* 1546 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1547 * This function detect card Voltage. 1548 */ 1549 STATIC int 1550 cb_detect_voltage(sc) 1551 struct pccbb_softc *sc; 1552 { 1553 u_int32_t psr; /* socket present-state reg */ 1554 bus_space_tag_t iot = sc->sc_base_memt; 1555 bus_space_handle_t ioh = sc->sc_base_memh; 1556 int vol = PCCARD_VCC_UKN; /* set 0 */ 1557 1558 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1559 1560 if (0x400u & psr) { 1561 vol |= PCCARD_VCC_5V; 1562 } 1563 if (0x800u & psr) { 1564 vol |= PCCARD_VCC_3V; 1565 } 1566 1567 return vol; 1568 } 1569 1570 STATIC int 1571 cbbprint(aux, pcic) 1572 void *aux; 1573 const char *pcic; 1574 { 1575 /* 1576 struct cbslot_attach_args *cba = aux; 1577 1578 if (cba->cba_slot >= 0) { 1579 aprint_normal(" slot %d", cba->cba_slot); 1580 } 1581 */ 1582 return UNCONF; 1583 } 1584 1585 /* 1586 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1587 * This function enables and disables the card 1588 */ 1589 STATIC int 1590 pccbb_cardenable(sc, function) 1591 struct pccbb_softc *sc; 1592 int function; 1593 { 1594 u_int32_t command = 1595 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1596 1597 DPRINTF(("pccbb_cardenable:")); 1598 switch (function) { 1599 case CARDBUS_IO_ENABLE: 1600 command |= PCI_COMMAND_IO_ENABLE; 1601 break; 1602 case CARDBUS_IO_DISABLE: 1603 command &= ~PCI_COMMAND_IO_ENABLE; 1604 break; 1605 case CARDBUS_MEM_ENABLE: 1606 command |= PCI_COMMAND_MEM_ENABLE; 1607 break; 1608 case CARDBUS_MEM_DISABLE: 1609 command &= ~PCI_COMMAND_MEM_ENABLE; 1610 break; 1611 case CARDBUS_BM_ENABLE: 1612 command |= PCI_COMMAND_MASTER_ENABLE; 1613 break; 1614 case CARDBUS_BM_DISABLE: 1615 command &= ~PCI_COMMAND_MASTER_ENABLE; 1616 break; 1617 default: 1618 return 0; 1619 } 1620 1621 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1622 DPRINTF((" command reg 0x%x\n", command)); 1623 return 1; 1624 } 1625 1626 #if !rbus 1627 /* 1628 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1629 */ 1630 static int 1631 pccbb_io_open(ct, win, start, end) 1632 cardbus_chipset_tag_t ct; 1633 int win; 1634 u_int32_t start, end; 1635 { 1636 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1637 int basereg; 1638 int limitreg; 1639 1640 if ((win < 0) || (win > 2)) { 1641 #if defined DIAGNOSTIC 1642 printf("cardbus_io_open: window out of range %d\n", win); 1643 #endif 1644 return 0; 1645 } 1646 1647 basereg = win * 8 + 0x2c; 1648 limitreg = win * 8 + 0x30; 1649 1650 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1651 start, basereg, end, limitreg)); 1652 1653 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1654 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1655 return 1; 1656 } 1657 1658 /* 1659 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1660 */ 1661 static int 1662 pccbb_io_close(ct, win) 1663 cardbus_chipset_tag_t ct; 1664 int win; 1665 { 1666 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1667 int basereg; 1668 int limitreg; 1669 1670 if ((win < 0) || (win > 2)) { 1671 #if defined DIAGNOSTIC 1672 printf("cardbus_io_close: window out of range %d\n", win); 1673 #endif 1674 return 0; 1675 } 1676 1677 basereg = win * 8 + 0x2c; 1678 limitreg = win * 8 + 0x30; 1679 1680 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1681 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1682 return 1; 1683 } 1684 1685 /* 1686 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1687 */ 1688 static int 1689 pccbb_mem_open(ct, win, start, end) 1690 cardbus_chipset_tag_t ct; 1691 int win; 1692 u_int32_t start, end; 1693 { 1694 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1695 int basereg; 1696 int limitreg; 1697 1698 if ((win < 0) || (win > 2)) { 1699 #if defined DIAGNOSTIC 1700 printf("cardbus_mem_open: window out of range %d\n", win); 1701 #endif 1702 return 0; 1703 } 1704 1705 basereg = win * 8 + 0x1c; 1706 limitreg = win * 8 + 0x20; 1707 1708 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1709 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1710 return 1; 1711 } 1712 1713 /* 1714 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1715 */ 1716 static int 1717 pccbb_mem_close(ct, win) 1718 cardbus_chipset_tag_t ct; 1719 int win; 1720 { 1721 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1722 int basereg; 1723 int limitreg; 1724 1725 if ((win < 0) || (win > 2)) { 1726 #if defined DIAGNOSTIC 1727 printf("cardbus_mem_close: window out of range %d\n", win); 1728 #endif 1729 return 0; 1730 } 1731 1732 basereg = win * 8 + 0x1c; 1733 limitreg = win * 8 + 0x20; 1734 1735 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1736 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1737 return 1; 1738 } 1739 #endif 1740 1741 /* 1742 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1743 * int irq, 1744 * int level, 1745 * int (* func)(void *), 1746 * void *arg) 1747 * 1748 * This function registers an interrupt handler at the bridge, in 1749 * order not to call the interrupt handlers of child devices when 1750 * a card-deletion interrupt occurs. 1751 * 1752 * The arguments irq and level are not used. 1753 */ 1754 static void * 1755 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1756 cardbus_chipset_tag_t ct; 1757 int irq, level; 1758 int (*func)(void *); 1759 void *arg; 1760 { 1761 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1762 1763 return pccbb_intr_establish(sc, irq, level, func, arg); 1764 } 1765 1766 1767 /* 1768 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1769 * void *ih) 1770 * 1771 * This function removes an interrupt handler pointed by ih. 1772 */ 1773 static void 1774 pccbb_cb_intr_disestablish(ct, ih) 1775 cardbus_chipset_tag_t ct; 1776 void *ih; 1777 { 1778 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1779 1780 pccbb_intr_disestablish(sc, ih); 1781 } 1782 1783 1784 void 1785 pccbb_intr_route(sc) 1786 struct pccbb_softc *sc; 1787 { 1788 pcireg_t reg; 1789 1790 /* initialize bridge intr routing */ 1791 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1792 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1793 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1794 1795 switch (sc->sc_chipset) { 1796 case CB_TI113X: 1797 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1798 /* functional intr enabled */ 1799 reg |= PCI113X_CBCTRL_PCI_INTR; 1800 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1801 break; 1802 default: 1803 break; 1804 } 1805 } 1806 1807 /* 1808 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1809 * int irq, 1810 * int level, 1811 * int (* func)(void *), 1812 * void *arg) 1813 * 1814 * This function registers an interrupt handler at the bridge, in 1815 * order not to call the interrupt handlers of child devices when 1816 * a card-deletion interrupt occurs. 1817 * 1818 * The arguments irq is not used because pccbb selects intr vector. 1819 */ 1820 static void * 1821 pccbb_intr_establish(sc, irq, level, func, arg) 1822 struct pccbb_softc *sc; 1823 int irq, level; 1824 int (*func)(void *); 1825 void *arg; 1826 { 1827 struct pccbb_intrhand_list *pil, *newpil; 1828 1829 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1830 1831 if (LIST_EMPTY(&sc->sc_pil)) { 1832 pccbb_intr_route(sc); 1833 } 1834 1835 /* 1836 * Allocate a room for interrupt handler structure. 1837 */ 1838 if (NULL == (newpil = 1839 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1840 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1841 return NULL; 1842 } 1843 1844 newpil->pil_func = func; 1845 newpil->pil_arg = arg; 1846 newpil->pil_level = level; 1847 1848 if (LIST_EMPTY(&sc->sc_pil)) { 1849 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1850 } else { 1851 for (pil = LIST_FIRST(&sc->sc_pil); 1852 LIST_NEXT(pil, pil_next) != NULL; 1853 pil = LIST_NEXT(pil, pil_next)); 1854 LIST_INSERT_AFTER(pil, newpil, pil_next); 1855 } 1856 1857 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1858 LIST_FIRST(&sc->sc_pil))); 1859 1860 return newpil; 1861 } 1862 1863 /* 1864 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1865 * void *ih) 1866 * 1867 * This function removes an interrupt handler pointed by ih. ih 1868 * should be the value returned by cardbus_intr_establish() or 1869 * NULL. 1870 * 1871 * When ih is NULL, this function will do nothing. 1872 */ 1873 static void 1874 pccbb_intr_disestablish(sc, ih) 1875 struct pccbb_softc *sc; 1876 void *ih; 1877 { 1878 struct pccbb_intrhand_list *pil; 1879 pcireg_t reg; 1880 1881 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1882 LIST_FIRST(&sc->sc_pil))); 1883 1884 if (ih == NULL) { 1885 /* intr handler is not set */ 1886 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1887 return; 1888 } 1889 1890 #ifdef DIAGNOSTIC 1891 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1892 pil = LIST_NEXT(pil, pil_next)) { 1893 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1894 if (pil == ih) { 1895 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1896 break; 1897 } 1898 } 1899 if (pil == NULL) { 1900 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1901 sc->sc_dev.dv_xname, ih); 1902 } 1903 #endif 1904 1905 pil = (struct pccbb_intrhand_list *)ih; 1906 LIST_REMOVE(pil, pil_next); 1907 free(pil, M_DEVBUF); 1908 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1909 1910 if (LIST_EMPTY(&sc->sc_pil)) { 1911 /* No interrupt handlers */ 1912 1913 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1914 1915 /* stop routing PCI intr */ 1916 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1917 reg |= CB_BCR_INTR_IREQ_ENABLE; 1918 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1919 1920 switch (sc->sc_chipset) { 1921 case CB_TI113X: 1922 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1923 /* functional intr disabled */ 1924 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1925 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1926 break; 1927 default: 1928 break; 1929 } 1930 } 1931 } 1932 1933 #if defined SHOW_REGS 1934 static void 1935 cb_show_regs(pc, tag, memt, memh) 1936 pci_chipset_tag_t pc; 1937 pcitag_t tag; 1938 bus_space_tag_t memt; 1939 bus_space_handle_t memh; 1940 { 1941 int i; 1942 printf("PCI config regs:"); 1943 for (i = 0; i < 0x50; i += 4) { 1944 if (i % 16 == 0) { 1945 printf("\n 0x%02x:", i); 1946 } 1947 printf(" %08x", pci_conf_read(pc, tag, i)); 1948 } 1949 for (i = 0x80; i < 0xb0; i += 4) { 1950 if (i % 16 == 0) { 1951 printf("\n 0x%02x:", i); 1952 } 1953 printf(" %08x", pci_conf_read(pc, tag, i)); 1954 } 1955 1956 if (memh == 0) { 1957 printf("\n"); 1958 return; 1959 } 1960 1961 printf("\nsocket regs:"); 1962 for (i = 0; i <= 0x10; i += 0x04) { 1963 printf(" %08x", bus_space_read_4(memt, memh, i)); 1964 } 1965 printf("\nExCA regs:"); 1966 for (i = 0; i < 0x08; ++i) { 1967 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1968 } 1969 printf("\n"); 1970 return; 1971 } 1972 #endif 1973 1974 /* 1975 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1976 * int busno, int devno, int function) 1977 * This is the function to make a tag to access config space of 1978 * a CardBus Card. It works same as pci_conf_read. 1979 */ 1980 static cardbustag_t 1981 pccbb_make_tag(cc, busno, devno, function) 1982 cardbus_chipset_tag_t cc; 1983 int busno, devno, function; 1984 { 1985 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1986 1987 return pci_make_tag(sc->sc_pc, busno, devno, function); 1988 } 1989 1990 static void 1991 pccbb_free_tag(cc, tag) 1992 cardbus_chipset_tag_t cc; 1993 cardbustag_t tag; 1994 { 1995 } 1996 1997 /* 1998 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1999 * cardbustag_t tag, int offset) 2000 * This is the function to read the config space of a CardBus Card. 2001 * It works same as pci_conf_read. 2002 */ 2003 static cardbusreg_t 2004 pccbb_conf_read(cc, tag, offset) 2005 cardbus_chipset_tag_t cc; 2006 cardbustag_t tag; 2007 int offset; /* register offset */ 2008 { 2009 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2010 2011 return pci_conf_read(sc->sc_pc, tag, offset); 2012 } 2013 2014 /* 2015 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 2016 * int offs, cardbusreg_t val) 2017 * This is the function to write the config space of a CardBus Card. 2018 * It works same as pci_conf_write. 2019 */ 2020 static void 2021 pccbb_conf_write(cc, tag, reg, val) 2022 cardbus_chipset_tag_t cc; 2023 cardbustag_t tag; 2024 int reg; /* register offset */ 2025 cardbusreg_t val; 2026 { 2027 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2028 2029 pci_conf_write(sc->sc_pc, tag, reg, val); 2030 } 2031 2032 #if 0 2033 STATIC int 2034 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2035 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2036 int speed, int flags, 2037 bus_space_handle_t * iohp) 2038 #endif 2039 /* 2040 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2041 * bus_addr_t start, bus_size_t size, 2042 * bus_size_t align, 2043 * struct pcmcia_io_handle *pcihp 2044 * 2045 * This function only allocates I/O region for pccard. This function 2046 * never maps the allocated region to pccard I/O area. 2047 * 2048 * XXX: The interface of this function is not very good, I believe. 2049 */ 2050 STATIC int 2051 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2052 pcmcia_chipset_handle_t pch; 2053 bus_addr_t start; /* start address */ 2054 bus_size_t size; 2055 bus_size_t align; 2056 struct pcmcia_io_handle *pcihp; 2057 { 2058 struct pcic_handle *ph = (struct pcic_handle *)pch; 2059 bus_addr_t ioaddr; 2060 int flags = 0; 2061 bus_space_tag_t iot; 2062 bus_space_handle_t ioh; 2063 bus_addr_t mask; 2064 #if rbus 2065 rbus_tag_t rb; 2066 #endif 2067 if (align == 0) { 2068 align = size; /* XXX: funny??? */ 2069 } 2070 2071 if (start != 0) { 2072 /* XXX: assume all card decode lower 10 bits by its hardware */ 2073 mask = 0x3ff; 2074 /* enforce to use only masked address */ 2075 start &= mask; 2076 } else { 2077 /* 2078 * calculate mask: 2079 * 1. get the most significant bit of size (call it msb). 2080 * 2. compare msb with the value of size. 2081 * 3. if size is larger, shift msb left once. 2082 * 4. obtain mask value to decrement msb. 2083 */ 2084 bus_size_t size_tmp = size; 2085 int shifts = 0; 2086 2087 mask = 1; 2088 while (size_tmp) { 2089 ++shifts; 2090 size_tmp >>= 1; 2091 } 2092 mask = (1 << shifts); 2093 if (mask < size) { 2094 mask <<= 1; 2095 } 2096 --mask; 2097 } 2098 2099 /* 2100 * Allocate some arbitrary I/O space. 2101 */ 2102 2103 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2104 2105 #if rbus 2106 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2107 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2108 return 1; 2109 } 2110 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2111 (u_long) ioaddr, (u_long) size)); 2112 #else 2113 if (start) { 2114 ioaddr = start; 2115 if (bus_space_map(iot, start, size, 0, &ioh)) { 2116 return 1; 2117 } 2118 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2119 (u_long) ioaddr, (u_long) size)); 2120 } else { 2121 flags |= PCMCIA_IO_ALLOCATED; 2122 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2123 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2124 size, align, 0, 0, &ioaddr, &ioh)) { 2125 /* No room be able to be get. */ 2126 return 1; 2127 } 2128 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2129 (u_long) ioaddr, (u_long) size)); 2130 } 2131 #endif 2132 2133 pcihp->iot = iot; 2134 pcihp->ioh = ioh; 2135 pcihp->addr = ioaddr; 2136 pcihp->size = size; 2137 pcihp->flags = flags; 2138 2139 return 0; 2140 } 2141 2142 /* 2143 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2144 * struct pcmcia_io_handle *pcihp) 2145 * 2146 * This function only frees I/O region for pccard. 2147 * 2148 * XXX: The interface of this function is not very good, I believe. 2149 */ 2150 void 2151 pccbb_pcmcia_io_free(pch, pcihp) 2152 pcmcia_chipset_handle_t pch; 2153 struct pcmcia_io_handle *pcihp; 2154 { 2155 #if !rbus 2156 bus_space_tag_t iot = pcihp->iot; 2157 #endif 2158 bus_space_handle_t ioh = pcihp->ioh; 2159 bus_size_t size = pcihp->size; 2160 2161 #if rbus 2162 struct pccbb_softc *sc = 2163 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2164 rbus_tag_t rb = sc->sc_rbus_iot; 2165 2166 rbus_space_free(rb, ioh, size, NULL); 2167 #else 2168 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2169 bus_space_free(iot, ioh, size); 2170 else 2171 bus_space_unmap(iot, ioh, size); 2172 #endif 2173 } 2174 2175 /* 2176 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2177 * bus_addr_t offset, bus_size_t size, 2178 * struct pcmcia_io_handle *pcihp, 2179 * int *windowp) 2180 * 2181 * This function maps the allocated I/O region to pccard. This function 2182 * never allocates any I/O region for pccard I/O area. I don't 2183 * understand why the original authors of pcmciabus separated alloc and 2184 * map. I believe the two must be unite. 2185 * 2186 * XXX: no wait timing control? 2187 */ 2188 int 2189 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2190 pcmcia_chipset_handle_t pch; 2191 int width; 2192 bus_addr_t offset; 2193 bus_size_t size; 2194 struct pcmcia_io_handle *pcihp; 2195 int *windowp; 2196 { 2197 struct pcic_handle *ph = (struct pcic_handle *)pch; 2198 bus_addr_t ioaddr = pcihp->addr + offset; 2199 int i, win; 2200 #if defined CBB_DEBUG 2201 static char *width_names[] = { "dynamic", "io8", "io16" }; 2202 #endif 2203 2204 /* Sanity check I/O handle. */ 2205 2206 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2207 panic("pccbb_pcmcia_io_map iot is bogus"); 2208 } 2209 2210 /* XXX Sanity check offset/size. */ 2211 2212 win = -1; 2213 for (i = 0; i < PCIC_IO_WINS; i++) { 2214 if ((ph->ioalloc & (1 << i)) == 0) { 2215 win = i; 2216 ph->ioalloc |= (1 << i); 2217 break; 2218 } 2219 } 2220 2221 if (win == -1) { 2222 return 1; 2223 } 2224 2225 *windowp = win; 2226 2227 /* XXX this is pretty gross */ 2228 2229 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2230 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2231 2232 /* XXX wtf is this doing here? */ 2233 2234 #if 0 2235 printf(" port 0x%lx", (u_long) ioaddr); 2236 if (size > 1) { 2237 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2238 } 2239 #endif 2240 2241 ph->io[win].addr = ioaddr; 2242 ph->io[win].size = size; 2243 ph->io[win].width = width; 2244 2245 /* actual dirty register-value changing in the function below. */ 2246 pccbb_pcmcia_do_io_map(ph, win); 2247 2248 return 0; 2249 } 2250 2251 /* 2252 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2253 * 2254 * This function changes register-value to map I/O region for pccard. 2255 */ 2256 static void 2257 pccbb_pcmcia_do_io_map(ph, win) 2258 struct pcic_handle *ph; 2259 int win; 2260 { 2261 static u_int8_t pcic_iowidth[3] = { 2262 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2263 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2264 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2265 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2266 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2267 }; 2268 2269 #define PCIC_SIA_START_LOW 0 2270 #define PCIC_SIA_START_HIGH 1 2271 #define PCIC_SIA_STOP_LOW 2 2272 #define PCIC_SIA_STOP_HIGH 3 2273 2274 int regbase_win = 0x8 + win * 0x04; 2275 u_int8_t ioctl, enable; 2276 2277 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2278 "width %d\n", win, (unsigned long)ph->io[win].addr, 2279 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2280 2281 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2282 ph->io[win].addr & 0xff); 2283 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2284 (ph->io[win].addr >> 8) & 0xff); 2285 2286 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2287 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2288 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2289 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2290 2291 ioctl = Pcic_read(ph, PCIC_IOCTL); 2292 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2293 switch (win) { 2294 case 0: 2295 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2296 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2297 PCIC_IOCTL_IO0_DATASIZE_MASK); 2298 ioctl |= pcic_iowidth[ph->io[win].width]; 2299 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2300 break; 2301 case 1: 2302 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2303 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2304 PCIC_IOCTL_IO1_DATASIZE_MASK); 2305 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2306 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2307 break; 2308 } 2309 Pcic_write(ph, PCIC_IOCTL, ioctl); 2310 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2311 #if defined CBB_DEBUG 2312 { 2313 u_int8_t start_low = 2314 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2315 u_int8_t start_high = 2316 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2317 u_int8_t stop_low = 2318 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2319 u_int8_t stop_high = 2320 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2321 printf 2322 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2323 start_low, start_high, stop_low, stop_high, ioctl, enable); 2324 } 2325 #endif 2326 } 2327 2328 /* 2329 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2330 * 2331 * This function unmaps I/O region. No return value. 2332 */ 2333 STATIC void 2334 pccbb_pcmcia_io_unmap(pch, win) 2335 pcmcia_chipset_handle_t pch; 2336 int win; 2337 { 2338 struct pcic_handle *ph = (struct pcic_handle *)pch; 2339 int reg; 2340 2341 if (win >= PCIC_IO_WINS || win < 0) { 2342 panic("pccbb_pcmcia_io_unmap: window out of range"); 2343 } 2344 2345 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2346 switch (win) { 2347 case 0: 2348 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2349 break; 2350 case 1: 2351 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2352 break; 2353 } 2354 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2355 2356 ph->ioalloc &= ~(1 << win); 2357 } 2358 2359 static int 2360 pccbb_pcmcia_wait_ready(ph) 2361 struct pcic_handle *ph; 2362 { 2363 u_int8_t stat; 2364 int i; 2365 2366 /* wait an initial 10ms for quick cards */ 2367 stat = Pcic_read(ph, PCIC_IF_STATUS); 2368 if (stat & PCIC_IF_STATUS_READY) 2369 return (0); 2370 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2371 for (i = 0; i < 50; i++) { 2372 stat = Pcic_read(ph, PCIC_IF_STATUS); 2373 if (stat & PCIC_IF_STATUS_READY) 2374 return (0); 2375 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2376 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2377 return (ENXIO); 2378 /* wait .1s (100ms) each iteration now */ 2379 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2380 } 2381 2382 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2383 return (EWOULDBLOCK); 2384 } 2385 2386 /* 2387 * Perform long (msec order) delay. 2388 */ 2389 static void 2390 pccbb_pcmcia_delay(ph, timo, wmesg) 2391 struct pcic_handle *ph; 2392 int timo; /* in ms. must not be zero */ 2393 const char *wmesg; 2394 { 2395 2396 #ifdef DIAGNOSTIC 2397 if (timo <= 0) 2398 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2399 if (!curlwp) 2400 panic("pccbb_pcmcia_delay: called in interrupt context"); 2401 #if 0 2402 if (!ph->event_thread) 2403 panic("pccbb_pcmcia_delay: no event thread"); 2404 #endif 2405 #endif 2406 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2407 wmesg, ph->event_thread, timo)); 2408 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2409 } 2410 2411 /* 2412 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2413 * 2414 * This function enables the card. All information is stored in 2415 * the first argument, pcmcia_chipset_handle_t. 2416 */ 2417 STATIC void 2418 pccbb_pcmcia_socket_enable(pch) 2419 pcmcia_chipset_handle_t pch; 2420 { 2421 struct pcic_handle *ph = (struct pcic_handle *)pch; 2422 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2423 pcireg_t spsr; 2424 int voltage; 2425 int win; 2426 u_int8_t power, intr; 2427 #ifdef DIAGNOSTIC 2428 int reg; 2429 #endif 2430 2431 /* this bit is mostly stolen from pcic_attach_card */ 2432 2433 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2434 2435 /* get card Vcc info */ 2436 spsr = 2437 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2438 CB_SOCKET_STAT); 2439 if (spsr & CB_SOCKET_STAT_5VCARD) { 2440 DPRINTF(("5V card\n")); 2441 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2442 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2443 DPRINTF(("3V card\n")); 2444 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2445 } else { 2446 printf("?V card, 0x%x\n", spsr); /* XXX */ 2447 return; 2448 } 2449 2450 /* disable interrupts; assert RESET */ 2451 intr = Pcic_read(ph, PCIC_INTR); 2452 intr &= PCIC_INTR_ENABLE; 2453 Pcic_write(ph, PCIC_INTR, intr); 2454 2455 /* zero out the address windows */ 2456 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2457 2458 /* power down the socket to reset it, clear the card reset pin */ 2459 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2460 2461 /* power off; assert output enable bit */ 2462 power = PCIC_PWRCTL_OE; 2463 Pcic_write(ph, PCIC_PWRCTL, power); 2464 2465 /* power up the socket */ 2466 if (pccbb_power(sc, voltage) == 0) 2467 return; 2468 2469 /* 2470 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2471 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2472 * RESET Width (Th (Hi-z RESET)) = 1ms 2473 * RESET Width (Tw (RESET)) = 10us 2474 */ 2475 pccbb_pcmcia_delay(ph, 1, "pccen1"); 2476 2477 /* negate RESET */ 2478 intr |= PCIC_INTR_RESET; 2479 Pcic_write(ph, PCIC_INTR, intr); 2480 2481 /* 2482 * RESET Setup Time (Tsu (RESET)) = 20ms 2483 */ 2484 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2485 2486 #ifdef DIAGNOSTIC 2487 reg = Pcic_read(ph, PCIC_IF_STATUS); 2488 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2489 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2490 #endif 2491 2492 /* wait for the chip to finish initializing */ 2493 if (pccbb_pcmcia_wait_ready(ph)) { 2494 /* XXX return a failure status?? */ 2495 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2496 Pcic_write(ph, PCIC_PWRCTL, 0); 2497 return; 2498 } 2499 2500 /* reinstall all the memory and io mappings */ 2501 for (win = 0; win < PCIC_MEM_WINS; ++win) 2502 if (ph->memalloc & (1 << win)) 2503 pccbb_pcmcia_do_mem_map(ph, win); 2504 for (win = 0; win < PCIC_IO_WINS; ++win) 2505 if (ph->ioalloc & (1 << win)) 2506 pccbb_pcmcia_do_io_map(ph, win); 2507 } 2508 2509 /* 2510 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2511 * 2512 * This function disables the card. All information is stored in 2513 * the first argument, pcmcia_chipset_handle_t. 2514 */ 2515 STATIC void 2516 pccbb_pcmcia_socket_disable(pch) 2517 pcmcia_chipset_handle_t pch; 2518 { 2519 struct pcic_handle *ph = (struct pcic_handle *)pch; 2520 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2521 u_int8_t intr; 2522 2523 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2524 2525 /* disable interrupts; assert RESET */ 2526 intr = Pcic_read(ph, PCIC_INTR); 2527 intr &= PCIC_INTR_ENABLE; 2528 Pcic_write(ph, PCIC_INTR, intr); 2529 2530 /* zero out the address windows */ 2531 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2532 2533 /* power down the socket to reset it, clear the card reset pin */ 2534 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2535 2536 /* disable socket: negate output enable bit and power off */ 2537 Pcic_write(ph, PCIC_PWRCTL, 0); 2538 2539 /* 2540 * Vcc Falling Time (Tpf) = 300ms 2541 */ 2542 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2543 } 2544 2545 STATIC void 2546 pccbb_pcmcia_socket_settype(pch, type) 2547 pcmcia_chipset_handle_t pch; 2548 int type; 2549 { 2550 struct pcic_handle *ph = (struct pcic_handle *)pch; 2551 u_int8_t intr; 2552 2553 /* set the card type */ 2554 2555 intr = Pcic_read(ph, PCIC_INTR); 2556 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2557 if (type == PCMCIA_IFTYPE_IO) 2558 intr |= PCIC_INTR_CARDTYPE_IO; 2559 else 2560 intr |= PCIC_INTR_CARDTYPE_MEM; 2561 Pcic_write(ph, PCIC_INTR, intr); 2562 2563 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2564 ph->ph_parent->dv_xname, ph->sock, 2565 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2566 } 2567 2568 /* 2569 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2570 * 2571 * This function detects whether a card is in the slot or not. 2572 * If a card is inserted, return 1. Otherwise, return 0. 2573 */ 2574 STATIC int 2575 pccbb_pcmcia_card_detect(pch) 2576 pcmcia_chipset_handle_t pch; 2577 { 2578 struct pcic_handle *ph = (struct pcic_handle *)pch; 2579 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2580 2581 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2582 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2583 } 2584 2585 #if 0 2586 STATIC int 2587 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2588 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2589 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2590 #endif 2591 /* 2592 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2593 * bus_size_t size, 2594 * struct pcmcia_mem_handle *pcmhp) 2595 * 2596 * This function only allocates memory region for pccard. This 2597 * function never maps the allocated region to pccard memory area. 2598 * 2599 * XXX: Why the argument of start address is not in? 2600 */ 2601 STATIC int 2602 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2603 pcmcia_chipset_handle_t pch; 2604 bus_size_t size; 2605 struct pcmcia_mem_handle *pcmhp; 2606 { 2607 struct pcic_handle *ph = (struct pcic_handle *)pch; 2608 bus_space_handle_t memh; 2609 bus_addr_t addr; 2610 bus_size_t sizepg; 2611 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2612 #if rbus 2613 rbus_tag_t rb; 2614 #endif 2615 2616 /* Check that the card is still there. */ 2617 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2618 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2619 return 1; 2620 2621 /* out of sc->memh, allocate as many pages as necessary */ 2622 2623 /* convert size to PCIC pages */ 2624 /* 2625 * This is not enough; when the requested region is on the page 2626 * boundaries, this may calculate wrong result. 2627 */ 2628 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2629 #if 0 2630 if (sizepg > PCIC_MAX_MEM_PAGES) { 2631 return 1; 2632 } 2633 #endif 2634 2635 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2636 return 1; 2637 } 2638 2639 addr = 0; /* XXX gcc -Wuninitialized */ 2640 2641 #if rbus 2642 rb = sc->sc_rbus_memt; 2643 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2644 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2645 &addr, &memh)) { 2646 return 1; 2647 } 2648 #else 2649 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2650 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2651 0, /* boundary */ 2652 0, /* flags */ 2653 &addr, &memh)) { 2654 return 1; 2655 } 2656 #endif 2657 2658 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2659 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2660 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2661 2662 pcmhp->memt = sc->sc_memt; 2663 pcmhp->memh = memh; 2664 pcmhp->addr = addr; 2665 pcmhp->size = size; 2666 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2667 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2668 pcmhp->mhandle = 0; 2669 /* No offset??? Funny. */ 2670 2671 return 0; 2672 } 2673 2674 /* 2675 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2676 * struct pcmcia_mem_handle *pcmhp) 2677 * 2678 * This function release the memory space allocated by the function 2679 * pccbb_pcmcia_mem_alloc(). 2680 */ 2681 STATIC void 2682 pccbb_pcmcia_mem_free(pch, pcmhp) 2683 pcmcia_chipset_handle_t pch; 2684 struct pcmcia_mem_handle *pcmhp; 2685 { 2686 #if rbus 2687 struct pcic_handle *ph = (struct pcic_handle *)pch; 2688 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2689 2690 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2691 #else 2692 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2693 #endif 2694 } 2695 2696 /* 2697 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2698 * 2699 * This function release the memory space allocated by the function 2700 * pccbb_pcmcia_mem_alloc(). 2701 */ 2702 STATIC void 2703 pccbb_pcmcia_do_mem_map(ph, win) 2704 struct pcic_handle *ph; 2705 int win; 2706 { 2707 int regbase_win; 2708 bus_addr_t phys_addr; 2709 bus_addr_t phys_end; 2710 2711 #define PCIC_SMM_START_LOW 0 2712 #define PCIC_SMM_START_HIGH 1 2713 #define PCIC_SMM_STOP_LOW 2 2714 #define PCIC_SMM_STOP_HIGH 3 2715 #define PCIC_CMA_LOW 4 2716 #define PCIC_CMA_HIGH 5 2717 2718 u_int8_t start_low, start_high = 0; 2719 u_int8_t stop_low, stop_high; 2720 u_int8_t off_low, off_high; 2721 u_int8_t mem_window; 2722 int reg; 2723 2724 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2725 int mem8 = 2726 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2727 || (kind == PCMCIA_MEM_ATTR); 2728 2729 regbase_win = 0x10 + win * 0x08; 2730 2731 phys_addr = ph->mem[win].addr; 2732 phys_end = phys_addr + ph->mem[win].size; 2733 2734 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2735 (unsigned long)phys_addr, (unsigned long)phys_end, 2736 (unsigned long)ph->mem[win].offset)); 2737 2738 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2739 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2740 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2741 2742 /* bit 19:12 */ 2743 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2744 /* bit 23:20 and bit 7 on */ 2745 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2746 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2747 /* bit 31:24, for 32-bit address */ 2748 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2749 2750 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2751 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2752 2753 if (((struct pccbb_softc *)ph-> 2754 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2755 Pcic_write(ph, 0x40 + win, mem_window); 2756 } 2757 2758 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2759 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2760 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2761 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2762 2763 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2764 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2765 2766 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2767 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2768 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2769 | ((kind == PCMCIA_MEM_ATTR) ? 2770 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2771 2772 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2773 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2774 2775 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2776 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2777 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2778 2779 #if defined CBB_DEBUG 2780 { 2781 int r1, r2, r3, r4, r5, r6, r7 = 0; 2782 2783 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2784 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2785 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2786 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2787 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2788 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2789 if (((struct pccbb_softc *)(ph-> 2790 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2791 r7 = Pcic_read(ph, 0x40 + win); 2792 } 2793 2794 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2795 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2796 if (((struct pccbb_softc *)(ph-> 2797 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2798 DPRINTF((" %02x", r7)); 2799 } 2800 DPRINTF(("\n")); 2801 } 2802 #endif 2803 } 2804 2805 /* 2806 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2807 * bus_addr_t card_addr, bus_size_t size, 2808 * struct pcmcia_mem_handle *pcmhp, 2809 * bus_addr_t *offsetp, int *windowp) 2810 * 2811 * This function maps memory space allocated by the function 2812 * pccbb_pcmcia_mem_alloc(). 2813 */ 2814 STATIC int 2815 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2816 pcmcia_chipset_handle_t pch; 2817 int kind; 2818 bus_addr_t card_addr; 2819 bus_size_t size; 2820 struct pcmcia_mem_handle *pcmhp; 2821 bus_addr_t *offsetp; 2822 int *windowp; 2823 { 2824 struct pcic_handle *ph = (struct pcic_handle *)pch; 2825 bus_addr_t busaddr; 2826 long card_offset; 2827 int win; 2828 2829 /* Check that the card is still there. */ 2830 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2831 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2832 return 1; 2833 2834 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2835 if ((ph->memalloc & (1 << win)) == 0) { 2836 ph->memalloc |= (1 << win); 2837 break; 2838 } 2839 } 2840 2841 if (win == PCIC_MEM_WINS) { 2842 return 1; 2843 } 2844 2845 *windowp = win; 2846 2847 /* XXX this is pretty gross */ 2848 2849 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2850 panic("pccbb_pcmcia_mem_map memt is bogus"); 2851 } 2852 2853 busaddr = pcmhp->addr; 2854 2855 /* 2856 * compute the address offset to the pcmcia address space for the 2857 * pcic. this is intentionally signed. The masks and shifts below 2858 * will cause TRT to happen in the pcic registers. Deal with making 2859 * sure the address is aligned, and return the alignment offset. 2860 */ 2861 2862 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2863 card_addr -= *offsetp; 2864 2865 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2866 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2867 (u_long) card_addr)); 2868 2869 /* 2870 * include the offset in the size, and decrement size by one, since 2871 * the hw wants start/stop 2872 */ 2873 size += *offsetp - 1; 2874 2875 card_offset = (((long)card_addr) - ((long)busaddr)); 2876 2877 ph->mem[win].addr = busaddr; 2878 ph->mem[win].size = size; 2879 ph->mem[win].offset = card_offset; 2880 ph->mem[win].kind = kind; 2881 2882 pccbb_pcmcia_do_mem_map(ph, win); 2883 2884 return 0; 2885 } 2886 2887 /* 2888 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2889 * int window) 2890 * 2891 * This function unmaps memory space which mapped by the function 2892 * pccbb_pcmcia_mem_map(). 2893 */ 2894 STATIC void 2895 pccbb_pcmcia_mem_unmap(pch, window) 2896 pcmcia_chipset_handle_t pch; 2897 int window; 2898 { 2899 struct pcic_handle *ph = (struct pcic_handle *)pch; 2900 int reg; 2901 2902 if (window >= PCIC_MEM_WINS) { 2903 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2904 } 2905 2906 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2907 reg &= ~(1 << window); 2908 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2909 2910 ph->memalloc &= ~(1 << window); 2911 } 2912 2913 #if defined PCCBB_PCMCIA_POLL 2914 struct pccbb_poll_str { 2915 void *arg; 2916 int (*func)(void *); 2917 int level; 2918 struct pcic_handle *ph; 2919 int count; 2920 int num; 2921 struct callout poll_ch; 2922 }; 2923 2924 static struct pccbb_poll_str pccbb_poll[10]; 2925 static int pccbb_poll_n = 0; 2926 2927 static void pccbb_pcmcia_poll(void *arg); 2928 2929 static void 2930 pccbb_pcmcia_poll(arg) 2931 void *arg; 2932 { 2933 struct pccbb_poll_str *poll = arg; 2934 struct pcic_handle *ph = poll->ph; 2935 struct pccbb_softc *sc = ph->sc; 2936 int s; 2937 u_int32_t spsr; /* socket present-state reg */ 2938 2939 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2940 switch (poll->level) { 2941 case IPL_NET: 2942 s = splnet(); 2943 break; 2944 case IPL_BIO: 2945 s = splbio(); 2946 break; 2947 case IPL_TTY: /* fallthrough */ 2948 default: 2949 s = spltty(); 2950 break; 2951 } 2952 2953 spsr = 2954 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2955 CB_SOCKET_STAT); 2956 2957 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2958 if (!(spsr & 0x40)) /* CINT low */ 2959 #else 2960 if (1) 2961 #endif 2962 { 2963 if ((*poll->func) (poll->arg) > 0) { 2964 ++poll->count; 2965 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2966 #if defined LEVEL2 2967 } else { 2968 printf("intr: miss! 0x%x\n", spsr); 2969 #endif 2970 } 2971 } 2972 splx(s); 2973 } 2974 #endif /* defined CB_PCMCIA_POLL */ 2975 2976 /* 2977 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2978 * struct pcmcia_function *pf, 2979 * int ipl, 2980 * int (*func)(void *), 2981 * void *arg); 2982 * 2983 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2984 */ 2985 STATIC void * 2986 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2987 pcmcia_chipset_handle_t pch; 2988 struct pcmcia_function *pf; 2989 int ipl; 2990 int (*func)(void *); 2991 void *arg; 2992 { 2993 struct pcic_handle *ph = (struct pcic_handle *)pch; 2994 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2995 2996 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2997 /* what should I do? */ 2998 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2999 DPRINTF(("%s does not provide edge nor pulse " 3000 "interrupt\n", sc->sc_dev.dv_xname)); 3001 return NULL; 3002 } 3003 /* 3004 * XXX Noooooo! The interrupt flag must set properly!! 3005 * dumb pcmcia driver!! 3006 */ 3007 } 3008 3009 return pccbb_intr_establish(sc, 0, ipl, func, arg); 3010 } 3011 3012 /* 3013 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 3014 * void *ih) 3015 * 3016 * This function disables PC-Card interrupt. 3017 */ 3018 STATIC void 3019 pccbb_pcmcia_intr_disestablish(pch, ih) 3020 pcmcia_chipset_handle_t pch; 3021 void *ih; 3022 { 3023 struct pcic_handle *ph = (struct pcic_handle *)pch; 3024 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3025 3026 pccbb_intr_disestablish(sc, ih); 3027 } 3028 3029 #if rbus 3030 /* 3031 * static int 3032 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3033 * bus_addr_t addr, bus_size_t size, 3034 * bus_addr_t mask, bus_size_t align, 3035 * int flags, bus_addr_t *addrp; 3036 * bus_space_handle_t *bshp) 3037 * 3038 * This function allocates a portion of memory or io space for 3039 * clients. This function is called from CardBus card drivers. 3040 */ 3041 static int 3042 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3043 cardbus_chipset_tag_t ct; 3044 rbus_tag_t rb; 3045 bus_addr_t addr; 3046 bus_size_t size; 3047 bus_addr_t mask; 3048 bus_size_t align; 3049 int flags; 3050 bus_addr_t *addrp; 3051 bus_space_handle_t *bshp; 3052 { 3053 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3054 3055 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3056 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3057 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3058 3059 if (align == 0) { 3060 align = size; 3061 } 3062 3063 if (rb->rb_bt == sc->sc_memt) { 3064 if (align < 16) { 3065 return 1; 3066 } 3067 /* 3068 * XXX: align more than 0x1000 to avoid overwrapping 3069 * memory windows for two or more devices. 0x1000 3070 * means memory window's granularity. 3071 * 3072 * Two or more devices should be able to share same 3073 * memory window region. However, overrapping memory 3074 * window is not good because some devices, such as 3075 * 3Com 3C575[BC], have a broken address decoder and 3076 * intrude other's memory region. 3077 */ 3078 if (align < 0x1000) { 3079 align = 0x1000; 3080 } 3081 } else if (rb->rb_bt == sc->sc_iot) { 3082 if (align < 4) { 3083 return 1; 3084 } 3085 /* XXX: hack for avoiding ISA image */ 3086 if (mask < 0x0100) { 3087 mask = 0x3ff; 3088 addr = 0x300; 3089 } 3090 3091 } else { 3092 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3093 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3094 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3095 (unsigned long)sc->sc_memt)); 3096 return 1; 3097 /* XXX: panic here? */ 3098 } 3099 3100 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3101 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3102 return 1; 3103 } 3104 3105 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3106 3107 return 0; 3108 } 3109 3110 /* 3111 * static int 3112 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3113 * bus_space_handle_t *bshp, bus_size_t size); 3114 * 3115 * This function is called from CardBus card drivers. 3116 */ 3117 static int 3118 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3119 cardbus_chipset_tag_t ct; 3120 rbus_tag_t rb; 3121 bus_space_handle_t bsh; 3122 bus_size_t size; 3123 { 3124 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3125 bus_space_tag_t bt = rb->rb_bt; 3126 3127 pccbb_close_win(sc, bt, bsh, size); 3128 3129 if (bt == sc->sc_memt) { 3130 } else if (bt == sc->sc_iot) { 3131 } else { 3132 return 1; 3133 /* XXX: panic here? */ 3134 } 3135 3136 return rbus_space_free(rb, bsh, size, NULL); 3137 } 3138 #endif /* rbus */ 3139 3140 #if rbus 3141 3142 static int 3143 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3144 struct pccbb_softc *sc; 3145 bus_space_tag_t bst; 3146 bus_addr_t addr; 3147 bus_size_t size; 3148 bus_space_handle_t bsh; 3149 int flags; 3150 { 3151 struct pccbb_win_chain_head *head; 3152 bus_addr_t align; 3153 3154 head = &sc->sc_iowindow; 3155 align = 0x04; 3156 if (sc->sc_memt == bst) { 3157 head = &sc->sc_memwindow; 3158 align = 0x1000; 3159 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3160 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3161 (unsigned long)bst)); 3162 } 3163 3164 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3165 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3166 sc->sc_dev.dv_xname, 3167 (head == &sc->sc_memwindow) ? "mem" : "io"); 3168 } 3169 pccbb_winset(align, sc, bst); 3170 3171 return 0; 3172 } 3173 3174 static int 3175 pccbb_close_win(sc, bst, bsh, size) 3176 struct pccbb_softc *sc; 3177 bus_space_tag_t bst; 3178 bus_space_handle_t bsh; 3179 bus_size_t size; 3180 { 3181 struct pccbb_win_chain_head *head; 3182 bus_addr_t align; 3183 3184 head = &sc->sc_iowindow; 3185 align = 0x04; 3186 if (sc->sc_memt == bst) { 3187 head = &sc->sc_memwindow; 3188 align = 0x1000; 3189 } 3190 3191 if (pccbb_winlist_delete(head, bsh, size)) { 3192 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3193 sc->sc_dev.dv_xname, 3194 (head == &sc->sc_memwindow) ? "mem" : "io"); 3195 } 3196 pccbb_winset(align, sc, bst); 3197 3198 return 0; 3199 } 3200 3201 static int 3202 pccbb_winlist_insert(head, start, size, bsh, flags) 3203 struct pccbb_win_chain_head *head; 3204 bus_addr_t start; 3205 bus_size_t size; 3206 bus_space_handle_t bsh; 3207 int flags; 3208 { 3209 struct pccbb_win_chain *chainp, *elem; 3210 3211 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3212 M_NOWAIT)) == NULL) 3213 return (1); /* fail */ 3214 3215 elem->wc_start = start; 3216 elem->wc_end = start + (size - 1); 3217 elem->wc_handle = bsh; 3218 elem->wc_flags = flags; 3219 3220 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3221 chainp = TAILQ_NEXT(chainp, wc_list)) { 3222 if (chainp->wc_end < start) 3223 continue; 3224 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3225 return (0); 3226 } 3227 3228 TAILQ_INSERT_TAIL(head, elem, wc_list); 3229 return (0); 3230 } 3231 3232 static int 3233 pccbb_winlist_delete(head, bsh, size) 3234 struct pccbb_win_chain_head *head; 3235 bus_space_handle_t bsh; 3236 bus_size_t size; 3237 { 3238 struct pccbb_win_chain *chainp; 3239 3240 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3241 chainp = TAILQ_NEXT(chainp, wc_list)) { 3242 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3243 continue; 3244 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3245 printf("pccbb_winlist_delete: window 0x%lx size " 3246 "inconsistent: 0x%lx, 0x%lx\n", 3247 (unsigned long)chainp->wc_start, 3248 (unsigned long)(chainp->wc_end - chainp->wc_start), 3249 (unsigned long)(size - 1)); 3250 return 1; 3251 } 3252 3253 TAILQ_REMOVE(head, chainp, wc_list); 3254 free(chainp, M_DEVBUF); 3255 3256 return 0; 3257 } 3258 3259 return 1; /* fail: no candidate to remove */ 3260 } 3261 3262 static void 3263 pccbb_winset(align, sc, bst) 3264 bus_addr_t align; 3265 struct pccbb_softc *sc; 3266 bus_space_tag_t bst; 3267 { 3268 pci_chipset_tag_t pc; 3269 pcitag_t tag; 3270 bus_addr_t mask = ~(align - 1); 3271 struct { 3272 cardbusreg_t win_start; 3273 cardbusreg_t win_limit; 3274 int win_flags; 3275 } win[2]; 3276 struct pccbb_win_chain *chainp; 3277 int offs; 3278 3279 win[0].win_start = win[1].win_start = 0xffffffff; 3280 win[0].win_limit = win[1].win_limit = 0; 3281 win[0].win_flags = win[1].win_flags = 0; 3282 3283 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3284 offs = 0x2c; 3285 if (sc->sc_memt == bst) { 3286 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3287 offs = 0x1c; 3288 } 3289 3290 if (chainp != NULL) { 3291 win[0].win_start = chainp->wc_start & mask; 3292 win[0].win_limit = chainp->wc_end & mask; 3293 win[0].win_flags = chainp->wc_flags; 3294 chainp = TAILQ_NEXT(chainp, wc_list); 3295 } 3296 3297 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3298 if (win[1].win_start == 0xffffffff) { 3299 /* window 1 is not used */ 3300 if ((win[0].win_flags == chainp->wc_flags) && 3301 (win[0].win_limit + align >= 3302 (chainp->wc_start & mask))) { 3303 /* concatenate */ 3304 win[0].win_limit = chainp->wc_end & mask; 3305 } else { 3306 /* make new window */ 3307 win[1].win_start = chainp->wc_start & mask; 3308 win[1].win_limit = chainp->wc_end & mask; 3309 win[1].win_flags = chainp->wc_flags; 3310 } 3311 continue; 3312 } 3313 3314 /* Both windows are engaged. */ 3315 if (win[0].win_flags == win[1].win_flags) { 3316 /* same flags */ 3317 if (win[0].win_flags == chainp->wc_flags) { 3318 if (win[1].win_start - (win[0].win_limit + 3319 align) < 3320 (chainp->wc_start & mask) - 3321 ((chainp->wc_end & mask) + align)) { 3322 /* 3323 * merge window 0 and 1, and set win1 3324 * to chainp 3325 */ 3326 win[0].win_limit = win[1].win_limit; 3327 win[1].win_start = 3328 chainp->wc_start & mask; 3329 win[1].win_limit = 3330 chainp->wc_end & mask; 3331 } else { 3332 win[1].win_limit = 3333 chainp->wc_end & mask; 3334 } 3335 } else { 3336 /* different flags */ 3337 3338 /* concatenate win0 and win1 */ 3339 win[0].win_limit = win[1].win_limit; 3340 /* allocate win[1] to new space */ 3341 win[1].win_start = chainp->wc_start & mask; 3342 win[1].win_limit = chainp->wc_end & mask; 3343 win[1].win_flags = chainp->wc_flags; 3344 } 3345 } else { 3346 /* the flags of win[0] and win[1] is different */ 3347 if (win[0].win_flags == chainp->wc_flags) { 3348 win[0].win_limit = chainp->wc_end & mask; 3349 /* 3350 * XXX this creates overlapping windows, so 3351 * what should the poor bridge do if one is 3352 * cachable, and the other is not? 3353 */ 3354 printf("%s: overlapping windows\n", 3355 sc->sc_dev.dv_xname); 3356 } else { 3357 win[1].win_limit = chainp->wc_end & mask; 3358 } 3359 } 3360 } 3361 3362 pc = sc->sc_pc; 3363 tag = sc->sc_tag; 3364 pci_conf_write(pc, tag, offs, win[0].win_start); 3365 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3366 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3367 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3368 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3369 (unsigned long)pci_conf_read(pc, tag, offs), 3370 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3371 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3372 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3373 3374 if (bst == sc->sc_memt) { 3375 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3376 3377 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3378 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3379 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3380 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3381 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3382 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3383 } 3384 } 3385 3386 #endif /* rbus */ 3387 3388 static void 3389 pccbb_powerhook(why, arg) 3390 int why; 3391 void *arg; 3392 { 3393 struct pccbb_softc *sc = arg; 3394 pcireg_t reg; 3395 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3396 bus_space_handle_t base_memh = sc->sc_base_memh; 3397 3398 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3399 3400 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3401 DPRINTF(("%s: power: why %d stopping intr\n", 3402 sc->sc_dev.dv_xname, why)); 3403 if (sc->sc_pil_intr_enable) { 3404 (void)pccbbintr_function(sc); 3405 } 3406 sc->sc_pil_intr_enable = 0; 3407 3408 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3409 3410 /* ToDo: deactivate or suspend child devices */ 3411 3412 } 3413 3414 if (why == PWR_RESUME) { 3415 if (sc->sc_pwrmgt_offs != 0) { 3416 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3417 sc->sc_pwrmgt_offs + 4); 3418 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3419 reg & 0x100) { 3420 /* powrstate != D0 */ 3421 3422 printf("%s going back to D0 mode\n", 3423 sc->sc_dev.dv_xname); 3424 reg &= ~PCI_PMCSR_STATE_MASK; 3425 reg |= PCI_PMCSR_STATE_D0; 3426 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3427 pci_conf_write(sc->sc_pc, sc->sc_tag, 3428 sc->sc_pwrmgt_offs + 4, reg); 3429 3430 pci_conf_write(sc->sc_pc, sc->sc_tag, 3431 PCI_SOCKBASE, sc->sc_sockbase); 3432 pci_conf_write(sc->sc_pc, sc->sc_tag, 3433 PCI_BUSNUM, sc->sc_busnum); 3434 pccbb_chipinit(sc); 3435 /* setup memory and io space window for CB */ 3436 pccbb_winset(0x1000, sc, sc->sc_memt); 3437 pccbb_winset(0x04, sc, sc->sc_iot); 3438 goto norestore; 3439 } 3440 } 3441 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3442 norestore: 3443 3444 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3445 /* BIOS did not recover this register */ 3446 pci_conf_write (sc->sc_pc, sc->sc_tag, 3447 PCI_SOCKBASE, sc->sc_sockbase); 3448 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3449 /* BIOS did not recover this register */ 3450 pci_conf_write (sc->sc_pc, sc->sc_tag, 3451 PCI_BUSNUM, sc->sc_busnum); 3452 /* CSC Interrupt: Card detect interrupt on */ 3453 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3454 /* Card detect intr is turned on. */ 3455 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3456 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3457 /* reset interrupt */ 3458 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3459 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3460 3461 /* 3462 * check for card insertion or removal during suspend period. 3463 * XXX: the code can't cope with card swap (remove then 3464 * insert). how can we detect such situation? 3465 */ 3466 (void)pccbbintr(sc); 3467 3468 sc->sc_pil_intr_enable = 1; 3469 DPRINTF(("%s: power: RESUME enabling intr\n", 3470 sc->sc_dev.dv_xname)); 3471 3472 /* ToDo: activate or wakeup child devices */ 3473 } 3474 } 3475
Indexes created Thu Sep 25 16:09:42 GMT 2025