pccbb.c revision 1.124.2.6
1 /* $NetBSD: pccbb.c,v 1.124.2.6 2007/12/07 17:30:27 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.124.2.6 2007/12/07 17:30:27 yamt Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 /* 42 * BROKEN! 43 #define PCCBB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <sys/intr.h> 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 int pccbb_burstup = 1; 97 98 /* 99 * delay_ms() is wait in milliseconds. It should be used instead 100 * of delay() if you want to wait more than 1 ms. 101 */ 102 static inline void 103 delay_ms(int millis, void *param) 104 { 105 if (cold) 106 delay(millis * 1000); 107 else 108 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 109 } 110 111 int pcicbbmatch(struct device *, struct cfdata *, void *); 112 void pccbbattach(struct device *, struct device *, void *); 113 int pccbbintr(void *); 114 static void pci113x_insert(void *); 115 static int pccbbintr_function(struct pccbb_softc *); 116 117 static int pccbb_detect_card(struct pccbb_softc *); 118 119 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 120 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 121 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 122 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 123 124 STATIC int cb_reset(struct pccbb_softc *); 125 STATIC int cb_detect_voltage(struct pccbb_softc *); 126 STATIC int cbbprint(void *, const char *); 127 128 static int cb_chipset(u_int32_t, int *); 129 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 130 struct pcmciabus_attach_args *); 131 #if 0 132 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 133 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 134 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 135 #endif 136 137 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 138 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 139 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 140 #if !rbus 141 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 142 static int pccbb_io_close(cardbus_chipset_tag_t, int); 143 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 144 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 145 #endif /* !rbus */ 146 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 147 int level, int (*ih) (void *), void *sc); 148 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 149 150 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 151 int level, int (*ih) (void *), void *sc); 152 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 153 154 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 155 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 156 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 157 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 158 cardbusreg_t); 159 static void pccbb_chipinit(struct pccbb_softc *); 160 161 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 162 struct pcmcia_mem_handle *); 163 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 164 struct pcmcia_mem_handle *); 165 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 166 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 167 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 168 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 169 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 170 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 171 struct pcmcia_io_handle *); 172 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 173 bus_size_t, struct pcmcia_io_handle *, int *); 174 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 175 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 176 struct pcmcia_function *, int, int (*)(void *), void *); 177 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 178 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 179 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 180 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 181 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 182 183 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 184 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 185 186 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 187 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 188 static void pccbb_powerhook(int, void *); 189 190 /* bus-space allocation and deallocation functions */ 191 #if rbus 192 193 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 194 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 195 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 196 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 197 bus_space_handle_t, bus_size_t); 198 199 #endif /* rbus */ 200 201 #if rbus 202 203 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 204 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 205 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 206 bus_space_handle_t, bus_size_t); 207 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 208 bus_size_t, bus_space_handle_t, int); 209 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 210 bus_space_handle_t, bus_size_t); 211 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 212 bus_space_tag_t); 213 void pccbb_winlist_show(struct pccbb_win_chain *); 214 215 #endif /* rbus */ 216 217 /* for config_defer */ 218 static void pccbb_pci_callback(struct device *); 219 220 #if defined SHOW_REGS 221 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 222 bus_space_tag_t memt, bus_space_handle_t memh); 223 #endif 224 225 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 226 pcicbbmatch, pccbbattach, NULL, NULL); 227 228 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 229 pccbb_pcmcia_mem_alloc, 230 pccbb_pcmcia_mem_free, 231 pccbb_pcmcia_mem_map, 232 pccbb_pcmcia_mem_unmap, 233 pccbb_pcmcia_io_alloc, 234 pccbb_pcmcia_io_free, 235 pccbb_pcmcia_io_map, 236 pccbb_pcmcia_io_unmap, 237 pccbb_pcmcia_intr_establish, 238 pccbb_pcmcia_intr_disestablish, 239 pccbb_pcmcia_socket_enable, 240 pccbb_pcmcia_socket_disable, 241 pccbb_pcmcia_socket_settype, 242 pccbb_pcmcia_card_detect 243 }; 244 245 #if rbus 246 static struct cardbus_functions pccbb_funcs = { 247 pccbb_rbus_cb_space_alloc, 248 pccbb_rbus_cb_space_free, 249 pccbb_cb_intr_establish, 250 pccbb_cb_intr_disestablish, 251 pccbb_ctrl, 252 pccbb_power, 253 pccbb_make_tag, 254 pccbb_free_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #else 259 static struct cardbus_functions pccbb_funcs = { 260 pccbb_ctrl, 261 pccbb_power, 262 pccbb_mem_open, 263 pccbb_mem_close, 264 pccbb_io_open, 265 pccbb_io_close, 266 pccbb_cb_intr_establish, 267 pccbb_cb_intr_disestablish, 268 pccbb_make_tag, 269 pccbb_conf_read, 270 pccbb_conf_write, 271 }; 272 #endif 273 274 int 275 pcicbbmatch(struct device *parent, struct cfdata *match, void *aux) 276 { 277 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 278 279 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 280 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 281 PCI_INTERFACE(pa->pa_class) == 0) { 282 return 1; 283 } 284 285 return 0; 286 } 287 288 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 289 | ((prod) << PCI_PRODUCT_SHIFT)) 290 291 const struct yenta_chipinfo { 292 pcireg_t yc_id; /* vendor tag | product tag */ 293 int yc_chiptype; 294 int yc_flags; 295 } yc_chipsets[] = { 296 /* Texas Instruments chips */ 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 330 /* Ricoh chips */ 331 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 332 PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 344 /* Toshiba products */ 345 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 346 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 348 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 350 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 354 /* Cirrus Logic products */ 355 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 356 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 360 /* sentinel, or Generic chip */ 361 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 362 }; 363 364 static int 365 cb_chipset(u_int32_t pci_id, int *flagp) 366 { 367 const struct yenta_chipinfo *yc; 368 369 /* Loop over except the last default entry. */ 370 for (yc = yc_chipsets; yc < yc_chipsets + 371 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 372 if (pci_id == yc->yc_id) 373 break; 374 375 if (flagp != NULL) 376 *flagp = yc->yc_flags; 377 378 return (yc->yc_chiptype); 379 } 380 381 static void 382 pccbb_shutdown(void *arg) 383 { 384 struct pccbb_softc *sc = arg; 385 pcireg_t command; 386 387 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 388 389 /* 390 * turn off power 391 * 392 * XXX - do not turn off power if chipset is TI 113X because 393 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 394 */ 395 if (sc->sc_chipset != CB_TI113X) { 396 pccbb_power((cardbus_chipset_tag_t)sc, 397 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 398 } 399 400 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 401 0); 402 403 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 404 405 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 406 PCI_COMMAND_MASTER_ENABLE); 407 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 408 409 } 410 411 void 412 pccbbattach(struct device *parent, struct device *self, void *aux) 413 { 414 struct pccbb_softc *sc = (void *)self; 415 struct pci_attach_args *pa = aux; 416 pci_chipset_tag_t pc = pa->pa_pc; 417 pcireg_t busreg, reg, sock_base; 418 bus_addr_t sockbase; 419 char devinfo[256]; 420 int flags; 421 int pwrmgt_offs; 422 423 #ifdef __HAVE_PCCBB_ATTACH_HOOK 424 pccbb_attach_hook(parent, self, pa); 425 #endif 426 427 callout_init(&sc->sc_insert_ch, 0); 428 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 429 430 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 431 432 aprint_naive("\n"); 433 434 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 435 aprint_normal(": %s (rev. 0x%02x)", devinfo, 436 PCI_REVISION(pa->pa_class)); 437 DPRINTF((" (chipflags %x)", flags)); 438 aprint_normal("\n"); 439 440 TAILQ_INIT(&sc->sc_memwindow); 441 TAILQ_INIT(&sc->sc_iowindow); 442 443 #if rbus 444 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 445 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 446 447 #if 0 448 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 449 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 450 #endif 451 #endif /* rbus */ 452 453 sc->sc_flags &= ~CBB_MEMHMAPPED; 454 455 /* power management: set D0 state */ 456 sc->sc_pwrmgt_offs = 0; 457 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 458 &pwrmgt_offs, 0)) { 459 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 460 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 461 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 462 reg &= ~PCI_PMCSR_STATE_MASK; 463 reg |= PCI_PMCSR_STATE_D0; 464 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 465 pci_conf_write(pc, pa->pa_tag, 466 pwrmgt_offs + PCI_PMCSR, reg); 467 } 468 469 sc->sc_pwrmgt_offs = pwrmgt_offs; 470 } 471 472 /* 473 * MAP socket registers and ExCA registers on memory-space 474 * When no valid address is set on socket base registers (on pci 475 * config space), get it not polite way. 476 */ 477 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 478 479 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 480 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 481 /* The address must be valid. */ 482 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 483 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 484 aprint_error("%s: can't map socket base address 0x%lx\n", 485 sc->sc_dev.dv_xname, (unsigned long)sock_base); 486 /* 487 * I think it's funny: socket base registers must be 488 * mapped on memory space, but ... 489 */ 490 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 491 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 492 NULL)) { 493 aprint_error("%s: can't map socket base address" 494 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 495 (unsigned long)sockbase); 496 /* give up... allocate reg space via rbus. */ 497 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 498 } else 499 sc->sc_flags |= CBB_MEMHMAPPED; 500 } else { 501 DPRINTF(("%s: socket base address 0x%lx\n", 502 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 503 sc->sc_flags |= CBB_MEMHMAPPED; 504 } 505 } 506 507 sc->sc_mem_start = 0; /* XXX */ 508 sc->sc_mem_end = 0xffffffff; /* XXX */ 509 510 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 511 512 /* pccbb_machdep.c end */ 513 514 #if defined CBB_DEBUG 515 { 516 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 517 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 518 intrname[pa->pa_intrpin], pa->pa_intrline); 519 } 520 #endif 521 522 /* setup softc */ 523 sc->sc_pc = pc; 524 sc->sc_iot = pa->pa_iot; 525 sc->sc_memt = pa->pa_memt; 526 sc->sc_dmat = pa->pa_dmat; 527 sc->sc_tag = pa->pa_tag; 528 sc->sc_function = pa->pa_function; 529 sc->sc_sockbase = sock_base; 530 sc->sc_busnum = busreg; 531 532 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 533 534 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 535 536 shutdownhook_establish(pccbb_shutdown, sc); 537 538 /* Disable legacy register mapping. */ 539 switch (sc->sc_chipset) { 540 case CB_RX5C46X: /* fallthrough */ 541 #if 0 542 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 543 case CB_RX5C47X: 544 #endif 545 /* 546 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 547 * cannot be disabled by substituting 0 into PCI_LEGACY 548 * register. Ricoh CardBus bridges have special bits on Bridge 549 * control reg (addr 0x3e on PCI config space). 550 */ 551 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 552 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 553 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 554 break; 555 556 default: 557 /* XXX I don't know proper way to kill legacy I/O. */ 558 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 559 break; 560 } 561 562 config_defer(self, pccbb_pci_callback); 563 } 564 565 566 567 568 /* 569 * static void pccbb_pci_callback(struct device *self) 570 * 571 * The actual attach routine: get memory space for YENTA register 572 * space, setup YENTA register and route interrupt. 573 * 574 * This function should be deferred because this device may obtain 575 * memory space dynamically. This function must avoid obtaining 576 * memory area which has already kept for another device. 577 */ 578 static void 579 pccbb_pci_callback(struct device *self) 580 { 581 struct pccbb_softc *sc = (void *)self; 582 pci_chipset_tag_t pc = sc->sc_pc; 583 pci_intr_handle_t ih; 584 const char *intrstr = NULL; 585 bus_addr_t sockbase; 586 struct cbslot_attach_args cba; 587 struct pcmciabus_attach_args paa; 588 struct cardslot_attach_args caa; 589 struct cardslot_softc *csc; 590 591 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 592 /* The socket registers aren't mapped correctly. */ 593 #if rbus 594 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 595 (sc->sc_chipset == CB_RX5C47X 596 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 597 0, &sockbase, &sc->sc_base_memh)) { 598 return; 599 } 600 sc->sc_base_memt = sc->sc_memt; 601 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 602 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 603 sc->sc_dev.dv_xname, (unsigned long)sockbase, 604 (unsigned long)pci_conf_read(pc, sc->sc_tag, 605 PCI_SOCKBASE))); 606 #else 607 sc->sc_base_memt = sc->sc_memt; 608 #if !defined CBB_PCI_BASE 609 #define CBB_PCI_BASE 0x20000000 610 #endif 611 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 612 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 613 /* cannot allocate memory space */ 614 return; 615 } 616 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 617 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 618 sc->sc_dev.dv_xname, (unsigned long)sock_base, 619 (unsigned long)pci_conf_read(pc, 620 sc->sc_tag, PCI_SOCKBASE))); 621 sc->sc_sockbase = sockbase; 622 #endif 623 sc->sc_flags |= CBB_MEMHMAPPED; 624 } 625 626 /* bus bridge initialization */ 627 pccbb_chipinit(sc); 628 629 /* clear data structure for child device interrupt handlers */ 630 LIST_INIT(&sc->sc_pil); 631 sc->sc_pil_intr_enable = 1; 632 633 /* Map and establish the interrupt. */ 634 if (pci_intr_map(&sc->sc_pa, &ih)) { 635 aprint_error("%s: couldn't map interrupt\n", 636 sc->sc_dev.dv_xname); 637 return; 638 } 639 intrstr = pci_intr_string(pc, ih); 640 641 /* 642 * XXX pccbbintr should be called under the priority lower 643 * than any other hard interupts. 644 */ 645 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 646 647 if (sc->sc_ih == NULL) { 648 aprint_error("%s: couldn't establish interrupt", 649 sc->sc_dev.dv_xname); 650 if (intrstr != NULL) { 651 aprint_normal(" at %s", intrstr); 652 } 653 aprint_normal("\n"); 654 return; 655 } 656 657 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 658 powerhook_establish(sc->sc_dev.dv_xname, pccbb_powerhook, sc); 659 660 { 661 u_int32_t sockstat; 662 663 sockstat = bus_space_read_4(sc->sc_base_memt, 664 sc->sc_base_memh, CB_SOCKET_STAT); 665 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 666 sc->sc_flags |= CBB_CARDEXIST; 667 } 668 } 669 670 /* 671 * attach cardbus 672 */ 673 { 674 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 675 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 676 677 /* initialize cbslot_attach */ 678 cba.cba_busname = "cardbus"; 679 cba.cba_iot = sc->sc_iot; 680 cba.cba_memt = sc->sc_memt; 681 cba.cba_dmat = sc->sc_dmat; 682 cba.cba_bus = (busreg >> 8) & 0x0ff; 683 cba.cba_cc = (void *)sc; 684 cba.cba_cf = &pccbb_funcs; 685 cba.cba_intrline = sc->sc_pa.pa_intrline; 686 687 #if rbus 688 cba.cba_rbus_iot = sc->sc_rbus_iot; 689 cba.cba_rbus_memt = sc->sc_rbus_memt; 690 #endif 691 692 cba.cba_cacheline = PCI_CACHELINE(bhlc); 693 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 694 695 if (bootverbose) { 696 printf("%s: cacheline 0x%x lattimer 0x%x\n", 697 sc->sc_dev.dv_xname, cba.cba_cacheline, 698 cba.cba_max_lattimer); 699 printf("%s: bhlc 0x%x\n", 700 device_xname(&sc->sc_dev), bhlc); 701 } 702 #if defined SHOW_REGS 703 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 704 sc->sc_base_memh); 705 #endif 706 } 707 708 pccbb_pcmcia_attach_setup(sc, &paa); 709 caa.caa_cb_attach = NULL; 710 if (cba.cba_bus == 0) 711 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 712 else 713 caa.caa_cb_attach = &cba; 714 caa.caa_16_attach = &paa; 715 caa.caa_ph = &sc->sc_pcmcia_h; 716 717 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 718 DPRINTF(("%s: found cardslot\n", __func__)); 719 sc->sc_csc = csc; 720 } 721 722 return; 723 } 724 725 726 727 728 729 /* 730 * static void pccbb_chipinit(struct pccbb_softc *sc) 731 * 732 * This function initialize YENTA chip registers listed below: 733 * 1) PCI command reg, 734 * 2) PCI and CardBus latency timer, 735 * 3) route PCI interrupt, 736 * 4) close all memory and io windows. 737 * 5) turn off bus power. 738 * 6) card detect and power cycle interrupts on. 739 * 7) clear interrupt 740 */ 741 static void 742 pccbb_chipinit(struct pccbb_softc *sc) 743 { 744 pci_chipset_tag_t pc = sc->sc_pc; 745 pcitag_t tag = sc->sc_tag; 746 bus_space_tag_t bmt = sc->sc_base_memt; 747 bus_space_handle_t bmh = sc->sc_base_memh; 748 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 749 sockmask, sysctrl; 750 751 /* 752 * Set PCI command reg. 753 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 754 */ 755 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 756 /* I believe it is harmless. */ 757 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 758 PCI_COMMAND_MASTER_ENABLE); 759 csr |= (PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 760 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 761 762 /* 763 * Set CardBus latency timer. 764 */ 765 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 766 if (PCI_CB_LATENCY(lscp) < 0x20) { 767 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 768 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 769 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 770 } 771 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 772 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 773 774 /* 775 * Set PCI latency timer. 776 */ 777 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 778 if (PCI_LATTIMER(bhlc) < 0x10) { 779 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 780 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 781 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 782 } 783 DPRINTF(("PCI latency timer 0x%x (%x)\n", 784 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 785 786 787 /* Route functional interrupts to PCI. */ 788 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 789 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 790 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 791 /* assert reset */ 792 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 793 /* Set master abort mode to 1, forward SERR# from secondary 794 * to primary, and detect parity errors on secondary. 795 */ 796 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 797 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 798 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 799 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 800 801 switch (sc->sc_chipset) { 802 case CB_TI113X: 803 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 804 /* This bit is shared, but may read as 0 on some chips, so set 805 it explicitly on both functions. */ 806 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 807 /* CSC intr enable */ 808 cbctl |= PCI113X_CBCTRL_PCI_CSC; 809 /* functional intr prohibit | prohibit ISA routing */ 810 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 811 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 812 break; 813 814 case CB_TI1420: 815 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 816 mrburst = pccbb_burstup 817 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 818 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 819 printf("%s: %swrite bursts enabled\n", 820 device_xname(&sc->sc_dev), 821 pccbb_burstup ? "read/" : ""); 822 } else if (pccbb_burstup) { 823 printf("%s: enabling read/write bursts\n", 824 device_xname(&sc->sc_dev)); 825 sysctrl |= PCI1420_SYSCTRL_MRBURST; 826 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 827 } else { 828 printf("%s: disabling read bursts, " 829 "enabling write bursts\n", 830 device_xname(&sc->sc_dev)); 831 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 832 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 833 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 834 } 835 /*FALLTHROUGH*/ 836 case CB_TI12XX: 837 /* 838 * Some TI 12xx (and [14][45]xx) based pci cards 839 * sometimes have issues with the MFUNC register not 840 * being initialized due to a bad EEPROM on board. 841 * Laptops that this matters on have this register 842 * properly initialized. 843 * 844 * The TI125X parts have a different register. 845 */ 846 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 847 if (mfunc == 0) { 848 mfunc &= ~PCI12XX_MFUNC_PIN0; 849 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 850 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 851 PCI12XX_SYSCTRL_INTRTIE) == 0) { 852 mfunc &= ~PCI12XX_MFUNC_PIN1; 853 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 854 } 855 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 856 } 857 /* fallthrough */ 858 859 case CB_TI125X: 860 /* 861 * Disable zoom video. Some machines initialize this 862 * improperly and experience has shown that this helps 863 * prevent strange behavior. 864 */ 865 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 866 867 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 868 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 869 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 870 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 871 cbctl |= PCI12XX_CBCTRL_CSC; 872 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 873 break; 874 875 case CB_TOPIC95B: 876 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 877 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 878 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 879 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 880 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 881 sc->sc_dev.dv_xname, slotctl)); 882 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 883 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 884 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 885 DPRINTF(("0x%x\n", slotctl)); 886 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 887 break; 888 889 case CB_TOPIC97: 890 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 891 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 892 sc->sc_dev.dv_xname, slotctl)); 893 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 894 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 895 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 896 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 897 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 898 DPRINTF(("0x%x\n", slotctl)); 899 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 900 /* make sure to assert LV card support bits */ 901 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 902 0x800 + 0x3e, 903 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 904 0x800 + 0x3e) | 0x03); 905 break; 906 } 907 908 /* Close all memory and I/O windows. */ 909 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 910 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 911 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 912 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 913 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 914 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 915 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 916 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 917 918 /* reset 16-bit pcmcia bus */ 919 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 920 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 921 922 /* turn off power */ 923 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 924 925 /* CSC Interrupt: Card detect and power cycle interrupts on */ 926 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 927 sockmask |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 928 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 929 /* reset interrupt */ 930 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 931 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 932 } 933 934 935 936 937 /* 938 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 939 * struct pcmciabus_attach_args *paa) 940 * 941 * This function attaches 16-bit PCcard bus. 942 */ 943 STATIC void 944 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 945 struct pcmciabus_attach_args *paa) 946 { 947 struct pcic_handle *ph = &sc->sc_pcmcia_h; 948 #if rbus 949 rbus_tag_t rb; 950 #endif 951 952 /* initialize pcmcia part in pccbb_softc */ 953 ph->ph_parent = (struct device *)sc; 954 ph->sock = sc->sc_function; 955 ph->flags = 0; 956 ph->shutdown = 0; 957 ph->ih_irq = sc->sc_pa.pa_intrline; 958 ph->ph_bus_t = sc->sc_base_memt; 959 ph->ph_bus_h = sc->sc_base_memh; 960 ph->ph_read = pccbb_pcmcia_read; 961 ph->ph_write = pccbb_pcmcia_write; 962 sc->sc_pct = &pccbb_pcmcia_funcs; 963 964 /* 965 * We need to do a few things here: 966 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 967 * setting the IRQ numbers to 0. 968 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 969 * routing of CSC interrupts (e.g. card removal) to PCI while in 970 * PCMCIA mode. We just leave this set all the time. 971 * 3) Enable card insertion/removal interrupts in case the chip also 972 * needs that while in PCMCIA mode. 973 * 4) Clear any pending CSC interrupt. 974 */ 975 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 976 if (sc->sc_chipset == CB_TI113X) { 977 Pcic_write(ph, PCIC_CSC_INTR, 0); 978 } else { 979 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 980 Pcic_read(ph, PCIC_CSC); 981 } 982 983 /* initialize pcmcia bus attachment */ 984 paa->paa_busname = "pcmcia"; 985 paa->pct = sc->sc_pct; 986 paa->pch = ph; 987 paa->iobase = 0; /* I don't use them */ 988 paa->iosize = 0; 989 #if rbus 990 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 991 paa->iobase = rb->rb_start + rb->rb_offset; 992 paa->iosize = rb->rb_end - rb->rb_start; 993 #endif 994 995 return; 996 } 997 998 #if 0 999 STATIC void 1000 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 1001 { 1002 if (ph->flags & PCIC_FLAG_CARDP) { 1003 panic("pccbb_pcmcia_attach_card: already attached"); 1004 } 1005 1006 /* call the MI attach function */ 1007 pcmcia_card_attach(ph->pcmcia); 1008 1009 ph->flags |= PCIC_FLAG_CARDP; 1010 } 1011 1012 STATIC void 1013 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 1014 { 1015 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1016 panic("pccbb_pcmcia_detach_card: already detached"); 1017 } 1018 1019 ph->flags &= ~PCIC_FLAG_CARDP; 1020 1021 /* call the MI detach function */ 1022 pcmcia_card_detach(ph->pcmcia, flags); 1023 } 1024 #endif 1025 1026 /* 1027 * int pccbbintr(arg) 1028 * void *arg; 1029 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1030 * itself. 1031 */ 1032 int 1033 pccbbintr(void *arg) 1034 { 1035 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1036 u_int32_t sockevent, sockstate; 1037 bus_space_tag_t memt = sc->sc_base_memt; 1038 bus_space_handle_t memh = sc->sc_base_memh; 1039 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1040 1041 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1042 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1043 Pcic_read(ph, PCIC_CSC); 1044 1045 if (sockevent != 0) { 1046 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1047 sockevent); 1048 } 1049 1050 /* Sometimes a change of CSTSCHG# accompanies the first 1051 * interrupt from an Atheros WLAN. That generates a 1052 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1053 * isn't interesting to pccbb(4), so we used to ignore the 1054 * interrupt. Now, let the child devices try to handle 1055 * the interrupt, instead. The Atheros NIC produces 1056 * interrupts more reliably, now: used to be that it would 1057 * only interrupt if the driver avoided powering down the 1058 * NIC's cardslot, and then the NIC would only work after 1059 * it was reset a second time. 1060 */ 1061 if (sockevent == 0 || 1062 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1063 /* This intr is not for me: it may be for my child devices. */ 1064 if (sc->sc_pil_intr_enable) { 1065 return pccbbintr_function(sc); 1066 } else { 1067 return 0; 1068 } 1069 } 1070 1071 if (sockevent & CB_SOCKET_EVENT_CD) { 1072 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1073 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1074 /* A card should be removed. */ 1075 if (sc->sc_flags & CBB_CARDEXIST) { 1076 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1077 sockevent)); 1078 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1079 sc->sc_flags &= ~CBB_CARDEXIST; 1080 if (sc->sc_csc->sc_status & 1081 CARDSLOT_STATUS_CARD_16) { 1082 #if 0 1083 struct pcic_handle *ph = 1084 &sc->sc_pcmcia_h; 1085 1086 pcmcia_card_deactivate(ph->pcmcia); 1087 pccbb_pcmcia_socket_disable(ph); 1088 pccbb_pcmcia_detach_card(ph, 1089 DETACH_FORCE); 1090 #endif 1091 cardslot_event_throw(sc->sc_csc, 1092 CARDSLOT_EVENT_REMOVAL_16); 1093 } else if (sc->sc_csc->sc_status & 1094 CARDSLOT_STATUS_CARD_CB) { 1095 /* Cardbus intr removed */ 1096 cardslot_event_throw(sc->sc_csc, 1097 CARDSLOT_EVENT_REMOVAL_CB); 1098 } 1099 } else if (sc->sc_flags & CBB_INSERTING) { 1100 sc->sc_flags &= ~CBB_INSERTING; 1101 callout_stop(&sc->sc_insert_ch); 1102 } 1103 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1104 /* 1105 * The pccbbintr may called from powerdown hook when 1106 * the system resumed, to detect the card 1107 * insertion/removal during suspension. 1108 */ 1109 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1110 if (sc->sc_flags & CBB_INSERTING) { 1111 callout_stop(&sc->sc_insert_ch); 1112 } 1113 callout_schedule(&sc->sc_insert_ch, hz / 5); 1114 sc->sc_flags |= CBB_INSERTING; 1115 } 1116 } 1117 1118 /* XXX sockevent == 9 does occur in the wild. handle it. */ 1119 if (sockevent & CB_SOCKET_EVENT_POWER) { 1120 DPRINTF(("Powercycling because of socket event\n")); 1121 /* XXX: Does not happen when attaching a 16-bit card */ 1122 sc->sc_pwrcycle++; 1123 wakeup(&sc->sc_pwrcycle); 1124 } 1125 1126 return (1); 1127 } 1128 1129 /* 1130 * static int pccbbintr_function(struct pccbb_softc *sc) 1131 * 1132 * This function calls each interrupt handler registered at the 1133 * bridge. The interrupt handlers are called in registered order. 1134 */ 1135 static int 1136 pccbbintr_function(struct pccbb_softc *sc) 1137 { 1138 int retval = 0, val; 1139 struct pccbb_intrhand_list *pil; 1140 int s; 1141 1142 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1143 pil = LIST_NEXT(pil, pil_next)) { 1144 s = splraiseipl(pil->pil_icookie); 1145 val = (*pil->pil_func)(pil->pil_arg); 1146 splx(s); 1147 1148 retval = retval == 1 ? 1 : 1149 retval == 0 ? val : val != 0 ? val : retval; 1150 } 1151 1152 return retval; 1153 } 1154 1155 static void 1156 pci113x_insert(void *arg) 1157 { 1158 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1159 u_int32_t sockevent, sockstate; 1160 1161 if (!(sc->sc_flags & CBB_INSERTING)) { 1162 /* We add a card only under inserting state. */ 1163 return; 1164 } 1165 sc->sc_flags &= ~CBB_INSERTING; 1166 1167 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1168 CB_SOCKET_EVENT); 1169 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1170 CB_SOCKET_STAT); 1171 1172 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1173 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1174 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1175 sc->sc_flags |= CBB_CARDEXIST; 1176 /* call pccard interrupt handler here */ 1177 if (sockstate & CB_SOCKET_STAT_16BIT) { 1178 /* 16-bit card found */ 1179 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1180 cardslot_event_throw(sc->sc_csc, 1181 CARDSLOT_EVENT_INSERTION_16); 1182 } else if (sockstate & CB_SOCKET_STAT_CB) { 1183 /* cardbus card found */ 1184 /* cardbus_attach_card(sc->sc_csc); */ 1185 cardslot_event_throw(sc->sc_csc, 1186 CARDSLOT_EVENT_INSERTION_CB); 1187 } else { 1188 /* who are you? */ 1189 } 1190 } else { 1191 callout_schedule(&sc->sc_insert_ch, hz / 10); 1192 } 1193 } 1194 1195 #define PCCBB_PCMCIA_OFFSET 0x800 1196 static u_int8_t 1197 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1198 { 1199 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1200 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1201 1202 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1203 PCCBB_PCMCIA_OFFSET + reg); 1204 } 1205 1206 static void 1207 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, u_int8_t val) 1208 { 1209 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1210 val); 1211 1212 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1213 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1214 } 1215 1216 /* 1217 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1218 */ 1219 STATIC int 1220 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1221 { 1222 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1223 1224 switch (command) { 1225 case CARDBUS_CD: 1226 if (2 == pccbb_detect_card(sc)) { 1227 int retval = 0; 1228 int status = cb_detect_voltage(sc); 1229 if (PCCARD_VCC_5V & status) { 1230 retval |= CARDBUS_5V_CARD; 1231 } 1232 if (PCCARD_VCC_3V & status) { 1233 retval |= CARDBUS_3V_CARD; 1234 } 1235 if (PCCARD_VCC_XV & status) { 1236 retval |= CARDBUS_XV_CARD; 1237 } 1238 if (PCCARD_VCC_YV & status) { 1239 retval |= CARDBUS_YV_CARD; 1240 } 1241 return retval; 1242 } else { 1243 return 0; 1244 } 1245 case CARDBUS_RESET: 1246 return cb_reset(sc); 1247 case CARDBUS_IO_ENABLE: /* fallthrough */ 1248 case CARDBUS_IO_DISABLE: /* fallthrough */ 1249 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1250 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1251 case CARDBUS_BM_ENABLE: /* fallthrough */ 1252 case CARDBUS_BM_DISABLE: /* fallthrough */ 1253 /* XXX: I think we don't need to call this function below. */ 1254 return pccbb_cardenable(sc, command); 1255 } 1256 1257 return 0; 1258 } 1259 1260 /* 1261 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1262 * This function returns true when it succeeds and returns false when 1263 * it fails. 1264 */ 1265 STATIC int 1266 pccbb_power(cardbus_chipset_tag_t ct, int command) 1267 { 1268 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1269 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1270 bus_space_tag_t memt = sc->sc_base_memt; 1271 bus_space_handle_t memh = sc->sc_base_memh; 1272 int on = 0, pwrcycle, s, times; 1273 struct timeval before, after, diff; 1274 1275 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1276 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1277 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1278 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1279 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1280 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1281 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1282 "UNKNOWN", 1283 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1284 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1285 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1286 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1287 "UNKNOWN", command)); 1288 1289 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1290 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1291 1292 switch (command & CARDBUS_VCCMASK) { 1293 case CARDBUS_VCC_UC: 1294 break; 1295 case CARDBUS_VCC_5V: 1296 on++; 1297 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1298 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1299 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1300 } else { 1301 printf("%s: BAD voltage request: no 5 V card\n", 1302 sc->sc_dev.dv_xname); 1303 return 0; 1304 } 1305 break; 1306 case CARDBUS_VCC_3V: 1307 on++; 1308 if (CB_SOCKET_STAT_3VCARD & status) { 1309 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1310 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1311 } else { 1312 printf("%s: BAD voltage request: no 3.3 V card\n", 1313 sc->sc_dev.dv_xname); 1314 return 0; 1315 } 1316 break; 1317 case CARDBUS_VCC_0V: 1318 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1319 break; 1320 default: 1321 return 0; /* power NEVER changed */ 1322 } 1323 1324 switch (command & CARDBUS_VPPMASK) { 1325 case CARDBUS_VPP_UC: 1326 break; 1327 case CARDBUS_VPP_0V: 1328 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1329 break; 1330 case CARDBUS_VPP_VCC: 1331 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1332 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1333 break; 1334 case CARDBUS_VPP_12V: 1335 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1336 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1337 break; 1338 } 1339 1340 pwrcycle = sc->sc_pwrcycle; 1341 aprint_debug("%s: osock_ctrl %#" PRIx32 " sock_ctrl %#" PRIx32 "\n", 1342 device_xname(&sc->sc_dev), osock_ctrl, sock_ctrl); 1343 1344 microtime(&before); 1345 s = splbio(); 1346 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1347 1348 /* 1349 * Wait as long as 200ms for a power-cycle interrupt. If 1350 * interrupts are enabled, but the socket has already 1351 * changed to the desired status, keep waiting for the 1352 * interrupt. "Consuming" the interrupt in this way keeps 1353 * the interrupt from prematurely waking some subsequent 1354 * pccbb_power call. 1355 * 1356 * XXX Not every bridge interrupts on the ->OFF transition. 1357 * XXX That's ok, we will time-out after 200ms. 1358 * 1359 * XXX The power cycle event will never happen when attaching 1360 * XXX a 16-bit card. That's ok, we will time-out after 1361 * XXX 200ms. 1362 */ 1363 for (times = 5; --times >= 0; ) { 1364 if (cold) 1365 DELAY(40 * 1000); 1366 else { 1367 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1368 hz / 25); 1369 if (pwrcycle == sc->sc_pwrcycle) 1370 continue; 1371 } 1372 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1373 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1374 break; 1375 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1376 break; 1377 } 1378 splx(s); 1379 microtime(&after); 1380 timersub(&after, &before, &diff); 1381 aprint_debug("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1382 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1383 1384 /* 1385 * Ok, wait a bit longer for things to settle. 1386 */ 1387 if (on && sc->sc_chipset == CB_TOPIC95B) 1388 delay_ms(100, sc); 1389 1390 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1391 1392 if (on && sc->sc_chipset != CB_TOPIC95B) { 1393 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1394 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1395 } 1396 1397 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1398 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1399 sc->sc_dev.dv_xname, sock_ctrl, status); 1400 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1401 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1402 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1403 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1404 status &= ~CB_SOCKET_STAT_BADVCC; 1405 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1406 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1407 CB_SOCKET_STAT)); 1408 return 0; 1409 } 1410 1411 if (sc->sc_chipset == CB_TOPIC97) { 1412 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1413 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1414 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1415 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1416 else 1417 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1418 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1419 } 1420 1421 return 1; /* power changed correctly */ 1422 } 1423 1424 #if defined CB_PCMCIA_POLL 1425 struct cb_poll_str { 1426 void *arg; 1427 int (*func)(void *); 1428 int level; 1429 pccard_chipset_tag_t ct; 1430 int count; 1431 struct callout poll_ch; 1432 }; 1433 1434 static struct cb_poll_str cb_poll[10]; 1435 static int cb_poll_n = 0; 1436 1437 static void cb_pcmcia_poll(void *arg); 1438 1439 static void 1440 cb_pcmcia_poll(void *arg) 1441 { 1442 struct cb_poll_str *poll = arg; 1443 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1444 struct pccbb_softc *sc = psc->cpc_parent; 1445 int s; 1446 u_int32_t spsr; /* socket present-state reg */ 1447 1448 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1449 switch (poll->level) { 1450 case IPL_NET: 1451 s = splnet(); 1452 break; 1453 case IPL_BIO: 1454 s = splbio(); 1455 break; 1456 case IPL_TTY: /* fallthrough */ 1457 default: 1458 s = spltty(); 1459 break; 1460 } 1461 1462 spsr = 1463 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1464 CB_SOCKET_STAT); 1465 1466 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1467 if (!(spsr & 0x40)) { /* CINT low */ 1468 #else 1469 if (1) { 1470 #endif 1471 if ((*poll->func) (poll->arg) == 1) { 1472 ++poll->count; 1473 printf("intr: reported from poller, 0x%x\n", spsr); 1474 #if defined LEVEL2 1475 } else { 1476 printf("intr: miss! 0x%x\n", spsr); 1477 #endif 1478 } 1479 } 1480 splx(s); 1481 } 1482 #endif /* defined CB_PCMCIA_POLL */ 1483 1484 /* 1485 * static int pccbb_detect_card(struct pccbb_softc *sc) 1486 * return value: 0 if no card exists. 1487 * 1 if 16-bit card exists. 1488 * 2 if cardbus card exists. 1489 */ 1490 static int 1491 pccbb_detect_card(struct pccbb_softc *sc) 1492 { 1493 bus_space_handle_t base_memh = sc->sc_base_memh; 1494 bus_space_tag_t base_memt = sc->sc_base_memt; 1495 u_int32_t sockstat = 1496 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1497 int retval = 0; 1498 1499 /* CD1 and CD2 asserted */ 1500 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1501 /* card must be present */ 1502 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1503 /* NOTACARD DEASSERTED */ 1504 if (CB_SOCKET_STAT_CB & sockstat) { 1505 /* CardBus mode */ 1506 retval = 2; 1507 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1508 /* 16-bit mode */ 1509 retval = 1; 1510 } 1511 } 1512 } 1513 return retval; 1514 } 1515 1516 /* 1517 * STATIC int cb_reset(struct pccbb_softc *sc) 1518 * This function resets CardBus card. 1519 */ 1520 STATIC int 1521 cb_reset(struct pccbb_softc *sc) 1522 { 1523 /* 1524 * Reset Assert at least 20 ms 1525 * Some machines request longer duration. 1526 */ 1527 int reset_duration = 1528 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1529 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1530 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1531 1532 /* Reset bit Assert (bit 6 at 0x3E) */ 1533 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1534 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1535 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1536 delay_ms(reset_duration, sc); 1537 1538 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1539 /* Reset bit Deassert (bit 6 at 0x3E) */ 1540 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1541 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1542 bcr); 1543 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1544 delay_ms(reset_duration, sc); 1545 aprint_debug("%s: end of delay\n", __func__); 1546 } 1547 /* No card found on the slot. Keep Reset. */ 1548 return 1; 1549 } 1550 1551 /* 1552 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1553 * This function detect card Voltage. 1554 */ 1555 STATIC int 1556 cb_detect_voltage(struct pccbb_softc *sc) 1557 { 1558 u_int32_t psr; /* socket present-state reg */ 1559 bus_space_tag_t iot = sc->sc_base_memt; 1560 bus_space_handle_t ioh = sc->sc_base_memh; 1561 int vol = PCCARD_VCC_UKN; /* set 0 */ 1562 1563 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1564 1565 if (0x400u & psr) { 1566 vol |= PCCARD_VCC_5V; 1567 } 1568 if (0x800u & psr) { 1569 vol |= PCCARD_VCC_3V; 1570 } 1571 1572 return vol; 1573 } 1574 1575 STATIC int 1576 cbbprint(void *aux, const char *pcic) 1577 { 1578 #if 0 1579 struct cbslot_attach_args *cba = aux; 1580 1581 if (cba->cba_slot >= 0) { 1582 aprint_normal(" slot %d", cba->cba_slot); 1583 } 1584 #endif 1585 return UNCONF; 1586 } 1587 1588 /* 1589 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1590 * This function enables and disables the card 1591 */ 1592 STATIC int 1593 pccbb_cardenable(struct pccbb_softc *sc, int function) 1594 { 1595 u_int32_t command = 1596 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1597 1598 DPRINTF(("pccbb_cardenable:")); 1599 switch (function) { 1600 case CARDBUS_IO_ENABLE: 1601 command |= PCI_COMMAND_IO_ENABLE; 1602 break; 1603 case CARDBUS_IO_DISABLE: 1604 command &= ~PCI_COMMAND_IO_ENABLE; 1605 break; 1606 case CARDBUS_MEM_ENABLE: 1607 command |= PCI_COMMAND_MEM_ENABLE; 1608 break; 1609 case CARDBUS_MEM_DISABLE: 1610 command &= ~PCI_COMMAND_MEM_ENABLE; 1611 break; 1612 case CARDBUS_BM_ENABLE: 1613 command |= PCI_COMMAND_MASTER_ENABLE; 1614 break; 1615 case CARDBUS_BM_DISABLE: 1616 command &= ~PCI_COMMAND_MASTER_ENABLE; 1617 break; 1618 default: 1619 return 0; 1620 } 1621 1622 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1623 DPRINTF((" command reg 0x%x\n", command)); 1624 return 1; 1625 } 1626 1627 #if !rbus 1628 static int 1629 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1630 { 1631 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1632 int basereg; 1633 int limitreg; 1634 1635 if ((win < 0) || (win > 2)) { 1636 #if defined DIAGNOSTIC 1637 printf("cardbus_io_open: window out of range %d\n", win); 1638 #endif 1639 return 0; 1640 } 1641 1642 basereg = win * 8 + 0x2c; 1643 limitreg = win * 8 + 0x30; 1644 1645 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1646 start, basereg, end, limitreg)); 1647 1648 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1649 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1650 return 1; 1651 } 1652 1653 /* 1654 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1655 */ 1656 static int 1657 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1658 { 1659 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1660 int basereg; 1661 int limitreg; 1662 1663 if ((win < 0) || (win > 2)) { 1664 #if defined DIAGNOSTIC 1665 printf("cardbus_io_close: window out of range %d\n", win); 1666 #endif 1667 return 0; 1668 } 1669 1670 basereg = win * 8 + 0x2c; 1671 limitreg = win * 8 + 0x30; 1672 1673 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1674 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1675 return 1; 1676 } 1677 1678 static int 1679 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1680 { 1681 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1682 int basereg; 1683 int limitreg; 1684 1685 if ((win < 0) || (win > 2)) { 1686 #if defined DIAGNOSTIC 1687 printf("cardbus_mem_open: window out of range %d\n", win); 1688 #endif 1689 return 0; 1690 } 1691 1692 basereg = win * 8 + 0x1c; 1693 limitreg = win * 8 + 0x20; 1694 1695 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1696 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1697 return 1; 1698 } 1699 1700 static int 1701 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1702 { 1703 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1704 int basereg; 1705 int limitreg; 1706 1707 if ((win < 0) || (win > 2)) { 1708 #if defined DIAGNOSTIC 1709 printf("cardbus_mem_close: window out of range %d\n", win); 1710 #endif 1711 return 0; 1712 } 1713 1714 basereg = win * 8 + 0x1c; 1715 limitreg = win * 8 + 0x20; 1716 1717 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1718 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1719 return 1; 1720 } 1721 #endif 1722 1723 /* 1724 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1725 * int irq, 1726 * int level, 1727 * int (* func)(void *), 1728 * void *arg) 1729 * 1730 * This function registers an interrupt handler at the bridge, in 1731 * order not to call the interrupt handlers of child devices when 1732 * a card-deletion interrupt occurs. 1733 * 1734 * The arguments irq and level are not used. 1735 */ 1736 static void * 1737 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1738 int (*func)(void *), void *arg) 1739 { 1740 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1741 1742 return pccbb_intr_establish(sc, irq, level, func, arg); 1743 } 1744 1745 1746 /* 1747 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1748 * void *ih) 1749 * 1750 * This function removes an interrupt handler pointed by ih. 1751 */ 1752 static void 1753 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1754 { 1755 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1756 1757 pccbb_intr_disestablish(sc, ih); 1758 } 1759 1760 1761 void 1762 pccbb_intr_route(struct pccbb_softc *sc) 1763 { 1764 pcireg_t bcr, cbctrl; 1765 1766 /* initialize bridge intr routing */ 1767 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1768 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1769 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1770 1771 switch (sc->sc_chipset) { 1772 case CB_TI113X: 1773 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1774 /* functional intr enabled */ 1775 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1776 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1777 break; 1778 default: 1779 break; 1780 } 1781 } 1782 1783 /* 1784 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1785 * int irq, 1786 * int level, 1787 * int (* func)(void *), 1788 * void *arg) 1789 * 1790 * This function registers an interrupt handler at the bridge, in 1791 * order not to call the interrupt handlers of child devices when 1792 * a card-deletion interrupt occurs. 1793 * 1794 * The arguments irq is not used because pccbb selects intr vector. 1795 */ 1796 static void * 1797 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1798 int (*func)(void *), void *arg) 1799 { 1800 struct pccbb_intrhand_list *pil, *newpil; 1801 1802 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1803 1804 if (LIST_EMPTY(&sc->sc_pil)) { 1805 pccbb_intr_route(sc); 1806 } 1807 1808 /* 1809 * Allocate a room for interrupt handler structure. 1810 */ 1811 if (NULL == (newpil = 1812 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1813 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1814 return NULL; 1815 } 1816 1817 newpil->pil_func = func; 1818 newpil->pil_arg = arg; 1819 newpil->pil_icookie = makeiplcookie(level); 1820 1821 if (LIST_EMPTY(&sc->sc_pil)) { 1822 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1823 } else { 1824 for (pil = LIST_FIRST(&sc->sc_pil); 1825 LIST_NEXT(pil, pil_next) != NULL; 1826 pil = LIST_NEXT(pil, pil_next)); 1827 LIST_INSERT_AFTER(pil, newpil, pil_next); 1828 } 1829 1830 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1831 LIST_FIRST(&sc->sc_pil))); 1832 1833 return newpil; 1834 } 1835 1836 /* 1837 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1838 * void *ih) 1839 * 1840 * This function removes an interrupt handler pointed by ih. ih 1841 * should be the value returned by cardbus_intr_establish() or 1842 * NULL. 1843 * 1844 * When ih is NULL, this function will do nothing. 1845 */ 1846 static void 1847 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1848 { 1849 struct pccbb_intrhand_list *pil; 1850 pcireg_t reg; 1851 1852 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1853 LIST_FIRST(&sc->sc_pil))); 1854 1855 if (ih == NULL) { 1856 /* intr handler is not set */ 1857 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1858 return; 1859 } 1860 1861 #ifdef DIAGNOSTIC 1862 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1863 pil = LIST_NEXT(pil, pil_next)) { 1864 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1865 if (pil == ih) { 1866 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1867 break; 1868 } 1869 } 1870 if (pil == NULL) { 1871 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1872 sc->sc_dev.dv_xname, ih); 1873 } 1874 #endif 1875 1876 pil = (struct pccbb_intrhand_list *)ih; 1877 LIST_REMOVE(pil, pil_next); 1878 free(pil, M_DEVBUF); 1879 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1880 1881 if (LIST_EMPTY(&sc->sc_pil)) { 1882 /* No interrupt handlers */ 1883 1884 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1885 1886 /* stop routing PCI intr */ 1887 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1888 reg |= CB_BCR_INTR_IREQ_ENABLE; 1889 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1890 1891 switch (sc->sc_chipset) { 1892 case CB_TI113X: 1893 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1894 /* functional intr disabled */ 1895 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1896 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1897 break; 1898 default: 1899 break; 1900 } 1901 } 1902 } 1903 1904 #if defined SHOW_REGS 1905 static void 1906 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1907 bus_space_handle_t memh) 1908 { 1909 int i; 1910 printf("PCI config regs:"); 1911 for (i = 0; i < 0x50; i += 4) { 1912 if (i % 16 == 0) 1913 printf("\n 0x%02x:", i); 1914 printf(" %08x", pci_conf_read(pc, tag, i)); 1915 } 1916 for (i = 0x80; i < 0xb0; i += 4) { 1917 if (i % 16 == 0) 1918 printf("\n 0x%02x:", i); 1919 printf(" %08x", pci_conf_read(pc, tag, i)); 1920 } 1921 1922 if (memh == 0) { 1923 printf("\n"); 1924 return; 1925 } 1926 1927 printf("\nsocket regs:"); 1928 for (i = 0; i <= 0x10; i += 0x04) 1929 printf(" %08x", bus_space_read_4(memt, memh, i)); 1930 printf("\nExCA regs:"); 1931 for (i = 0; i < 0x08; ++i) 1932 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1933 printf("\n"); 1934 return; 1935 } 1936 #endif 1937 1938 /* 1939 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1940 * int busno, int function) 1941 * This is the function to make a tag to access config space of 1942 * a CardBus Card. It works same as pci_conf_read. 1943 */ 1944 static cardbustag_t 1945 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1946 { 1947 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1948 1949 return pci_make_tag(sc->sc_pc, busno, 0, function); 1950 } 1951 1952 static void 1953 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1954 { 1955 } 1956 1957 /* 1958 * pccbb_conf_read 1959 * 1960 * This is the function to read the config space of a CardBus card. 1961 * It works the same as pci_conf_read(9). 1962 */ 1963 static cardbusreg_t 1964 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1965 { 1966 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1967 1968 return pci_conf_read(sc->sc_pc, tag, offset); 1969 } 1970 1971 /* 1972 * pccbb_conf_write 1973 * 1974 * This is the function to write the config space of a CardBus 1975 * card. It works the same as pci_conf_write(9). 1976 */ 1977 static void 1978 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1979 cardbusreg_t val) 1980 { 1981 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1982 1983 pci_conf_write(sc->sc_pc, tag, reg, val); 1984 } 1985 1986 #if 0 1987 STATIC int 1988 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1989 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1990 int speed, int flags, 1991 bus_space_handle_t * iohp) 1992 #endif 1993 /* 1994 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1995 * bus_addr_t start, bus_size_t size, 1996 * bus_size_t align, 1997 * struct pcmcia_io_handle *pcihp 1998 * 1999 * This function only allocates I/O region for pccard. This function 2000 * never maps the allocated region to pccard I/O area. 2001 * 2002 * XXX: The interface of this function is not very good, I believe. 2003 */ 2004 STATIC int 2005 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 2006 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 2007 { 2008 struct pcic_handle *ph = (struct pcic_handle *)pch; 2009 bus_addr_t ioaddr; 2010 int flags = 0; 2011 bus_space_tag_t iot; 2012 bus_space_handle_t ioh; 2013 bus_addr_t mask; 2014 #if rbus 2015 rbus_tag_t rb; 2016 #endif 2017 if (align == 0) { 2018 align = size; /* XXX: funny??? */ 2019 } 2020 2021 if (start != 0) { 2022 /* XXX: assume all card decode lower 10 bits by its hardware */ 2023 mask = 0x3ff; 2024 /* enforce to use only masked address */ 2025 start &= mask; 2026 } else { 2027 /* 2028 * calculate mask: 2029 * 1. get the most significant bit of size (call it msb). 2030 * 2. compare msb with the value of size. 2031 * 3. if size is larger, shift msb left once. 2032 * 4. obtain mask value to decrement msb. 2033 */ 2034 bus_size_t size_tmp = size; 2035 int shifts = 0; 2036 2037 mask = 1; 2038 while (size_tmp) { 2039 ++shifts; 2040 size_tmp >>= 1; 2041 } 2042 mask = (1 << shifts); 2043 if (mask < size) { 2044 mask <<= 1; 2045 } 2046 --mask; 2047 } 2048 2049 /* 2050 * Allocate some arbitrary I/O space. 2051 */ 2052 2053 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2054 2055 #if rbus 2056 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2057 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2058 return 1; 2059 } 2060 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2061 (u_long) ioaddr, (u_long) size)); 2062 #else 2063 if (start) { 2064 ioaddr = start; 2065 if (bus_space_map(iot, start, size, 0, &ioh)) { 2066 return 1; 2067 } 2068 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2069 (u_long) ioaddr, (u_long) size)); 2070 } else { 2071 flags |= PCMCIA_IO_ALLOCATED; 2072 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2073 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2074 size, align, 0, 0, &ioaddr, &ioh)) { 2075 /* No room be able to be get. */ 2076 return 1; 2077 } 2078 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2079 (u_long) ioaddr, (u_long) size)); 2080 } 2081 #endif 2082 2083 pcihp->iot = iot; 2084 pcihp->ioh = ioh; 2085 pcihp->addr = ioaddr; 2086 pcihp->size = size; 2087 pcihp->flags = flags; 2088 2089 return 0; 2090 } 2091 2092 /* 2093 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2094 * struct pcmcia_io_handle *pcihp) 2095 * 2096 * This function only frees I/O region for pccard. 2097 * 2098 * XXX: The interface of this function is not very good, I believe. 2099 */ 2100 void 2101 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2102 struct pcmcia_io_handle *pcihp) 2103 { 2104 #if !rbus 2105 bus_space_tag_t iot = pcihp->iot; 2106 #endif 2107 bus_space_handle_t ioh = pcihp->ioh; 2108 bus_size_t size = pcihp->size; 2109 2110 #if rbus 2111 struct pccbb_softc *sc = 2112 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2113 rbus_tag_t rb = sc->sc_rbus_iot; 2114 2115 rbus_space_free(rb, ioh, size, NULL); 2116 #else 2117 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2118 bus_space_free(iot, ioh, size); 2119 else 2120 bus_space_unmap(iot, ioh, size); 2121 #endif 2122 } 2123 2124 /* 2125 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2126 * bus_addr_t offset, bus_size_t size, 2127 * struct pcmcia_io_handle *pcihp, 2128 * int *windowp) 2129 * 2130 * This function maps the allocated I/O region to pccard. This function 2131 * never allocates any I/O region for pccard I/O area. I don't 2132 * understand why the original authors of pcmciabus separated alloc and 2133 * map. I believe the two must be unite. 2134 * 2135 * XXX: no wait timing control? 2136 */ 2137 int 2138 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2139 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2140 { 2141 struct pcic_handle *ph = (struct pcic_handle *)pch; 2142 bus_addr_t ioaddr = pcihp->addr + offset; 2143 int i, win; 2144 #if defined CBB_DEBUG 2145 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2146 #endif 2147 2148 /* Sanity check I/O handle. */ 2149 2150 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2151 panic("pccbb_pcmcia_io_map iot is bogus"); 2152 } 2153 2154 /* XXX Sanity check offset/size. */ 2155 2156 win = -1; 2157 for (i = 0; i < PCIC_IO_WINS; i++) { 2158 if ((ph->ioalloc & (1 << i)) == 0) { 2159 win = i; 2160 ph->ioalloc |= (1 << i); 2161 break; 2162 } 2163 } 2164 2165 if (win == -1) { 2166 return 1; 2167 } 2168 2169 *windowp = win; 2170 2171 /* XXX this is pretty gross */ 2172 2173 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2174 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2175 2176 /* XXX wtf is this doing here? */ 2177 2178 #if 0 2179 printf(" port 0x%lx", (u_long) ioaddr); 2180 if (size > 1) { 2181 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2182 } 2183 #endif 2184 2185 ph->io[win].addr = ioaddr; 2186 ph->io[win].size = size; 2187 ph->io[win].width = width; 2188 2189 /* actual dirty register-value changing in the function below. */ 2190 pccbb_pcmcia_do_io_map(ph, win); 2191 2192 return 0; 2193 } 2194 2195 /* 2196 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2197 * 2198 * This function changes register-value to map I/O region for pccard. 2199 */ 2200 static void 2201 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 2202 { 2203 static u_int8_t pcic_iowidth[3] = { 2204 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2205 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2206 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2207 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2208 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2209 }; 2210 2211 #define PCIC_SIA_START_LOW 0 2212 #define PCIC_SIA_START_HIGH 1 2213 #define PCIC_SIA_STOP_LOW 2 2214 #define PCIC_SIA_STOP_HIGH 3 2215 2216 int regbase_win = 0x8 + win * 0x04; 2217 u_int8_t ioctl, enable; 2218 2219 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2220 "width %d\n", win, (unsigned long)ph->io[win].addr, 2221 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2222 2223 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2224 ph->io[win].addr & 0xff); 2225 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2226 (ph->io[win].addr >> 8) & 0xff); 2227 2228 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2229 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2230 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2231 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2232 2233 ioctl = Pcic_read(ph, PCIC_IOCTL); 2234 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2235 switch (win) { 2236 case 0: 2237 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2238 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2239 PCIC_IOCTL_IO0_DATASIZE_MASK); 2240 ioctl |= pcic_iowidth[ph->io[win].width]; 2241 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2242 break; 2243 case 1: 2244 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2245 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2246 PCIC_IOCTL_IO1_DATASIZE_MASK); 2247 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2248 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2249 break; 2250 } 2251 Pcic_write(ph, PCIC_IOCTL, ioctl); 2252 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2253 #if defined(CBB_DEBUG) 2254 { 2255 u_int8_t start_low = 2256 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2257 u_int8_t start_high = 2258 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2259 u_int8_t stop_low = 2260 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2261 u_int8_t stop_high = 2262 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2263 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2264 "stop %02x %02x, ioctl %02x enable %02x\n", 2265 start_low, start_high, stop_low, stop_high, ioctl, enable); 2266 } 2267 #endif 2268 } 2269 2270 /* 2271 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2272 * 2273 * This function unmaps I/O region. No return value. 2274 */ 2275 STATIC void 2276 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2277 { 2278 struct pcic_handle *ph = (struct pcic_handle *)pch; 2279 int reg; 2280 2281 if (win >= PCIC_IO_WINS || win < 0) { 2282 panic("pccbb_pcmcia_io_unmap: window out of range"); 2283 } 2284 2285 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2286 switch (win) { 2287 case 0: 2288 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2289 break; 2290 case 1: 2291 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2292 break; 2293 } 2294 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2295 2296 ph->ioalloc &= ~(1 << win); 2297 } 2298 2299 static int 2300 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2301 { 2302 u_int8_t stat; 2303 int i; 2304 2305 /* wait an initial 10ms for quick cards */ 2306 stat = Pcic_read(ph, PCIC_IF_STATUS); 2307 if (stat & PCIC_IF_STATUS_READY) 2308 return (0); 2309 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2310 for (i = 0; i < 50; i++) { 2311 stat = Pcic_read(ph, PCIC_IF_STATUS); 2312 if (stat & PCIC_IF_STATUS_READY) 2313 return (0); 2314 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2315 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2316 return (ENXIO); 2317 /* wait .1s (100ms) each iteration now */ 2318 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2319 } 2320 2321 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2322 return (EWOULDBLOCK); 2323 } 2324 2325 /* 2326 * Perform long (msec order) delay. timo is in milliseconds. 2327 */ 2328 static void 2329 pccbb_pcmcia_delay(struct pcic_handle *ph, int timo, const char *wmesg) 2330 { 2331 #ifdef DIAGNOSTIC 2332 if (timo <= 0) 2333 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2334 if (!curlwp) 2335 panic("pccbb_pcmcia_delay: called in interrupt context"); 2336 #if 0 2337 if (!ph->event_thread) 2338 panic("pccbb_pcmcia_delay: no event thread"); 2339 #endif 2340 #endif 2341 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2342 wmesg, ph->event_thread, timo)); 2343 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2344 } 2345 2346 /* 2347 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2348 * 2349 * This function enables the card. All information is stored in 2350 * the first argument, pcmcia_chipset_handle_t. 2351 */ 2352 STATIC void 2353 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2354 { 2355 struct pcic_handle *ph = (struct pcic_handle *)pch; 2356 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2357 pcireg_t spsr; 2358 int voltage; 2359 int win; 2360 u_int8_t power, intr; 2361 #ifdef DIAGNOSTIC 2362 int reg; 2363 #endif 2364 2365 /* this bit is mostly stolen from pcic_attach_card */ 2366 2367 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2368 2369 /* get card Vcc info */ 2370 spsr = 2371 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2372 CB_SOCKET_STAT); 2373 if (spsr & CB_SOCKET_STAT_5VCARD) { 2374 DPRINTF(("5V card\n")); 2375 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2376 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2377 DPRINTF(("3V card\n")); 2378 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2379 } else { 2380 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2381 return; 2382 } 2383 2384 /* disable interrupts; assert RESET */ 2385 intr = Pcic_read(ph, PCIC_INTR); 2386 intr &= PCIC_INTR_ENABLE; 2387 Pcic_write(ph, PCIC_INTR, intr); 2388 2389 /* zero out the address windows */ 2390 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2391 2392 /* power down the socket to reset it, clear the card reset pin */ 2393 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2394 2395 /* power off; assert output enable bit */ 2396 power = PCIC_PWRCTL_OE; 2397 Pcic_write(ph, PCIC_PWRCTL, power); 2398 2399 /* power up the socket */ 2400 if (pccbb_power(sc, voltage) == 0) 2401 return; 2402 2403 /* 2404 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2405 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2406 * RESET Width (Th (Hi-z RESET)) = 1ms 2407 * RESET Width (Tw (RESET)) = 10us 2408 * 2409 * some machines require some more time to be settled 2410 * for example old toshiba topic bridges! 2411 * (100ms is added here). 2412 */ 2413 pccbb_pcmcia_delay(ph, 200 + 1, "pccen1"); 2414 2415 /* negate RESET */ 2416 intr |= PCIC_INTR_RESET; 2417 Pcic_write(ph, PCIC_INTR, intr); 2418 2419 /* 2420 * RESET Setup Time (Tsu (RESET)) = 20ms 2421 */ 2422 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2423 2424 #ifdef DIAGNOSTIC 2425 reg = Pcic_read(ph, PCIC_IF_STATUS); 2426 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2427 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2428 #endif 2429 2430 /* wait for the chip to finish initializing */ 2431 if (pccbb_pcmcia_wait_ready(ph)) { 2432 #ifdef DIAGNOSTIC 2433 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2434 #endif 2435 /* XXX return a failure status?? */ 2436 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2437 Pcic_write(ph, PCIC_PWRCTL, 0); 2438 return; 2439 } 2440 2441 /* reinstall all the memory and io mappings */ 2442 for (win = 0; win < PCIC_MEM_WINS; ++win) 2443 if (ph->memalloc & (1 << win)) 2444 pccbb_pcmcia_do_mem_map(ph, win); 2445 for (win = 0; win < PCIC_IO_WINS; ++win) 2446 if (ph->ioalloc & (1 << win)) 2447 pccbb_pcmcia_do_io_map(ph, win); 2448 } 2449 2450 /* 2451 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2452 * 2453 * This function disables the card. All information is stored in 2454 * the first argument, pcmcia_chipset_handle_t. 2455 */ 2456 STATIC void 2457 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2458 { 2459 struct pcic_handle *ph = (struct pcic_handle *)pch; 2460 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2461 u_int8_t intr; 2462 2463 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2464 2465 /* disable interrupts; assert RESET */ 2466 intr = Pcic_read(ph, PCIC_INTR); 2467 intr &= PCIC_INTR_ENABLE; 2468 Pcic_write(ph, PCIC_INTR, intr); 2469 2470 /* zero out the address windows */ 2471 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2472 2473 /* power down the socket to reset it, clear the card reset pin */ 2474 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2475 2476 /* disable socket: negate output enable bit and power off */ 2477 Pcic_write(ph, PCIC_PWRCTL, 0); 2478 2479 /* 2480 * Vcc Falling Time (Tpf) = 300ms 2481 */ 2482 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2483 } 2484 2485 STATIC void 2486 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2487 { 2488 struct pcic_handle *ph = (struct pcic_handle *)pch; 2489 u_int8_t intr; 2490 2491 /* set the card type */ 2492 2493 intr = Pcic_read(ph, PCIC_INTR); 2494 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2495 if (type == PCMCIA_IFTYPE_IO) 2496 intr |= PCIC_INTR_CARDTYPE_IO; 2497 else 2498 intr |= PCIC_INTR_CARDTYPE_MEM; 2499 Pcic_write(ph, PCIC_INTR, intr); 2500 2501 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2502 ph->ph_parent->dv_xname, ph->sock, 2503 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2504 } 2505 2506 /* 2507 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2508 * 2509 * This function detects whether a card is in the slot or not. 2510 * If a card is inserted, return 1. Otherwise, return 0. 2511 */ 2512 STATIC int 2513 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2514 { 2515 struct pcic_handle *ph = (struct pcic_handle *)pch; 2516 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2517 2518 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2519 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2520 } 2521 2522 #if 0 2523 STATIC int 2524 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2525 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2526 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2527 #endif 2528 /* 2529 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2530 * bus_size_t size, 2531 * struct pcmcia_mem_handle *pcmhp) 2532 * 2533 * This function only allocates memory region for pccard. This 2534 * function never maps the allocated region to pccard memory area. 2535 * 2536 * XXX: Why the argument of start address is not in? 2537 */ 2538 STATIC int 2539 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2540 struct pcmcia_mem_handle *pcmhp) 2541 { 2542 struct pcic_handle *ph = (struct pcic_handle *)pch; 2543 bus_space_handle_t memh; 2544 bus_addr_t addr; 2545 bus_size_t sizepg; 2546 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2547 #if rbus 2548 rbus_tag_t rb; 2549 #endif 2550 2551 /* Check that the card is still there. */ 2552 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2553 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2554 return 1; 2555 2556 /* out of sc->memh, allocate as many pages as necessary */ 2557 2558 /* convert size to PCIC pages */ 2559 /* 2560 * This is not enough; when the requested region is on the page 2561 * boundaries, this may calculate wrong result. 2562 */ 2563 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2564 #if 0 2565 if (sizepg > PCIC_MAX_MEM_PAGES) { 2566 return 1; 2567 } 2568 #endif 2569 2570 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2571 return 1; 2572 } 2573 2574 addr = 0; /* XXX gcc -Wuninitialized */ 2575 2576 #if rbus 2577 rb = sc->sc_rbus_memt; 2578 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2579 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2580 &addr, &memh)) { 2581 return 1; 2582 } 2583 #else 2584 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2585 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2586 0, /* boundary */ 2587 0, /* flags */ 2588 &addr, &memh)) { 2589 return 1; 2590 } 2591 #endif 2592 2593 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2594 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2595 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2596 2597 pcmhp->memt = sc->sc_memt; 2598 pcmhp->memh = memh; 2599 pcmhp->addr = addr; 2600 pcmhp->size = size; 2601 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2602 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2603 pcmhp->mhandle = 0; 2604 /* No offset??? Funny. */ 2605 2606 return 0; 2607 } 2608 2609 /* 2610 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2611 * struct pcmcia_mem_handle *pcmhp) 2612 * 2613 * This function release the memory space allocated by the function 2614 * pccbb_pcmcia_mem_alloc(). 2615 */ 2616 STATIC void 2617 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2618 struct pcmcia_mem_handle *pcmhp) 2619 { 2620 #if rbus 2621 struct pcic_handle *ph = (struct pcic_handle *)pch; 2622 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2623 2624 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2625 #else 2626 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2627 #endif 2628 } 2629 2630 /* 2631 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2632 * 2633 * This function release the memory space allocated by the function 2634 * pccbb_pcmcia_mem_alloc(). 2635 */ 2636 STATIC void 2637 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2638 { 2639 int regbase_win; 2640 bus_addr_t phys_addr; 2641 bus_addr_t phys_end; 2642 2643 #define PCIC_SMM_START_LOW 0 2644 #define PCIC_SMM_START_HIGH 1 2645 #define PCIC_SMM_STOP_LOW 2 2646 #define PCIC_SMM_STOP_HIGH 3 2647 #define PCIC_CMA_LOW 4 2648 #define PCIC_CMA_HIGH 5 2649 2650 u_int8_t start_low, start_high = 0; 2651 u_int8_t stop_low, stop_high; 2652 u_int8_t off_low, off_high; 2653 u_int8_t mem_window; 2654 int reg; 2655 2656 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2657 int mem8 = 2658 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2659 || (kind == PCMCIA_MEM_ATTR); 2660 2661 regbase_win = 0x10 + win * 0x08; 2662 2663 phys_addr = ph->mem[win].addr; 2664 phys_end = phys_addr + ph->mem[win].size; 2665 2666 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2667 (unsigned long)phys_addr, (unsigned long)phys_end, 2668 (unsigned long)ph->mem[win].offset)); 2669 2670 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2671 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2672 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2673 2674 /* bit 19:12 */ 2675 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2676 /* bit 23:20 and bit 7 on */ 2677 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2678 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2679 /* bit 31:24, for 32-bit address */ 2680 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2681 2682 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2683 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2684 2685 if (((struct pccbb_softc *)ph-> 2686 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2687 Pcic_write(ph, 0x40 + win, mem_window); 2688 } 2689 2690 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2691 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2692 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2693 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2694 2695 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2696 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2697 2698 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2699 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2700 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2701 | ((kind == PCMCIA_MEM_ATTR) ? 2702 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2703 2704 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2705 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2706 2707 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2708 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2709 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2710 2711 #if defined(CBB_DEBUG) 2712 { 2713 int r1, r2, r3, r4, r5, r6, r7 = 0; 2714 2715 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2716 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2717 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2718 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2719 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2720 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2721 if (((struct pccbb_softc *)(ph-> 2722 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2723 r7 = Pcic_read(ph, 0x40 + win); 2724 } 2725 2726 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2727 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2728 if (((struct pccbb_softc *)(ph-> 2729 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2730 printf(" %02x", r7); 2731 } 2732 printf("\n"); 2733 } 2734 #endif 2735 } 2736 2737 /* 2738 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2739 * bus_addr_t card_addr, bus_size_t size, 2740 * struct pcmcia_mem_handle *pcmhp, 2741 * bus_addr_t *offsetp, int *windowp) 2742 * 2743 * This function maps memory space allocated by the function 2744 * pccbb_pcmcia_mem_alloc(). 2745 */ 2746 STATIC int 2747 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2748 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2749 bus_addr_t *offsetp, int *windowp) 2750 { 2751 struct pcic_handle *ph = (struct pcic_handle *)pch; 2752 bus_addr_t busaddr; 2753 long card_offset; 2754 int win; 2755 2756 /* Check that the card is still there. */ 2757 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2758 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2759 return 1; 2760 2761 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2762 if ((ph->memalloc & (1 << win)) == 0) { 2763 ph->memalloc |= (1 << win); 2764 break; 2765 } 2766 } 2767 2768 if (win == PCIC_MEM_WINS) { 2769 return 1; 2770 } 2771 2772 *windowp = win; 2773 2774 /* XXX this is pretty gross */ 2775 2776 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2777 panic("pccbb_pcmcia_mem_map memt is bogus"); 2778 } 2779 2780 busaddr = pcmhp->addr; 2781 2782 /* 2783 * compute the address offset to the pcmcia address space for the 2784 * pcic. this is intentionally signed. The masks and shifts below 2785 * will cause TRT to happen in the pcic registers. Deal with making 2786 * sure the address is aligned, and return the alignment offset. 2787 */ 2788 2789 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2790 card_addr -= *offsetp; 2791 2792 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2793 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2794 (u_long) card_addr)); 2795 2796 /* 2797 * include the offset in the size, and decrement size by one, since 2798 * the hw wants start/stop 2799 */ 2800 size += *offsetp - 1; 2801 2802 card_offset = (((long)card_addr) - ((long)busaddr)); 2803 2804 ph->mem[win].addr = busaddr; 2805 ph->mem[win].size = size; 2806 ph->mem[win].offset = card_offset; 2807 ph->mem[win].kind = kind; 2808 2809 pccbb_pcmcia_do_mem_map(ph, win); 2810 2811 return 0; 2812 } 2813 2814 /* 2815 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2816 * int window) 2817 * 2818 * This function unmaps memory space which mapped by the function 2819 * pccbb_pcmcia_mem_map(). 2820 */ 2821 STATIC void 2822 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2823 { 2824 struct pcic_handle *ph = (struct pcic_handle *)pch; 2825 int reg; 2826 2827 if (window >= PCIC_MEM_WINS) { 2828 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2829 } 2830 2831 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2832 reg &= ~(1 << window); 2833 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2834 2835 ph->memalloc &= ~(1 << window); 2836 } 2837 2838 #if defined PCCBB_PCMCIA_POLL 2839 struct pccbb_poll_str { 2840 void *arg; 2841 int (*func)(void *); 2842 int level; 2843 struct pcic_handle *ph; 2844 int count; 2845 int num; 2846 struct callout poll_ch; 2847 }; 2848 2849 static struct pccbb_poll_str pccbb_poll[10]; 2850 static int pccbb_poll_n = 0; 2851 2852 static void pccbb_pcmcia_poll(void *arg); 2853 2854 static void 2855 pccbb_pcmcia_poll(void *arg) 2856 { 2857 struct pccbb_poll_str *poll = arg; 2858 struct pcic_handle *ph = poll->ph; 2859 struct pccbb_softc *sc = ph->sc; 2860 int s; 2861 u_int32_t spsr; /* socket present-state reg */ 2862 2863 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2864 switch (poll->level) { 2865 case IPL_NET: 2866 s = splnet(); 2867 break; 2868 case IPL_BIO: 2869 s = splbio(); 2870 break; 2871 case IPL_TTY: /* fallthrough */ 2872 default: 2873 s = spltty(); 2874 break; 2875 } 2876 2877 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2878 CB_SOCKET_STAT); 2879 2880 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2881 if (!(spsr & 0x40)) /* CINT low */ 2882 #else 2883 if (1) 2884 #endif 2885 { 2886 if ((*poll->func) (poll->arg) > 0) { 2887 ++poll->count; 2888 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2889 #if defined LEVEL2 2890 } else { 2891 printf("intr: miss! 0x%x\n", spsr); 2892 #endif 2893 } 2894 } 2895 splx(s); 2896 } 2897 #endif /* defined CB_PCMCIA_POLL */ 2898 2899 /* 2900 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2901 * struct pcmcia_function *pf, 2902 * int ipl, 2903 * int (*func)(void *), 2904 * void *arg); 2905 * 2906 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2907 */ 2908 STATIC void * 2909 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2910 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2911 { 2912 struct pcic_handle *ph = (struct pcic_handle *)pch; 2913 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2914 2915 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2916 /* what should I do? */ 2917 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2918 DPRINTF(("%s does not provide edge nor pulse " 2919 "interrupt\n", sc->sc_dev.dv_xname)); 2920 return NULL; 2921 } 2922 /* 2923 * XXX Noooooo! The interrupt flag must set properly!! 2924 * dumb pcmcia driver!! 2925 */ 2926 } 2927 2928 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2929 } 2930 2931 /* 2932 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2933 * void *ih) 2934 * 2935 * This function disables PC-Card interrupt. 2936 */ 2937 STATIC void 2938 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2939 { 2940 struct pcic_handle *ph = (struct pcic_handle *)pch; 2941 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2942 2943 pccbb_intr_disestablish(sc, ih); 2944 } 2945 2946 #if rbus 2947 /* 2948 * static int 2949 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2950 * bus_addr_t addr, bus_size_t size, 2951 * bus_addr_t mask, bus_size_t align, 2952 * int flags, bus_addr_t *addrp; 2953 * bus_space_handle_t *bshp) 2954 * 2955 * This function allocates a portion of memory or io space for 2956 * clients. This function is called from CardBus card drivers. 2957 */ 2958 static int 2959 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2960 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2961 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2962 { 2963 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2964 2965 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2966 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2967 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2968 2969 if (align == 0) { 2970 align = size; 2971 } 2972 2973 if (rb->rb_bt == sc->sc_memt) { 2974 if (align < 16) { 2975 return 1; 2976 } 2977 /* 2978 * XXX: align more than 0x1000 to avoid overwrapping 2979 * memory windows for two or more devices. 0x1000 2980 * means memory window's granularity. 2981 * 2982 * Two or more devices should be able to share same 2983 * memory window region. However, overrapping memory 2984 * window is not good because some devices, such as 2985 * 3Com 3C575[BC], have a broken address decoder and 2986 * intrude other's memory region. 2987 */ 2988 if (align < 0x1000) { 2989 align = 0x1000; 2990 } 2991 } else if (rb->rb_bt == sc->sc_iot) { 2992 if (align < 4) { 2993 return 1; 2994 } 2995 /* XXX: hack for avoiding ISA image */ 2996 if (mask < 0x0100) { 2997 mask = 0x3ff; 2998 addr = 0x300; 2999 } 3000 3001 } else { 3002 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3003 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3004 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3005 (unsigned long)sc->sc_memt)); 3006 return 1; 3007 /* XXX: panic here? */ 3008 } 3009 3010 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3011 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3012 return 1; 3013 } 3014 3015 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3016 3017 return 0; 3018 } 3019 3020 /* 3021 * static int 3022 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3023 * bus_space_handle_t *bshp, bus_size_t size); 3024 * 3025 * This function is called from CardBus card drivers. 3026 */ 3027 static int 3028 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3029 bus_space_handle_t bsh, bus_size_t size) 3030 { 3031 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3032 bus_space_tag_t bt = rb->rb_bt; 3033 3034 pccbb_close_win(sc, bt, bsh, size); 3035 3036 if (bt == sc->sc_memt) { 3037 } else if (bt == sc->sc_iot) { 3038 } else { 3039 return 1; 3040 /* XXX: panic here? */ 3041 } 3042 3043 return rbus_space_free(rb, bsh, size, NULL); 3044 } 3045 #endif /* rbus */ 3046 3047 #if rbus 3048 3049 static int 3050 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 3051 bus_size_t size, bus_space_handle_t bsh, int flags) 3052 { 3053 struct pccbb_win_chain_head *head; 3054 bus_addr_t align; 3055 3056 head = &sc->sc_iowindow; 3057 align = 0x04; 3058 if (sc->sc_memt == bst) { 3059 head = &sc->sc_memwindow; 3060 align = 0x1000; 3061 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3062 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3063 (unsigned long)bst)); 3064 } 3065 3066 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3067 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3068 sc->sc_dev.dv_xname, 3069 (head == &sc->sc_memwindow) ? "mem" : "io"); 3070 } 3071 pccbb_winset(align, sc, bst); 3072 3073 return 0; 3074 } 3075 3076 static int 3077 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 3078 bus_space_handle_t bsh, bus_size_t size) 3079 { 3080 struct pccbb_win_chain_head *head; 3081 bus_addr_t align; 3082 3083 head = &sc->sc_iowindow; 3084 align = 0x04; 3085 if (sc->sc_memt == bst) { 3086 head = &sc->sc_memwindow; 3087 align = 0x1000; 3088 } 3089 3090 if (pccbb_winlist_delete(head, bsh, size)) { 3091 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3092 sc->sc_dev.dv_xname, 3093 (head == &sc->sc_memwindow) ? "mem" : "io"); 3094 } 3095 pccbb_winset(align, sc, bst); 3096 3097 return 0; 3098 } 3099 3100 static int 3101 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 3102 bus_size_t size, bus_space_handle_t bsh, int flags) 3103 { 3104 struct pccbb_win_chain *chainp, *elem; 3105 3106 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3107 M_NOWAIT)) == NULL) 3108 return (1); /* fail */ 3109 3110 elem->wc_start = start; 3111 elem->wc_end = start + (size - 1); 3112 elem->wc_handle = bsh; 3113 elem->wc_flags = flags; 3114 3115 TAILQ_FOREACH(chainp, head, wc_list) { 3116 if (chainp->wc_end >= start) 3117 break; 3118 } 3119 if (chainp != NULL) 3120 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3121 else 3122 TAILQ_INSERT_TAIL(head, elem, wc_list); 3123 return (0); 3124 } 3125 3126 static int 3127 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3128 bus_size_t size) 3129 { 3130 struct pccbb_win_chain *chainp; 3131 3132 TAILQ_FOREACH(chainp, head, wc_list) { 3133 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3134 break; 3135 } 3136 if (chainp == NULL) 3137 return 1; /* fail: no candidate to remove */ 3138 3139 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3140 printf("pccbb_winlist_delete: window 0x%lx size " 3141 "inconsistent: 0x%lx, 0x%lx\n", 3142 (unsigned long)chainp->wc_start, 3143 (unsigned long)(chainp->wc_end - chainp->wc_start), 3144 (unsigned long)(size - 1)); 3145 return 1; 3146 } 3147 3148 TAILQ_REMOVE(head, chainp, wc_list); 3149 free(chainp, M_DEVBUF); 3150 3151 return 0; 3152 } 3153 3154 static void 3155 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3156 { 3157 pci_chipset_tag_t pc; 3158 pcitag_t tag; 3159 bus_addr_t mask = ~(align - 1); 3160 struct { 3161 cardbusreg_t win_start; 3162 cardbusreg_t win_limit; 3163 int win_flags; 3164 } win[2]; 3165 struct pccbb_win_chain *chainp; 3166 int offs; 3167 3168 win[0].win_start = win[1].win_start = 0xffffffff; 3169 win[0].win_limit = win[1].win_limit = 0; 3170 win[0].win_flags = win[1].win_flags = 0; 3171 3172 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3173 offs = 0x2c; 3174 if (sc->sc_memt == bst) { 3175 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3176 offs = 0x1c; 3177 } 3178 3179 if (chainp != NULL) { 3180 win[0].win_start = chainp->wc_start & mask; 3181 win[0].win_limit = chainp->wc_end & mask; 3182 win[0].win_flags = chainp->wc_flags; 3183 chainp = TAILQ_NEXT(chainp, wc_list); 3184 } 3185 3186 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3187 if (win[1].win_start == 0xffffffff) { 3188 /* window 1 is not used */ 3189 if ((win[0].win_flags == chainp->wc_flags) && 3190 (win[0].win_limit + align >= 3191 (chainp->wc_start & mask))) { 3192 /* concatenate */ 3193 win[0].win_limit = chainp->wc_end & mask; 3194 } else { 3195 /* make new window */ 3196 win[1].win_start = chainp->wc_start & mask; 3197 win[1].win_limit = chainp->wc_end & mask; 3198 win[1].win_flags = chainp->wc_flags; 3199 } 3200 continue; 3201 } 3202 3203 /* Both windows are engaged. */ 3204 if (win[0].win_flags == win[1].win_flags) { 3205 /* same flags */ 3206 if (win[0].win_flags == chainp->wc_flags) { 3207 if (win[1].win_start - (win[0].win_limit + 3208 align) < 3209 (chainp->wc_start & mask) - 3210 ((chainp->wc_end & mask) + align)) { 3211 /* 3212 * merge window 0 and 1, and set win1 3213 * to chainp 3214 */ 3215 win[0].win_limit = win[1].win_limit; 3216 win[1].win_start = 3217 chainp->wc_start & mask; 3218 win[1].win_limit = 3219 chainp->wc_end & mask; 3220 } else { 3221 win[1].win_limit = 3222 chainp->wc_end & mask; 3223 } 3224 } else { 3225 /* different flags */ 3226 3227 /* concatenate win0 and win1 */ 3228 win[0].win_limit = win[1].win_limit; 3229 /* allocate win[1] to new space */ 3230 win[1].win_start = chainp->wc_start & mask; 3231 win[1].win_limit = chainp->wc_end & mask; 3232 win[1].win_flags = chainp->wc_flags; 3233 } 3234 } else { 3235 /* the flags of win[0] and win[1] is different */ 3236 if (win[0].win_flags == chainp->wc_flags) { 3237 win[0].win_limit = chainp->wc_end & mask; 3238 /* 3239 * XXX this creates overlapping windows, so 3240 * what should the poor bridge do if one is 3241 * cachable, and the other is not? 3242 */ 3243 printf("%s: overlapping windows\n", 3244 sc->sc_dev.dv_xname); 3245 } else { 3246 win[1].win_limit = chainp->wc_end & mask; 3247 } 3248 } 3249 } 3250 3251 pc = sc->sc_pc; 3252 tag = sc->sc_tag; 3253 pci_conf_write(pc, tag, offs, win[0].win_start); 3254 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3255 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3256 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3257 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3258 (unsigned long)pci_conf_read(pc, tag, offs), 3259 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3260 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3261 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3262 3263 if (bst == sc->sc_memt) { 3264 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3265 3266 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3267 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3268 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3269 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3270 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3271 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3272 } 3273 } 3274 3275 #endif /* rbus */ 3276 3277 static void 3278 pccbb_powerhook(int why, void *arg) 3279 { 3280 struct pccbb_softc *sc = arg; 3281 pcireg_t reg; 3282 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3283 bus_space_handle_t base_memh = sc->sc_base_memh; 3284 3285 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3286 3287 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3288 DPRINTF(("%s: power: why %d stopping intr\n", 3289 sc->sc_dev.dv_xname, why)); 3290 if (sc->sc_pil_intr_enable) { 3291 (void)pccbbintr_function(sc); 3292 } 3293 sc->sc_pil_intr_enable = 0; 3294 3295 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3296 3297 if (sc->sc_chipset == CB_RX5C47X) 3298 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3299 sc->sc_tag, 3300 RICOH_PCI_MISC_CTRL); 3301 3302 /* ToDo: deactivate or suspend child devices */ 3303 } 3304 3305 if (why == PWR_RESUME) { 3306 if (sc->sc_pwrmgt_offs != 0) { 3307 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3308 sc->sc_pwrmgt_offs + PCI_PMCSR); 3309 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3310 reg & PCI_PMCSR_PME_EN) { 3311 /* powrstate != D0 */ 3312 3313 printf("%s going back to D0 mode\n", 3314 sc->sc_dev.dv_xname); 3315 reg &= ~PCI_PMCSR_STATE_MASK; 3316 reg |= PCI_PMCSR_STATE_D0; 3317 reg &= ~PCI_PMCSR_PME_EN; 3318 pci_conf_write(sc->sc_pc, sc->sc_tag, 3319 sc->sc_pwrmgt_offs + PCI_PMCSR, reg); 3320 3321 pci_conf_write(sc->sc_pc, sc->sc_tag, 3322 PCI_SOCKBASE, sc->sc_sockbase); 3323 pci_conf_write(sc->sc_pc, sc->sc_tag, 3324 PCI_BUSNUM, sc->sc_busnum); 3325 pccbb_chipinit(sc); 3326 /* setup memory and io space window for CB */ 3327 pccbb_winset(0x1000, sc, sc->sc_memt); 3328 pccbb_winset(0x04, sc, sc->sc_iot); 3329 goto norestore; 3330 } 3331 } 3332 3333 norestore: 3334 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3335 if (sc->sc_chipset == CB_RX5C47X) { 3336 pci_conf_write(sc->sc_pc, sc->sc_tag, 3337 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3338 } 3339 3340 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3341 /* BIOS did not recover this register */ 3342 pci_conf_write (sc->sc_pc, sc->sc_tag, 3343 PCI_SOCKBASE, sc->sc_sockbase); 3344 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3345 /* BIOS did not recover this register */ 3346 pci_conf_write (sc->sc_pc, sc->sc_tag, 3347 PCI_BUSNUM, sc->sc_busnum); 3348 /* CSC Interrupt: Card detect interrupt on */ 3349 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3350 /* Card detect intr is turned on. */ 3351 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3352 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3353 /* reset interrupt */ 3354 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3355 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3356 3357 /* 3358 * check for card insertion or removal during suspend period. 3359 * XXX: the code can't cope with card swap (remove then 3360 * insert). how can we detect such situation? 3361 */ 3362 (void)pccbbintr(sc); 3363 3364 sc->sc_pil_intr_enable = 1; 3365 DPRINTF(("%s: power: RESUME enabling intr\n", 3366 sc->sc_dev.dv_xname)); 3367 3368 /* ToDo: activate or wakeup child devices */ 3369 } 3370 } 3371
Indexes created Mon Oct 13 14:09:54 GMT 2025