pccbb.c revision 1.125
1 /* $NetBSD: pccbb.c,v 1.125 2005/09/09 14:50:58 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.125 2005/09/09 14:50:58 drochner Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 42 /* 43 #define CB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL_ONLY 45 #define LEVEL2 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/ioctl.h> 53 #include <sys/reboot.h> /* for bootverbose */ 54 #include <sys/syslog.h> 55 #include <sys/device.h> 56 #include <sys/malloc.h> 57 #include <sys/proc.h> 58 59 #include <machine/intr.h> 60 #include <machine/bus.h> 61 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcidevs.h> 65 66 #include <dev/pci/pccbbreg.h> 67 68 #include <dev/cardbus/cardslotvar.h> 69 70 #include <dev/cardbus/cardbusvar.h> 71 72 #include <dev/pcmcia/pcmciareg.h> 73 #include <dev/pcmcia/pcmciavar.h> 74 75 #include <dev/ic/i82365reg.h> 76 #include <dev/ic/i82365var.h> 77 #include <dev/pci/pccbbvar.h> 78 79 #include "locators.h" 80 81 #if defined(__i386__) 82 #include "ioapic.h" 83 #endif 84 85 #ifndef __NetBSD_Version__ 86 struct cfdriver cbb_cd = { 87 NULL, "cbb", DV_DULL 88 }; 89 #endif 90 91 #ifdef CBB_DEBUG 92 #define DPRINTF(x) printf x 93 #define STATIC 94 #else 95 #define DPRINTF(x) 96 #define STATIC static 97 #endif 98 99 /* 100 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 101 * if you want to wait more than 1 ms. 102 */ 103 #define DELAY_MS(time, param) \ 104 do { \ 105 if (cold == 0) { \ 106 int xtick = (hz*(time))/1000; \ 107 \ 108 if (xtick <= 1) { \ 109 xtick = 2; \ 110 } \ 111 tsleep((void *)(param), PWAIT, "pccbb", xtick); \ 112 } else { \ 113 delay((time)*1000); \ 114 } \ 115 } while (/*CONSTCOND*/0) 116 117 int pcicbbmatch(struct device *, struct cfdata *, void *); 118 void pccbbattach(struct device *, struct device *, void *); 119 int pccbbintr(void *); 120 static void pci113x_insert(void *); 121 static int pccbbintr_function(struct pccbb_softc *); 122 123 static int pccbb_detect_card(struct pccbb_softc *); 124 125 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 126 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 127 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 128 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 129 130 STATIC int cb_reset(struct pccbb_softc *); 131 STATIC int cb_detect_voltage(struct pccbb_softc *); 132 STATIC int cbbprint(void *, const char *); 133 134 static int cb_chipset(u_int32_t, int *); 135 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 136 struct pcmciabus_attach_args *); 137 #if 0 138 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 139 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 140 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 141 #endif 142 143 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 144 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 145 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 146 #if !rbus 147 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 148 static int pccbb_io_close(cardbus_chipset_tag_t, int); 149 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 150 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 151 #endif /* !rbus */ 152 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 153 int level, int (*ih) (void *), void *sc); 154 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 155 156 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 157 int level, int (*ih) (void *), void *sc); 158 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 159 160 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 161 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 162 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 163 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t); 165 static void pccbb_chipinit(struct pccbb_softc *); 166 167 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *); 169 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *); 171 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 173 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 174 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 176 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *); 178 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *); 180 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 181 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *); 183 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 184 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 185 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 186 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 187 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 188 189 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 190 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 191 192 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 193 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 194 static void pccbb_powerhook(int, void *); 195 196 /* bus-space allocation and deallocation functions */ 197 #if rbus 198 199 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 200 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 201 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 202 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 203 bus_space_handle_t, bus_size_t); 204 205 #endif /* rbus */ 206 207 #if rbus 208 209 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 210 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 211 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 212 bus_space_handle_t, bus_size_t); 213 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 214 bus_size_t, bus_space_handle_t, int); 215 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 216 bus_space_handle_t, bus_size_t); 217 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 218 bus_space_tag_t); 219 void pccbb_winlist_show(struct pccbb_win_chain *); 220 221 #endif /* rbus */ 222 223 /* for config_defer */ 224 static void pccbb_pci_callback(struct device *); 225 226 #if defined SHOW_REGS 227 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 228 bus_space_tag_t memt, bus_space_handle_t memh); 229 #endif 230 231 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 232 pcicbbmatch, pccbbattach, NULL, NULL); 233 234 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 235 pccbb_pcmcia_mem_alloc, 236 pccbb_pcmcia_mem_free, 237 pccbb_pcmcia_mem_map, 238 pccbb_pcmcia_mem_unmap, 239 pccbb_pcmcia_io_alloc, 240 pccbb_pcmcia_io_free, 241 pccbb_pcmcia_io_map, 242 pccbb_pcmcia_io_unmap, 243 pccbb_pcmcia_intr_establish, 244 pccbb_pcmcia_intr_disestablish, 245 pccbb_pcmcia_socket_enable, 246 pccbb_pcmcia_socket_disable, 247 pccbb_pcmcia_socket_settype, 248 pccbb_pcmcia_card_detect 249 }; 250 251 #if rbus 252 static struct cardbus_functions pccbb_funcs = { 253 pccbb_rbus_cb_space_alloc, 254 pccbb_rbus_cb_space_free, 255 pccbb_cb_intr_establish, 256 pccbb_cb_intr_disestablish, 257 pccbb_ctrl, 258 pccbb_power, 259 pccbb_make_tag, 260 pccbb_free_tag, 261 pccbb_conf_read, 262 pccbb_conf_write, 263 }; 264 #else 265 static struct cardbus_functions pccbb_funcs = { 266 pccbb_ctrl, 267 pccbb_power, 268 pccbb_mem_open, 269 pccbb_mem_close, 270 pccbb_io_open, 271 pccbb_io_close, 272 pccbb_cb_intr_establish, 273 pccbb_cb_intr_disestablish, 274 pccbb_make_tag, 275 pccbb_conf_read, 276 pccbb_conf_write, 277 }; 278 #endif 279 280 int 281 pcicbbmatch(parent, match, aux) 282 struct device *parent; 283 struct cfdata *match; 284 void *aux; 285 { 286 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 287 288 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 289 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 290 PCI_INTERFACE(pa->pa_class) == 0) { 291 return 1; 292 } 293 294 return 0; 295 } 296 297 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 298 | ((prod) << PCI_PRODUCT_SHIFT)) 299 300 const struct yenta_chipinfo { 301 pcireg_t yc_id; /* vendor tag | product tag */ 302 int yc_chiptype; 303 int yc_flags; 304 } yc_chipsets[] = { 305 /* Texas Instruments chips */ 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 333 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 335 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 337 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 338 339 /* Ricoh chips */ 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 345 PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 347 PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 349 PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 351 PCCBB_PCMCIA_MEM_32}, 352 353 /* Toshiba products */ 354 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 355 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 356 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 357 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 358 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 359 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 361 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 362 363 /* Cirrus Logic products */ 364 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 365 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 366 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 367 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 368 369 /* sentinel, or Generic chip */ 370 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 371 }; 372 373 static int 374 cb_chipset(pci_id, flagp) 375 u_int32_t pci_id; 376 int *flagp; 377 { 378 const struct yenta_chipinfo *yc; 379 380 /* Loop over except the last default entry. */ 381 for (yc = yc_chipsets; yc < yc_chipsets + 382 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 383 if (pci_id == yc->yc_id) 384 break; 385 386 if (flagp != NULL) 387 *flagp = yc->yc_flags; 388 389 return (yc->yc_chiptype); 390 } 391 392 static void 393 pccbb_shutdown(void *arg) 394 { 395 struct pccbb_softc *sc = arg; 396 pcireg_t command; 397 398 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 399 400 /* 401 * turn off power 402 * 403 * XXX - do not turn off power if chipset is TI 113X because 404 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 405 */ 406 if (sc->sc_chipset != CB_TI113X) { 407 pccbb_power((cardbus_chipset_tag_t)sc, 408 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 409 } 410 411 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 412 0); 413 414 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 415 416 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 417 PCI_COMMAND_MASTER_ENABLE); 418 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 419 420 } 421 422 void 423 pccbbattach(parent, self, aux) 424 struct device *parent; 425 struct device *self; 426 void *aux; 427 { 428 struct pccbb_softc *sc = (void *)self; 429 struct pci_attach_args *pa = aux; 430 pci_chipset_tag_t pc = pa->pa_pc; 431 pcireg_t busreg, reg, sock_base; 432 bus_addr_t sockbase; 433 char devinfo[256]; 434 int flags; 435 int pwrmgt_offs; 436 437 #ifdef __HAVE_PCCBB_ATTACH_HOOK 438 pccbb_attach_hook(parent, self, pa); 439 #endif 440 441 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 442 443 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 444 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 445 #ifdef CBB_DEBUG 446 printf(" (chipflags %x)", flags); 447 #endif 448 printf("\n"); 449 450 TAILQ_INIT(&sc->sc_memwindow); 451 TAILQ_INIT(&sc->sc_iowindow); 452 453 #if rbus 454 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 455 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 456 457 #if 0 458 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 459 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 460 #endif 461 #endif /* rbus */ 462 463 sc->sc_flags &= ~CBB_MEMHMAPPED; 464 465 /* power management: set D0 state */ 466 sc->sc_pwrmgt_offs = 0; 467 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 468 &pwrmgt_offs, 0)) { 469 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 470 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 471 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 472 reg &= ~PCI_PMCSR_STATE_MASK; 473 reg |= PCI_PMCSR_STATE_D0; 474 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 475 pci_conf_write(pc, pa->pa_tag, 476 pwrmgt_offs + PCI_PMCSR, reg); 477 } 478 479 sc->sc_pwrmgt_offs = pwrmgt_offs; 480 } 481 482 /* 483 * MAP socket registers and ExCA registers on memory-space 484 * When no valid address is set on socket base registers (on pci 485 * config space), get it not polite way. 486 */ 487 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 488 489 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 490 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 491 /* The address must be valid. */ 492 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 493 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 494 printf("%s: can't map socket base address 0x%lx\n", 495 sc->sc_dev.dv_xname, (unsigned long)sock_base); 496 /* 497 * I think it's funny: socket base registers must be 498 * mapped on memory space, but ... 499 */ 500 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 501 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 502 NULL)) { 503 printf("%s: can't map socket base address" 504 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 505 (unsigned long)sockbase); 506 /* give up... allocate reg space via rbus. */ 507 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 508 } else 509 sc->sc_flags |= CBB_MEMHMAPPED; 510 } else { 511 DPRINTF(("%s: socket base address 0x%lx\n", 512 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 513 sc->sc_flags |= CBB_MEMHMAPPED; 514 } 515 } 516 517 sc->sc_mem_start = 0; /* XXX */ 518 sc->sc_mem_end = 0xffffffff; /* XXX */ 519 520 /* 521 * When interrupt isn't routed correctly, give up probing cbb and do 522 * not kill pcic-compatible port. 523 * 524 * However, if we are using an ioapic, avoid this check -- pa_intrline 525 * may well be zero, with the interrupt routed through the apic. 526 */ 527 528 #if NIOAPIC > 0 529 printf("%s: using ioapic for interrupt\n", sc->sc_dev.dv_xname); 530 #else 531 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 532 printf("%s: NOT USED because of unconfigured interrupt\n", 533 sc->sc_dev.dv_xname); 534 return; 535 } 536 #endif 537 538 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 539 540 /* pccbb_machdep.c end */ 541 542 #if defined CBB_DEBUG 543 { 544 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 545 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 546 intrname[pa->pa_intrpin], pa->pa_intrline); 547 } 548 #endif 549 550 /* setup softc */ 551 sc->sc_pc = pc; 552 sc->sc_iot = pa->pa_iot; 553 sc->sc_memt = pa->pa_memt; 554 sc->sc_dmat = pa->pa_dmat; 555 sc->sc_tag = pa->pa_tag; 556 sc->sc_function = pa->pa_function; 557 sc->sc_sockbase = sock_base; 558 sc->sc_busnum = busreg; 559 560 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 561 562 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 563 564 shutdownhook_establish(pccbb_shutdown, sc); 565 566 /* Disable legacy register mapping. */ 567 switch (sc->sc_chipset) { 568 case CB_RX5C46X: /* fallthrough */ 569 #if 0 570 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 571 case CB_RX5C47X: 572 #endif 573 /* 574 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 575 * cannot be disabled by substituting 0 into PCI_LEGACY 576 * register. Ricoh CardBus bridges have special bits on Bridge 577 * control reg (addr 0x3e on PCI config space). 578 */ 579 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 580 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 581 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 582 break; 583 584 default: 585 /* XXX I don't know proper way to kill legacy I/O. */ 586 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 587 break; 588 } 589 590 config_defer(self, pccbb_pci_callback); 591 } 592 593 594 595 596 /* 597 * static void pccbb_pci_callback(struct device *self) 598 * 599 * The actual attach routine: get memory space for YENTA register 600 * space, setup YENTA register and route interrupt. 601 * 602 * This function should be deferred because this device may obtain 603 * memory space dynamically. This function must avoid obtaining 604 * memory area which has already kept for another device. 605 */ 606 static void 607 pccbb_pci_callback(self) 608 struct device *self; 609 { 610 struct pccbb_softc *sc = (void *)self; 611 pci_chipset_tag_t pc = sc->sc_pc; 612 pci_intr_handle_t ih; 613 const char *intrstr = NULL; 614 bus_addr_t sockbase; 615 struct cbslot_attach_args cba; 616 struct pcmciabus_attach_args paa; 617 struct cardslot_attach_args caa; 618 struct cardslot_softc *csc; 619 620 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 621 /* The socket registers aren't mapped correctly. */ 622 #if rbus 623 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 624 (sc->sc_chipset == CB_RX5C47X 625 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 626 0, &sockbase, &sc->sc_base_memh)) { 627 return; 628 } 629 sc->sc_base_memt = sc->sc_memt; 630 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 631 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 632 sc->sc_dev.dv_xname, (unsigned long)sockbase, 633 (unsigned long)pci_conf_read(pc, sc->sc_tag, 634 PCI_SOCKBASE))); 635 #else 636 sc->sc_base_memt = sc->sc_memt; 637 #if !defined CBB_PCI_BASE 638 #define CBB_PCI_BASE 0x20000000 639 #endif 640 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 641 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 642 /* cannot allocate memory space */ 643 return; 644 } 645 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 646 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 647 sc->sc_dev.dv_xname, (unsigned long)sock_base, 648 (unsigned long)pci_conf_read(pc, 649 sc->sc_tag, PCI_SOCKBASE))); 650 sc->sc_sockbase = sockbase; 651 #endif 652 sc->sc_flags |= CBB_MEMHMAPPED; 653 } 654 655 /* bus bridge initialization */ 656 pccbb_chipinit(sc); 657 658 /* clear data structure for child device interrupt handlers */ 659 LIST_INIT(&sc->sc_pil); 660 sc->sc_pil_intr_enable = 1; 661 662 /* Map and establish the interrupt. */ 663 if (pci_intr_map(&sc->sc_pa, &ih)) { 664 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 665 return; 666 } 667 intrstr = pci_intr_string(pc, ih); 668 669 /* 670 * XXX pccbbintr should be called under the priority lower 671 * than any other hard interupts. 672 */ 673 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 674 675 if (sc->sc_ih == NULL) { 676 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 677 if (intrstr != NULL) { 678 printf(" at %s", intrstr); 679 } 680 printf("\n"); 681 return; 682 } 683 684 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 685 powerhook_establish(pccbb_powerhook, sc); 686 687 { 688 u_int32_t sockstat; 689 690 sockstat = bus_space_read_4(sc->sc_base_memt, 691 sc->sc_base_memh, CB_SOCKET_STAT); 692 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 693 sc->sc_flags |= CBB_CARDEXIST; 694 } 695 } 696 697 /* 698 * attach cardbus 699 */ 700 { 701 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 702 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 703 704 /* initialize cbslot_attach */ 705 cba.cba_busname = "cardbus"; 706 cba.cba_iot = sc->sc_iot; 707 cba.cba_memt = sc->sc_memt; 708 cba.cba_dmat = sc->sc_dmat; 709 cba.cba_bus = (busreg >> 8) & 0x0ff; 710 cba.cba_cc = (void *)sc; 711 cba.cba_cf = &pccbb_funcs; 712 cba.cba_intrline = sc->sc_pa.pa_intrline; 713 714 #if rbus 715 cba.cba_rbus_iot = sc->sc_rbus_iot; 716 cba.cba_rbus_memt = sc->sc_rbus_memt; 717 #endif 718 719 cba.cba_cacheline = PCI_CACHELINE(bhlc); 720 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 721 722 if (bootverbose) { 723 printf("%s: cacheline 0x%x lattimer 0x%x\n", 724 sc->sc_dev.dv_xname, cba.cba_cacheline, 725 cba.cba_lattimer); 726 printf("%s: bhlc 0x%x lscp 0x%x\n", 727 sc->sc_dev.dv_xname, bhlc, busreg); 728 } 729 #if defined SHOW_REGS 730 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 731 sc->sc_base_memh); 732 #endif 733 } 734 735 pccbb_pcmcia_attach_setup(sc, &paa); 736 caa.caa_cb_attach = NULL; 737 if (cba.cba_bus == 0) 738 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 739 else 740 caa.caa_cb_attach = &cba; 741 caa.caa_16_attach = &paa; 742 caa.caa_ph = &sc->sc_pcmcia_h; 743 744 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 745 DPRINTF(("pccbbattach: found cardslot\n")); 746 sc->sc_csc = csc; 747 } 748 749 return; 750 } 751 752 753 754 755 756 /* 757 * static void pccbb_chipinit(struct pccbb_softc *sc) 758 * 759 * This function initialize YENTA chip registers listed below: 760 * 1) PCI command reg, 761 * 2) PCI and CardBus latency timer, 762 * 3) route PCI interrupt, 763 * 4) close all memory and io windows. 764 * 5) turn off bus power. 765 * 6) card detect and power cycle interrupts on. 766 * 7) clear interrupt 767 */ 768 static void 769 pccbb_chipinit(sc) 770 struct pccbb_softc *sc; 771 { 772 pci_chipset_tag_t pc = sc->sc_pc; 773 pcitag_t tag = sc->sc_tag; 774 bus_space_tag_t bmt = sc->sc_base_memt; 775 bus_space_handle_t bmh = sc->sc_base_memh; 776 pcireg_t reg; 777 778 /* 779 * Set PCI command reg. 780 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 781 */ 782 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 783 /* I believe it is harmless. */ 784 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 785 PCI_COMMAND_MASTER_ENABLE); 786 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 787 788 /* 789 * Set CardBus latency timer. 790 */ 791 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 792 if (PCI_CB_LATENCY(reg) < 0x20) { 793 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 794 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 795 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 796 } 797 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 798 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 799 800 /* 801 * Set PCI latency timer. 802 */ 803 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 804 if (PCI_LATTIMER(reg) < 0x10) { 805 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 806 reg |= (0x10 << PCI_LATTIMER_SHIFT); 807 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 808 } 809 DPRINTF(("PCI latency timer 0x%x (%x)\n", 810 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 811 812 813 /* Route functional interrupts to PCI. */ 814 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 815 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 816 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 817 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 818 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 819 820 switch (sc->sc_chipset) { 821 case CB_TI113X: 822 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 823 /* This bit is shared, but may read as 0 on some chips, so set 824 it explicitly on both functions. */ 825 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 826 /* CSC intr enable */ 827 reg |= PCI113X_CBCTRL_PCI_CSC; 828 /* functional intr prohibit | prohibit ISA routing */ 829 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 830 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 831 break; 832 833 case CB_TI12XX: 834 /* 835 * Some TI 12xx (and [14][45]xx) based pci cards 836 * sometimes have issues with the MFUNC register not 837 * being initialized due to a bad EEPROM on board. 838 * Laptops that this matters on have this register 839 * properly initialized. 840 * 841 * The TI125X parts have a different register. 842 */ 843 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 844 if (reg == 0) { 845 reg &= ~PCI12XX_MFUNC_PIN0; 846 reg |= PCI12XX_MFUNC_PIN0_INTA; 847 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 848 PCI12XX_SYSCTRL_INTRTIE) == 0) { 849 reg &= ~PCI12XX_MFUNC_PIN1; 850 reg |= PCI12XX_MFUNC_PIN1_INTB; 851 } 852 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 853 } 854 /* fallthrough */ 855 856 case CB_TI125X: 857 /* 858 * Disable zoom video. Some machines initialize this 859 * improperly and experience has shown that this helps 860 * prevent strange behavior. 861 */ 862 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 863 864 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 865 reg |= PCI12XX_SYSCTRL_VCCPROT; 866 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 867 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 868 reg |= PCI12XX_CBCTRL_CSC; 869 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 870 break; 871 872 case CB_TOPIC95B: 873 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 874 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 875 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 876 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 877 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 878 sc->sc_dev.dv_xname, reg)); 879 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 880 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 881 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 882 DPRINTF(("0x%x\n", reg)); 883 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 884 break; 885 886 case CB_TOPIC97: 887 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 888 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 889 sc->sc_dev.dv_xname, reg)); 890 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 891 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 892 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 893 reg |= TOPIC97_SLOT_CTRL_PCIINT; 894 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 895 DPRINTF(("0x%x\n", reg)); 896 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 897 /* make sure to assert LV card support bits */ 898 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 899 0x800 + 0x3e, 900 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 901 0x800 + 0x3e) | 0x03); 902 break; 903 } 904 905 /* Close all memory and I/O windows. */ 906 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 907 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 908 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 909 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 910 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 911 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 912 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 913 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 914 915 /* reset 16-bit pcmcia bus */ 916 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 917 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 918 919 /* turn off power */ 920 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 921 922 /* CSC Interrupt: Card detect and power cycle interrupts on */ 923 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 924 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 925 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 926 /* reset interrupt */ 927 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 928 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 929 } 930 931 932 933 934 /* 935 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 936 * struct pcmciabus_attach_args *paa) 937 * 938 * This function attaches 16-bit PCcard bus. 939 */ 940 STATIC void 941 pccbb_pcmcia_attach_setup(sc, paa) 942 struct pccbb_softc *sc; 943 struct pcmciabus_attach_args *paa; 944 { 945 struct pcic_handle *ph = &sc->sc_pcmcia_h; 946 #if rbus 947 rbus_tag_t rb; 948 #endif 949 950 /* initialize pcmcia part in pccbb_softc */ 951 ph->ph_parent = (struct device *)sc; 952 ph->sock = sc->sc_function; 953 ph->flags = 0; 954 ph->shutdown = 0; 955 ph->ih_irq = sc->sc_pa.pa_intrline; 956 ph->ph_bus_t = sc->sc_base_memt; 957 ph->ph_bus_h = sc->sc_base_memh; 958 ph->ph_read = pccbb_pcmcia_read; 959 ph->ph_write = pccbb_pcmcia_write; 960 sc->sc_pct = &pccbb_pcmcia_funcs; 961 962 /* 963 * We need to do a few things here: 964 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 965 * setting the IRQ numbers to 0. 966 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 967 * routing of CSC interrupts (e.g. card removal) to PCI while in 968 * PCMCIA mode. We just leave this set all the time. 969 * 3) Enable card insertion/removal interrupts in case the chip also 970 * needs that while in PCMCIA mode. 971 * 4) Clear any pending CSC interrupt. 972 */ 973 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 974 if (sc->sc_chipset == CB_TI113X) { 975 Pcic_write(ph, PCIC_CSC_INTR, 0); 976 } else { 977 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 978 Pcic_read(ph, PCIC_CSC); 979 } 980 981 /* initialize pcmcia bus attachment */ 982 paa->paa_busname = "pcmcia"; 983 paa->pct = sc->sc_pct; 984 paa->pch = ph; 985 paa->iobase = 0; /* I don't use them */ 986 paa->iosize = 0; 987 #if rbus 988 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 989 paa->iobase = rb->rb_start + rb->rb_offset; 990 paa->iosize = rb->rb_end - rb->rb_start; 991 #endif 992 993 return; 994 } 995 996 #if 0 997 STATIC void 998 pccbb_pcmcia_attach_card(ph) 999 struct pcic_handle *ph; 1000 { 1001 if (ph->flags & PCIC_FLAG_CARDP) { 1002 panic("pccbb_pcmcia_attach_card: already attached"); 1003 } 1004 1005 /* call the MI attach function */ 1006 pcmcia_card_attach(ph->pcmcia); 1007 1008 ph->flags |= PCIC_FLAG_CARDP; 1009 } 1010 1011 STATIC void 1012 pccbb_pcmcia_detach_card(ph, flags) 1013 struct pcic_handle *ph; 1014 int flags; 1015 { 1016 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1017 panic("pccbb_pcmcia_detach_card: already detached"); 1018 } 1019 1020 ph->flags &= ~PCIC_FLAG_CARDP; 1021 1022 /* call the MI detach function */ 1023 pcmcia_card_detach(ph->pcmcia, flags); 1024 } 1025 #endif 1026 1027 /* 1028 * int pccbbintr(arg) 1029 * void *arg; 1030 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1031 * itself. 1032 */ 1033 int 1034 pccbbintr(arg) 1035 void *arg; 1036 { 1037 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1038 u_int32_t sockevent, sockstate; 1039 bus_space_tag_t memt = sc->sc_base_memt; 1040 bus_space_handle_t memh = sc->sc_base_memh; 1041 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1042 1043 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1044 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1045 Pcic_read(ph, PCIC_CSC); 1046 1047 if (sockevent == 0) { 1048 /* This intr is not for me: it may be for my child devices. */ 1049 if (sc->sc_pil_intr_enable) { 1050 return pccbbintr_function(sc); 1051 } else { 1052 return 0; 1053 } 1054 } 1055 1056 if (sockevent & CB_SOCKET_EVENT_CD) { 1057 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1058 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1059 /* A card should be removed. */ 1060 if (sc->sc_flags & CBB_CARDEXIST) { 1061 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1062 sockevent)); 1063 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1064 sc->sc_flags &= ~CBB_CARDEXIST; 1065 if (sc->sc_csc->sc_status & 1066 CARDSLOT_STATUS_CARD_16) { 1067 #if 0 1068 struct pcic_handle *ph = 1069 &sc->sc_pcmcia_h; 1070 1071 pcmcia_card_deactivate(ph->pcmcia); 1072 pccbb_pcmcia_socket_disable(ph); 1073 pccbb_pcmcia_detach_card(ph, 1074 DETACH_FORCE); 1075 #endif 1076 cardslot_event_throw(sc->sc_csc, 1077 CARDSLOT_EVENT_REMOVAL_16); 1078 } else if (sc->sc_csc->sc_status & 1079 CARDSLOT_STATUS_CARD_CB) { 1080 /* Cardbus intr removed */ 1081 cardslot_event_throw(sc->sc_csc, 1082 CARDSLOT_EVENT_REMOVAL_CB); 1083 } 1084 } else if (sc->sc_flags & CBB_INSERTING) { 1085 sc->sc_flags &= ~CBB_INSERTING; 1086 callout_stop(&sc->sc_insert_ch); 1087 } 1088 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1089 /* 1090 * The pccbbintr may called from powerdown hook when 1091 * the system resumed, to detect the card 1092 * insertion/removal during suspension. 1093 */ 1094 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1095 if (sc->sc_flags & CBB_INSERTING) { 1096 callout_stop(&sc->sc_insert_ch); 1097 } 1098 callout_reset(&sc->sc_insert_ch, hz / 5, 1099 pci113x_insert, sc); 1100 sc->sc_flags |= CBB_INSERTING; 1101 } 1102 } 1103 1104 if (sockevent & CB_SOCKET_EVENT_POWER) { 1105 /* XXX: Does not happen when attaching a 16-bit card */ 1106 sc->sc_pwrcycle++; 1107 wakeup(&sc->sc_pwrcycle); 1108 } 1109 1110 return (1); 1111 } 1112 1113 /* 1114 * static int pccbbintr_function(struct pccbb_softc *sc) 1115 * 1116 * This function calls each interrupt handler registered at the 1117 * bridge. The interrupt handlers are called in registered order. 1118 */ 1119 static int 1120 pccbbintr_function(sc) 1121 struct pccbb_softc *sc; 1122 { 1123 int retval = 0, val; 1124 struct pccbb_intrhand_list *pil; 1125 int s, splchanged; 1126 1127 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1128 pil = LIST_NEXT(pil, pil_next)) { 1129 /* 1130 * XXX priority change. gross. I use if-else 1131 * sentense instead of switch-case sentense because of 1132 * avoiding duplicate case value error. More than one 1133 * IPL_XXX use same value. It depends on 1134 * implimentation. 1135 */ 1136 splchanged = 1; 1137 if (pil->pil_level == IPL_SERIAL) { 1138 s = splserial(); 1139 } else if (pil->pil_level == IPL_HIGH) { 1140 s = splhigh(); 1141 } else if (pil->pil_level == IPL_CLOCK) { 1142 s = splclock(); 1143 } else if (pil->pil_level == IPL_AUDIO) { 1144 s = splaudio(); 1145 } else if (pil->pil_level == IPL_VM) { 1146 s = splvm(); 1147 } else if (pil->pil_level == IPL_TTY) { 1148 s = spltty(); 1149 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1150 s = splsoftserial(); 1151 } else if (pil->pil_level == IPL_NET) { 1152 s = splnet(); 1153 } else { 1154 s = 0; /* XXX: gcc */ 1155 splchanged = 0; 1156 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1157 } 1158 1159 val = (*pil->pil_func)(pil->pil_arg); 1160 1161 if (splchanged != 0) { 1162 splx(s); 1163 } 1164 1165 retval = retval == 1 ? 1 : 1166 retval == 0 ? val : val != 0 ? val : retval; 1167 } 1168 1169 return retval; 1170 } 1171 1172 static void 1173 pci113x_insert(arg) 1174 void *arg; 1175 { 1176 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1177 u_int32_t sockevent, sockstate; 1178 1179 if (!(sc->sc_flags & CBB_INSERTING)) { 1180 /* We add a card only under inserting state. */ 1181 return; 1182 } 1183 sc->sc_flags &= ~CBB_INSERTING; 1184 1185 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1186 CB_SOCKET_EVENT); 1187 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1188 CB_SOCKET_STAT); 1189 1190 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1191 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1192 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1193 sc->sc_flags |= CBB_CARDEXIST; 1194 /* call pccard interrupt handler here */ 1195 if (sockstate & CB_SOCKET_STAT_16BIT) { 1196 /* 16-bit card found */ 1197 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1198 cardslot_event_throw(sc->sc_csc, 1199 CARDSLOT_EVENT_INSERTION_16); 1200 } else if (sockstate & CB_SOCKET_STAT_CB) { 1201 /* cardbus card found */ 1202 /* cardbus_attach_card(sc->sc_csc); */ 1203 cardslot_event_throw(sc->sc_csc, 1204 CARDSLOT_EVENT_INSERTION_CB); 1205 } else { 1206 /* who are you? */ 1207 } 1208 } else { 1209 callout_reset(&sc->sc_insert_ch, hz / 10, 1210 pci113x_insert, sc); 1211 } 1212 } 1213 1214 #define PCCBB_PCMCIA_OFFSET 0x800 1215 static u_int8_t 1216 pccbb_pcmcia_read(ph, reg) 1217 struct pcic_handle *ph; 1218 int reg; 1219 { 1220 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1221 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1222 1223 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1224 PCCBB_PCMCIA_OFFSET + reg); 1225 } 1226 1227 static void 1228 pccbb_pcmcia_write(ph, reg, val) 1229 struct pcic_handle *ph; 1230 int reg; 1231 u_int8_t val; 1232 { 1233 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1234 val); 1235 1236 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1237 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1238 } 1239 1240 /* 1241 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1242 */ 1243 STATIC int 1244 pccbb_ctrl(ct, command) 1245 cardbus_chipset_tag_t ct; 1246 int command; 1247 { 1248 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1249 1250 switch (command) { 1251 case CARDBUS_CD: 1252 if (2 == pccbb_detect_card(sc)) { 1253 int retval = 0; 1254 int status = cb_detect_voltage(sc); 1255 if (PCCARD_VCC_5V & status) { 1256 retval |= CARDBUS_5V_CARD; 1257 } 1258 if (PCCARD_VCC_3V & status) { 1259 retval |= CARDBUS_3V_CARD; 1260 } 1261 if (PCCARD_VCC_XV & status) { 1262 retval |= CARDBUS_XV_CARD; 1263 } 1264 if (PCCARD_VCC_YV & status) { 1265 retval |= CARDBUS_YV_CARD; 1266 } 1267 return retval; 1268 } else { 1269 return 0; 1270 } 1271 case CARDBUS_RESET: 1272 return cb_reset(sc); 1273 case CARDBUS_IO_ENABLE: /* fallthrough */ 1274 case CARDBUS_IO_DISABLE: /* fallthrough */ 1275 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1276 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1277 case CARDBUS_BM_ENABLE: /* fallthrough */ 1278 case CARDBUS_BM_DISABLE: /* fallthrough */ 1279 /* XXX: I think we don't need to call this function below. */ 1280 return pccbb_cardenable(sc, command); 1281 } 1282 1283 return 0; 1284 } 1285 1286 /* 1287 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1288 * This function returns true when it succeeds and returns false when 1289 * it fails. 1290 */ 1291 STATIC int 1292 pccbb_power(ct, command) 1293 cardbus_chipset_tag_t ct; 1294 int command; 1295 { 1296 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1297 u_int32_t status, sock_ctrl, reg_ctrl; 1298 bus_space_tag_t memt = sc->sc_base_memt; 1299 bus_space_handle_t memh = sc->sc_base_memh; 1300 int on = 0, pwrcycle; 1301 1302 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1303 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1304 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1305 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1306 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1307 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1308 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1309 "UNKNOWN", 1310 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1311 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1312 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1313 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1314 "UNKNOWN", command)); 1315 1316 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1317 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1318 1319 switch (command & CARDBUS_VCCMASK) { 1320 case CARDBUS_VCC_UC: 1321 break; 1322 case CARDBUS_VCC_5V: 1323 on++; 1324 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1325 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1326 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1327 } else { 1328 printf("%s: BAD voltage request: no 5 V card\n", 1329 sc->sc_dev.dv_xname); 1330 return 0; 1331 } 1332 break; 1333 case CARDBUS_VCC_3V: 1334 on++; 1335 if (CB_SOCKET_STAT_3VCARD & status) { 1336 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1337 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1338 } else { 1339 printf("%s: BAD voltage request: no 3.3 V card\n", 1340 sc->sc_dev.dv_xname); 1341 return 0; 1342 } 1343 break; 1344 case CARDBUS_VCC_0V: 1345 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1346 break; 1347 default: 1348 return 0; /* power NEVER changed */ 1349 } 1350 1351 switch (command & CARDBUS_VPPMASK) { 1352 case CARDBUS_VPP_UC: 1353 break; 1354 case CARDBUS_VPP_0V: 1355 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1356 break; 1357 case CARDBUS_VPP_VCC: 1358 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1359 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1360 break; 1361 case CARDBUS_VPP_12V: 1362 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1363 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1364 break; 1365 } 1366 1367 pwrcycle = sc->sc_pwrcycle; 1368 1369 #if 0 1370 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1371 #endif 1372 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1373 1374 if (on) { 1375 int s, error = 0; 1376 struct timeval before, after, diff; 1377 1378 microtime(&before); 1379 s = splbio(); 1380 while (pwrcycle == sc->sc_pwrcycle) { 1381 /* 1382 * XXX: Set timeout to 200ms because power cycle event 1383 * will be never happen when attaching a 16-bit card. 1384 */ 1385 if ((error = tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1386 hz / 5)) == EWOULDBLOCK) 1387 break; 1388 } 1389 splx(s); 1390 microtime(&after); 1391 timersub(&after, &before, &diff); 1392 printf("%s: wait took%s %ld.%06lds\n", sc->sc_dev.dv_xname, 1393 error == EWOULDBLOCK ? " too long" : "", 1394 diff.tv_sec, diff.tv_usec); 1395 } 1396 1397 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1398 1399 if (on) { 1400 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1401 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1402 } 1403 1404 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1405 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1406 sc->sc_dev.dv_xname, sock_ctrl, status); 1407 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1408 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1409 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1410 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1411 status &= ~CB_SOCKET_STAT_BADVCC; 1412 bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1413 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1414 CB_SOCKET_STAT)); 1415 return 0; 1416 } 1417 1418 if (sc->sc_chipset == CB_TOPIC97) { 1419 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1420 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1421 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1422 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1423 else 1424 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1425 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1426 } 1427 1428 return 1; /* power changed correctly */ 1429 } 1430 1431 #if defined CB_PCMCIA_POLL 1432 struct cb_poll_str { 1433 void *arg; 1434 int (*func)(void *); 1435 int level; 1436 pccard_chipset_tag_t ct; 1437 int count; 1438 struct callout poll_ch; 1439 }; 1440 1441 static struct cb_poll_str cb_poll[10]; 1442 static int cb_poll_n = 0; 1443 1444 static void cb_pcmcia_poll(void *arg); 1445 1446 static void 1447 cb_pcmcia_poll(arg) 1448 void *arg; 1449 { 1450 struct cb_poll_str *poll = arg; 1451 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1452 struct pccbb_softc *sc = psc->cpc_parent; 1453 int s; 1454 u_int32_t spsr; /* socket present-state reg */ 1455 1456 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1457 switch (poll->level) { 1458 case IPL_NET: 1459 s = splnet(); 1460 break; 1461 case IPL_BIO: 1462 s = splbio(); 1463 break; 1464 case IPL_TTY: /* fallthrough */ 1465 default: 1466 s = spltty(); 1467 break; 1468 } 1469 1470 spsr = 1471 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1472 CB_SOCKET_STAT); 1473 1474 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1475 if (!(spsr & 0x40)) { /* CINT low */ 1476 #else 1477 if (1) { 1478 #endif 1479 if ((*poll->func) (poll->arg) == 1) { 1480 ++poll->count; 1481 printf("intr: reported from poller, 0x%x\n", spsr); 1482 #if defined LEVEL2 1483 } else { 1484 printf("intr: miss! 0x%x\n", spsr); 1485 #endif 1486 } 1487 } 1488 splx(s); 1489 } 1490 #endif /* defined CB_PCMCIA_POLL */ 1491 1492 /* 1493 * static int pccbb_detect_card(struct pccbb_softc *sc) 1494 * return value: 0 if no card exists. 1495 * 1 if 16-bit card exists. 1496 * 2 if cardbus card exists. 1497 */ 1498 static int 1499 pccbb_detect_card(sc) 1500 struct pccbb_softc *sc; 1501 { 1502 bus_space_handle_t base_memh = sc->sc_base_memh; 1503 bus_space_tag_t base_memt = sc->sc_base_memt; 1504 u_int32_t sockstat = 1505 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1506 int retval = 0; 1507 1508 /* CD1 and CD2 asserted */ 1509 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1510 /* card must be present */ 1511 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1512 /* NOTACARD DEASSERTED */ 1513 if (CB_SOCKET_STAT_CB & sockstat) { 1514 /* CardBus mode */ 1515 retval = 2; 1516 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1517 /* 16-bit mode */ 1518 retval = 1; 1519 } 1520 } 1521 } 1522 return retval; 1523 } 1524 1525 /* 1526 * STATIC int cb_reset(struct pccbb_softc *sc) 1527 * This function resets CardBus card. 1528 */ 1529 STATIC int 1530 cb_reset(sc) 1531 struct pccbb_softc *sc; 1532 { 1533 /* 1534 * Reset Assert at least 20 ms 1535 * Some machines request longer duration. 1536 */ 1537 int reset_duration = 1538 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1539 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1540 1541 /* Reset bit Assert (bit 6 at 0x3E) */ 1542 bcr |= CB_BCR_RESET_ENABLE; 1543 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1544 DELAY_MS(reset_duration, sc); 1545 1546 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1547 /* Reset bit Deassert (bit 6 at 0x3E) */ 1548 bcr &= ~CB_BCR_RESET_ENABLE; 1549 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1550 DELAY_MS(reset_duration, sc); 1551 } 1552 /* No card found on the slot. Keep Reset. */ 1553 return 1; 1554 } 1555 1556 /* 1557 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1558 * This function detect card Voltage. 1559 */ 1560 STATIC int 1561 cb_detect_voltage(sc) 1562 struct pccbb_softc *sc; 1563 { 1564 u_int32_t psr; /* socket present-state reg */ 1565 bus_space_tag_t iot = sc->sc_base_memt; 1566 bus_space_handle_t ioh = sc->sc_base_memh; 1567 int vol = PCCARD_VCC_UKN; /* set 0 */ 1568 1569 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1570 1571 if (0x400u & psr) { 1572 vol |= PCCARD_VCC_5V; 1573 } 1574 if (0x800u & psr) { 1575 vol |= PCCARD_VCC_3V; 1576 } 1577 1578 return vol; 1579 } 1580 1581 STATIC int 1582 cbbprint(aux, pcic) 1583 void *aux; 1584 const char *pcic; 1585 { 1586 /* 1587 struct cbslot_attach_args *cba = aux; 1588 1589 if (cba->cba_slot >= 0) { 1590 aprint_normal(" slot %d", cba->cba_slot); 1591 } 1592 */ 1593 return UNCONF; 1594 } 1595 1596 /* 1597 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1598 * This function enables and disables the card 1599 */ 1600 STATIC int 1601 pccbb_cardenable(sc, function) 1602 struct pccbb_softc *sc; 1603 int function; 1604 { 1605 u_int32_t command = 1606 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1607 1608 DPRINTF(("pccbb_cardenable:")); 1609 switch (function) { 1610 case CARDBUS_IO_ENABLE: 1611 command |= PCI_COMMAND_IO_ENABLE; 1612 break; 1613 case CARDBUS_IO_DISABLE: 1614 command &= ~PCI_COMMAND_IO_ENABLE; 1615 break; 1616 case CARDBUS_MEM_ENABLE: 1617 command |= PCI_COMMAND_MEM_ENABLE; 1618 break; 1619 case CARDBUS_MEM_DISABLE: 1620 command &= ~PCI_COMMAND_MEM_ENABLE; 1621 break; 1622 case CARDBUS_BM_ENABLE: 1623 command |= PCI_COMMAND_MASTER_ENABLE; 1624 break; 1625 case CARDBUS_BM_DISABLE: 1626 command &= ~PCI_COMMAND_MASTER_ENABLE; 1627 break; 1628 default: 1629 return 0; 1630 } 1631 1632 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1633 DPRINTF((" command reg 0x%x\n", command)); 1634 return 1; 1635 } 1636 1637 #if !rbus 1638 /* 1639 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1640 */ 1641 static int 1642 pccbb_io_open(ct, win, start, end) 1643 cardbus_chipset_tag_t ct; 1644 int win; 1645 u_int32_t start, end; 1646 { 1647 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1648 int basereg; 1649 int limitreg; 1650 1651 if ((win < 0) || (win > 2)) { 1652 #if defined DIAGNOSTIC 1653 printf("cardbus_io_open: window out of range %d\n", win); 1654 #endif 1655 return 0; 1656 } 1657 1658 basereg = win * 8 + 0x2c; 1659 limitreg = win * 8 + 0x30; 1660 1661 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1662 start, basereg, end, limitreg)); 1663 1664 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1665 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1666 return 1; 1667 } 1668 1669 /* 1670 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1671 */ 1672 static int 1673 pccbb_io_close(ct, win) 1674 cardbus_chipset_tag_t ct; 1675 int win; 1676 { 1677 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1678 int basereg; 1679 int limitreg; 1680 1681 if ((win < 0) || (win > 2)) { 1682 #if defined DIAGNOSTIC 1683 printf("cardbus_io_close: window out of range %d\n", win); 1684 #endif 1685 return 0; 1686 } 1687 1688 basereg = win * 8 + 0x2c; 1689 limitreg = win * 8 + 0x30; 1690 1691 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1692 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1693 return 1; 1694 } 1695 1696 /* 1697 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1698 */ 1699 static int 1700 pccbb_mem_open(ct, win, start, end) 1701 cardbus_chipset_tag_t ct; 1702 int win; 1703 u_int32_t start, end; 1704 { 1705 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1706 int basereg; 1707 int limitreg; 1708 1709 if ((win < 0) || (win > 2)) { 1710 #if defined DIAGNOSTIC 1711 printf("cardbus_mem_open: window out of range %d\n", win); 1712 #endif 1713 return 0; 1714 } 1715 1716 basereg = win * 8 + 0x1c; 1717 limitreg = win * 8 + 0x20; 1718 1719 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1720 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1721 return 1; 1722 } 1723 1724 /* 1725 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1726 */ 1727 static int 1728 pccbb_mem_close(ct, win) 1729 cardbus_chipset_tag_t ct; 1730 int win; 1731 { 1732 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1733 int basereg; 1734 int limitreg; 1735 1736 if ((win < 0) || (win > 2)) { 1737 #if defined DIAGNOSTIC 1738 printf("cardbus_mem_close: window out of range %d\n", win); 1739 #endif 1740 return 0; 1741 } 1742 1743 basereg = win * 8 + 0x1c; 1744 limitreg = win * 8 + 0x20; 1745 1746 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1747 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1748 return 1; 1749 } 1750 #endif 1751 1752 /* 1753 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1754 * int irq, 1755 * int level, 1756 * int (* func)(void *), 1757 * void *arg) 1758 * 1759 * This function registers an interrupt handler at the bridge, in 1760 * order not to call the interrupt handlers of child devices when 1761 * a card-deletion interrupt occurs. 1762 * 1763 * The arguments irq and level are not used. 1764 */ 1765 static void * 1766 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1767 cardbus_chipset_tag_t ct; 1768 int irq, level; 1769 int (*func)(void *); 1770 void *arg; 1771 { 1772 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1773 1774 return pccbb_intr_establish(sc, irq, level, func, arg); 1775 } 1776 1777 1778 /* 1779 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1780 * void *ih) 1781 * 1782 * This function removes an interrupt handler pointed by ih. 1783 */ 1784 static void 1785 pccbb_cb_intr_disestablish(ct, ih) 1786 cardbus_chipset_tag_t ct; 1787 void *ih; 1788 { 1789 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1790 1791 pccbb_intr_disestablish(sc, ih); 1792 } 1793 1794 1795 void 1796 pccbb_intr_route(sc) 1797 struct pccbb_softc *sc; 1798 { 1799 pcireg_t reg; 1800 1801 /* initialize bridge intr routing */ 1802 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1803 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1804 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1805 1806 switch (sc->sc_chipset) { 1807 case CB_TI113X: 1808 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1809 /* functional intr enabled */ 1810 reg |= PCI113X_CBCTRL_PCI_INTR; 1811 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1812 break; 1813 default: 1814 break; 1815 } 1816 } 1817 1818 /* 1819 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1820 * int irq, 1821 * int level, 1822 * int (* func)(void *), 1823 * void *arg) 1824 * 1825 * This function registers an interrupt handler at the bridge, in 1826 * order not to call the interrupt handlers of child devices when 1827 * a card-deletion interrupt occurs. 1828 * 1829 * The arguments irq is not used because pccbb selects intr vector. 1830 */ 1831 static void * 1832 pccbb_intr_establish(sc, irq, level, func, arg) 1833 struct pccbb_softc *sc; 1834 int irq, level; 1835 int (*func)(void *); 1836 void *arg; 1837 { 1838 struct pccbb_intrhand_list *pil, *newpil; 1839 1840 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1841 1842 if (LIST_EMPTY(&sc->sc_pil)) { 1843 pccbb_intr_route(sc); 1844 } 1845 1846 /* 1847 * Allocate a room for interrupt handler structure. 1848 */ 1849 if (NULL == (newpil = 1850 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1851 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1852 return NULL; 1853 } 1854 1855 newpil->pil_func = func; 1856 newpil->pil_arg = arg; 1857 newpil->pil_level = level; 1858 1859 if (LIST_EMPTY(&sc->sc_pil)) { 1860 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1861 } else { 1862 for (pil = LIST_FIRST(&sc->sc_pil); 1863 LIST_NEXT(pil, pil_next) != NULL; 1864 pil = LIST_NEXT(pil, pil_next)); 1865 LIST_INSERT_AFTER(pil, newpil, pil_next); 1866 } 1867 1868 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1869 LIST_FIRST(&sc->sc_pil))); 1870 1871 return newpil; 1872 } 1873 1874 /* 1875 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1876 * void *ih) 1877 * 1878 * This function removes an interrupt handler pointed by ih. ih 1879 * should be the value returned by cardbus_intr_establish() or 1880 * NULL. 1881 * 1882 * When ih is NULL, this function will do nothing. 1883 */ 1884 static void 1885 pccbb_intr_disestablish(sc, ih) 1886 struct pccbb_softc *sc; 1887 void *ih; 1888 { 1889 struct pccbb_intrhand_list *pil; 1890 pcireg_t reg; 1891 1892 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1893 LIST_FIRST(&sc->sc_pil))); 1894 1895 if (ih == NULL) { 1896 /* intr handler is not set */ 1897 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1898 return; 1899 } 1900 1901 #ifdef DIAGNOSTIC 1902 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1903 pil = LIST_NEXT(pil, pil_next)) { 1904 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1905 if (pil == ih) { 1906 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1907 break; 1908 } 1909 } 1910 if (pil == NULL) { 1911 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1912 sc->sc_dev.dv_xname, ih); 1913 } 1914 #endif 1915 1916 pil = (struct pccbb_intrhand_list *)ih; 1917 LIST_REMOVE(pil, pil_next); 1918 free(pil, M_DEVBUF); 1919 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1920 1921 if (LIST_EMPTY(&sc->sc_pil)) { 1922 /* No interrupt handlers */ 1923 1924 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1925 1926 /* stop routing PCI intr */ 1927 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1928 reg |= CB_BCR_INTR_IREQ_ENABLE; 1929 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1930 1931 switch (sc->sc_chipset) { 1932 case CB_TI113X: 1933 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1934 /* functional intr disabled */ 1935 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1936 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1937 break; 1938 default: 1939 break; 1940 } 1941 } 1942 } 1943 1944 #if defined SHOW_REGS 1945 static void 1946 cb_show_regs(pc, tag, memt, memh) 1947 pci_chipset_tag_t pc; 1948 pcitag_t tag; 1949 bus_space_tag_t memt; 1950 bus_space_handle_t memh; 1951 { 1952 int i; 1953 printf("PCI config regs:"); 1954 for (i = 0; i < 0x50; i += 4) { 1955 if (i % 16 == 0) { 1956 printf("\n 0x%02x:", i); 1957 } 1958 printf(" %08x", pci_conf_read(pc, tag, i)); 1959 } 1960 for (i = 0x80; i < 0xb0; i += 4) { 1961 if (i % 16 == 0) { 1962 printf("\n 0x%02x:", i); 1963 } 1964 printf(" %08x", pci_conf_read(pc, tag, i)); 1965 } 1966 1967 if (memh == 0) { 1968 printf("\n"); 1969 return; 1970 } 1971 1972 printf("\nsocket regs:"); 1973 for (i = 0; i <= 0x10; i += 0x04) { 1974 printf(" %08x", bus_space_read_4(memt, memh, i)); 1975 } 1976 printf("\nExCA regs:"); 1977 for (i = 0; i < 0x08; ++i) { 1978 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1979 } 1980 printf("\n"); 1981 return; 1982 } 1983 #endif 1984 1985 /* 1986 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1987 * int busno, int function) 1988 * This is the function to make a tag to access config space of 1989 * a CardBus Card. It works same as pci_conf_read. 1990 */ 1991 static cardbustag_t 1992 pccbb_make_tag(cc, busno, function) 1993 cardbus_chipset_tag_t cc; 1994 int busno, function; 1995 { 1996 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1997 1998 return pci_make_tag(sc->sc_pc, busno, 0, function); 1999 } 2000 2001 static void 2002 pccbb_free_tag(cc, tag) 2003 cardbus_chipset_tag_t cc; 2004 cardbustag_t tag; 2005 { 2006 } 2007 2008 /* 2009 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 2010 * cardbustag_t tag, int offset) 2011 * This is the function to read the config space of a CardBus Card. 2012 * It works same as pci_conf_read. 2013 */ 2014 static cardbusreg_t 2015 pccbb_conf_read(cc, tag, offset) 2016 cardbus_chipset_tag_t cc; 2017 cardbustag_t tag; 2018 int offset; /* register offset */ 2019 { 2020 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2021 2022 return pci_conf_read(sc->sc_pc, tag, offset); 2023 } 2024 2025 /* 2026 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 2027 * int offs, cardbusreg_t val) 2028 * This is the function to write the config space of a CardBus Card. 2029 * It works same as pci_conf_write. 2030 */ 2031 static void 2032 pccbb_conf_write(cc, tag, reg, val) 2033 cardbus_chipset_tag_t cc; 2034 cardbustag_t tag; 2035 int reg; /* register offset */ 2036 cardbusreg_t val; 2037 { 2038 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2039 2040 pci_conf_write(sc->sc_pc, tag, reg, val); 2041 } 2042 2043 #if 0 2044 STATIC int 2045 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2046 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2047 int speed, int flags, 2048 bus_space_handle_t * iohp) 2049 #endif 2050 /* 2051 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2052 * bus_addr_t start, bus_size_t size, 2053 * bus_size_t align, 2054 * struct pcmcia_io_handle *pcihp 2055 * 2056 * This function only allocates I/O region for pccard. This function 2057 * never maps the allocated region to pccard I/O area. 2058 * 2059 * XXX: The interface of this function is not very good, I believe. 2060 */ 2061 STATIC int 2062 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2063 pcmcia_chipset_handle_t pch; 2064 bus_addr_t start; /* start address */ 2065 bus_size_t size; 2066 bus_size_t align; 2067 struct pcmcia_io_handle *pcihp; 2068 { 2069 struct pcic_handle *ph = (struct pcic_handle *)pch; 2070 bus_addr_t ioaddr; 2071 int flags = 0; 2072 bus_space_tag_t iot; 2073 bus_space_handle_t ioh; 2074 bus_addr_t mask; 2075 #if rbus 2076 rbus_tag_t rb; 2077 #endif 2078 if (align == 0) { 2079 align = size; /* XXX: funny??? */ 2080 } 2081 2082 if (start != 0) { 2083 /* XXX: assume all card decode lower 10 bits by its hardware */ 2084 mask = 0x3ff; 2085 /* enforce to use only masked address */ 2086 start &= mask; 2087 } else { 2088 /* 2089 * calculate mask: 2090 * 1. get the most significant bit of size (call it msb). 2091 * 2. compare msb with the value of size. 2092 * 3. if size is larger, shift msb left once. 2093 * 4. obtain mask value to decrement msb. 2094 */ 2095 bus_size_t size_tmp = size; 2096 int shifts = 0; 2097 2098 mask = 1; 2099 while (size_tmp) { 2100 ++shifts; 2101 size_tmp >>= 1; 2102 } 2103 mask = (1 << shifts); 2104 if (mask < size) { 2105 mask <<= 1; 2106 } 2107 --mask; 2108 } 2109 2110 /* 2111 * Allocate some arbitrary I/O space. 2112 */ 2113 2114 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2115 2116 #if rbus 2117 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2118 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2119 return 1; 2120 } 2121 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2122 (u_long) ioaddr, (u_long) size)); 2123 #else 2124 if (start) { 2125 ioaddr = start; 2126 if (bus_space_map(iot, start, size, 0, &ioh)) { 2127 return 1; 2128 } 2129 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2130 (u_long) ioaddr, (u_long) size)); 2131 } else { 2132 flags |= PCMCIA_IO_ALLOCATED; 2133 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2134 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2135 size, align, 0, 0, &ioaddr, &ioh)) { 2136 /* No room be able to be get. */ 2137 return 1; 2138 } 2139 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2140 (u_long) ioaddr, (u_long) size)); 2141 } 2142 #endif 2143 2144 pcihp->iot = iot; 2145 pcihp->ioh = ioh; 2146 pcihp->addr = ioaddr; 2147 pcihp->size = size; 2148 pcihp->flags = flags; 2149 2150 return 0; 2151 } 2152 2153 /* 2154 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2155 * struct pcmcia_io_handle *pcihp) 2156 * 2157 * This function only frees I/O region for pccard. 2158 * 2159 * XXX: The interface of this function is not very good, I believe. 2160 */ 2161 void 2162 pccbb_pcmcia_io_free(pch, pcihp) 2163 pcmcia_chipset_handle_t pch; 2164 struct pcmcia_io_handle *pcihp; 2165 { 2166 #if !rbus 2167 bus_space_tag_t iot = pcihp->iot; 2168 #endif 2169 bus_space_handle_t ioh = pcihp->ioh; 2170 bus_size_t size = pcihp->size; 2171 2172 #if rbus 2173 struct pccbb_softc *sc = 2174 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2175 rbus_tag_t rb = sc->sc_rbus_iot; 2176 2177 rbus_space_free(rb, ioh, size, NULL); 2178 #else 2179 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2180 bus_space_free(iot, ioh, size); 2181 else 2182 bus_space_unmap(iot, ioh, size); 2183 #endif 2184 } 2185 2186 /* 2187 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2188 * bus_addr_t offset, bus_size_t size, 2189 * struct pcmcia_io_handle *pcihp, 2190 * int *windowp) 2191 * 2192 * This function maps the allocated I/O region to pccard. This function 2193 * never allocates any I/O region for pccard I/O area. I don't 2194 * understand why the original authors of pcmciabus separated alloc and 2195 * map. I believe the two must be unite. 2196 * 2197 * XXX: no wait timing control? 2198 */ 2199 int 2200 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2201 pcmcia_chipset_handle_t pch; 2202 int width; 2203 bus_addr_t offset; 2204 bus_size_t size; 2205 struct pcmcia_io_handle *pcihp; 2206 int *windowp; 2207 { 2208 struct pcic_handle *ph = (struct pcic_handle *)pch; 2209 bus_addr_t ioaddr = pcihp->addr + offset; 2210 int i, win; 2211 #if defined CBB_DEBUG 2212 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2213 #endif 2214 2215 /* Sanity check I/O handle. */ 2216 2217 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2218 panic("pccbb_pcmcia_io_map iot is bogus"); 2219 } 2220 2221 /* XXX Sanity check offset/size. */ 2222 2223 win = -1; 2224 for (i = 0; i < PCIC_IO_WINS; i++) { 2225 if ((ph->ioalloc & (1 << i)) == 0) { 2226 win = i; 2227 ph->ioalloc |= (1 << i); 2228 break; 2229 } 2230 } 2231 2232 if (win == -1) { 2233 return 1; 2234 } 2235 2236 *windowp = win; 2237 2238 /* XXX this is pretty gross */ 2239 2240 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2241 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2242 2243 /* XXX wtf is this doing here? */ 2244 2245 #if 0 2246 printf(" port 0x%lx", (u_long) ioaddr); 2247 if (size > 1) { 2248 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2249 } 2250 #endif 2251 2252 ph->io[win].addr = ioaddr; 2253 ph->io[win].size = size; 2254 ph->io[win].width = width; 2255 2256 /* actual dirty register-value changing in the function below. */ 2257 pccbb_pcmcia_do_io_map(ph, win); 2258 2259 return 0; 2260 } 2261 2262 /* 2263 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2264 * 2265 * This function changes register-value to map I/O region for pccard. 2266 */ 2267 static void 2268 pccbb_pcmcia_do_io_map(ph, win) 2269 struct pcic_handle *ph; 2270 int win; 2271 { 2272 static u_int8_t pcic_iowidth[3] = { 2273 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2274 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2275 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2276 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2277 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2278 }; 2279 2280 #define PCIC_SIA_START_LOW 0 2281 #define PCIC_SIA_START_HIGH 1 2282 #define PCIC_SIA_STOP_LOW 2 2283 #define PCIC_SIA_STOP_HIGH 3 2284 2285 int regbase_win = 0x8 + win * 0x04; 2286 u_int8_t ioctl, enable; 2287 2288 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2289 "width %d\n", win, (unsigned long)ph->io[win].addr, 2290 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2291 2292 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2293 ph->io[win].addr & 0xff); 2294 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2295 (ph->io[win].addr >> 8) & 0xff); 2296 2297 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2298 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2299 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2300 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2301 2302 ioctl = Pcic_read(ph, PCIC_IOCTL); 2303 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2304 switch (win) { 2305 case 0: 2306 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2307 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2308 PCIC_IOCTL_IO0_DATASIZE_MASK); 2309 ioctl |= pcic_iowidth[ph->io[win].width]; 2310 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2311 break; 2312 case 1: 2313 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2314 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2315 PCIC_IOCTL_IO1_DATASIZE_MASK); 2316 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2317 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2318 break; 2319 } 2320 Pcic_write(ph, PCIC_IOCTL, ioctl); 2321 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2322 #if defined CBB_DEBUG 2323 { 2324 u_int8_t start_low = 2325 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2326 u_int8_t start_high = 2327 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2328 u_int8_t stop_low = 2329 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2330 u_int8_t stop_high = 2331 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2332 printf 2333 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2334 start_low, start_high, stop_low, stop_high, ioctl, enable); 2335 } 2336 #endif 2337 } 2338 2339 /* 2340 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2341 * 2342 * This function unmaps I/O region. No return value. 2343 */ 2344 STATIC void 2345 pccbb_pcmcia_io_unmap(pch, win) 2346 pcmcia_chipset_handle_t pch; 2347 int win; 2348 { 2349 struct pcic_handle *ph = (struct pcic_handle *)pch; 2350 int reg; 2351 2352 if (win >= PCIC_IO_WINS || win < 0) { 2353 panic("pccbb_pcmcia_io_unmap: window out of range"); 2354 } 2355 2356 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2357 switch (win) { 2358 case 0: 2359 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2360 break; 2361 case 1: 2362 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2363 break; 2364 } 2365 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2366 2367 ph->ioalloc &= ~(1 << win); 2368 } 2369 2370 static int 2371 pccbb_pcmcia_wait_ready(ph) 2372 struct pcic_handle *ph; 2373 { 2374 u_int8_t stat; 2375 int i; 2376 2377 /* wait an initial 10ms for quick cards */ 2378 stat = Pcic_read(ph, PCIC_IF_STATUS); 2379 if (stat & PCIC_IF_STATUS_READY) 2380 return (0); 2381 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2382 for (i = 0; i < 50; i++) { 2383 stat = Pcic_read(ph, PCIC_IF_STATUS); 2384 if (stat & PCIC_IF_STATUS_READY) 2385 return (0); 2386 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2387 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2388 return (ENXIO); 2389 /* wait .1s (100ms) each iteration now */ 2390 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2391 } 2392 2393 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2394 return (EWOULDBLOCK); 2395 } 2396 2397 /* 2398 * Perform long (msec order) delay. 2399 */ 2400 static void 2401 pccbb_pcmcia_delay(ph, timo, wmesg) 2402 struct pcic_handle *ph; 2403 int timo; /* in ms. must not be zero */ 2404 const char *wmesg; 2405 { 2406 2407 #ifdef DIAGNOSTIC 2408 if (timo <= 0) 2409 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2410 if (!curlwp) 2411 panic("pccbb_pcmcia_delay: called in interrupt context"); 2412 #if 0 2413 if (!ph->event_thread) 2414 panic("pccbb_pcmcia_delay: no event thread"); 2415 #endif 2416 #endif 2417 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2418 wmesg, ph->event_thread, timo)); 2419 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2420 } 2421 2422 /* 2423 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2424 * 2425 * This function enables the card. All information is stored in 2426 * the first argument, pcmcia_chipset_handle_t. 2427 */ 2428 STATIC void 2429 pccbb_pcmcia_socket_enable(pch) 2430 pcmcia_chipset_handle_t pch; 2431 { 2432 struct pcic_handle *ph = (struct pcic_handle *)pch; 2433 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2434 pcireg_t spsr; 2435 int voltage; 2436 int win; 2437 u_int8_t power, intr; 2438 #ifdef DIAGNOSTIC 2439 int reg; 2440 #endif 2441 2442 /* this bit is mostly stolen from pcic_attach_card */ 2443 2444 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2445 2446 /* get card Vcc info */ 2447 spsr = 2448 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2449 CB_SOCKET_STAT); 2450 if (spsr & CB_SOCKET_STAT_5VCARD) { 2451 DPRINTF(("5V card\n")); 2452 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2453 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2454 DPRINTF(("3V card\n")); 2455 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2456 } else { 2457 printf("?V card, 0x%x\n", spsr); /* XXX */ 2458 return; 2459 } 2460 2461 /* disable interrupts; assert RESET */ 2462 intr = Pcic_read(ph, PCIC_INTR); 2463 intr &= PCIC_INTR_ENABLE; 2464 Pcic_write(ph, PCIC_INTR, intr); 2465 2466 /* zero out the address windows */ 2467 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2468 2469 /* power down the socket to reset it, clear the card reset pin */ 2470 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2471 2472 /* power off; assert output enable bit */ 2473 power = PCIC_PWRCTL_OE; 2474 Pcic_write(ph, PCIC_PWRCTL, power); 2475 2476 /* power up the socket */ 2477 if (pccbb_power(sc, voltage) == 0) 2478 return; 2479 2480 /* 2481 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2482 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2483 * RESET Width (Th (Hi-z RESET)) = 1ms 2484 * RESET Width (Tw (RESET)) = 10us 2485 */ 2486 pccbb_pcmcia_delay(ph, 1, "pccen1"); 2487 2488 /* negate RESET */ 2489 intr |= PCIC_INTR_RESET; 2490 Pcic_write(ph, PCIC_INTR, intr); 2491 2492 /* 2493 * RESET Setup Time (Tsu (RESET)) = 20ms 2494 */ 2495 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2496 2497 #ifdef DIAGNOSTIC 2498 reg = Pcic_read(ph, PCIC_IF_STATUS); 2499 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2500 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2501 #endif 2502 2503 /* wait for the chip to finish initializing */ 2504 if (pccbb_pcmcia_wait_ready(ph)) { 2505 /* XXX return a failure status?? */ 2506 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2507 Pcic_write(ph, PCIC_PWRCTL, 0); 2508 return; 2509 } 2510 2511 /* reinstall all the memory and io mappings */ 2512 for (win = 0; win < PCIC_MEM_WINS; ++win) 2513 if (ph->memalloc & (1 << win)) 2514 pccbb_pcmcia_do_mem_map(ph, win); 2515 for (win = 0; win < PCIC_IO_WINS; ++win) 2516 if (ph->ioalloc & (1 << win)) 2517 pccbb_pcmcia_do_io_map(ph, win); 2518 } 2519 2520 /* 2521 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2522 * 2523 * This function disables the card. All information is stored in 2524 * the first argument, pcmcia_chipset_handle_t. 2525 */ 2526 STATIC void 2527 pccbb_pcmcia_socket_disable(pch) 2528 pcmcia_chipset_handle_t pch; 2529 { 2530 struct pcic_handle *ph = (struct pcic_handle *)pch; 2531 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2532 u_int8_t intr; 2533 2534 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2535 2536 /* disable interrupts; assert RESET */ 2537 intr = Pcic_read(ph, PCIC_INTR); 2538 intr &= PCIC_INTR_ENABLE; 2539 Pcic_write(ph, PCIC_INTR, intr); 2540 2541 /* zero out the address windows */ 2542 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2543 2544 /* power down the socket to reset it, clear the card reset pin */ 2545 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2546 2547 /* disable socket: negate output enable bit and power off */ 2548 Pcic_write(ph, PCIC_PWRCTL, 0); 2549 2550 /* 2551 * Vcc Falling Time (Tpf) = 300ms 2552 */ 2553 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2554 } 2555 2556 STATIC void 2557 pccbb_pcmcia_socket_settype(pch, type) 2558 pcmcia_chipset_handle_t pch; 2559 int type; 2560 { 2561 struct pcic_handle *ph = (struct pcic_handle *)pch; 2562 u_int8_t intr; 2563 2564 /* set the card type */ 2565 2566 intr = Pcic_read(ph, PCIC_INTR); 2567 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2568 if (type == PCMCIA_IFTYPE_IO) 2569 intr |= PCIC_INTR_CARDTYPE_IO; 2570 else 2571 intr |= PCIC_INTR_CARDTYPE_MEM; 2572 Pcic_write(ph, PCIC_INTR, intr); 2573 2574 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2575 ph->ph_parent->dv_xname, ph->sock, 2576 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2577 } 2578 2579 /* 2580 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2581 * 2582 * This function detects whether a card is in the slot or not. 2583 * If a card is inserted, return 1. Otherwise, return 0. 2584 */ 2585 STATIC int 2586 pccbb_pcmcia_card_detect(pch) 2587 pcmcia_chipset_handle_t pch; 2588 { 2589 struct pcic_handle *ph = (struct pcic_handle *)pch; 2590 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2591 2592 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2593 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2594 } 2595 2596 #if 0 2597 STATIC int 2598 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2599 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2600 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2601 #endif 2602 /* 2603 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2604 * bus_size_t size, 2605 * struct pcmcia_mem_handle *pcmhp) 2606 * 2607 * This function only allocates memory region for pccard. This 2608 * function never maps the allocated region to pccard memory area. 2609 * 2610 * XXX: Why the argument of start address is not in? 2611 */ 2612 STATIC int 2613 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2614 pcmcia_chipset_handle_t pch; 2615 bus_size_t size; 2616 struct pcmcia_mem_handle *pcmhp; 2617 { 2618 struct pcic_handle *ph = (struct pcic_handle *)pch; 2619 bus_space_handle_t memh; 2620 bus_addr_t addr; 2621 bus_size_t sizepg; 2622 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2623 #if rbus 2624 rbus_tag_t rb; 2625 #endif 2626 2627 /* Check that the card is still there. */ 2628 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2629 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2630 return 1; 2631 2632 /* out of sc->memh, allocate as many pages as necessary */ 2633 2634 /* convert size to PCIC pages */ 2635 /* 2636 * This is not enough; when the requested region is on the page 2637 * boundaries, this may calculate wrong result. 2638 */ 2639 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2640 #if 0 2641 if (sizepg > PCIC_MAX_MEM_PAGES) { 2642 return 1; 2643 } 2644 #endif 2645 2646 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2647 return 1; 2648 } 2649 2650 addr = 0; /* XXX gcc -Wuninitialized */ 2651 2652 #if rbus 2653 rb = sc->sc_rbus_memt; 2654 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2655 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2656 &addr, &memh)) { 2657 return 1; 2658 } 2659 #else 2660 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2661 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2662 0, /* boundary */ 2663 0, /* flags */ 2664 &addr, &memh)) { 2665 return 1; 2666 } 2667 #endif 2668 2669 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2670 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2671 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2672 2673 pcmhp->memt = sc->sc_memt; 2674 pcmhp->memh = memh; 2675 pcmhp->addr = addr; 2676 pcmhp->size = size; 2677 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2678 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2679 pcmhp->mhandle = 0; 2680 /* No offset??? Funny. */ 2681 2682 return 0; 2683 } 2684 2685 /* 2686 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2687 * struct pcmcia_mem_handle *pcmhp) 2688 * 2689 * This function release the memory space allocated by the function 2690 * pccbb_pcmcia_mem_alloc(). 2691 */ 2692 STATIC void 2693 pccbb_pcmcia_mem_free(pch, pcmhp) 2694 pcmcia_chipset_handle_t pch; 2695 struct pcmcia_mem_handle *pcmhp; 2696 { 2697 #if rbus 2698 struct pcic_handle *ph = (struct pcic_handle *)pch; 2699 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2700 2701 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2702 #else 2703 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2704 #endif 2705 } 2706 2707 /* 2708 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2709 * 2710 * This function release the memory space allocated by the function 2711 * pccbb_pcmcia_mem_alloc(). 2712 */ 2713 STATIC void 2714 pccbb_pcmcia_do_mem_map(ph, win) 2715 struct pcic_handle *ph; 2716 int win; 2717 { 2718 int regbase_win; 2719 bus_addr_t phys_addr; 2720 bus_addr_t phys_end; 2721 2722 #define PCIC_SMM_START_LOW 0 2723 #define PCIC_SMM_START_HIGH 1 2724 #define PCIC_SMM_STOP_LOW 2 2725 #define PCIC_SMM_STOP_HIGH 3 2726 #define PCIC_CMA_LOW 4 2727 #define PCIC_CMA_HIGH 5 2728 2729 u_int8_t start_low, start_high = 0; 2730 u_int8_t stop_low, stop_high; 2731 u_int8_t off_low, off_high; 2732 u_int8_t mem_window; 2733 int reg; 2734 2735 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2736 int mem8 = 2737 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2738 || (kind == PCMCIA_MEM_ATTR); 2739 2740 regbase_win = 0x10 + win * 0x08; 2741 2742 phys_addr = ph->mem[win].addr; 2743 phys_end = phys_addr + ph->mem[win].size; 2744 2745 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2746 (unsigned long)phys_addr, (unsigned long)phys_end, 2747 (unsigned long)ph->mem[win].offset)); 2748 2749 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2750 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2751 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2752 2753 /* bit 19:12 */ 2754 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2755 /* bit 23:20 and bit 7 on */ 2756 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2757 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2758 /* bit 31:24, for 32-bit address */ 2759 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2760 2761 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2762 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2763 2764 if (((struct pccbb_softc *)ph-> 2765 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2766 Pcic_write(ph, 0x40 + win, mem_window); 2767 } 2768 2769 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2770 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2771 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2772 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2773 2774 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2775 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2776 2777 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2778 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2779 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2780 | ((kind == PCMCIA_MEM_ATTR) ? 2781 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2782 2783 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2784 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2785 2786 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2787 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2788 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2789 2790 #if defined CBB_DEBUG 2791 { 2792 int r1, r2, r3, r4, r5, r6, r7 = 0; 2793 2794 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2795 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2796 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2797 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2798 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2799 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2800 if (((struct pccbb_softc *)(ph-> 2801 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2802 r7 = Pcic_read(ph, 0x40 + win); 2803 } 2804 2805 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2806 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2807 if (((struct pccbb_softc *)(ph-> 2808 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2809 DPRINTF((" %02x", r7)); 2810 } 2811 DPRINTF(("\n")); 2812 } 2813 #endif 2814 } 2815 2816 /* 2817 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2818 * bus_addr_t card_addr, bus_size_t size, 2819 * struct pcmcia_mem_handle *pcmhp, 2820 * bus_addr_t *offsetp, int *windowp) 2821 * 2822 * This function maps memory space allocated by the function 2823 * pccbb_pcmcia_mem_alloc(). 2824 */ 2825 STATIC int 2826 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2827 pcmcia_chipset_handle_t pch; 2828 int kind; 2829 bus_addr_t card_addr; 2830 bus_size_t size; 2831 struct pcmcia_mem_handle *pcmhp; 2832 bus_addr_t *offsetp; 2833 int *windowp; 2834 { 2835 struct pcic_handle *ph = (struct pcic_handle *)pch; 2836 bus_addr_t busaddr; 2837 long card_offset; 2838 int win; 2839 2840 /* Check that the card is still there. */ 2841 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2842 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2843 return 1; 2844 2845 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2846 if ((ph->memalloc & (1 << win)) == 0) { 2847 ph->memalloc |= (1 << win); 2848 break; 2849 } 2850 } 2851 2852 if (win == PCIC_MEM_WINS) { 2853 return 1; 2854 } 2855 2856 *windowp = win; 2857 2858 /* XXX this is pretty gross */ 2859 2860 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2861 panic("pccbb_pcmcia_mem_map memt is bogus"); 2862 } 2863 2864 busaddr = pcmhp->addr; 2865 2866 /* 2867 * compute the address offset to the pcmcia address space for the 2868 * pcic. this is intentionally signed. The masks and shifts below 2869 * will cause TRT to happen in the pcic registers. Deal with making 2870 * sure the address is aligned, and return the alignment offset. 2871 */ 2872 2873 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2874 card_addr -= *offsetp; 2875 2876 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2877 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2878 (u_long) card_addr)); 2879 2880 /* 2881 * include the offset in the size, and decrement size by one, since 2882 * the hw wants start/stop 2883 */ 2884 size += *offsetp - 1; 2885 2886 card_offset = (((long)card_addr) - ((long)busaddr)); 2887 2888 ph->mem[win].addr = busaddr; 2889 ph->mem[win].size = size; 2890 ph->mem[win].offset = card_offset; 2891 ph->mem[win].kind = kind; 2892 2893 pccbb_pcmcia_do_mem_map(ph, win); 2894 2895 return 0; 2896 } 2897 2898 /* 2899 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2900 * int window) 2901 * 2902 * This function unmaps memory space which mapped by the function 2903 * pccbb_pcmcia_mem_map(). 2904 */ 2905 STATIC void 2906 pccbb_pcmcia_mem_unmap(pch, window) 2907 pcmcia_chipset_handle_t pch; 2908 int window; 2909 { 2910 struct pcic_handle *ph = (struct pcic_handle *)pch; 2911 int reg; 2912 2913 if (window >= PCIC_MEM_WINS) { 2914 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2915 } 2916 2917 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2918 reg &= ~(1 << window); 2919 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2920 2921 ph->memalloc &= ~(1 << window); 2922 } 2923 2924 #if defined PCCBB_PCMCIA_POLL 2925 struct pccbb_poll_str { 2926 void *arg; 2927 int (*func)(void *); 2928 int level; 2929 struct pcic_handle *ph; 2930 int count; 2931 int num; 2932 struct callout poll_ch; 2933 }; 2934 2935 static struct pccbb_poll_str pccbb_poll[10]; 2936 static int pccbb_poll_n = 0; 2937 2938 static void pccbb_pcmcia_poll(void *arg); 2939 2940 static void 2941 pccbb_pcmcia_poll(arg) 2942 void *arg; 2943 { 2944 struct pccbb_poll_str *poll = arg; 2945 struct pcic_handle *ph = poll->ph; 2946 struct pccbb_softc *sc = ph->sc; 2947 int s; 2948 u_int32_t spsr; /* socket present-state reg */ 2949 2950 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2951 switch (poll->level) { 2952 case IPL_NET: 2953 s = splnet(); 2954 break; 2955 case IPL_BIO: 2956 s = splbio(); 2957 break; 2958 case IPL_TTY: /* fallthrough */ 2959 default: 2960 s = spltty(); 2961 break; 2962 } 2963 2964 spsr = 2965 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2966 CB_SOCKET_STAT); 2967 2968 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2969 if (!(spsr & 0x40)) /* CINT low */ 2970 #else 2971 if (1) 2972 #endif 2973 { 2974 if ((*poll->func) (poll->arg) > 0) { 2975 ++poll->count; 2976 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2977 #if defined LEVEL2 2978 } else { 2979 printf("intr: miss! 0x%x\n", spsr); 2980 #endif 2981 } 2982 } 2983 splx(s); 2984 } 2985 #endif /* defined CB_PCMCIA_POLL */ 2986 2987 /* 2988 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2989 * struct pcmcia_function *pf, 2990 * int ipl, 2991 * int (*func)(void *), 2992 * void *arg); 2993 * 2994 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2995 */ 2996 STATIC void * 2997 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2998 pcmcia_chipset_handle_t pch; 2999 struct pcmcia_function *pf; 3000 int ipl; 3001 int (*func)(void *); 3002 void *arg; 3003 { 3004 struct pcic_handle *ph = (struct pcic_handle *)pch; 3005 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3006 3007 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3008 /* what should I do? */ 3009 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3010 DPRINTF(("%s does not provide edge nor pulse " 3011 "interrupt\n", sc->sc_dev.dv_xname)); 3012 return NULL; 3013 } 3014 /* 3015 * XXX Noooooo! The interrupt flag must set properly!! 3016 * dumb pcmcia driver!! 3017 */ 3018 } 3019 3020 return pccbb_intr_establish(sc, 0, ipl, func, arg); 3021 } 3022 3023 /* 3024 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 3025 * void *ih) 3026 * 3027 * This function disables PC-Card interrupt. 3028 */ 3029 STATIC void 3030 pccbb_pcmcia_intr_disestablish(pch, ih) 3031 pcmcia_chipset_handle_t pch; 3032 void *ih; 3033 { 3034 struct pcic_handle *ph = (struct pcic_handle *)pch; 3035 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3036 3037 pccbb_intr_disestablish(sc, ih); 3038 } 3039 3040 #if rbus 3041 /* 3042 * static int 3043 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3044 * bus_addr_t addr, bus_size_t size, 3045 * bus_addr_t mask, bus_size_t align, 3046 * int flags, bus_addr_t *addrp; 3047 * bus_space_handle_t *bshp) 3048 * 3049 * This function allocates a portion of memory or io space for 3050 * clients. This function is called from CardBus card drivers. 3051 */ 3052 static int 3053 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3054 cardbus_chipset_tag_t ct; 3055 rbus_tag_t rb; 3056 bus_addr_t addr; 3057 bus_size_t size; 3058 bus_addr_t mask; 3059 bus_size_t align; 3060 int flags; 3061 bus_addr_t *addrp; 3062 bus_space_handle_t *bshp; 3063 { 3064 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3065 3066 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3067 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3068 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3069 3070 if (align == 0) { 3071 align = size; 3072 } 3073 3074 if (rb->rb_bt == sc->sc_memt) { 3075 if (align < 16) { 3076 return 1; 3077 } 3078 /* 3079 * XXX: align more than 0x1000 to avoid overwrapping 3080 * memory windows for two or more devices. 0x1000 3081 * means memory window's granularity. 3082 * 3083 * Two or more devices should be able to share same 3084 * memory window region. However, overrapping memory 3085 * window is not good because some devices, such as 3086 * 3Com 3C575[BC], have a broken address decoder and 3087 * intrude other's memory region. 3088 */ 3089 if (align < 0x1000) { 3090 align = 0x1000; 3091 } 3092 } else if (rb->rb_bt == sc->sc_iot) { 3093 if (align < 4) { 3094 return 1; 3095 } 3096 /* XXX: hack for avoiding ISA image */ 3097 if (mask < 0x0100) { 3098 mask = 0x3ff; 3099 addr = 0x300; 3100 } 3101 3102 } else { 3103 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3104 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3105 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3106 (unsigned long)sc->sc_memt)); 3107 return 1; 3108 /* XXX: panic here? */ 3109 } 3110 3111 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3112 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3113 return 1; 3114 } 3115 3116 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3117 3118 return 0; 3119 } 3120 3121 /* 3122 * static int 3123 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3124 * bus_space_handle_t *bshp, bus_size_t size); 3125 * 3126 * This function is called from CardBus card drivers. 3127 */ 3128 static int 3129 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3130 cardbus_chipset_tag_t ct; 3131 rbus_tag_t rb; 3132 bus_space_handle_t bsh; 3133 bus_size_t size; 3134 { 3135 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3136 bus_space_tag_t bt = rb->rb_bt; 3137 3138 pccbb_close_win(sc, bt, bsh, size); 3139 3140 if (bt == sc->sc_memt) { 3141 } else if (bt == sc->sc_iot) { 3142 } else { 3143 return 1; 3144 /* XXX: panic here? */ 3145 } 3146 3147 return rbus_space_free(rb, bsh, size, NULL); 3148 } 3149 #endif /* rbus */ 3150 3151 #if rbus 3152 3153 static int 3154 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3155 struct pccbb_softc *sc; 3156 bus_space_tag_t bst; 3157 bus_addr_t addr; 3158 bus_size_t size; 3159 bus_space_handle_t bsh; 3160 int flags; 3161 { 3162 struct pccbb_win_chain_head *head; 3163 bus_addr_t align; 3164 3165 head = &sc->sc_iowindow; 3166 align = 0x04; 3167 if (sc->sc_memt == bst) { 3168 head = &sc->sc_memwindow; 3169 align = 0x1000; 3170 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3171 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3172 (unsigned long)bst)); 3173 } 3174 3175 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3176 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3177 sc->sc_dev.dv_xname, 3178 (head == &sc->sc_memwindow) ? "mem" : "io"); 3179 } 3180 pccbb_winset(align, sc, bst); 3181 3182 return 0; 3183 } 3184 3185 static int 3186 pccbb_close_win(sc, bst, bsh, size) 3187 struct pccbb_softc *sc; 3188 bus_space_tag_t bst; 3189 bus_space_handle_t bsh; 3190 bus_size_t size; 3191 { 3192 struct pccbb_win_chain_head *head; 3193 bus_addr_t align; 3194 3195 head = &sc->sc_iowindow; 3196 align = 0x04; 3197 if (sc->sc_memt == bst) { 3198 head = &sc->sc_memwindow; 3199 align = 0x1000; 3200 } 3201 3202 if (pccbb_winlist_delete(head, bsh, size)) { 3203 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3204 sc->sc_dev.dv_xname, 3205 (head == &sc->sc_memwindow) ? "mem" : "io"); 3206 } 3207 pccbb_winset(align, sc, bst); 3208 3209 return 0; 3210 } 3211 3212 static int 3213 pccbb_winlist_insert(head, start, size, bsh, flags) 3214 struct pccbb_win_chain_head *head; 3215 bus_addr_t start; 3216 bus_size_t size; 3217 bus_space_handle_t bsh; 3218 int flags; 3219 { 3220 struct pccbb_win_chain *chainp, *elem; 3221 3222 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3223 M_NOWAIT)) == NULL) 3224 return (1); /* fail */ 3225 3226 elem->wc_start = start; 3227 elem->wc_end = start + (size - 1); 3228 elem->wc_handle = bsh; 3229 elem->wc_flags = flags; 3230 3231 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3232 chainp = TAILQ_NEXT(chainp, wc_list)) { 3233 if (chainp->wc_end < start) 3234 continue; 3235 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3236 return (0); 3237 } 3238 3239 TAILQ_INSERT_TAIL(head, elem, wc_list); 3240 return (0); 3241 } 3242 3243 static int 3244 pccbb_winlist_delete(head, bsh, size) 3245 struct pccbb_win_chain_head *head; 3246 bus_space_handle_t bsh; 3247 bus_size_t size; 3248 { 3249 struct pccbb_win_chain *chainp; 3250 3251 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3252 chainp = TAILQ_NEXT(chainp, wc_list)) { 3253 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3254 continue; 3255 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3256 printf("pccbb_winlist_delete: window 0x%lx size " 3257 "inconsistent: 0x%lx, 0x%lx\n", 3258 (unsigned long)chainp->wc_start, 3259 (unsigned long)(chainp->wc_end - chainp->wc_start), 3260 (unsigned long)(size - 1)); 3261 return 1; 3262 } 3263 3264 TAILQ_REMOVE(head, chainp, wc_list); 3265 free(chainp, M_DEVBUF); 3266 3267 return 0; 3268 } 3269 3270 return 1; /* fail: no candidate to remove */ 3271 } 3272 3273 static void 3274 pccbb_winset(align, sc, bst) 3275 bus_addr_t align; 3276 struct pccbb_softc *sc; 3277 bus_space_tag_t bst; 3278 { 3279 pci_chipset_tag_t pc; 3280 pcitag_t tag; 3281 bus_addr_t mask = ~(align - 1); 3282 struct { 3283 cardbusreg_t win_start; 3284 cardbusreg_t win_limit; 3285 int win_flags; 3286 } win[2]; 3287 struct pccbb_win_chain *chainp; 3288 int offs; 3289 3290 win[0].win_start = win[1].win_start = 0xffffffff; 3291 win[0].win_limit = win[1].win_limit = 0; 3292 win[0].win_flags = win[1].win_flags = 0; 3293 3294 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3295 offs = 0x2c; 3296 if (sc->sc_memt == bst) { 3297 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3298 offs = 0x1c; 3299 } 3300 3301 if (chainp != NULL) { 3302 win[0].win_start = chainp->wc_start & mask; 3303 win[0].win_limit = chainp->wc_end & mask; 3304 win[0].win_flags = chainp->wc_flags; 3305 chainp = TAILQ_NEXT(chainp, wc_list); 3306 } 3307 3308 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3309 if (win[1].win_start == 0xffffffff) { 3310 /* window 1 is not used */ 3311 if ((win[0].win_flags == chainp->wc_flags) && 3312 (win[0].win_limit + align >= 3313 (chainp->wc_start & mask))) { 3314 /* concatenate */ 3315 win[0].win_limit = chainp->wc_end & mask; 3316 } else { 3317 /* make new window */ 3318 win[1].win_start = chainp->wc_start & mask; 3319 win[1].win_limit = chainp->wc_end & mask; 3320 win[1].win_flags = chainp->wc_flags; 3321 } 3322 continue; 3323 } 3324 3325 /* Both windows are engaged. */ 3326 if (win[0].win_flags == win[1].win_flags) { 3327 /* same flags */ 3328 if (win[0].win_flags == chainp->wc_flags) { 3329 if (win[1].win_start - (win[0].win_limit + 3330 align) < 3331 (chainp->wc_start & mask) - 3332 ((chainp->wc_end & mask) + align)) { 3333 /* 3334 * merge window 0 and 1, and set win1 3335 * to chainp 3336 */ 3337 win[0].win_limit = win[1].win_limit; 3338 win[1].win_start = 3339 chainp->wc_start & mask; 3340 win[1].win_limit = 3341 chainp->wc_end & mask; 3342 } else { 3343 win[1].win_limit = 3344 chainp->wc_end & mask; 3345 } 3346 } else { 3347 /* different flags */ 3348 3349 /* concatenate win0 and win1 */ 3350 win[0].win_limit = win[1].win_limit; 3351 /* allocate win[1] to new space */ 3352 win[1].win_start = chainp->wc_start & mask; 3353 win[1].win_limit = chainp->wc_end & mask; 3354 win[1].win_flags = chainp->wc_flags; 3355 } 3356 } else { 3357 /* the flags of win[0] and win[1] is different */ 3358 if (win[0].win_flags == chainp->wc_flags) { 3359 win[0].win_limit = chainp->wc_end & mask; 3360 /* 3361 * XXX this creates overlapping windows, so 3362 * what should the poor bridge do if one is 3363 * cachable, and the other is not? 3364 */ 3365 printf("%s: overlapping windows\n", 3366 sc->sc_dev.dv_xname); 3367 } else { 3368 win[1].win_limit = chainp->wc_end & mask; 3369 } 3370 } 3371 } 3372 3373 pc = sc->sc_pc; 3374 tag = sc->sc_tag; 3375 pci_conf_write(pc, tag, offs, win[0].win_start); 3376 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3377 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3378 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3379 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3380 (unsigned long)pci_conf_read(pc, tag, offs), 3381 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3382 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3383 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3384 3385 if (bst == sc->sc_memt) { 3386 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3387 3388 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3389 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3390 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3391 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3392 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3393 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3394 } 3395 } 3396 3397 #endif /* rbus */ 3398 3399 static void 3400 pccbb_powerhook(why, arg) 3401 int why; 3402 void *arg; 3403 { 3404 struct pccbb_softc *sc = arg; 3405 pcireg_t reg; 3406 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3407 bus_space_handle_t base_memh = sc->sc_base_memh; 3408 3409 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3410 3411 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3412 DPRINTF(("%s: power: why %d stopping intr\n", 3413 sc->sc_dev.dv_xname, why)); 3414 if (sc->sc_pil_intr_enable) { 3415 (void)pccbbintr_function(sc); 3416 } 3417 sc->sc_pil_intr_enable = 0; 3418 3419 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3420 3421 /* ToDo: deactivate or suspend child devices */ 3422 3423 } 3424 3425 if (why == PWR_RESUME) { 3426 if (sc->sc_pwrmgt_offs != 0) { 3427 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3428 sc->sc_pwrmgt_offs + 4); 3429 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3430 reg & 0x100) { 3431 /* powrstate != D0 */ 3432 3433 printf("%s going back to D0 mode\n", 3434 sc->sc_dev.dv_xname); 3435 reg &= ~PCI_PMCSR_STATE_MASK; 3436 reg |= PCI_PMCSR_STATE_D0; 3437 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3438 pci_conf_write(sc->sc_pc, sc->sc_tag, 3439 sc->sc_pwrmgt_offs + 4, reg); 3440 3441 pci_conf_write(sc->sc_pc, sc->sc_tag, 3442 PCI_SOCKBASE, sc->sc_sockbase); 3443 pci_conf_write(sc->sc_pc, sc->sc_tag, 3444 PCI_BUSNUM, sc->sc_busnum); 3445 pccbb_chipinit(sc); 3446 /* setup memory and io space window for CB */ 3447 pccbb_winset(0x1000, sc, sc->sc_memt); 3448 pccbb_winset(0x04, sc, sc->sc_iot); 3449 goto norestore; 3450 } 3451 } 3452 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3453 norestore: 3454 3455 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3456 /* BIOS did not recover this register */ 3457 pci_conf_write (sc->sc_pc, sc->sc_tag, 3458 PCI_SOCKBASE, sc->sc_sockbase); 3459 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3460 /* BIOS did not recover this register */ 3461 pci_conf_write (sc->sc_pc, sc->sc_tag, 3462 PCI_BUSNUM, sc->sc_busnum); 3463 /* CSC Interrupt: Card detect interrupt on */ 3464 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3465 /* Card detect intr is turned on. */ 3466 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3467 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3468 /* reset interrupt */ 3469 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3470 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3471 3472 /* 3473 * check for card insertion or removal during suspend period. 3474 * XXX: the code can't cope with card swap (remove then 3475 * insert). how can we detect such situation? 3476 */ 3477 (void)pccbbintr(sc); 3478 3479 sc->sc_pil_intr_enable = 1; 3480 DPRINTF(("%s: power: RESUME enabling intr\n", 3481 sc->sc_dev.dv_xname)); 3482 3483 /* ToDo: activate or wakeup child devices */ 3484 } 3485 } 3486
Indexes created Fri Sep 26 08:10:20 GMT 2025