pccbb.c revision 1.129
1 /* $NetBSD: pccbb.c,v 1.129 2006/06/17 17:06:51 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.129 2006/06/17 17:06:51 jmcneill Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 42 /* 43 #define CB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL_ONLY 45 #define LEVEL2 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/ioctl.h> 53 #include <sys/reboot.h> /* for bootverbose */ 54 #include <sys/syslog.h> 55 #include <sys/device.h> 56 #include <sys/malloc.h> 57 #include <sys/proc.h> 58 59 #include <machine/intr.h> 60 #include <machine/bus.h> 61 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcidevs.h> 65 66 #include <dev/pci/pccbbreg.h> 67 68 #include <dev/cardbus/cardslotvar.h> 69 70 #include <dev/cardbus/cardbusvar.h> 71 72 #include <dev/pcmcia/pcmciareg.h> 73 #include <dev/pcmcia/pcmciavar.h> 74 75 #include <dev/ic/i82365reg.h> 76 #include <dev/ic/i82365var.h> 77 #include <dev/pci/pccbbvar.h> 78 79 #include "locators.h" 80 81 #if defined(__i386__) 82 #include "ioapic.h" 83 #endif 84 85 #ifndef __NetBSD_Version__ 86 struct cfdriver cbb_cd = { 87 NULL, "cbb", DV_DULL 88 }; 89 #endif 90 91 #ifdef CBB_DEBUG 92 #define DPRINTF(x) printf x 93 #define STATIC 94 #else 95 #define DPRINTF(x) 96 #define STATIC static 97 #endif 98 99 /* 100 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 101 * if you want to wait more than 1 ms. 102 */ 103 #define DELAY_MS(time, param) \ 104 do { \ 105 if (cold == 0) { \ 106 int xtick = (hz*(time))/1000; \ 107 \ 108 if (xtick <= 1) { \ 109 xtick = 2; \ 110 } \ 111 tsleep((void *)(param), PWAIT, "pccbb", xtick); \ 112 } else { \ 113 delay((time)*1000); \ 114 } \ 115 } while (/*CONSTCOND*/0) 116 117 int pcicbbmatch(struct device *, struct cfdata *, void *); 118 void pccbbattach(struct device *, struct device *, void *); 119 int pccbbintr(void *); 120 static void pci113x_insert(void *); 121 static int pccbbintr_function(struct pccbb_softc *); 122 123 static int pccbb_detect_card(struct pccbb_softc *); 124 125 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 126 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 127 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 128 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 129 130 STATIC int cb_reset(struct pccbb_softc *); 131 STATIC int cb_detect_voltage(struct pccbb_softc *); 132 STATIC int cbbprint(void *, const char *); 133 134 static int cb_chipset(u_int32_t, int *); 135 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 136 struct pcmciabus_attach_args *); 137 #if 0 138 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 139 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 140 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 141 #endif 142 143 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 144 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 145 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 146 #if !rbus 147 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 148 static int pccbb_io_close(cardbus_chipset_tag_t, int); 149 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 150 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 151 #endif /* !rbus */ 152 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 153 int level, int (*ih) (void *), void *sc); 154 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 155 156 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 157 int level, int (*ih) (void *), void *sc); 158 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 159 160 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 161 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 162 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 163 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t); 165 static void pccbb_chipinit(struct pccbb_softc *); 166 167 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *); 169 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *); 171 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 173 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 174 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 176 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *); 178 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *); 180 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 181 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *); 183 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 184 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 185 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 186 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 187 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 188 189 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 190 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 191 192 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 193 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 194 static void pccbb_powerhook(int, void *); 195 196 /* bus-space allocation and deallocation functions */ 197 #if rbus 198 199 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 200 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 201 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 202 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 203 bus_space_handle_t, bus_size_t); 204 205 #endif /* rbus */ 206 207 #if rbus 208 209 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 210 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 211 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 212 bus_space_handle_t, bus_size_t); 213 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 214 bus_size_t, bus_space_handle_t, int); 215 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 216 bus_space_handle_t, bus_size_t); 217 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 218 bus_space_tag_t); 219 void pccbb_winlist_show(struct pccbb_win_chain *); 220 221 #endif /* rbus */ 222 223 /* for config_defer */ 224 static void pccbb_pci_callback(struct device *); 225 226 #if defined SHOW_REGS 227 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 228 bus_space_tag_t memt, bus_space_handle_t memh); 229 #endif 230 231 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 232 pcicbbmatch, pccbbattach, NULL, NULL); 233 234 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 235 pccbb_pcmcia_mem_alloc, 236 pccbb_pcmcia_mem_free, 237 pccbb_pcmcia_mem_map, 238 pccbb_pcmcia_mem_unmap, 239 pccbb_pcmcia_io_alloc, 240 pccbb_pcmcia_io_free, 241 pccbb_pcmcia_io_map, 242 pccbb_pcmcia_io_unmap, 243 pccbb_pcmcia_intr_establish, 244 pccbb_pcmcia_intr_disestablish, 245 pccbb_pcmcia_socket_enable, 246 pccbb_pcmcia_socket_disable, 247 pccbb_pcmcia_socket_settype, 248 pccbb_pcmcia_card_detect 249 }; 250 251 #if rbus 252 static struct cardbus_functions pccbb_funcs = { 253 pccbb_rbus_cb_space_alloc, 254 pccbb_rbus_cb_space_free, 255 pccbb_cb_intr_establish, 256 pccbb_cb_intr_disestablish, 257 pccbb_ctrl, 258 pccbb_power, 259 pccbb_make_tag, 260 pccbb_free_tag, 261 pccbb_conf_read, 262 pccbb_conf_write, 263 }; 264 #else 265 static struct cardbus_functions pccbb_funcs = { 266 pccbb_ctrl, 267 pccbb_power, 268 pccbb_mem_open, 269 pccbb_mem_close, 270 pccbb_io_open, 271 pccbb_io_close, 272 pccbb_cb_intr_establish, 273 pccbb_cb_intr_disestablish, 274 pccbb_make_tag, 275 pccbb_conf_read, 276 pccbb_conf_write, 277 }; 278 #endif 279 280 int 281 pcicbbmatch(parent, match, aux) 282 struct device *parent; 283 struct cfdata *match; 284 void *aux; 285 { 286 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 287 288 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 289 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 290 PCI_INTERFACE(pa->pa_class) == 0) { 291 return 1; 292 } 293 294 return 0; 295 } 296 297 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 298 | ((prod) << PCI_PRODUCT_SHIFT)) 299 300 const struct yenta_chipinfo { 301 pcireg_t yc_id; /* vendor tag | product tag */ 302 int yc_chiptype; 303 int yc_flags; 304 } yc_chipsets[] = { 305 /* Texas Instruments chips */ 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 331 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 333 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 335 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 337 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 338 339 /* Ricoh chips */ 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 343 PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 345 PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 347 PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 349 PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 351 PCCBB_PCMCIA_MEM_32}, 352 353 /* Toshiba products */ 354 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 355 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 356 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 357 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 358 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 359 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 361 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 362 363 /* Cirrus Logic products */ 364 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 365 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 366 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 367 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 368 369 /* sentinel, or Generic chip */ 370 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 371 }; 372 373 static int 374 cb_chipset(pci_id, flagp) 375 u_int32_t pci_id; 376 int *flagp; 377 { 378 const struct yenta_chipinfo *yc; 379 380 /* Loop over except the last default entry. */ 381 for (yc = yc_chipsets; yc < yc_chipsets + 382 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 383 if (pci_id == yc->yc_id) 384 break; 385 386 if (flagp != NULL) 387 *flagp = yc->yc_flags; 388 389 return (yc->yc_chiptype); 390 } 391 392 static void 393 pccbb_shutdown(void *arg) 394 { 395 struct pccbb_softc *sc = arg; 396 pcireg_t command; 397 398 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 399 400 /* 401 * turn off power 402 * 403 * XXX - do not turn off power if chipset is TI 113X because 404 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 405 */ 406 if (sc->sc_chipset != CB_TI113X) { 407 pccbb_power((cardbus_chipset_tag_t)sc, 408 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 409 } 410 411 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 412 0); 413 414 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 415 416 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 417 PCI_COMMAND_MASTER_ENABLE); 418 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 419 420 } 421 422 void 423 pccbbattach(parent, self, aux) 424 struct device *parent; 425 struct device *self; 426 void *aux; 427 { 428 struct pccbb_softc *sc = (void *)self; 429 struct pci_attach_args *pa = aux; 430 pci_chipset_tag_t pc = pa->pa_pc; 431 pcireg_t busreg, reg, sock_base; 432 bus_addr_t sockbase; 433 char devinfo[256]; 434 int flags; 435 int pwrmgt_offs; 436 437 #ifdef __HAVE_PCCBB_ATTACH_HOOK 438 pccbb_attach_hook(parent, self, pa); 439 #endif 440 441 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 442 443 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 444 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 445 #ifdef CBB_DEBUG 446 printf(" (chipflags %x)", flags); 447 #endif 448 printf("\n"); 449 450 TAILQ_INIT(&sc->sc_memwindow); 451 TAILQ_INIT(&sc->sc_iowindow); 452 453 #if rbus 454 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 455 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 456 457 #if 0 458 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 459 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 460 #endif 461 #endif /* rbus */ 462 463 sc->sc_flags &= ~CBB_MEMHMAPPED; 464 465 /* power management: set D0 state */ 466 sc->sc_pwrmgt_offs = 0; 467 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 468 &pwrmgt_offs, 0)) { 469 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 470 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 471 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 472 reg &= ~PCI_PMCSR_STATE_MASK; 473 reg |= PCI_PMCSR_STATE_D0; 474 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 475 pci_conf_write(pc, pa->pa_tag, 476 pwrmgt_offs + PCI_PMCSR, reg); 477 } 478 479 sc->sc_pwrmgt_offs = pwrmgt_offs; 480 } 481 482 /* 483 * MAP socket registers and ExCA registers on memory-space 484 * When no valid address is set on socket base registers (on pci 485 * config space), get it not polite way. 486 */ 487 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 488 489 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 490 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 491 /* The address must be valid. */ 492 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 493 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 494 printf("%s: can't map socket base address 0x%lx\n", 495 sc->sc_dev.dv_xname, (unsigned long)sock_base); 496 /* 497 * I think it's funny: socket base registers must be 498 * mapped on memory space, but ... 499 */ 500 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 501 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 502 NULL)) { 503 printf("%s: can't map socket base address" 504 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 505 (unsigned long)sockbase); 506 /* give up... allocate reg space via rbus. */ 507 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 508 } else 509 sc->sc_flags |= CBB_MEMHMAPPED; 510 } else { 511 DPRINTF(("%s: socket base address 0x%lx\n", 512 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 513 sc->sc_flags |= CBB_MEMHMAPPED; 514 } 515 } 516 517 sc->sc_mem_start = 0; /* XXX */ 518 sc->sc_mem_end = 0xffffffff; /* XXX */ 519 520 /* 521 * When interrupt isn't routed correctly, give up probing cbb and do 522 * not kill pcic-compatible port. 523 * 524 * However, if we are using an ioapic, avoid this check -- pa_intrline 525 * may well be zero, with the interrupt routed through the apic. 526 */ 527 528 #if NIOAPIC > 0 529 printf("%s: using ioapic for interrupt\n", sc->sc_dev.dv_xname); 530 #else 531 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 532 printf("%s: NOT USED because of unconfigured interrupt\n", 533 sc->sc_dev.dv_xname); 534 return; 535 } 536 #endif 537 538 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 539 540 /* pccbb_machdep.c end */ 541 542 #if defined CBB_DEBUG 543 { 544 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 545 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 546 intrname[pa->pa_intrpin], pa->pa_intrline); 547 } 548 #endif 549 550 /* setup softc */ 551 sc->sc_pc = pc; 552 sc->sc_iot = pa->pa_iot; 553 sc->sc_memt = pa->pa_memt; 554 sc->sc_dmat = pa->pa_dmat; 555 sc->sc_tag = pa->pa_tag; 556 sc->sc_function = pa->pa_function; 557 sc->sc_sockbase = sock_base; 558 sc->sc_busnum = busreg; 559 560 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 561 562 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 563 564 shutdownhook_establish(pccbb_shutdown, sc); 565 566 /* Disable legacy register mapping. */ 567 switch (sc->sc_chipset) { 568 case CB_RX5C46X: /* fallthrough */ 569 #if 0 570 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 571 case CB_RX5C47X: 572 #endif 573 /* 574 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 575 * cannot be disabled by substituting 0 into PCI_LEGACY 576 * register. Ricoh CardBus bridges have special bits on Bridge 577 * control reg (addr 0x3e on PCI config space). 578 */ 579 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 580 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 581 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 582 break; 583 584 default: 585 /* XXX I don't know proper way to kill legacy I/O. */ 586 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 587 break; 588 } 589 590 config_defer(self, pccbb_pci_callback); 591 } 592 593 594 595 596 /* 597 * static void pccbb_pci_callback(struct device *self) 598 * 599 * The actual attach routine: get memory space for YENTA register 600 * space, setup YENTA register and route interrupt. 601 * 602 * This function should be deferred because this device may obtain 603 * memory space dynamically. This function must avoid obtaining 604 * memory area which has already kept for another device. 605 */ 606 static void 607 pccbb_pci_callback(self) 608 struct device *self; 609 { 610 struct pccbb_softc *sc = (void *)self; 611 pci_chipset_tag_t pc = sc->sc_pc; 612 pci_intr_handle_t ih; 613 const char *intrstr = NULL; 614 bus_addr_t sockbase; 615 struct cbslot_attach_args cba; 616 struct pcmciabus_attach_args paa; 617 struct cardslot_attach_args caa; 618 struct cardslot_softc *csc; 619 620 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 621 /* The socket registers aren't mapped correctly. */ 622 #if rbus 623 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 624 (sc->sc_chipset == CB_RX5C47X 625 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 626 0, &sockbase, &sc->sc_base_memh)) { 627 return; 628 } 629 sc->sc_base_memt = sc->sc_memt; 630 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 631 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 632 sc->sc_dev.dv_xname, (unsigned long)sockbase, 633 (unsigned long)pci_conf_read(pc, sc->sc_tag, 634 PCI_SOCKBASE))); 635 #else 636 sc->sc_base_memt = sc->sc_memt; 637 #if !defined CBB_PCI_BASE 638 #define CBB_PCI_BASE 0x20000000 639 #endif 640 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 641 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 642 /* cannot allocate memory space */ 643 return; 644 } 645 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 646 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 647 sc->sc_dev.dv_xname, (unsigned long)sock_base, 648 (unsigned long)pci_conf_read(pc, 649 sc->sc_tag, PCI_SOCKBASE))); 650 sc->sc_sockbase = sockbase; 651 #endif 652 sc->sc_flags |= CBB_MEMHMAPPED; 653 } 654 655 /* bus bridge initialization */ 656 pccbb_chipinit(sc); 657 658 /* clear data structure for child device interrupt handlers */ 659 LIST_INIT(&sc->sc_pil); 660 sc->sc_pil_intr_enable = 1; 661 662 /* Map and establish the interrupt. */ 663 if (pci_intr_map(&sc->sc_pa, &ih)) { 664 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 665 return; 666 } 667 intrstr = pci_intr_string(pc, ih); 668 669 /* 670 * XXX pccbbintr should be called under the priority lower 671 * than any other hard interupts. 672 */ 673 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 674 675 if (sc->sc_ih == NULL) { 676 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 677 if (intrstr != NULL) { 678 printf(" at %s", intrstr); 679 } 680 printf("\n"); 681 return; 682 } 683 684 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 685 powerhook_establish(pccbb_powerhook, sc); 686 687 { 688 u_int32_t sockstat; 689 690 sockstat = bus_space_read_4(sc->sc_base_memt, 691 sc->sc_base_memh, CB_SOCKET_STAT); 692 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 693 sc->sc_flags |= CBB_CARDEXIST; 694 } 695 } 696 697 /* 698 * attach cardbus 699 */ 700 { 701 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 702 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 703 704 /* initialize cbslot_attach */ 705 cba.cba_busname = "cardbus"; 706 cba.cba_iot = sc->sc_iot; 707 cba.cba_memt = sc->sc_memt; 708 cba.cba_dmat = sc->sc_dmat; 709 cba.cba_bus = (busreg >> 8) & 0x0ff; 710 cba.cba_cc = (void *)sc; 711 cba.cba_cf = &pccbb_funcs; 712 cba.cba_intrline = sc->sc_pa.pa_intrline; 713 714 #if rbus 715 cba.cba_rbus_iot = sc->sc_rbus_iot; 716 cba.cba_rbus_memt = sc->sc_rbus_memt; 717 #endif 718 719 cba.cba_cacheline = PCI_CACHELINE(bhlc); 720 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 721 722 if (bootverbose) { 723 printf("%s: cacheline 0x%x lattimer 0x%x\n", 724 sc->sc_dev.dv_xname, cba.cba_cacheline, 725 cba.cba_lattimer); 726 printf("%s: bhlc 0x%x lscp 0x%x\n", 727 sc->sc_dev.dv_xname, bhlc, busreg); 728 } 729 #if defined SHOW_REGS 730 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 731 sc->sc_base_memh); 732 #endif 733 } 734 735 pccbb_pcmcia_attach_setup(sc, &paa); 736 caa.caa_cb_attach = NULL; 737 if (cba.cba_bus == 0) 738 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 739 else 740 caa.caa_cb_attach = &cba; 741 caa.caa_16_attach = &paa; 742 caa.caa_ph = &sc->sc_pcmcia_h; 743 744 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 745 DPRINTF(("pccbbattach: found cardslot\n")); 746 sc->sc_csc = csc; 747 } 748 749 return; 750 } 751 752 753 754 755 756 /* 757 * static void pccbb_chipinit(struct pccbb_softc *sc) 758 * 759 * This function initialize YENTA chip registers listed below: 760 * 1) PCI command reg, 761 * 2) PCI and CardBus latency timer, 762 * 3) route PCI interrupt, 763 * 4) close all memory and io windows. 764 * 5) turn off bus power. 765 * 6) card detect and power cycle interrupts on. 766 * 7) clear interrupt 767 */ 768 static void 769 pccbb_chipinit(sc) 770 struct pccbb_softc *sc; 771 { 772 pci_chipset_tag_t pc = sc->sc_pc; 773 pcitag_t tag = sc->sc_tag; 774 bus_space_tag_t bmt = sc->sc_base_memt; 775 bus_space_handle_t bmh = sc->sc_base_memh; 776 pcireg_t reg; 777 778 /* 779 * Set PCI command reg. 780 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 781 */ 782 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 783 /* I believe it is harmless. */ 784 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 785 PCI_COMMAND_MASTER_ENABLE); 786 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 787 788 /* 789 * Set CardBus latency timer. 790 */ 791 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 792 if (PCI_CB_LATENCY(reg) < 0x20) { 793 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 794 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 795 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 796 } 797 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 798 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 799 800 /* 801 * Set PCI latency timer. 802 */ 803 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 804 if (PCI_LATTIMER(reg) < 0x10) { 805 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 806 reg |= (0x10 << PCI_LATTIMER_SHIFT); 807 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 808 } 809 DPRINTF(("PCI latency timer 0x%x (%x)\n", 810 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 811 812 813 /* Route functional interrupts to PCI. */ 814 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 815 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 816 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 817 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 818 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 819 820 switch (sc->sc_chipset) { 821 case CB_TI113X: 822 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 823 /* This bit is shared, but may read as 0 on some chips, so set 824 it explicitly on both functions. */ 825 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 826 /* CSC intr enable */ 827 reg |= PCI113X_CBCTRL_PCI_CSC; 828 /* functional intr prohibit | prohibit ISA routing */ 829 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 830 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 831 break; 832 833 case CB_TI12XX: 834 /* 835 * Some TI 12xx (and [14][45]xx) based pci cards 836 * sometimes have issues with the MFUNC register not 837 * being initialized due to a bad EEPROM on board. 838 * Laptops that this matters on have this register 839 * properly initialized. 840 * 841 * The TI125X parts have a different register. 842 */ 843 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 844 if (reg == 0) { 845 reg &= ~PCI12XX_MFUNC_PIN0; 846 reg |= PCI12XX_MFUNC_PIN0_INTA; 847 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 848 PCI12XX_SYSCTRL_INTRTIE) == 0) { 849 reg &= ~PCI12XX_MFUNC_PIN1; 850 reg |= PCI12XX_MFUNC_PIN1_INTB; 851 } 852 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 853 } 854 /* fallthrough */ 855 856 case CB_TI125X: 857 /* 858 * Disable zoom video. Some machines initialize this 859 * improperly and experience has shown that this helps 860 * prevent strange behavior. 861 */ 862 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 863 864 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 865 reg |= PCI12XX_SYSCTRL_VCCPROT; 866 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 867 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 868 reg |= PCI12XX_CBCTRL_CSC; 869 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 870 break; 871 872 case CB_TOPIC95B: 873 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 874 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 875 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 876 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 877 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 878 sc->sc_dev.dv_xname, reg)); 879 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 880 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 881 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 882 DPRINTF(("0x%x\n", reg)); 883 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 884 break; 885 886 case CB_TOPIC97: 887 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 888 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 889 sc->sc_dev.dv_xname, reg)); 890 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 891 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 892 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 893 reg |= TOPIC97_SLOT_CTRL_PCIINT; 894 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 895 DPRINTF(("0x%x\n", reg)); 896 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 897 /* make sure to assert LV card support bits */ 898 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 899 0x800 + 0x3e, 900 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 901 0x800 + 0x3e) | 0x03); 902 break; 903 } 904 905 /* Close all memory and I/O windows. */ 906 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 907 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 908 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 909 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 910 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 911 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 912 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 913 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 914 915 /* reset 16-bit pcmcia bus */ 916 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 917 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 918 919 /* turn off power */ 920 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 921 922 /* CSC Interrupt: Card detect and power cycle interrupts on */ 923 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 924 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 925 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 926 /* reset interrupt */ 927 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 928 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 929 } 930 931 932 933 934 /* 935 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 936 * struct pcmciabus_attach_args *paa) 937 * 938 * This function attaches 16-bit PCcard bus. 939 */ 940 STATIC void 941 pccbb_pcmcia_attach_setup(sc, paa) 942 struct pccbb_softc *sc; 943 struct pcmciabus_attach_args *paa; 944 { 945 struct pcic_handle *ph = &sc->sc_pcmcia_h; 946 #if rbus 947 rbus_tag_t rb; 948 #endif 949 950 /* initialize pcmcia part in pccbb_softc */ 951 ph->ph_parent = (struct device *)sc; 952 ph->sock = sc->sc_function; 953 ph->flags = 0; 954 ph->shutdown = 0; 955 ph->ih_irq = sc->sc_pa.pa_intrline; 956 ph->ph_bus_t = sc->sc_base_memt; 957 ph->ph_bus_h = sc->sc_base_memh; 958 ph->ph_read = pccbb_pcmcia_read; 959 ph->ph_write = pccbb_pcmcia_write; 960 sc->sc_pct = &pccbb_pcmcia_funcs; 961 962 /* 963 * We need to do a few things here: 964 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 965 * setting the IRQ numbers to 0. 966 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 967 * routing of CSC interrupts (e.g. card removal) to PCI while in 968 * PCMCIA mode. We just leave this set all the time. 969 * 3) Enable card insertion/removal interrupts in case the chip also 970 * needs that while in PCMCIA mode. 971 * 4) Clear any pending CSC interrupt. 972 */ 973 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 974 if (sc->sc_chipset == CB_TI113X) { 975 Pcic_write(ph, PCIC_CSC_INTR, 0); 976 } else { 977 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 978 Pcic_read(ph, PCIC_CSC); 979 } 980 981 /* initialize pcmcia bus attachment */ 982 paa->paa_busname = "pcmcia"; 983 paa->pct = sc->sc_pct; 984 paa->pch = ph; 985 paa->iobase = 0; /* I don't use them */ 986 paa->iosize = 0; 987 #if rbus 988 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 989 paa->iobase = rb->rb_start + rb->rb_offset; 990 paa->iosize = rb->rb_end - rb->rb_start; 991 #endif 992 993 return; 994 } 995 996 #if 0 997 STATIC void 998 pccbb_pcmcia_attach_card(ph) 999 struct pcic_handle *ph; 1000 { 1001 if (ph->flags & PCIC_FLAG_CARDP) { 1002 panic("pccbb_pcmcia_attach_card: already attached"); 1003 } 1004 1005 /* call the MI attach function */ 1006 pcmcia_card_attach(ph->pcmcia); 1007 1008 ph->flags |= PCIC_FLAG_CARDP; 1009 } 1010 1011 STATIC void 1012 pccbb_pcmcia_detach_card(ph, flags) 1013 struct pcic_handle *ph; 1014 int flags; 1015 { 1016 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1017 panic("pccbb_pcmcia_detach_card: already detached"); 1018 } 1019 1020 ph->flags &= ~PCIC_FLAG_CARDP; 1021 1022 /* call the MI detach function */ 1023 pcmcia_card_detach(ph->pcmcia, flags); 1024 } 1025 #endif 1026 1027 /* 1028 * int pccbbintr(arg) 1029 * void *arg; 1030 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1031 * itself. 1032 */ 1033 int 1034 pccbbintr(arg) 1035 void *arg; 1036 { 1037 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1038 u_int32_t sockevent, sockstate; 1039 bus_space_tag_t memt = sc->sc_base_memt; 1040 bus_space_handle_t memh = sc->sc_base_memh; 1041 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1042 1043 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1044 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1045 Pcic_read(ph, PCIC_CSC); 1046 1047 if (sockevent == 0) { 1048 /* This intr is not for me: it may be for my child devices. */ 1049 if (sc->sc_pil_intr_enable) { 1050 return pccbbintr_function(sc); 1051 } else { 1052 return 0; 1053 } 1054 } 1055 1056 if (sockevent & CB_SOCKET_EVENT_CD) { 1057 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1058 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1059 /* A card should be removed. */ 1060 if (sc->sc_flags & CBB_CARDEXIST) { 1061 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1062 sockevent)); 1063 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1064 sc->sc_flags &= ~CBB_CARDEXIST; 1065 if (sc->sc_csc->sc_status & 1066 CARDSLOT_STATUS_CARD_16) { 1067 #if 0 1068 struct pcic_handle *ph = 1069 &sc->sc_pcmcia_h; 1070 1071 pcmcia_card_deactivate(ph->pcmcia); 1072 pccbb_pcmcia_socket_disable(ph); 1073 pccbb_pcmcia_detach_card(ph, 1074 DETACH_FORCE); 1075 #endif 1076 cardslot_event_throw(sc->sc_csc, 1077 CARDSLOT_EVENT_REMOVAL_16); 1078 } else if (sc->sc_csc->sc_status & 1079 CARDSLOT_STATUS_CARD_CB) { 1080 /* Cardbus intr removed */ 1081 cardslot_event_throw(sc->sc_csc, 1082 CARDSLOT_EVENT_REMOVAL_CB); 1083 } 1084 } else if (sc->sc_flags & CBB_INSERTING) { 1085 sc->sc_flags &= ~CBB_INSERTING; 1086 callout_stop(&sc->sc_insert_ch); 1087 } 1088 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1089 /* 1090 * The pccbbintr may called from powerdown hook when 1091 * the system resumed, to detect the card 1092 * insertion/removal during suspension. 1093 */ 1094 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1095 if (sc->sc_flags & CBB_INSERTING) { 1096 callout_stop(&sc->sc_insert_ch); 1097 } 1098 callout_reset(&sc->sc_insert_ch, hz / 5, 1099 pci113x_insert, sc); 1100 sc->sc_flags |= CBB_INSERTING; 1101 } 1102 } 1103 1104 if (sockevent & CB_SOCKET_EVENT_POWER) { 1105 /* XXX: Does not happen when attaching a 16-bit card */ 1106 sc->sc_pwrcycle++; 1107 wakeup(&sc->sc_pwrcycle); 1108 } 1109 1110 return (1); 1111 } 1112 1113 /* 1114 * static int pccbbintr_function(struct pccbb_softc *sc) 1115 * 1116 * This function calls each interrupt handler registered at the 1117 * bridge. The interrupt handlers are called in registered order. 1118 */ 1119 static int 1120 pccbbintr_function(sc) 1121 struct pccbb_softc *sc; 1122 { 1123 int retval = 0, val; 1124 struct pccbb_intrhand_list *pil; 1125 int s, splchanged; 1126 1127 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1128 pil = LIST_NEXT(pil, pil_next)) { 1129 /* 1130 * XXX priority change. gross. I use if-else 1131 * sentense instead of switch-case sentense because of 1132 * avoiding duplicate case value error. More than one 1133 * IPL_XXX use same value. It depends on 1134 * implimentation. 1135 */ 1136 splchanged = 1; 1137 if (pil->pil_level == IPL_SERIAL) { 1138 s = splserial(); 1139 } else if (pil->pil_level == IPL_HIGH) { 1140 s = splhigh(); 1141 } else if (pil->pil_level == IPL_CLOCK) { 1142 s = splclock(); 1143 } else if (pil->pil_level == IPL_AUDIO) { 1144 s = splaudio(); 1145 } else if (pil->pil_level == IPL_VM) { 1146 s = splvm(); 1147 } else if (pil->pil_level == IPL_TTY) { 1148 s = spltty(); 1149 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1150 s = splsoftserial(); 1151 } else if (pil->pil_level == IPL_NET) { 1152 s = splnet(); 1153 } else { 1154 s = 0; /* XXX: gcc */ 1155 splchanged = 0; 1156 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1157 } 1158 1159 val = (*pil->pil_func)(pil->pil_arg); 1160 1161 if (splchanged != 0) { 1162 splx(s); 1163 } 1164 1165 retval = retval == 1 ? 1 : 1166 retval == 0 ? val : val != 0 ? val : retval; 1167 } 1168 1169 return retval; 1170 } 1171 1172 static void 1173 pci113x_insert(arg) 1174 void *arg; 1175 { 1176 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1177 u_int32_t sockevent, sockstate; 1178 1179 if (!(sc->sc_flags & CBB_INSERTING)) { 1180 /* We add a card only under inserting state. */ 1181 return; 1182 } 1183 sc->sc_flags &= ~CBB_INSERTING; 1184 1185 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1186 CB_SOCKET_EVENT); 1187 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1188 CB_SOCKET_STAT); 1189 1190 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1191 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1192 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1193 sc->sc_flags |= CBB_CARDEXIST; 1194 /* call pccard interrupt handler here */ 1195 if (sockstate & CB_SOCKET_STAT_16BIT) { 1196 /* 16-bit card found */ 1197 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1198 cardslot_event_throw(sc->sc_csc, 1199 CARDSLOT_EVENT_INSERTION_16); 1200 } else if (sockstate & CB_SOCKET_STAT_CB) { 1201 /* cardbus card found */ 1202 /* cardbus_attach_card(sc->sc_csc); */ 1203 cardslot_event_throw(sc->sc_csc, 1204 CARDSLOT_EVENT_INSERTION_CB); 1205 } else { 1206 /* who are you? */ 1207 } 1208 } else { 1209 callout_reset(&sc->sc_insert_ch, hz / 10, 1210 pci113x_insert, sc); 1211 } 1212 } 1213 1214 #define PCCBB_PCMCIA_OFFSET 0x800 1215 static u_int8_t 1216 pccbb_pcmcia_read(ph, reg) 1217 struct pcic_handle *ph; 1218 int reg; 1219 { 1220 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1221 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1222 1223 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1224 PCCBB_PCMCIA_OFFSET + reg); 1225 } 1226 1227 static void 1228 pccbb_pcmcia_write(ph, reg, val) 1229 struct pcic_handle *ph; 1230 int reg; 1231 u_int8_t val; 1232 { 1233 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1234 val); 1235 1236 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1237 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1238 } 1239 1240 /* 1241 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1242 */ 1243 STATIC int 1244 pccbb_ctrl(ct, command) 1245 cardbus_chipset_tag_t ct; 1246 int command; 1247 { 1248 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1249 1250 switch (command) { 1251 case CARDBUS_CD: 1252 if (2 == pccbb_detect_card(sc)) { 1253 int retval = 0; 1254 int status = cb_detect_voltage(sc); 1255 if (PCCARD_VCC_5V & status) { 1256 retval |= CARDBUS_5V_CARD; 1257 } 1258 if (PCCARD_VCC_3V & status) { 1259 retval |= CARDBUS_3V_CARD; 1260 } 1261 if (PCCARD_VCC_XV & status) { 1262 retval |= CARDBUS_XV_CARD; 1263 } 1264 if (PCCARD_VCC_YV & status) { 1265 retval |= CARDBUS_YV_CARD; 1266 } 1267 return retval; 1268 } else { 1269 return 0; 1270 } 1271 case CARDBUS_RESET: 1272 return cb_reset(sc); 1273 case CARDBUS_IO_ENABLE: /* fallthrough */ 1274 case CARDBUS_IO_DISABLE: /* fallthrough */ 1275 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1276 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1277 case CARDBUS_BM_ENABLE: /* fallthrough */ 1278 case CARDBUS_BM_DISABLE: /* fallthrough */ 1279 /* XXX: I think we don't need to call this function below. */ 1280 return pccbb_cardenable(sc, command); 1281 } 1282 1283 return 0; 1284 } 1285 1286 /* 1287 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1288 * This function returns true when it succeeds and returns false when 1289 * it fails. 1290 */ 1291 STATIC int 1292 pccbb_power(ct, command) 1293 cardbus_chipset_tag_t ct; 1294 int command; 1295 { 1296 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1297 u_int32_t status, sock_ctrl, reg_ctrl; 1298 bus_space_tag_t memt = sc->sc_base_memt; 1299 bus_space_handle_t memh = sc->sc_base_memh; 1300 int on = 0, pwrcycle; 1301 1302 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1303 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1304 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1305 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1306 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1307 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1308 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1309 "UNKNOWN", 1310 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1311 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1312 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1313 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1314 "UNKNOWN", command)); 1315 1316 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1317 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1318 1319 switch (command & CARDBUS_VCCMASK) { 1320 case CARDBUS_VCC_UC: 1321 break; 1322 case CARDBUS_VCC_5V: 1323 on++; 1324 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1325 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1326 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1327 } else { 1328 printf("%s: BAD voltage request: no 5 V card\n", 1329 sc->sc_dev.dv_xname); 1330 return 0; 1331 } 1332 break; 1333 case CARDBUS_VCC_3V: 1334 on++; 1335 if (CB_SOCKET_STAT_3VCARD & status) { 1336 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1337 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1338 } else { 1339 printf("%s: BAD voltage request: no 3.3 V card\n", 1340 sc->sc_dev.dv_xname); 1341 return 0; 1342 } 1343 break; 1344 case CARDBUS_VCC_0V: 1345 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1346 break; 1347 default: 1348 return 0; /* power NEVER changed */ 1349 } 1350 1351 switch (command & CARDBUS_VPPMASK) { 1352 case CARDBUS_VPP_UC: 1353 break; 1354 case CARDBUS_VPP_0V: 1355 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1356 break; 1357 case CARDBUS_VPP_VCC: 1358 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1359 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1360 break; 1361 case CARDBUS_VPP_12V: 1362 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1363 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1364 break; 1365 } 1366 1367 pwrcycle = sc->sc_pwrcycle; 1368 1369 #if 0 1370 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1371 #endif 1372 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1373 1374 if (on) { 1375 int s, error = 0; 1376 struct timeval before, after, diff; 1377 1378 microtime(&before); 1379 s = splbio(); 1380 while (pwrcycle == sc->sc_pwrcycle) { 1381 /* 1382 * XXX: Set timeout to 200ms because power cycle event 1383 * will never happen when attaching a 16-bit card. 1384 */ 1385 if ((error = tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1386 hz / 5)) == EWOULDBLOCK) 1387 break; 1388 } 1389 splx(s); 1390 microtime(&after); 1391 timersub(&after, &before, &diff); 1392 aprint_debug("%s: wait took%s %ld.%06lds\n", 1393 sc->sc_dev.dv_xname, 1394 error == EWOULDBLOCK ? " too long" : "", 1395 diff.tv_sec, diff.tv_usec); 1396 } 1397 1398 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1399 1400 if (on) { 1401 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1402 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1403 } 1404 1405 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1406 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1407 sc->sc_dev.dv_xname, sock_ctrl, status); 1408 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1409 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1410 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1411 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1412 status &= ~CB_SOCKET_STAT_BADVCC; 1413 bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1414 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1415 CB_SOCKET_STAT)); 1416 return 0; 1417 } 1418 1419 if (sc->sc_chipset == CB_TOPIC97) { 1420 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1421 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1422 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1423 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1424 else 1425 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1426 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1427 } 1428 1429 return 1; /* power changed correctly */ 1430 } 1431 1432 #if defined CB_PCMCIA_POLL 1433 struct cb_poll_str { 1434 void *arg; 1435 int (*func)(void *); 1436 int level; 1437 pccard_chipset_tag_t ct; 1438 int count; 1439 struct callout poll_ch; 1440 }; 1441 1442 static struct cb_poll_str cb_poll[10]; 1443 static int cb_poll_n = 0; 1444 1445 static void cb_pcmcia_poll(void *arg); 1446 1447 static void 1448 cb_pcmcia_poll(arg) 1449 void *arg; 1450 { 1451 struct cb_poll_str *poll = arg; 1452 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1453 struct pccbb_softc *sc = psc->cpc_parent; 1454 int s; 1455 u_int32_t spsr; /* socket present-state reg */ 1456 1457 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1458 switch (poll->level) { 1459 case IPL_NET: 1460 s = splnet(); 1461 break; 1462 case IPL_BIO: 1463 s = splbio(); 1464 break; 1465 case IPL_TTY: /* fallthrough */ 1466 default: 1467 s = spltty(); 1468 break; 1469 } 1470 1471 spsr = 1472 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1473 CB_SOCKET_STAT); 1474 1475 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1476 if (!(spsr & 0x40)) { /* CINT low */ 1477 #else 1478 if (1) { 1479 #endif 1480 if ((*poll->func) (poll->arg) == 1) { 1481 ++poll->count; 1482 printf("intr: reported from poller, 0x%x\n", spsr); 1483 #if defined LEVEL2 1484 } else { 1485 printf("intr: miss! 0x%x\n", spsr); 1486 #endif 1487 } 1488 } 1489 splx(s); 1490 } 1491 #endif /* defined CB_PCMCIA_POLL */ 1492 1493 /* 1494 * static int pccbb_detect_card(struct pccbb_softc *sc) 1495 * return value: 0 if no card exists. 1496 * 1 if 16-bit card exists. 1497 * 2 if cardbus card exists. 1498 */ 1499 static int 1500 pccbb_detect_card(sc) 1501 struct pccbb_softc *sc; 1502 { 1503 bus_space_handle_t base_memh = sc->sc_base_memh; 1504 bus_space_tag_t base_memt = sc->sc_base_memt; 1505 u_int32_t sockstat = 1506 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1507 int retval = 0; 1508 1509 /* CD1 and CD2 asserted */ 1510 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1511 /* card must be present */ 1512 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1513 /* NOTACARD DEASSERTED */ 1514 if (CB_SOCKET_STAT_CB & sockstat) { 1515 /* CardBus mode */ 1516 retval = 2; 1517 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1518 /* 16-bit mode */ 1519 retval = 1; 1520 } 1521 } 1522 } 1523 return retval; 1524 } 1525 1526 /* 1527 * STATIC int cb_reset(struct pccbb_softc *sc) 1528 * This function resets CardBus card. 1529 */ 1530 STATIC int 1531 cb_reset(sc) 1532 struct pccbb_softc *sc; 1533 { 1534 /* 1535 * Reset Assert at least 20 ms 1536 * Some machines request longer duration. 1537 */ 1538 int reset_duration = 1539 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1540 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1541 1542 /* Reset bit Assert (bit 6 at 0x3E) */ 1543 bcr |= CB_BCR_RESET_ENABLE; 1544 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1545 DELAY_MS(reset_duration, sc); 1546 1547 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1548 /* Reset bit Deassert (bit 6 at 0x3E) */ 1549 bcr &= ~CB_BCR_RESET_ENABLE; 1550 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1551 DELAY_MS(reset_duration, sc); 1552 } 1553 /* No card found on the slot. Keep Reset. */ 1554 return 1; 1555 } 1556 1557 /* 1558 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1559 * This function detect card Voltage. 1560 */ 1561 STATIC int 1562 cb_detect_voltage(sc) 1563 struct pccbb_softc *sc; 1564 { 1565 u_int32_t psr; /* socket present-state reg */ 1566 bus_space_tag_t iot = sc->sc_base_memt; 1567 bus_space_handle_t ioh = sc->sc_base_memh; 1568 int vol = PCCARD_VCC_UKN; /* set 0 */ 1569 1570 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1571 1572 if (0x400u & psr) { 1573 vol |= PCCARD_VCC_5V; 1574 } 1575 if (0x800u & psr) { 1576 vol |= PCCARD_VCC_3V; 1577 } 1578 1579 return vol; 1580 } 1581 1582 STATIC int 1583 cbbprint(aux, pcic) 1584 void *aux; 1585 const char *pcic; 1586 { 1587 /* 1588 struct cbslot_attach_args *cba = aux; 1589 1590 if (cba->cba_slot >= 0) { 1591 aprint_normal(" slot %d", cba->cba_slot); 1592 } 1593 */ 1594 return UNCONF; 1595 } 1596 1597 /* 1598 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1599 * This function enables and disables the card 1600 */ 1601 STATIC int 1602 pccbb_cardenable(sc, function) 1603 struct pccbb_softc *sc; 1604 int function; 1605 { 1606 u_int32_t command = 1607 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1608 1609 DPRINTF(("pccbb_cardenable:")); 1610 switch (function) { 1611 case CARDBUS_IO_ENABLE: 1612 command |= PCI_COMMAND_IO_ENABLE; 1613 break; 1614 case CARDBUS_IO_DISABLE: 1615 command &= ~PCI_COMMAND_IO_ENABLE; 1616 break; 1617 case CARDBUS_MEM_ENABLE: 1618 command |= PCI_COMMAND_MEM_ENABLE; 1619 break; 1620 case CARDBUS_MEM_DISABLE: 1621 command &= ~PCI_COMMAND_MEM_ENABLE; 1622 break; 1623 case CARDBUS_BM_ENABLE: 1624 command |= PCI_COMMAND_MASTER_ENABLE; 1625 break; 1626 case CARDBUS_BM_DISABLE: 1627 command &= ~PCI_COMMAND_MASTER_ENABLE; 1628 break; 1629 default: 1630 return 0; 1631 } 1632 1633 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1634 DPRINTF((" command reg 0x%x\n", command)); 1635 return 1; 1636 } 1637 1638 #if !rbus 1639 /* 1640 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1641 */ 1642 static int 1643 pccbb_io_open(ct, win, start, end) 1644 cardbus_chipset_tag_t ct; 1645 int win; 1646 u_int32_t start, end; 1647 { 1648 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1649 int basereg; 1650 int limitreg; 1651 1652 if ((win < 0) || (win > 2)) { 1653 #if defined DIAGNOSTIC 1654 printf("cardbus_io_open: window out of range %d\n", win); 1655 #endif 1656 return 0; 1657 } 1658 1659 basereg = win * 8 + 0x2c; 1660 limitreg = win * 8 + 0x30; 1661 1662 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1663 start, basereg, end, limitreg)); 1664 1665 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1666 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1667 return 1; 1668 } 1669 1670 /* 1671 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1672 */ 1673 static int 1674 pccbb_io_close(ct, win) 1675 cardbus_chipset_tag_t ct; 1676 int win; 1677 { 1678 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1679 int basereg; 1680 int limitreg; 1681 1682 if ((win < 0) || (win > 2)) { 1683 #if defined DIAGNOSTIC 1684 printf("cardbus_io_close: window out of range %d\n", win); 1685 #endif 1686 return 0; 1687 } 1688 1689 basereg = win * 8 + 0x2c; 1690 limitreg = win * 8 + 0x30; 1691 1692 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1693 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1694 return 1; 1695 } 1696 1697 /* 1698 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1699 */ 1700 static int 1701 pccbb_mem_open(ct, win, start, end) 1702 cardbus_chipset_tag_t ct; 1703 int win; 1704 u_int32_t start, end; 1705 { 1706 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1707 int basereg; 1708 int limitreg; 1709 1710 if ((win < 0) || (win > 2)) { 1711 #if defined DIAGNOSTIC 1712 printf("cardbus_mem_open: window out of range %d\n", win); 1713 #endif 1714 return 0; 1715 } 1716 1717 basereg = win * 8 + 0x1c; 1718 limitreg = win * 8 + 0x20; 1719 1720 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1721 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1722 return 1; 1723 } 1724 1725 /* 1726 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1727 */ 1728 static int 1729 pccbb_mem_close(ct, win) 1730 cardbus_chipset_tag_t ct; 1731 int win; 1732 { 1733 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1734 int basereg; 1735 int limitreg; 1736 1737 if ((win < 0) || (win > 2)) { 1738 #if defined DIAGNOSTIC 1739 printf("cardbus_mem_close: window out of range %d\n", win); 1740 #endif 1741 return 0; 1742 } 1743 1744 basereg = win * 8 + 0x1c; 1745 limitreg = win * 8 + 0x20; 1746 1747 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1748 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1749 return 1; 1750 } 1751 #endif 1752 1753 /* 1754 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1755 * int irq, 1756 * int level, 1757 * int (* func)(void *), 1758 * void *arg) 1759 * 1760 * This function registers an interrupt handler at the bridge, in 1761 * order not to call the interrupt handlers of child devices when 1762 * a card-deletion interrupt occurs. 1763 * 1764 * The arguments irq and level are not used. 1765 */ 1766 static void * 1767 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1768 cardbus_chipset_tag_t ct; 1769 int irq, level; 1770 int (*func)(void *); 1771 void *arg; 1772 { 1773 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1774 1775 return pccbb_intr_establish(sc, irq, level, func, arg); 1776 } 1777 1778 1779 /* 1780 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1781 * void *ih) 1782 * 1783 * This function removes an interrupt handler pointed by ih. 1784 */ 1785 static void 1786 pccbb_cb_intr_disestablish(ct, ih) 1787 cardbus_chipset_tag_t ct; 1788 void *ih; 1789 { 1790 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1791 1792 pccbb_intr_disestablish(sc, ih); 1793 } 1794 1795 1796 void 1797 pccbb_intr_route(sc) 1798 struct pccbb_softc *sc; 1799 { 1800 pcireg_t reg; 1801 1802 /* initialize bridge intr routing */ 1803 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1804 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1805 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1806 1807 switch (sc->sc_chipset) { 1808 case CB_TI113X: 1809 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1810 /* functional intr enabled */ 1811 reg |= PCI113X_CBCTRL_PCI_INTR; 1812 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1813 break; 1814 default: 1815 break; 1816 } 1817 } 1818 1819 /* 1820 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1821 * int irq, 1822 * int level, 1823 * int (* func)(void *), 1824 * void *arg) 1825 * 1826 * This function registers an interrupt handler at the bridge, in 1827 * order not to call the interrupt handlers of child devices when 1828 * a card-deletion interrupt occurs. 1829 * 1830 * The arguments irq is not used because pccbb selects intr vector. 1831 */ 1832 static void * 1833 pccbb_intr_establish(sc, irq, level, func, arg) 1834 struct pccbb_softc *sc; 1835 int irq, level; 1836 int (*func)(void *); 1837 void *arg; 1838 { 1839 struct pccbb_intrhand_list *pil, *newpil; 1840 1841 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1842 1843 if (LIST_EMPTY(&sc->sc_pil)) { 1844 pccbb_intr_route(sc); 1845 } 1846 1847 /* 1848 * Allocate a room for interrupt handler structure. 1849 */ 1850 if (NULL == (newpil = 1851 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1852 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1853 return NULL; 1854 } 1855 1856 newpil->pil_func = func; 1857 newpil->pil_arg = arg; 1858 newpil->pil_level = level; 1859 1860 if (LIST_EMPTY(&sc->sc_pil)) { 1861 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1862 } else { 1863 for (pil = LIST_FIRST(&sc->sc_pil); 1864 LIST_NEXT(pil, pil_next) != NULL; 1865 pil = LIST_NEXT(pil, pil_next)); 1866 LIST_INSERT_AFTER(pil, newpil, pil_next); 1867 } 1868 1869 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1870 LIST_FIRST(&sc->sc_pil))); 1871 1872 return newpil; 1873 } 1874 1875 /* 1876 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1877 * void *ih) 1878 * 1879 * This function removes an interrupt handler pointed by ih. ih 1880 * should be the value returned by cardbus_intr_establish() or 1881 * NULL. 1882 * 1883 * When ih is NULL, this function will do nothing. 1884 */ 1885 static void 1886 pccbb_intr_disestablish(sc, ih) 1887 struct pccbb_softc *sc; 1888 void *ih; 1889 { 1890 struct pccbb_intrhand_list *pil; 1891 pcireg_t reg; 1892 1893 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1894 LIST_FIRST(&sc->sc_pil))); 1895 1896 if (ih == NULL) { 1897 /* intr handler is not set */ 1898 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1899 return; 1900 } 1901 1902 #ifdef DIAGNOSTIC 1903 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1904 pil = LIST_NEXT(pil, pil_next)) { 1905 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1906 if (pil == ih) { 1907 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1908 break; 1909 } 1910 } 1911 if (pil == NULL) { 1912 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1913 sc->sc_dev.dv_xname, ih); 1914 } 1915 #endif 1916 1917 pil = (struct pccbb_intrhand_list *)ih; 1918 LIST_REMOVE(pil, pil_next); 1919 free(pil, M_DEVBUF); 1920 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1921 1922 if (LIST_EMPTY(&sc->sc_pil)) { 1923 /* No interrupt handlers */ 1924 1925 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1926 1927 /* stop routing PCI intr */ 1928 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1929 reg |= CB_BCR_INTR_IREQ_ENABLE; 1930 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1931 1932 switch (sc->sc_chipset) { 1933 case CB_TI113X: 1934 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1935 /* functional intr disabled */ 1936 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1937 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1938 break; 1939 default: 1940 break; 1941 } 1942 } 1943 } 1944 1945 #if defined SHOW_REGS 1946 static void 1947 cb_show_regs(pc, tag, memt, memh) 1948 pci_chipset_tag_t pc; 1949 pcitag_t tag; 1950 bus_space_tag_t memt; 1951 bus_space_handle_t memh; 1952 { 1953 int i; 1954 printf("PCI config regs:"); 1955 for (i = 0; i < 0x50; i += 4) { 1956 if (i % 16 == 0) { 1957 printf("\n 0x%02x:", i); 1958 } 1959 printf(" %08x", pci_conf_read(pc, tag, i)); 1960 } 1961 for (i = 0x80; i < 0xb0; i += 4) { 1962 if (i % 16 == 0) { 1963 printf("\n 0x%02x:", i); 1964 } 1965 printf(" %08x", pci_conf_read(pc, tag, i)); 1966 } 1967 1968 if (memh == 0) { 1969 printf("\n"); 1970 return; 1971 } 1972 1973 printf("\nsocket regs:"); 1974 for (i = 0; i <= 0x10; i += 0x04) { 1975 printf(" %08x", bus_space_read_4(memt, memh, i)); 1976 } 1977 printf("\nExCA regs:"); 1978 for (i = 0; i < 0x08; ++i) { 1979 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1980 } 1981 printf("\n"); 1982 return; 1983 } 1984 #endif 1985 1986 /* 1987 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1988 * int busno, int function) 1989 * This is the function to make a tag to access config space of 1990 * a CardBus Card. It works same as pci_conf_read. 1991 */ 1992 static cardbustag_t 1993 pccbb_make_tag(cc, busno, function) 1994 cardbus_chipset_tag_t cc; 1995 int busno, function; 1996 { 1997 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1998 1999 return pci_make_tag(sc->sc_pc, busno, 0, function); 2000 } 2001 2002 static void 2003 pccbb_free_tag(cc, tag) 2004 cardbus_chipset_tag_t cc; 2005 cardbustag_t tag; 2006 { 2007 } 2008 2009 /* 2010 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 2011 * cardbustag_t tag, int offset) 2012 * This is the function to read the config space of a CardBus Card. 2013 * It works same as pci_conf_read. 2014 */ 2015 static cardbusreg_t 2016 pccbb_conf_read(cc, tag, offset) 2017 cardbus_chipset_tag_t cc; 2018 cardbustag_t tag; 2019 int offset; /* register offset */ 2020 { 2021 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2022 2023 return pci_conf_read(sc->sc_pc, tag, offset); 2024 } 2025 2026 /* 2027 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 2028 * int offs, cardbusreg_t val) 2029 * This is the function to write the config space of a CardBus Card. 2030 * It works same as pci_conf_write. 2031 */ 2032 static void 2033 pccbb_conf_write(cc, tag, reg, val) 2034 cardbus_chipset_tag_t cc; 2035 cardbustag_t tag; 2036 int reg; /* register offset */ 2037 cardbusreg_t val; 2038 { 2039 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2040 2041 pci_conf_write(sc->sc_pc, tag, reg, val); 2042 } 2043 2044 #if 0 2045 STATIC int 2046 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2047 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2048 int speed, int flags, 2049 bus_space_handle_t * iohp) 2050 #endif 2051 /* 2052 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2053 * bus_addr_t start, bus_size_t size, 2054 * bus_size_t align, 2055 * struct pcmcia_io_handle *pcihp 2056 * 2057 * This function only allocates I/O region for pccard. This function 2058 * never maps the allocated region to pccard I/O area. 2059 * 2060 * XXX: The interface of this function is not very good, I believe. 2061 */ 2062 STATIC int 2063 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2064 pcmcia_chipset_handle_t pch; 2065 bus_addr_t start; /* start address */ 2066 bus_size_t size; 2067 bus_size_t align; 2068 struct pcmcia_io_handle *pcihp; 2069 { 2070 struct pcic_handle *ph = (struct pcic_handle *)pch; 2071 bus_addr_t ioaddr; 2072 int flags = 0; 2073 bus_space_tag_t iot; 2074 bus_space_handle_t ioh; 2075 bus_addr_t mask; 2076 #if rbus 2077 rbus_tag_t rb; 2078 #endif 2079 if (align == 0) { 2080 align = size; /* XXX: funny??? */ 2081 } 2082 2083 if (start != 0) { 2084 /* XXX: assume all card decode lower 10 bits by its hardware */ 2085 mask = 0x3ff; 2086 /* enforce to use only masked address */ 2087 start &= mask; 2088 } else { 2089 /* 2090 * calculate mask: 2091 * 1. get the most significant bit of size (call it msb). 2092 * 2. compare msb with the value of size. 2093 * 3. if size is larger, shift msb left once. 2094 * 4. obtain mask value to decrement msb. 2095 */ 2096 bus_size_t size_tmp = size; 2097 int shifts = 0; 2098 2099 mask = 1; 2100 while (size_tmp) { 2101 ++shifts; 2102 size_tmp >>= 1; 2103 } 2104 mask = (1 << shifts); 2105 if (mask < size) { 2106 mask <<= 1; 2107 } 2108 --mask; 2109 } 2110 2111 /* 2112 * Allocate some arbitrary I/O space. 2113 */ 2114 2115 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2116 2117 #if rbus 2118 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2119 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2120 return 1; 2121 } 2122 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2123 (u_long) ioaddr, (u_long) size)); 2124 #else 2125 if (start) { 2126 ioaddr = start; 2127 if (bus_space_map(iot, start, size, 0, &ioh)) { 2128 return 1; 2129 } 2130 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2131 (u_long) ioaddr, (u_long) size)); 2132 } else { 2133 flags |= PCMCIA_IO_ALLOCATED; 2134 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2135 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2136 size, align, 0, 0, &ioaddr, &ioh)) { 2137 /* No room be able to be get. */ 2138 return 1; 2139 } 2140 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2141 (u_long) ioaddr, (u_long) size)); 2142 } 2143 #endif 2144 2145 pcihp->iot = iot; 2146 pcihp->ioh = ioh; 2147 pcihp->addr = ioaddr; 2148 pcihp->size = size; 2149 pcihp->flags = flags; 2150 2151 return 0; 2152 } 2153 2154 /* 2155 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2156 * struct pcmcia_io_handle *pcihp) 2157 * 2158 * This function only frees I/O region for pccard. 2159 * 2160 * XXX: The interface of this function is not very good, I believe. 2161 */ 2162 void 2163 pccbb_pcmcia_io_free(pch, pcihp) 2164 pcmcia_chipset_handle_t pch; 2165 struct pcmcia_io_handle *pcihp; 2166 { 2167 #if !rbus 2168 bus_space_tag_t iot = pcihp->iot; 2169 #endif 2170 bus_space_handle_t ioh = pcihp->ioh; 2171 bus_size_t size = pcihp->size; 2172 2173 #if rbus 2174 struct pccbb_softc *sc = 2175 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2176 rbus_tag_t rb = sc->sc_rbus_iot; 2177 2178 rbus_space_free(rb, ioh, size, NULL); 2179 #else 2180 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2181 bus_space_free(iot, ioh, size); 2182 else 2183 bus_space_unmap(iot, ioh, size); 2184 #endif 2185 } 2186 2187 /* 2188 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2189 * bus_addr_t offset, bus_size_t size, 2190 * struct pcmcia_io_handle *pcihp, 2191 * int *windowp) 2192 * 2193 * This function maps the allocated I/O region to pccard. This function 2194 * never allocates any I/O region for pccard I/O area. I don't 2195 * understand why the original authors of pcmciabus separated alloc and 2196 * map. I believe the two must be unite. 2197 * 2198 * XXX: no wait timing control? 2199 */ 2200 int 2201 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2202 pcmcia_chipset_handle_t pch; 2203 int width; 2204 bus_addr_t offset; 2205 bus_size_t size; 2206 struct pcmcia_io_handle *pcihp; 2207 int *windowp; 2208 { 2209 struct pcic_handle *ph = (struct pcic_handle *)pch; 2210 bus_addr_t ioaddr = pcihp->addr + offset; 2211 int i, win; 2212 #if defined CBB_DEBUG 2213 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2214 #endif 2215 2216 /* Sanity check I/O handle. */ 2217 2218 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2219 panic("pccbb_pcmcia_io_map iot is bogus"); 2220 } 2221 2222 /* XXX Sanity check offset/size. */ 2223 2224 win = -1; 2225 for (i = 0; i < PCIC_IO_WINS; i++) { 2226 if ((ph->ioalloc & (1 << i)) == 0) { 2227 win = i; 2228 ph->ioalloc |= (1 << i); 2229 break; 2230 } 2231 } 2232 2233 if (win == -1) { 2234 return 1; 2235 } 2236 2237 *windowp = win; 2238 2239 /* XXX this is pretty gross */ 2240 2241 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2242 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2243 2244 /* XXX wtf is this doing here? */ 2245 2246 #if 0 2247 printf(" port 0x%lx", (u_long) ioaddr); 2248 if (size > 1) { 2249 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2250 } 2251 #endif 2252 2253 ph->io[win].addr = ioaddr; 2254 ph->io[win].size = size; 2255 ph->io[win].width = width; 2256 2257 /* actual dirty register-value changing in the function below. */ 2258 pccbb_pcmcia_do_io_map(ph, win); 2259 2260 return 0; 2261 } 2262 2263 /* 2264 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2265 * 2266 * This function changes register-value to map I/O region for pccard. 2267 */ 2268 static void 2269 pccbb_pcmcia_do_io_map(ph, win) 2270 struct pcic_handle *ph; 2271 int win; 2272 { 2273 static u_int8_t pcic_iowidth[3] = { 2274 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2275 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2276 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2277 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2278 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2279 }; 2280 2281 #define PCIC_SIA_START_LOW 0 2282 #define PCIC_SIA_START_HIGH 1 2283 #define PCIC_SIA_STOP_LOW 2 2284 #define PCIC_SIA_STOP_HIGH 3 2285 2286 int regbase_win = 0x8 + win * 0x04; 2287 u_int8_t ioctl, enable; 2288 2289 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2290 "width %d\n", win, (unsigned long)ph->io[win].addr, 2291 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2292 2293 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2294 ph->io[win].addr & 0xff); 2295 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2296 (ph->io[win].addr >> 8) & 0xff); 2297 2298 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2299 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2300 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2301 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2302 2303 ioctl = Pcic_read(ph, PCIC_IOCTL); 2304 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2305 switch (win) { 2306 case 0: 2307 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2308 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2309 PCIC_IOCTL_IO0_DATASIZE_MASK); 2310 ioctl |= pcic_iowidth[ph->io[win].width]; 2311 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2312 break; 2313 case 1: 2314 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2315 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2316 PCIC_IOCTL_IO1_DATASIZE_MASK); 2317 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2318 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2319 break; 2320 } 2321 Pcic_write(ph, PCIC_IOCTL, ioctl); 2322 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2323 #if defined CBB_DEBUG 2324 { 2325 u_int8_t start_low = 2326 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2327 u_int8_t start_high = 2328 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2329 u_int8_t stop_low = 2330 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2331 u_int8_t stop_high = 2332 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2333 printf 2334 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2335 start_low, start_high, stop_low, stop_high, ioctl, enable); 2336 } 2337 #endif 2338 } 2339 2340 /* 2341 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2342 * 2343 * This function unmaps I/O region. No return value. 2344 */ 2345 STATIC void 2346 pccbb_pcmcia_io_unmap(pch, win) 2347 pcmcia_chipset_handle_t pch; 2348 int win; 2349 { 2350 struct pcic_handle *ph = (struct pcic_handle *)pch; 2351 int reg; 2352 2353 if (win >= PCIC_IO_WINS || win < 0) { 2354 panic("pccbb_pcmcia_io_unmap: window out of range"); 2355 } 2356 2357 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2358 switch (win) { 2359 case 0: 2360 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2361 break; 2362 case 1: 2363 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2364 break; 2365 } 2366 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2367 2368 ph->ioalloc &= ~(1 << win); 2369 } 2370 2371 static int 2372 pccbb_pcmcia_wait_ready(ph) 2373 struct pcic_handle *ph; 2374 { 2375 u_int8_t stat; 2376 int i; 2377 2378 /* wait an initial 10ms for quick cards */ 2379 stat = Pcic_read(ph, PCIC_IF_STATUS); 2380 if (stat & PCIC_IF_STATUS_READY) 2381 return (0); 2382 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2383 for (i = 0; i < 50; i++) { 2384 stat = Pcic_read(ph, PCIC_IF_STATUS); 2385 if (stat & PCIC_IF_STATUS_READY) 2386 return (0); 2387 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2388 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2389 return (ENXIO); 2390 /* wait .1s (100ms) each iteration now */ 2391 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2392 } 2393 2394 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2395 return (EWOULDBLOCK); 2396 } 2397 2398 /* 2399 * Perform long (msec order) delay. 2400 */ 2401 static void 2402 pccbb_pcmcia_delay(ph, timo, wmesg) 2403 struct pcic_handle *ph; 2404 int timo; /* in ms. must not be zero */ 2405 const char *wmesg; 2406 { 2407 2408 #ifdef DIAGNOSTIC 2409 if (timo <= 0) 2410 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2411 if (!curlwp) 2412 panic("pccbb_pcmcia_delay: called in interrupt context"); 2413 #if 0 2414 if (!ph->event_thread) 2415 panic("pccbb_pcmcia_delay: no event thread"); 2416 #endif 2417 #endif 2418 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2419 wmesg, ph->event_thread, timo)); 2420 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2421 } 2422 2423 /* 2424 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2425 * 2426 * This function enables the card. All information is stored in 2427 * the first argument, pcmcia_chipset_handle_t. 2428 */ 2429 STATIC void 2430 pccbb_pcmcia_socket_enable(pch) 2431 pcmcia_chipset_handle_t pch; 2432 { 2433 struct pcic_handle *ph = (struct pcic_handle *)pch; 2434 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2435 pcireg_t spsr; 2436 int voltage; 2437 int win; 2438 u_int8_t power, intr; 2439 #ifdef DIAGNOSTIC 2440 int reg; 2441 #endif 2442 2443 /* this bit is mostly stolen from pcic_attach_card */ 2444 2445 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2446 2447 /* get card Vcc info */ 2448 spsr = 2449 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2450 CB_SOCKET_STAT); 2451 if (spsr & CB_SOCKET_STAT_5VCARD) { 2452 DPRINTF(("5V card\n")); 2453 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2454 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2455 DPRINTF(("3V card\n")); 2456 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2457 } else { 2458 printf("?V card, 0x%x\n", spsr); /* XXX */ 2459 return; 2460 } 2461 2462 /* disable interrupts; assert RESET */ 2463 intr = Pcic_read(ph, PCIC_INTR); 2464 intr &= PCIC_INTR_ENABLE; 2465 Pcic_write(ph, PCIC_INTR, intr); 2466 2467 /* zero out the address windows */ 2468 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2469 2470 /* power down the socket to reset it, clear the card reset pin */ 2471 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2472 2473 /* power off; assert output enable bit */ 2474 power = PCIC_PWRCTL_OE; 2475 Pcic_write(ph, PCIC_PWRCTL, power); 2476 2477 /* power up the socket */ 2478 if (pccbb_power(sc, voltage) == 0) 2479 return; 2480 2481 /* 2482 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2483 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2484 * RESET Width (Th (Hi-z RESET)) = 1ms 2485 * RESET Width (Tw (RESET)) = 10us 2486 */ 2487 pccbb_pcmcia_delay(ph, 1, "pccen1"); 2488 2489 /* negate RESET */ 2490 intr |= PCIC_INTR_RESET; 2491 Pcic_write(ph, PCIC_INTR, intr); 2492 2493 /* 2494 * RESET Setup Time (Tsu (RESET)) = 20ms 2495 */ 2496 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2497 2498 #ifdef DIAGNOSTIC 2499 reg = Pcic_read(ph, PCIC_IF_STATUS); 2500 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2501 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2502 #endif 2503 2504 /* wait for the chip to finish initializing */ 2505 if (pccbb_pcmcia_wait_ready(ph)) { 2506 /* XXX return a failure status?? */ 2507 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2508 Pcic_write(ph, PCIC_PWRCTL, 0); 2509 return; 2510 } 2511 2512 /* reinstall all the memory and io mappings */ 2513 for (win = 0; win < PCIC_MEM_WINS; ++win) 2514 if (ph->memalloc & (1 << win)) 2515 pccbb_pcmcia_do_mem_map(ph, win); 2516 for (win = 0; win < PCIC_IO_WINS; ++win) 2517 if (ph->ioalloc & (1 << win)) 2518 pccbb_pcmcia_do_io_map(ph, win); 2519 } 2520 2521 /* 2522 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2523 * 2524 * This function disables the card. All information is stored in 2525 * the first argument, pcmcia_chipset_handle_t. 2526 */ 2527 STATIC void 2528 pccbb_pcmcia_socket_disable(pch) 2529 pcmcia_chipset_handle_t pch; 2530 { 2531 struct pcic_handle *ph = (struct pcic_handle *)pch; 2532 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2533 u_int8_t intr; 2534 2535 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2536 2537 /* disable interrupts; assert RESET */ 2538 intr = Pcic_read(ph, PCIC_INTR); 2539 intr &= PCIC_INTR_ENABLE; 2540 Pcic_write(ph, PCIC_INTR, intr); 2541 2542 /* zero out the address windows */ 2543 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2544 2545 /* power down the socket to reset it, clear the card reset pin */ 2546 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2547 2548 /* disable socket: negate output enable bit and power off */ 2549 Pcic_write(ph, PCIC_PWRCTL, 0); 2550 2551 /* 2552 * Vcc Falling Time (Tpf) = 300ms 2553 */ 2554 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2555 } 2556 2557 STATIC void 2558 pccbb_pcmcia_socket_settype(pch, type) 2559 pcmcia_chipset_handle_t pch; 2560 int type; 2561 { 2562 struct pcic_handle *ph = (struct pcic_handle *)pch; 2563 u_int8_t intr; 2564 2565 /* set the card type */ 2566 2567 intr = Pcic_read(ph, PCIC_INTR); 2568 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2569 if (type == PCMCIA_IFTYPE_IO) 2570 intr |= PCIC_INTR_CARDTYPE_IO; 2571 else 2572 intr |= PCIC_INTR_CARDTYPE_MEM; 2573 Pcic_write(ph, PCIC_INTR, intr); 2574 2575 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2576 ph->ph_parent->dv_xname, ph->sock, 2577 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2578 } 2579 2580 /* 2581 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2582 * 2583 * This function detects whether a card is in the slot or not. 2584 * If a card is inserted, return 1. Otherwise, return 0. 2585 */ 2586 STATIC int 2587 pccbb_pcmcia_card_detect(pch) 2588 pcmcia_chipset_handle_t pch; 2589 { 2590 struct pcic_handle *ph = (struct pcic_handle *)pch; 2591 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2592 2593 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2594 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2595 } 2596 2597 #if 0 2598 STATIC int 2599 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2600 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2601 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2602 #endif 2603 /* 2604 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2605 * bus_size_t size, 2606 * struct pcmcia_mem_handle *pcmhp) 2607 * 2608 * This function only allocates memory region for pccard. This 2609 * function never maps the allocated region to pccard memory area. 2610 * 2611 * XXX: Why the argument of start address is not in? 2612 */ 2613 STATIC int 2614 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2615 pcmcia_chipset_handle_t pch; 2616 bus_size_t size; 2617 struct pcmcia_mem_handle *pcmhp; 2618 { 2619 struct pcic_handle *ph = (struct pcic_handle *)pch; 2620 bus_space_handle_t memh; 2621 bus_addr_t addr; 2622 bus_size_t sizepg; 2623 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2624 #if rbus 2625 rbus_tag_t rb; 2626 #endif 2627 2628 /* Check that the card is still there. */ 2629 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2630 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2631 return 1; 2632 2633 /* out of sc->memh, allocate as many pages as necessary */ 2634 2635 /* convert size to PCIC pages */ 2636 /* 2637 * This is not enough; when the requested region is on the page 2638 * boundaries, this may calculate wrong result. 2639 */ 2640 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2641 #if 0 2642 if (sizepg > PCIC_MAX_MEM_PAGES) { 2643 return 1; 2644 } 2645 #endif 2646 2647 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2648 return 1; 2649 } 2650 2651 addr = 0; /* XXX gcc -Wuninitialized */ 2652 2653 #if rbus 2654 rb = sc->sc_rbus_memt; 2655 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2656 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2657 &addr, &memh)) { 2658 return 1; 2659 } 2660 #else 2661 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2662 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2663 0, /* boundary */ 2664 0, /* flags */ 2665 &addr, &memh)) { 2666 return 1; 2667 } 2668 #endif 2669 2670 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2671 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2672 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2673 2674 pcmhp->memt = sc->sc_memt; 2675 pcmhp->memh = memh; 2676 pcmhp->addr = addr; 2677 pcmhp->size = size; 2678 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2679 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2680 pcmhp->mhandle = 0; 2681 /* No offset??? Funny. */ 2682 2683 return 0; 2684 } 2685 2686 /* 2687 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2688 * struct pcmcia_mem_handle *pcmhp) 2689 * 2690 * This function release the memory space allocated by the function 2691 * pccbb_pcmcia_mem_alloc(). 2692 */ 2693 STATIC void 2694 pccbb_pcmcia_mem_free(pch, pcmhp) 2695 pcmcia_chipset_handle_t pch; 2696 struct pcmcia_mem_handle *pcmhp; 2697 { 2698 #if rbus 2699 struct pcic_handle *ph = (struct pcic_handle *)pch; 2700 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2701 2702 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2703 #else 2704 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2705 #endif 2706 } 2707 2708 /* 2709 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2710 * 2711 * This function release the memory space allocated by the function 2712 * pccbb_pcmcia_mem_alloc(). 2713 */ 2714 STATIC void 2715 pccbb_pcmcia_do_mem_map(ph, win) 2716 struct pcic_handle *ph; 2717 int win; 2718 { 2719 int regbase_win; 2720 bus_addr_t phys_addr; 2721 bus_addr_t phys_end; 2722 2723 #define PCIC_SMM_START_LOW 0 2724 #define PCIC_SMM_START_HIGH 1 2725 #define PCIC_SMM_STOP_LOW 2 2726 #define PCIC_SMM_STOP_HIGH 3 2727 #define PCIC_CMA_LOW 4 2728 #define PCIC_CMA_HIGH 5 2729 2730 u_int8_t start_low, start_high = 0; 2731 u_int8_t stop_low, stop_high; 2732 u_int8_t off_low, off_high; 2733 u_int8_t mem_window; 2734 int reg; 2735 2736 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2737 int mem8 = 2738 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2739 || (kind == PCMCIA_MEM_ATTR); 2740 2741 regbase_win = 0x10 + win * 0x08; 2742 2743 phys_addr = ph->mem[win].addr; 2744 phys_end = phys_addr + ph->mem[win].size; 2745 2746 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2747 (unsigned long)phys_addr, (unsigned long)phys_end, 2748 (unsigned long)ph->mem[win].offset)); 2749 2750 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2751 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2752 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2753 2754 /* bit 19:12 */ 2755 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2756 /* bit 23:20 and bit 7 on */ 2757 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2758 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2759 /* bit 31:24, for 32-bit address */ 2760 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2761 2762 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2763 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2764 2765 if (((struct pccbb_softc *)ph-> 2766 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2767 Pcic_write(ph, 0x40 + win, mem_window); 2768 } 2769 2770 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2771 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2772 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2773 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2774 2775 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2776 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2777 2778 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2779 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2780 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2781 | ((kind == PCMCIA_MEM_ATTR) ? 2782 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2783 2784 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2785 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2786 2787 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2788 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2789 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2790 2791 #if defined CBB_DEBUG 2792 { 2793 int r1, r2, r3, r4, r5, r6, r7 = 0; 2794 2795 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2796 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2797 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2798 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2799 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2800 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2801 if (((struct pccbb_softc *)(ph-> 2802 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2803 r7 = Pcic_read(ph, 0x40 + win); 2804 } 2805 2806 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2807 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2808 if (((struct pccbb_softc *)(ph-> 2809 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2810 DPRINTF((" %02x", r7)); 2811 } 2812 DPRINTF(("\n")); 2813 } 2814 #endif 2815 } 2816 2817 /* 2818 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2819 * bus_addr_t card_addr, bus_size_t size, 2820 * struct pcmcia_mem_handle *pcmhp, 2821 * bus_addr_t *offsetp, int *windowp) 2822 * 2823 * This function maps memory space allocated by the function 2824 * pccbb_pcmcia_mem_alloc(). 2825 */ 2826 STATIC int 2827 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2828 pcmcia_chipset_handle_t pch; 2829 int kind; 2830 bus_addr_t card_addr; 2831 bus_size_t size; 2832 struct pcmcia_mem_handle *pcmhp; 2833 bus_addr_t *offsetp; 2834 int *windowp; 2835 { 2836 struct pcic_handle *ph = (struct pcic_handle *)pch; 2837 bus_addr_t busaddr; 2838 long card_offset; 2839 int win; 2840 2841 /* Check that the card is still there. */ 2842 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2843 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2844 return 1; 2845 2846 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2847 if ((ph->memalloc & (1 << win)) == 0) { 2848 ph->memalloc |= (1 << win); 2849 break; 2850 } 2851 } 2852 2853 if (win == PCIC_MEM_WINS) { 2854 return 1; 2855 } 2856 2857 *windowp = win; 2858 2859 /* XXX this is pretty gross */ 2860 2861 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2862 panic("pccbb_pcmcia_mem_map memt is bogus"); 2863 } 2864 2865 busaddr = pcmhp->addr; 2866 2867 /* 2868 * compute the address offset to the pcmcia address space for the 2869 * pcic. this is intentionally signed. The masks and shifts below 2870 * will cause TRT to happen in the pcic registers. Deal with making 2871 * sure the address is aligned, and return the alignment offset. 2872 */ 2873 2874 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2875 card_addr -= *offsetp; 2876 2877 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2878 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2879 (u_long) card_addr)); 2880 2881 /* 2882 * include the offset in the size, and decrement size by one, since 2883 * the hw wants start/stop 2884 */ 2885 size += *offsetp - 1; 2886 2887 card_offset = (((long)card_addr) - ((long)busaddr)); 2888 2889 ph->mem[win].addr = busaddr; 2890 ph->mem[win].size = size; 2891 ph->mem[win].offset = card_offset; 2892 ph->mem[win].kind = kind; 2893 2894 pccbb_pcmcia_do_mem_map(ph, win); 2895 2896 return 0; 2897 } 2898 2899 /* 2900 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2901 * int window) 2902 * 2903 * This function unmaps memory space which mapped by the function 2904 * pccbb_pcmcia_mem_map(). 2905 */ 2906 STATIC void 2907 pccbb_pcmcia_mem_unmap(pch, window) 2908 pcmcia_chipset_handle_t pch; 2909 int window; 2910 { 2911 struct pcic_handle *ph = (struct pcic_handle *)pch; 2912 int reg; 2913 2914 if (window >= PCIC_MEM_WINS) { 2915 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2916 } 2917 2918 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2919 reg &= ~(1 << window); 2920 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2921 2922 ph->memalloc &= ~(1 << window); 2923 } 2924 2925 #if defined PCCBB_PCMCIA_POLL 2926 struct pccbb_poll_str { 2927 void *arg; 2928 int (*func)(void *); 2929 int level; 2930 struct pcic_handle *ph; 2931 int count; 2932 int num; 2933 struct callout poll_ch; 2934 }; 2935 2936 static struct pccbb_poll_str pccbb_poll[10]; 2937 static int pccbb_poll_n = 0; 2938 2939 static void pccbb_pcmcia_poll(void *arg); 2940 2941 static void 2942 pccbb_pcmcia_poll(arg) 2943 void *arg; 2944 { 2945 struct pccbb_poll_str *poll = arg; 2946 struct pcic_handle *ph = poll->ph; 2947 struct pccbb_softc *sc = ph->sc; 2948 int s; 2949 u_int32_t spsr; /* socket present-state reg */ 2950 2951 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2952 switch (poll->level) { 2953 case IPL_NET: 2954 s = splnet(); 2955 break; 2956 case IPL_BIO: 2957 s = splbio(); 2958 break; 2959 case IPL_TTY: /* fallthrough */ 2960 default: 2961 s = spltty(); 2962 break; 2963 } 2964 2965 spsr = 2966 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2967 CB_SOCKET_STAT); 2968 2969 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2970 if (!(spsr & 0x40)) /* CINT low */ 2971 #else 2972 if (1) 2973 #endif 2974 { 2975 if ((*poll->func) (poll->arg) > 0) { 2976 ++poll->count; 2977 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2978 #if defined LEVEL2 2979 } else { 2980 printf("intr: miss! 0x%x\n", spsr); 2981 #endif 2982 } 2983 } 2984 splx(s); 2985 } 2986 #endif /* defined CB_PCMCIA_POLL */ 2987 2988 /* 2989 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2990 * struct pcmcia_function *pf, 2991 * int ipl, 2992 * int (*func)(void *), 2993 * void *arg); 2994 * 2995 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2996 */ 2997 STATIC void * 2998 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2999 pcmcia_chipset_handle_t pch; 3000 struct pcmcia_function *pf; 3001 int ipl; 3002 int (*func)(void *); 3003 void *arg; 3004 { 3005 struct pcic_handle *ph = (struct pcic_handle *)pch; 3006 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3007 3008 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3009 /* what should I do? */ 3010 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3011 DPRINTF(("%s does not provide edge nor pulse " 3012 "interrupt\n", sc->sc_dev.dv_xname)); 3013 return NULL; 3014 } 3015 /* 3016 * XXX Noooooo! The interrupt flag must set properly!! 3017 * dumb pcmcia driver!! 3018 */ 3019 } 3020 3021 return pccbb_intr_establish(sc, 0, ipl, func, arg); 3022 } 3023 3024 /* 3025 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 3026 * void *ih) 3027 * 3028 * This function disables PC-Card interrupt. 3029 */ 3030 STATIC void 3031 pccbb_pcmcia_intr_disestablish(pch, ih) 3032 pcmcia_chipset_handle_t pch; 3033 void *ih; 3034 { 3035 struct pcic_handle *ph = (struct pcic_handle *)pch; 3036 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3037 3038 pccbb_intr_disestablish(sc, ih); 3039 } 3040 3041 #if rbus 3042 /* 3043 * static int 3044 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3045 * bus_addr_t addr, bus_size_t size, 3046 * bus_addr_t mask, bus_size_t align, 3047 * int flags, bus_addr_t *addrp; 3048 * bus_space_handle_t *bshp) 3049 * 3050 * This function allocates a portion of memory or io space for 3051 * clients. This function is called from CardBus card drivers. 3052 */ 3053 static int 3054 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3055 cardbus_chipset_tag_t ct; 3056 rbus_tag_t rb; 3057 bus_addr_t addr; 3058 bus_size_t size; 3059 bus_addr_t mask; 3060 bus_size_t align; 3061 int flags; 3062 bus_addr_t *addrp; 3063 bus_space_handle_t *bshp; 3064 { 3065 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3066 3067 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3068 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3069 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3070 3071 if (align == 0) { 3072 align = size; 3073 } 3074 3075 if (rb->rb_bt == sc->sc_memt) { 3076 if (align < 16) { 3077 return 1; 3078 } 3079 /* 3080 * XXX: align more than 0x1000 to avoid overwrapping 3081 * memory windows for two or more devices. 0x1000 3082 * means memory window's granularity. 3083 * 3084 * Two or more devices should be able to share same 3085 * memory window region. However, overrapping memory 3086 * window is not good because some devices, such as 3087 * 3Com 3C575[BC], have a broken address decoder and 3088 * intrude other's memory region. 3089 */ 3090 if (align < 0x1000) { 3091 align = 0x1000; 3092 } 3093 } else if (rb->rb_bt == sc->sc_iot) { 3094 if (align < 4) { 3095 return 1; 3096 } 3097 /* XXX: hack for avoiding ISA image */ 3098 if (mask < 0x0100) { 3099 mask = 0x3ff; 3100 addr = 0x300; 3101 } 3102 3103 } else { 3104 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3105 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3106 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3107 (unsigned long)sc->sc_memt)); 3108 return 1; 3109 /* XXX: panic here? */ 3110 } 3111 3112 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3113 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3114 return 1; 3115 } 3116 3117 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3118 3119 return 0; 3120 } 3121 3122 /* 3123 * static int 3124 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3125 * bus_space_handle_t *bshp, bus_size_t size); 3126 * 3127 * This function is called from CardBus card drivers. 3128 */ 3129 static int 3130 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3131 cardbus_chipset_tag_t ct; 3132 rbus_tag_t rb; 3133 bus_space_handle_t bsh; 3134 bus_size_t size; 3135 { 3136 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3137 bus_space_tag_t bt = rb->rb_bt; 3138 3139 pccbb_close_win(sc, bt, bsh, size); 3140 3141 if (bt == sc->sc_memt) { 3142 } else if (bt == sc->sc_iot) { 3143 } else { 3144 return 1; 3145 /* XXX: panic here? */ 3146 } 3147 3148 return rbus_space_free(rb, bsh, size, NULL); 3149 } 3150 #endif /* rbus */ 3151 3152 #if rbus 3153 3154 static int 3155 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3156 struct pccbb_softc *sc; 3157 bus_space_tag_t bst; 3158 bus_addr_t addr; 3159 bus_size_t size; 3160 bus_space_handle_t bsh; 3161 int flags; 3162 { 3163 struct pccbb_win_chain_head *head; 3164 bus_addr_t align; 3165 3166 head = &sc->sc_iowindow; 3167 align = 0x04; 3168 if (sc->sc_memt == bst) { 3169 head = &sc->sc_memwindow; 3170 align = 0x1000; 3171 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3172 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3173 (unsigned long)bst)); 3174 } 3175 3176 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3177 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3178 sc->sc_dev.dv_xname, 3179 (head == &sc->sc_memwindow) ? "mem" : "io"); 3180 } 3181 pccbb_winset(align, sc, bst); 3182 3183 return 0; 3184 } 3185 3186 static int 3187 pccbb_close_win(sc, bst, bsh, size) 3188 struct pccbb_softc *sc; 3189 bus_space_tag_t bst; 3190 bus_space_handle_t bsh; 3191 bus_size_t size; 3192 { 3193 struct pccbb_win_chain_head *head; 3194 bus_addr_t align; 3195 3196 head = &sc->sc_iowindow; 3197 align = 0x04; 3198 if (sc->sc_memt == bst) { 3199 head = &sc->sc_memwindow; 3200 align = 0x1000; 3201 } 3202 3203 if (pccbb_winlist_delete(head, bsh, size)) { 3204 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3205 sc->sc_dev.dv_xname, 3206 (head == &sc->sc_memwindow) ? "mem" : "io"); 3207 } 3208 pccbb_winset(align, sc, bst); 3209 3210 return 0; 3211 } 3212 3213 static int 3214 pccbb_winlist_insert(head, start, size, bsh, flags) 3215 struct pccbb_win_chain_head *head; 3216 bus_addr_t start; 3217 bus_size_t size; 3218 bus_space_handle_t bsh; 3219 int flags; 3220 { 3221 struct pccbb_win_chain *chainp, *elem; 3222 3223 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3224 M_NOWAIT)) == NULL) 3225 return (1); /* fail */ 3226 3227 elem->wc_start = start; 3228 elem->wc_end = start + (size - 1); 3229 elem->wc_handle = bsh; 3230 elem->wc_flags = flags; 3231 3232 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3233 chainp = TAILQ_NEXT(chainp, wc_list)) { 3234 if (chainp->wc_end < start) 3235 continue; 3236 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3237 return (0); 3238 } 3239 3240 TAILQ_INSERT_TAIL(head, elem, wc_list); 3241 return (0); 3242 } 3243 3244 static int 3245 pccbb_winlist_delete(head, bsh, size) 3246 struct pccbb_win_chain_head *head; 3247 bus_space_handle_t bsh; 3248 bus_size_t size; 3249 { 3250 struct pccbb_win_chain *chainp; 3251 3252 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3253 chainp = TAILQ_NEXT(chainp, wc_list)) { 3254 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3255 continue; 3256 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3257 printf("pccbb_winlist_delete: window 0x%lx size " 3258 "inconsistent: 0x%lx, 0x%lx\n", 3259 (unsigned long)chainp->wc_start, 3260 (unsigned long)(chainp->wc_end - chainp->wc_start), 3261 (unsigned long)(size - 1)); 3262 return 1; 3263 } 3264 3265 TAILQ_REMOVE(head, chainp, wc_list); 3266 free(chainp, M_DEVBUF); 3267 3268 return 0; 3269 } 3270 3271 return 1; /* fail: no candidate to remove */ 3272 } 3273 3274 static void 3275 pccbb_winset(align, sc, bst) 3276 bus_addr_t align; 3277 struct pccbb_softc *sc; 3278 bus_space_tag_t bst; 3279 { 3280 pci_chipset_tag_t pc; 3281 pcitag_t tag; 3282 bus_addr_t mask = ~(align - 1); 3283 struct { 3284 cardbusreg_t win_start; 3285 cardbusreg_t win_limit; 3286 int win_flags; 3287 } win[2]; 3288 struct pccbb_win_chain *chainp; 3289 int offs; 3290 3291 win[0].win_start = win[1].win_start = 0xffffffff; 3292 win[0].win_limit = win[1].win_limit = 0; 3293 win[0].win_flags = win[1].win_flags = 0; 3294 3295 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3296 offs = 0x2c; 3297 if (sc->sc_memt == bst) { 3298 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3299 offs = 0x1c; 3300 } 3301 3302 if (chainp != NULL) { 3303 win[0].win_start = chainp->wc_start & mask; 3304 win[0].win_limit = chainp->wc_end & mask; 3305 win[0].win_flags = chainp->wc_flags; 3306 chainp = TAILQ_NEXT(chainp, wc_list); 3307 } 3308 3309 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3310 if (win[1].win_start == 0xffffffff) { 3311 /* window 1 is not used */ 3312 if ((win[0].win_flags == chainp->wc_flags) && 3313 (win[0].win_limit + align >= 3314 (chainp->wc_start & mask))) { 3315 /* concatenate */ 3316 win[0].win_limit = chainp->wc_end & mask; 3317 } else { 3318 /* make new window */ 3319 win[1].win_start = chainp->wc_start & mask; 3320 win[1].win_limit = chainp->wc_end & mask; 3321 win[1].win_flags = chainp->wc_flags; 3322 } 3323 continue; 3324 } 3325 3326 /* Both windows are engaged. */ 3327 if (win[0].win_flags == win[1].win_flags) { 3328 /* same flags */ 3329 if (win[0].win_flags == chainp->wc_flags) { 3330 if (win[1].win_start - (win[0].win_limit + 3331 align) < 3332 (chainp->wc_start & mask) - 3333 ((chainp->wc_end & mask) + align)) { 3334 /* 3335 * merge window 0 and 1, and set win1 3336 * to chainp 3337 */ 3338 win[0].win_limit = win[1].win_limit; 3339 win[1].win_start = 3340 chainp->wc_start & mask; 3341 win[1].win_limit = 3342 chainp->wc_end & mask; 3343 } else { 3344 win[1].win_limit = 3345 chainp->wc_end & mask; 3346 } 3347 } else { 3348 /* different flags */ 3349 3350 /* concatenate win0 and win1 */ 3351 win[0].win_limit = win[1].win_limit; 3352 /* allocate win[1] to new space */ 3353 win[1].win_start = chainp->wc_start & mask; 3354 win[1].win_limit = chainp->wc_end & mask; 3355 win[1].win_flags = chainp->wc_flags; 3356 } 3357 } else { 3358 /* the flags of win[0] and win[1] is different */ 3359 if (win[0].win_flags == chainp->wc_flags) { 3360 win[0].win_limit = chainp->wc_end & mask; 3361 /* 3362 * XXX this creates overlapping windows, so 3363 * what should the poor bridge do if one is 3364 * cachable, and the other is not? 3365 */ 3366 printf("%s: overlapping windows\n", 3367 sc->sc_dev.dv_xname); 3368 } else { 3369 win[1].win_limit = chainp->wc_end & mask; 3370 } 3371 } 3372 } 3373 3374 pc = sc->sc_pc; 3375 tag = sc->sc_tag; 3376 pci_conf_write(pc, tag, offs, win[0].win_start); 3377 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3378 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3379 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3380 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3381 (unsigned long)pci_conf_read(pc, tag, offs), 3382 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3383 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3384 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3385 3386 if (bst == sc->sc_memt) { 3387 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3388 3389 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3390 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3391 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3392 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3393 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3394 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3395 } 3396 } 3397 3398 #endif /* rbus */ 3399 3400 static void 3401 pccbb_powerhook(why, arg) 3402 int why; 3403 void *arg; 3404 { 3405 struct pccbb_softc *sc = arg; 3406 pcireg_t reg; 3407 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3408 bus_space_handle_t base_memh = sc->sc_base_memh; 3409 3410 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3411 3412 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3413 DPRINTF(("%s: power: why %d stopping intr\n", 3414 sc->sc_dev.dv_xname, why)); 3415 if (sc->sc_pil_intr_enable) { 3416 (void)pccbbintr_function(sc); 3417 } 3418 sc->sc_pil_intr_enable = 0; 3419 3420 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3421 3422 if (sc->sc_chipset == CB_RX5C47X) 3423 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3424 sc->sc_tag, 3425 RICOH_PCI_MISC_CTRL); 3426 3427 /* ToDo: deactivate or suspend child devices */ 3428 } 3429 3430 if (why == PWR_RESUME) { 3431 if (sc->sc_pwrmgt_offs != 0) { 3432 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3433 sc->sc_pwrmgt_offs + 4); 3434 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3435 reg & 0x100) { 3436 /* powrstate != D0 */ 3437 3438 printf("%s going back to D0 mode\n", 3439 sc->sc_dev.dv_xname); 3440 reg &= ~PCI_PMCSR_STATE_MASK; 3441 reg |= PCI_PMCSR_STATE_D0; 3442 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3443 pci_conf_write(sc->sc_pc, sc->sc_tag, 3444 sc->sc_pwrmgt_offs + 4, reg); 3445 3446 pci_conf_write(sc->sc_pc, sc->sc_tag, 3447 PCI_SOCKBASE, sc->sc_sockbase); 3448 pci_conf_write(sc->sc_pc, sc->sc_tag, 3449 PCI_BUSNUM, sc->sc_busnum); 3450 pccbb_chipinit(sc); 3451 /* setup memory and io space window for CB */ 3452 pccbb_winset(0x1000, sc, sc->sc_memt); 3453 pccbb_winset(0x04, sc, sc->sc_iot); 3454 goto norestore; 3455 } 3456 } 3457 3458 norestore: 3459 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3460 if (sc->sc_chipset == CB_RX5C47X) { 3461 pci_conf_write(sc->sc_pc, sc->sc_tag, 3462 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3463 } 3464 3465 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3466 /* BIOS did not recover this register */ 3467 pci_conf_write (sc->sc_pc, sc->sc_tag, 3468 PCI_SOCKBASE, sc->sc_sockbase); 3469 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3470 /* BIOS did not recover this register */ 3471 pci_conf_write (sc->sc_pc, sc->sc_tag, 3472 PCI_BUSNUM, sc->sc_busnum); 3473 /* CSC Interrupt: Card detect interrupt on */ 3474 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3475 /* Card detect intr is turned on. */ 3476 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3477 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3478 /* reset interrupt */ 3479 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3480 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3481 3482 /* 3483 * check for card insertion or removal during suspend period. 3484 * XXX: the code can't cope with card swap (remove then 3485 * insert). how can we detect such situation? 3486 */ 3487 (void)pccbbintr(sc); 3488 3489 sc->sc_pil_intr_enable = 1; 3490 DPRINTF(("%s: power: RESUME enabling intr\n", 3491 sc->sc_dev.dv_xname)); 3492 3493 /* ToDo: activate or wakeup child devices */ 3494 } 3495 } 3496
Indexes created Thu Sep 25 16:09:42 GMT 2025