pccbb.c revision 1.130
1 /* $NetBSD: pccbb.c,v 1.130 2006/07/04 00:30:23 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.130 2006/07/04 00:30:23 christos Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 42 /* 43 #define CB_PCMCIA_POLL 44 #define CB_PCMCIA_POLL_ONLY 45 #define LEVEL2 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/ioctl.h> 53 #include <sys/reboot.h> /* for bootverbose */ 54 #include <sys/syslog.h> 55 #include <sys/device.h> 56 #include <sys/malloc.h> 57 #include <sys/proc.h> 58 59 #include <machine/intr.h> 60 #include <machine/bus.h> 61 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcidevs.h> 65 66 #include <dev/pci/pccbbreg.h> 67 68 #include <dev/cardbus/cardslotvar.h> 69 70 #include <dev/cardbus/cardbusvar.h> 71 72 #include <dev/pcmcia/pcmciareg.h> 73 #include <dev/pcmcia/pcmciavar.h> 74 75 #include <dev/ic/i82365reg.h> 76 #include <dev/ic/i82365var.h> 77 #include <dev/pci/pccbbvar.h> 78 79 #include "locators.h" 80 81 #if defined(__i386__) 82 #include "ioapic.h" 83 #include "acpi.h" 84 #endif 85 86 #ifndef __NetBSD_Version__ 87 struct cfdriver cbb_cd = { 88 NULL, "cbb", DV_DULL 89 }; 90 #endif 91 92 #ifdef CBB_DEBUG 93 #define DPRINTF(x) printf x 94 #define STATIC 95 #else 96 #define DPRINTF(x) 97 #define STATIC static 98 #endif 99 100 /* 101 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 102 * if you want to wait more than 1 ms. 103 */ 104 #define DELAY_MS(time, param) \ 105 do { \ 106 if (cold == 0) { \ 107 int xtick = (hz*(time))/1000; \ 108 \ 109 if (xtick <= 1) { \ 110 xtick = 2; \ 111 } \ 112 tsleep((void *)(param), PWAIT, "pccbb", xtick); \ 113 } else { \ 114 delay((time)*1000); \ 115 } \ 116 } while (/*CONSTCOND*/0) 117 118 int pcicbbmatch(struct device *, struct cfdata *, void *); 119 void pccbbattach(struct device *, struct device *, void *); 120 int pccbbintr(void *); 121 static void pci113x_insert(void *); 122 static int pccbbintr_function(struct pccbb_softc *); 123 124 static int pccbb_detect_card(struct pccbb_softc *); 125 126 static void pccbb_pcmcia_write(struct pcic_handle *, int, u_int8_t); 127 static u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 128 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 129 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 130 131 STATIC int cb_reset(struct pccbb_softc *); 132 STATIC int cb_detect_voltage(struct pccbb_softc *); 133 STATIC int cbbprint(void *, const char *); 134 135 static int cb_chipset(u_int32_t, int *); 136 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 137 struct pcmciabus_attach_args *); 138 #if 0 139 STATIC void pccbb_pcmcia_attach_card(struct pcic_handle *); 140 STATIC void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 141 STATIC void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 142 #endif 143 144 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 145 STATIC int pccbb_power(cardbus_chipset_tag_t, int); 146 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 147 #if !rbus 148 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 149 static int pccbb_io_close(cardbus_chipset_tag_t, int); 150 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 151 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 152 #endif /* !rbus */ 153 static void *pccbb_intr_establish(struct pccbb_softc *, int irq, 154 int level, int (*ih) (void *), void *sc); 155 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 156 157 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, 158 int level, int (*ih) (void *), void *sc); 159 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 160 161 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 162 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 163 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 164 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 165 cardbusreg_t); 166 static void pccbb_chipinit(struct pccbb_softc *); 167 168 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 169 struct pcmcia_mem_handle *); 170 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 171 struct pcmcia_mem_handle *); 172 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 173 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 174 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 175 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 176 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 177 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 178 struct pcmcia_io_handle *); 179 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 180 bus_size_t, struct pcmcia_io_handle *, int *); 181 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 182 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 183 struct pcmcia_function *, int, int (*)(void *), void *); 184 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 185 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 186 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 187 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 188 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 189 190 static int pccbb_pcmcia_wait_ready(struct pcic_handle *); 191 static void pccbb_pcmcia_delay(struct pcic_handle *, int, const char *); 192 193 static void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 194 static void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 195 static void pccbb_powerhook(int, void *); 196 197 /* bus-space allocation and deallocation functions */ 198 #if rbus 199 200 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 201 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 202 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 203 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 204 bus_space_handle_t, bus_size_t); 205 206 #endif /* rbus */ 207 208 #if rbus 209 210 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 211 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 212 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 213 bus_space_handle_t, bus_size_t); 214 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 215 bus_size_t, bus_space_handle_t, int); 216 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 217 bus_space_handle_t, bus_size_t); 218 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 219 bus_space_tag_t); 220 void pccbb_winlist_show(struct pccbb_win_chain *); 221 222 #endif /* rbus */ 223 224 /* for config_defer */ 225 static void pccbb_pci_callback(struct device *); 226 227 #if defined SHOW_REGS 228 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 229 bus_space_tag_t memt, bus_space_handle_t memh); 230 #endif 231 232 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 233 pcicbbmatch, pccbbattach, NULL, NULL); 234 235 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 236 pccbb_pcmcia_mem_alloc, 237 pccbb_pcmcia_mem_free, 238 pccbb_pcmcia_mem_map, 239 pccbb_pcmcia_mem_unmap, 240 pccbb_pcmcia_io_alloc, 241 pccbb_pcmcia_io_free, 242 pccbb_pcmcia_io_map, 243 pccbb_pcmcia_io_unmap, 244 pccbb_pcmcia_intr_establish, 245 pccbb_pcmcia_intr_disestablish, 246 pccbb_pcmcia_socket_enable, 247 pccbb_pcmcia_socket_disable, 248 pccbb_pcmcia_socket_settype, 249 pccbb_pcmcia_card_detect 250 }; 251 252 #if rbus 253 static struct cardbus_functions pccbb_funcs = { 254 pccbb_rbus_cb_space_alloc, 255 pccbb_rbus_cb_space_free, 256 pccbb_cb_intr_establish, 257 pccbb_cb_intr_disestablish, 258 pccbb_ctrl, 259 pccbb_power, 260 pccbb_make_tag, 261 pccbb_free_tag, 262 pccbb_conf_read, 263 pccbb_conf_write, 264 }; 265 #else 266 static struct cardbus_functions pccbb_funcs = { 267 pccbb_ctrl, 268 pccbb_power, 269 pccbb_mem_open, 270 pccbb_mem_close, 271 pccbb_io_open, 272 pccbb_io_close, 273 pccbb_cb_intr_establish, 274 pccbb_cb_intr_disestablish, 275 pccbb_make_tag, 276 pccbb_conf_read, 277 pccbb_conf_write, 278 }; 279 #endif 280 281 int 282 pcicbbmatch(parent, match, aux) 283 struct device *parent; 284 struct cfdata *match; 285 void *aux; 286 { 287 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 288 289 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 290 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 291 PCI_INTERFACE(pa->pa_class) == 0) { 292 return 1; 293 } 294 295 return 0; 296 } 297 298 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 299 | ((prod) << PCI_PRODUCT_SHIFT)) 300 301 const struct yenta_chipinfo { 302 pcireg_t yc_id; /* vendor tag | product tag */ 303 int yc_chiptype; 304 int yc_flags; 305 } yc_chipsets[] = { 306 /* Texas Instruments chips */ 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 332 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 334 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 336 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 338 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 339 340 /* Ricoh chips */ 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 344 PCCBB_PCMCIA_MEM_32}, 345 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 346 PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 348 PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 350 PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 352 PCCBB_PCMCIA_MEM_32}, 353 354 /* Toshiba products */ 355 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 356 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 358 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 360 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 361 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 362 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 363 364 /* Cirrus Logic products */ 365 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 366 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 367 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 368 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 369 370 /* sentinel, or Generic chip */ 371 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 372 }; 373 374 static int 375 cb_chipset(pci_id, flagp) 376 u_int32_t pci_id; 377 int *flagp; 378 { 379 const struct yenta_chipinfo *yc; 380 381 /* Loop over except the last default entry. */ 382 for (yc = yc_chipsets; yc < yc_chipsets + 383 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 384 if (pci_id == yc->yc_id) 385 break; 386 387 if (flagp != NULL) 388 *flagp = yc->yc_flags; 389 390 return (yc->yc_chiptype); 391 } 392 393 static void 394 pccbb_shutdown(void *arg) 395 { 396 struct pccbb_softc *sc = arg; 397 pcireg_t command; 398 399 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 400 401 /* 402 * turn off power 403 * 404 * XXX - do not turn off power if chipset is TI 113X because 405 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 406 */ 407 if (sc->sc_chipset != CB_TI113X) { 408 pccbb_power((cardbus_chipset_tag_t)sc, 409 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 410 } 411 412 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 413 0); 414 415 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 416 417 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 418 PCI_COMMAND_MASTER_ENABLE); 419 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 420 421 } 422 423 void 424 pccbbattach(parent, self, aux) 425 struct device *parent; 426 struct device *self; 427 void *aux; 428 { 429 struct pccbb_softc *sc = (void *)self; 430 struct pci_attach_args *pa = aux; 431 pci_chipset_tag_t pc = pa->pa_pc; 432 pcireg_t busreg, reg, sock_base; 433 bus_addr_t sockbase; 434 char devinfo[256]; 435 int flags; 436 int pwrmgt_offs; 437 438 #ifdef __HAVE_PCCBB_ATTACH_HOOK 439 pccbb_attach_hook(parent, self, pa); 440 #endif 441 442 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 443 444 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 445 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 446 #ifdef CBB_DEBUG 447 printf(" (chipflags %x)", flags); 448 #endif 449 printf("\n"); 450 451 TAILQ_INIT(&sc->sc_memwindow); 452 TAILQ_INIT(&sc->sc_iowindow); 453 454 #if rbus 455 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 456 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 457 458 #if 0 459 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 460 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 461 #endif 462 #endif /* rbus */ 463 464 sc->sc_flags &= ~CBB_MEMHMAPPED; 465 466 /* power management: set D0 state */ 467 sc->sc_pwrmgt_offs = 0; 468 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 469 &pwrmgt_offs, 0)) { 470 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 471 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 472 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 473 reg &= ~PCI_PMCSR_STATE_MASK; 474 reg |= PCI_PMCSR_STATE_D0; 475 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 476 pci_conf_write(pc, pa->pa_tag, 477 pwrmgt_offs + PCI_PMCSR, reg); 478 } 479 480 sc->sc_pwrmgt_offs = pwrmgt_offs; 481 } 482 483 /* 484 * MAP socket registers and ExCA registers on memory-space 485 * When no valid address is set on socket base registers (on pci 486 * config space), get it not polite way. 487 */ 488 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 489 490 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 491 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 492 /* The address must be valid. */ 493 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 494 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 495 printf("%s: can't map socket base address 0x%lx\n", 496 sc->sc_dev.dv_xname, (unsigned long)sock_base); 497 /* 498 * I think it's funny: socket base registers must be 499 * mapped on memory space, but ... 500 */ 501 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 502 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 503 NULL)) { 504 printf("%s: can't map socket base address" 505 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 506 (unsigned long)sockbase); 507 /* give up... allocate reg space via rbus. */ 508 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 509 } else 510 sc->sc_flags |= CBB_MEMHMAPPED; 511 } else { 512 DPRINTF(("%s: socket base address 0x%lx\n", 513 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 514 sc->sc_flags |= CBB_MEMHMAPPED; 515 } 516 } 517 518 sc->sc_mem_start = 0; /* XXX */ 519 sc->sc_mem_end = 0xffffffff; /* XXX */ 520 521 /* 522 * When interrupt isn't routed correctly, give up probing cbb and do 523 * not kill pcic-compatible port. 524 * 525 * However, if we are using an ioapic, avoid this check -- pa_intrline 526 * may well be zero, with the interrupt routed through the apic. 527 */ 528 529 #if NIOAPIC == 0 && ACPI == 0 530 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 531 printf("%s: NOT USED because of unconfigured interrupt\n", 532 sc->sc_dev.dv_xname); 533 return; 534 } 535 #endif 536 537 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 538 539 /* pccbb_machdep.c end */ 540 541 #if defined CBB_DEBUG 542 { 543 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 544 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 545 intrname[pa->pa_intrpin], pa->pa_intrline); 546 } 547 #endif 548 549 /* setup softc */ 550 sc->sc_pc = pc; 551 sc->sc_iot = pa->pa_iot; 552 sc->sc_memt = pa->pa_memt; 553 sc->sc_dmat = pa->pa_dmat; 554 sc->sc_tag = pa->pa_tag; 555 sc->sc_function = pa->pa_function; 556 sc->sc_sockbase = sock_base; 557 sc->sc_busnum = busreg; 558 559 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 560 561 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 562 563 shutdownhook_establish(pccbb_shutdown, sc); 564 565 /* Disable legacy register mapping. */ 566 switch (sc->sc_chipset) { 567 case CB_RX5C46X: /* fallthrough */ 568 #if 0 569 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 570 case CB_RX5C47X: 571 #endif 572 /* 573 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 574 * cannot be disabled by substituting 0 into PCI_LEGACY 575 * register. Ricoh CardBus bridges have special bits on Bridge 576 * control reg (addr 0x3e on PCI config space). 577 */ 578 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 579 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 580 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 581 break; 582 583 default: 584 /* XXX I don't know proper way to kill legacy I/O. */ 585 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 586 break; 587 } 588 589 config_defer(self, pccbb_pci_callback); 590 } 591 592 593 594 595 /* 596 * static void pccbb_pci_callback(struct device *self) 597 * 598 * The actual attach routine: get memory space for YENTA register 599 * space, setup YENTA register and route interrupt. 600 * 601 * This function should be deferred because this device may obtain 602 * memory space dynamically. This function must avoid obtaining 603 * memory area which has already kept for another device. 604 */ 605 static void 606 pccbb_pci_callback(self) 607 struct device *self; 608 { 609 struct pccbb_softc *sc = (void *)self; 610 pci_chipset_tag_t pc = sc->sc_pc; 611 pci_intr_handle_t ih; 612 const char *intrstr = NULL; 613 bus_addr_t sockbase; 614 struct cbslot_attach_args cba; 615 struct pcmciabus_attach_args paa; 616 struct cardslot_attach_args caa; 617 struct cardslot_softc *csc; 618 619 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 620 /* The socket registers aren't mapped correctly. */ 621 #if rbus 622 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 623 (sc->sc_chipset == CB_RX5C47X 624 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 625 0, &sockbase, &sc->sc_base_memh)) { 626 return; 627 } 628 sc->sc_base_memt = sc->sc_memt; 629 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 630 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 631 sc->sc_dev.dv_xname, (unsigned long)sockbase, 632 (unsigned long)pci_conf_read(pc, sc->sc_tag, 633 PCI_SOCKBASE))); 634 #else 635 sc->sc_base_memt = sc->sc_memt; 636 #if !defined CBB_PCI_BASE 637 #define CBB_PCI_BASE 0x20000000 638 #endif 639 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 640 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 641 /* cannot allocate memory space */ 642 return; 643 } 644 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 645 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 646 sc->sc_dev.dv_xname, (unsigned long)sock_base, 647 (unsigned long)pci_conf_read(pc, 648 sc->sc_tag, PCI_SOCKBASE))); 649 sc->sc_sockbase = sockbase; 650 #endif 651 sc->sc_flags |= CBB_MEMHMAPPED; 652 } 653 654 /* bus bridge initialization */ 655 pccbb_chipinit(sc); 656 657 /* clear data structure for child device interrupt handlers */ 658 LIST_INIT(&sc->sc_pil); 659 sc->sc_pil_intr_enable = 1; 660 661 /* Map and establish the interrupt. */ 662 if (pci_intr_map(&sc->sc_pa, &ih)) { 663 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 664 return; 665 } 666 intrstr = pci_intr_string(pc, ih); 667 668 /* 669 * XXX pccbbintr should be called under the priority lower 670 * than any other hard interupts. 671 */ 672 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 673 674 if (sc->sc_ih == NULL) { 675 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 676 if (intrstr != NULL) { 677 printf(" at %s", intrstr); 678 } 679 printf("\n"); 680 return; 681 } 682 683 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 684 powerhook_establish(pccbb_powerhook, sc); 685 686 { 687 u_int32_t sockstat; 688 689 sockstat = bus_space_read_4(sc->sc_base_memt, 690 sc->sc_base_memh, CB_SOCKET_STAT); 691 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 692 sc->sc_flags |= CBB_CARDEXIST; 693 } 694 } 695 696 /* 697 * attach cardbus 698 */ 699 { 700 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 701 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 702 703 /* initialize cbslot_attach */ 704 cba.cba_busname = "cardbus"; 705 cba.cba_iot = sc->sc_iot; 706 cba.cba_memt = sc->sc_memt; 707 cba.cba_dmat = sc->sc_dmat; 708 cba.cba_bus = (busreg >> 8) & 0x0ff; 709 cba.cba_cc = (void *)sc; 710 cba.cba_cf = &pccbb_funcs; 711 cba.cba_intrline = sc->sc_pa.pa_intrline; 712 713 #if rbus 714 cba.cba_rbus_iot = sc->sc_rbus_iot; 715 cba.cba_rbus_memt = sc->sc_rbus_memt; 716 #endif 717 718 cba.cba_cacheline = PCI_CACHELINE(bhlc); 719 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 720 721 if (bootverbose) { 722 printf("%s: cacheline 0x%x lattimer 0x%x\n", 723 sc->sc_dev.dv_xname, cba.cba_cacheline, 724 cba.cba_lattimer); 725 printf("%s: bhlc 0x%x lscp 0x%x\n", 726 sc->sc_dev.dv_xname, bhlc, busreg); 727 } 728 #if defined SHOW_REGS 729 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 730 sc->sc_base_memh); 731 #endif 732 } 733 734 pccbb_pcmcia_attach_setup(sc, &paa); 735 caa.caa_cb_attach = NULL; 736 if (cba.cba_bus == 0) 737 printf("%s: secondary bus number uninitialized; try PCI_BUS_FIXUP\n", sc->sc_dev.dv_xname); 738 else 739 caa.caa_cb_attach = &cba; 740 caa.caa_16_attach = &paa; 741 caa.caa_ph = &sc->sc_pcmcia_h; 742 743 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 744 DPRINTF(("pccbbattach: found cardslot\n")); 745 sc->sc_csc = csc; 746 } 747 748 return; 749 } 750 751 752 753 754 755 /* 756 * static void pccbb_chipinit(struct pccbb_softc *sc) 757 * 758 * This function initialize YENTA chip registers listed below: 759 * 1) PCI command reg, 760 * 2) PCI and CardBus latency timer, 761 * 3) route PCI interrupt, 762 * 4) close all memory and io windows. 763 * 5) turn off bus power. 764 * 6) card detect and power cycle interrupts on. 765 * 7) clear interrupt 766 */ 767 static void 768 pccbb_chipinit(sc) 769 struct pccbb_softc *sc; 770 { 771 pci_chipset_tag_t pc = sc->sc_pc; 772 pcitag_t tag = sc->sc_tag; 773 bus_space_tag_t bmt = sc->sc_base_memt; 774 bus_space_handle_t bmh = sc->sc_base_memh; 775 pcireg_t reg; 776 777 /* 778 * Set PCI command reg. 779 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 780 */ 781 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 782 /* I believe it is harmless. */ 783 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 784 PCI_COMMAND_MASTER_ENABLE); 785 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 786 787 /* 788 * Set CardBus latency timer. 789 */ 790 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 791 if (PCI_CB_LATENCY(reg) < 0x20) { 792 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 793 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 794 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 795 } 796 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 797 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 798 799 /* 800 * Set PCI latency timer. 801 */ 802 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 803 if (PCI_LATTIMER(reg) < 0x10) { 804 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 805 reg |= (0x10 << PCI_LATTIMER_SHIFT); 806 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 807 } 808 DPRINTF(("PCI latency timer 0x%x (%x)\n", 809 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 810 811 812 /* Route functional interrupts to PCI. */ 813 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 814 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 815 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 816 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 817 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 818 819 switch (sc->sc_chipset) { 820 case CB_TI113X: 821 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 822 /* This bit is shared, but may read as 0 on some chips, so set 823 it explicitly on both functions. */ 824 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 825 /* CSC intr enable */ 826 reg |= PCI113X_CBCTRL_PCI_CSC; 827 /* functional intr prohibit | prohibit ISA routing */ 828 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 829 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 830 break; 831 832 case CB_TI12XX: 833 /* 834 * Some TI 12xx (and [14][45]xx) based pci cards 835 * sometimes have issues with the MFUNC register not 836 * being initialized due to a bad EEPROM on board. 837 * Laptops that this matters on have this register 838 * properly initialized. 839 * 840 * The TI125X parts have a different register. 841 */ 842 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 843 if (reg == 0) { 844 reg &= ~PCI12XX_MFUNC_PIN0; 845 reg |= PCI12XX_MFUNC_PIN0_INTA; 846 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 847 PCI12XX_SYSCTRL_INTRTIE) == 0) { 848 reg &= ~PCI12XX_MFUNC_PIN1; 849 reg |= PCI12XX_MFUNC_PIN1_INTB; 850 } 851 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 852 } 853 /* fallthrough */ 854 855 case CB_TI125X: 856 /* 857 * Disable zoom video. Some machines initialize this 858 * improperly and experience has shown that this helps 859 * prevent strange behavior. 860 */ 861 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 862 863 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 864 reg |= PCI12XX_SYSCTRL_VCCPROT; 865 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 866 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 867 reg |= PCI12XX_CBCTRL_CSC; 868 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 869 break; 870 871 case CB_TOPIC95B: 872 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 873 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 874 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 875 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 876 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 877 sc->sc_dev.dv_xname, reg)); 878 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 879 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 880 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 881 DPRINTF(("0x%x\n", reg)); 882 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 883 break; 884 885 case CB_TOPIC97: 886 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 887 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 888 sc->sc_dev.dv_xname, reg)); 889 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 890 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 891 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 892 reg |= TOPIC97_SLOT_CTRL_PCIINT; 893 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 894 DPRINTF(("0x%x\n", reg)); 895 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 896 /* make sure to assert LV card support bits */ 897 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 898 0x800 + 0x3e, 899 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 900 0x800 + 0x3e) | 0x03); 901 break; 902 } 903 904 /* Close all memory and I/O windows. */ 905 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 906 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 907 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 908 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 909 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 910 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 911 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 912 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 913 914 /* reset 16-bit pcmcia bus */ 915 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 916 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 917 918 /* turn off power */ 919 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 920 921 /* CSC Interrupt: Card detect and power cycle interrupts on */ 922 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 923 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 924 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 925 /* reset interrupt */ 926 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 927 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 928 } 929 930 931 932 933 /* 934 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 935 * struct pcmciabus_attach_args *paa) 936 * 937 * This function attaches 16-bit PCcard bus. 938 */ 939 STATIC void 940 pccbb_pcmcia_attach_setup(sc, paa) 941 struct pccbb_softc *sc; 942 struct pcmciabus_attach_args *paa; 943 { 944 struct pcic_handle *ph = &sc->sc_pcmcia_h; 945 #if rbus 946 rbus_tag_t rb; 947 #endif 948 949 /* initialize pcmcia part in pccbb_softc */ 950 ph->ph_parent = (struct device *)sc; 951 ph->sock = sc->sc_function; 952 ph->flags = 0; 953 ph->shutdown = 0; 954 ph->ih_irq = sc->sc_pa.pa_intrline; 955 ph->ph_bus_t = sc->sc_base_memt; 956 ph->ph_bus_h = sc->sc_base_memh; 957 ph->ph_read = pccbb_pcmcia_read; 958 ph->ph_write = pccbb_pcmcia_write; 959 sc->sc_pct = &pccbb_pcmcia_funcs; 960 961 /* 962 * We need to do a few things here: 963 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 964 * setting the IRQ numbers to 0. 965 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 966 * routing of CSC interrupts (e.g. card removal) to PCI while in 967 * PCMCIA mode. We just leave this set all the time. 968 * 3) Enable card insertion/removal interrupts in case the chip also 969 * needs that while in PCMCIA mode. 970 * 4) Clear any pending CSC interrupt. 971 */ 972 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 973 if (sc->sc_chipset == CB_TI113X) { 974 Pcic_write(ph, PCIC_CSC_INTR, 0); 975 } else { 976 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 977 Pcic_read(ph, PCIC_CSC); 978 } 979 980 /* initialize pcmcia bus attachment */ 981 paa->paa_busname = "pcmcia"; 982 paa->pct = sc->sc_pct; 983 paa->pch = ph; 984 paa->iobase = 0; /* I don't use them */ 985 paa->iosize = 0; 986 #if rbus 987 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 988 paa->iobase = rb->rb_start + rb->rb_offset; 989 paa->iosize = rb->rb_end - rb->rb_start; 990 #endif 991 992 return; 993 } 994 995 #if 0 996 STATIC void 997 pccbb_pcmcia_attach_card(ph) 998 struct pcic_handle *ph; 999 { 1000 if (ph->flags & PCIC_FLAG_CARDP) { 1001 panic("pccbb_pcmcia_attach_card: already attached"); 1002 } 1003 1004 /* call the MI attach function */ 1005 pcmcia_card_attach(ph->pcmcia); 1006 1007 ph->flags |= PCIC_FLAG_CARDP; 1008 } 1009 1010 STATIC void 1011 pccbb_pcmcia_detach_card(ph, flags) 1012 struct pcic_handle *ph; 1013 int flags; 1014 { 1015 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1016 panic("pccbb_pcmcia_detach_card: already detached"); 1017 } 1018 1019 ph->flags &= ~PCIC_FLAG_CARDP; 1020 1021 /* call the MI detach function */ 1022 pcmcia_card_detach(ph->pcmcia, flags); 1023 } 1024 #endif 1025 1026 /* 1027 * int pccbbintr(arg) 1028 * void *arg; 1029 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1030 * itself. 1031 */ 1032 int 1033 pccbbintr(arg) 1034 void *arg; 1035 { 1036 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1037 u_int32_t sockevent, sockstate; 1038 bus_space_tag_t memt = sc->sc_base_memt; 1039 bus_space_handle_t memh = sc->sc_base_memh; 1040 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1041 1042 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1043 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1044 Pcic_read(ph, PCIC_CSC); 1045 1046 if (sockevent == 0) { 1047 /* This intr is not for me: it may be for my child devices. */ 1048 if (sc->sc_pil_intr_enable) { 1049 return pccbbintr_function(sc); 1050 } else { 1051 return 0; 1052 } 1053 } 1054 1055 if (sockevent & CB_SOCKET_EVENT_CD) { 1056 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1057 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1058 /* A card should be removed. */ 1059 if (sc->sc_flags & CBB_CARDEXIST) { 1060 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1061 sockevent)); 1062 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1063 sc->sc_flags &= ~CBB_CARDEXIST; 1064 if (sc->sc_csc->sc_status & 1065 CARDSLOT_STATUS_CARD_16) { 1066 #if 0 1067 struct pcic_handle *ph = 1068 &sc->sc_pcmcia_h; 1069 1070 pcmcia_card_deactivate(ph->pcmcia); 1071 pccbb_pcmcia_socket_disable(ph); 1072 pccbb_pcmcia_detach_card(ph, 1073 DETACH_FORCE); 1074 #endif 1075 cardslot_event_throw(sc->sc_csc, 1076 CARDSLOT_EVENT_REMOVAL_16); 1077 } else if (sc->sc_csc->sc_status & 1078 CARDSLOT_STATUS_CARD_CB) { 1079 /* Cardbus intr removed */ 1080 cardslot_event_throw(sc->sc_csc, 1081 CARDSLOT_EVENT_REMOVAL_CB); 1082 } 1083 } else if (sc->sc_flags & CBB_INSERTING) { 1084 sc->sc_flags &= ~CBB_INSERTING; 1085 callout_stop(&sc->sc_insert_ch); 1086 } 1087 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1088 /* 1089 * The pccbbintr may called from powerdown hook when 1090 * the system resumed, to detect the card 1091 * insertion/removal during suspension. 1092 */ 1093 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1094 if (sc->sc_flags & CBB_INSERTING) { 1095 callout_stop(&sc->sc_insert_ch); 1096 } 1097 callout_reset(&sc->sc_insert_ch, hz / 5, 1098 pci113x_insert, sc); 1099 sc->sc_flags |= CBB_INSERTING; 1100 } 1101 } 1102 1103 if (sockevent & CB_SOCKET_EVENT_POWER) { 1104 /* XXX: Does not happen when attaching a 16-bit card */ 1105 sc->sc_pwrcycle++; 1106 wakeup(&sc->sc_pwrcycle); 1107 } 1108 1109 return (1); 1110 } 1111 1112 /* 1113 * static int pccbbintr_function(struct pccbb_softc *sc) 1114 * 1115 * This function calls each interrupt handler registered at the 1116 * bridge. The interrupt handlers are called in registered order. 1117 */ 1118 static int 1119 pccbbintr_function(sc) 1120 struct pccbb_softc *sc; 1121 { 1122 int retval = 0, val; 1123 struct pccbb_intrhand_list *pil; 1124 int s, splchanged; 1125 1126 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1127 pil = LIST_NEXT(pil, pil_next)) { 1128 /* 1129 * XXX priority change. gross. I use if-else 1130 * sentense instead of switch-case sentense because of 1131 * avoiding duplicate case value error. More than one 1132 * IPL_XXX use same value. It depends on 1133 * implimentation. 1134 */ 1135 splchanged = 1; 1136 if (pil->pil_level == IPL_SERIAL) { 1137 s = splserial(); 1138 } else if (pil->pil_level == IPL_HIGH) { 1139 s = splhigh(); 1140 } else if (pil->pil_level == IPL_CLOCK) { 1141 s = splclock(); 1142 } else if (pil->pil_level == IPL_AUDIO) { 1143 s = splaudio(); 1144 } else if (pil->pil_level == IPL_VM) { 1145 s = splvm(); 1146 } else if (pil->pil_level == IPL_TTY) { 1147 s = spltty(); 1148 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1149 s = splsoftserial(); 1150 } else if (pil->pil_level == IPL_NET) { 1151 s = splnet(); 1152 } else { 1153 s = 0; /* XXX: gcc */ 1154 splchanged = 0; 1155 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1156 } 1157 1158 val = (*pil->pil_func)(pil->pil_arg); 1159 1160 if (splchanged != 0) { 1161 splx(s); 1162 } 1163 1164 retval = retval == 1 ? 1 : 1165 retval == 0 ? val : val != 0 ? val : retval; 1166 } 1167 1168 return retval; 1169 } 1170 1171 static void 1172 pci113x_insert(arg) 1173 void *arg; 1174 { 1175 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1176 u_int32_t sockevent, sockstate; 1177 1178 if (!(sc->sc_flags & CBB_INSERTING)) { 1179 /* We add a card only under inserting state. */ 1180 return; 1181 } 1182 sc->sc_flags &= ~CBB_INSERTING; 1183 1184 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1185 CB_SOCKET_EVENT); 1186 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1187 CB_SOCKET_STAT); 1188 1189 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1190 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1191 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1192 sc->sc_flags |= CBB_CARDEXIST; 1193 /* call pccard interrupt handler here */ 1194 if (sockstate & CB_SOCKET_STAT_16BIT) { 1195 /* 16-bit card found */ 1196 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1197 cardslot_event_throw(sc->sc_csc, 1198 CARDSLOT_EVENT_INSERTION_16); 1199 } else if (sockstate & CB_SOCKET_STAT_CB) { 1200 /* cardbus card found */ 1201 /* cardbus_attach_card(sc->sc_csc); */ 1202 cardslot_event_throw(sc->sc_csc, 1203 CARDSLOT_EVENT_INSERTION_CB); 1204 } else { 1205 /* who are you? */ 1206 } 1207 } else { 1208 callout_reset(&sc->sc_insert_ch, hz / 10, 1209 pci113x_insert, sc); 1210 } 1211 } 1212 1213 #define PCCBB_PCMCIA_OFFSET 0x800 1214 static u_int8_t 1215 pccbb_pcmcia_read(ph, reg) 1216 struct pcic_handle *ph; 1217 int reg; 1218 { 1219 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1220 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1221 1222 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1223 PCCBB_PCMCIA_OFFSET + reg); 1224 } 1225 1226 static void 1227 pccbb_pcmcia_write(ph, reg, val) 1228 struct pcic_handle *ph; 1229 int reg; 1230 u_int8_t val; 1231 { 1232 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1233 val); 1234 1235 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1236 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1237 } 1238 1239 /* 1240 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1241 */ 1242 STATIC int 1243 pccbb_ctrl(ct, command) 1244 cardbus_chipset_tag_t ct; 1245 int command; 1246 { 1247 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1248 1249 switch (command) { 1250 case CARDBUS_CD: 1251 if (2 == pccbb_detect_card(sc)) { 1252 int retval = 0; 1253 int status = cb_detect_voltage(sc); 1254 if (PCCARD_VCC_5V & status) { 1255 retval |= CARDBUS_5V_CARD; 1256 } 1257 if (PCCARD_VCC_3V & status) { 1258 retval |= CARDBUS_3V_CARD; 1259 } 1260 if (PCCARD_VCC_XV & status) { 1261 retval |= CARDBUS_XV_CARD; 1262 } 1263 if (PCCARD_VCC_YV & status) { 1264 retval |= CARDBUS_YV_CARD; 1265 } 1266 return retval; 1267 } else { 1268 return 0; 1269 } 1270 case CARDBUS_RESET: 1271 return cb_reset(sc); 1272 case CARDBUS_IO_ENABLE: /* fallthrough */ 1273 case CARDBUS_IO_DISABLE: /* fallthrough */ 1274 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1275 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1276 case CARDBUS_BM_ENABLE: /* fallthrough */ 1277 case CARDBUS_BM_DISABLE: /* fallthrough */ 1278 /* XXX: I think we don't need to call this function below. */ 1279 return pccbb_cardenable(sc, command); 1280 } 1281 1282 return 0; 1283 } 1284 1285 /* 1286 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1287 * This function returns true when it succeeds and returns false when 1288 * it fails. 1289 */ 1290 STATIC int 1291 pccbb_power(ct, command) 1292 cardbus_chipset_tag_t ct; 1293 int command; 1294 { 1295 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1296 u_int32_t status, sock_ctrl, reg_ctrl; 1297 bus_space_tag_t memt = sc->sc_base_memt; 1298 bus_space_handle_t memh = sc->sc_base_memh; 1299 int on = 0, pwrcycle; 1300 1301 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1302 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1303 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1304 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1305 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1306 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1307 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1308 "UNKNOWN", 1309 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1310 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1311 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1312 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1313 "UNKNOWN", command)); 1314 1315 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1316 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1317 1318 switch (command & CARDBUS_VCCMASK) { 1319 case CARDBUS_VCC_UC: 1320 break; 1321 case CARDBUS_VCC_5V: 1322 on++; 1323 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1324 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1325 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1326 } else { 1327 printf("%s: BAD voltage request: no 5 V card\n", 1328 sc->sc_dev.dv_xname); 1329 return 0; 1330 } 1331 break; 1332 case CARDBUS_VCC_3V: 1333 on++; 1334 if (CB_SOCKET_STAT_3VCARD & status) { 1335 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1336 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1337 } else { 1338 printf("%s: BAD voltage request: no 3.3 V card\n", 1339 sc->sc_dev.dv_xname); 1340 return 0; 1341 } 1342 break; 1343 case CARDBUS_VCC_0V: 1344 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1345 break; 1346 default: 1347 return 0; /* power NEVER changed */ 1348 } 1349 1350 switch (command & CARDBUS_VPPMASK) { 1351 case CARDBUS_VPP_UC: 1352 break; 1353 case CARDBUS_VPP_0V: 1354 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1355 break; 1356 case CARDBUS_VPP_VCC: 1357 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1358 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1359 break; 1360 case CARDBUS_VPP_12V: 1361 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1362 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1363 break; 1364 } 1365 1366 pwrcycle = sc->sc_pwrcycle; 1367 1368 #if 0 1369 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1370 #endif 1371 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1372 1373 if (on) { 1374 int s, error = 0; 1375 struct timeval before, after, diff; 1376 1377 microtime(&before); 1378 s = splbio(); 1379 while (pwrcycle == sc->sc_pwrcycle) { 1380 /* 1381 * XXX: Set timeout to 200ms because power cycle event 1382 * will never happen when attaching a 16-bit card. 1383 */ 1384 if ((error = tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1385 hz / 5)) == EWOULDBLOCK) 1386 break; 1387 } 1388 splx(s); 1389 microtime(&after); 1390 timersub(&after, &before, &diff); 1391 aprint_debug("%s: wait took%s %ld.%06lds\n", 1392 sc->sc_dev.dv_xname, 1393 error == EWOULDBLOCK ? " too long" : "", 1394 diff.tv_sec, diff.tv_usec); 1395 } 1396 1397 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1398 1399 if (on) { 1400 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1401 printf("%s: power on failed?\n", sc->sc_dev.dv_xname); 1402 } 1403 1404 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1405 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1406 sc->sc_dev.dv_xname, sock_ctrl, status); 1407 printf("%s: disabling socket\n", sc->sc_dev.dv_xname); 1408 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1409 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1410 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1411 status &= ~CB_SOCKET_STAT_BADVCC; 1412 bus_space_write_4(memt, memh, CB_SOCKET_STAT, status); 1413 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1414 CB_SOCKET_STAT)); 1415 return 0; 1416 } 1417 1418 if (sc->sc_chipset == CB_TOPIC97) { 1419 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1420 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1421 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1422 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1423 else 1424 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1425 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1426 } 1427 1428 return 1; /* power changed correctly */ 1429 } 1430 1431 #if defined CB_PCMCIA_POLL 1432 struct cb_poll_str { 1433 void *arg; 1434 int (*func)(void *); 1435 int level; 1436 pccard_chipset_tag_t ct; 1437 int count; 1438 struct callout poll_ch; 1439 }; 1440 1441 static struct cb_poll_str cb_poll[10]; 1442 static int cb_poll_n = 0; 1443 1444 static void cb_pcmcia_poll(void *arg); 1445 1446 static void 1447 cb_pcmcia_poll(arg) 1448 void *arg; 1449 { 1450 struct cb_poll_str *poll = arg; 1451 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1452 struct pccbb_softc *sc = psc->cpc_parent; 1453 int s; 1454 u_int32_t spsr; /* socket present-state reg */ 1455 1456 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1457 switch (poll->level) { 1458 case IPL_NET: 1459 s = splnet(); 1460 break; 1461 case IPL_BIO: 1462 s = splbio(); 1463 break; 1464 case IPL_TTY: /* fallthrough */ 1465 default: 1466 s = spltty(); 1467 break; 1468 } 1469 1470 spsr = 1471 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1472 CB_SOCKET_STAT); 1473 1474 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1475 if (!(spsr & 0x40)) { /* CINT low */ 1476 #else 1477 if (1) { 1478 #endif 1479 if ((*poll->func) (poll->arg) == 1) { 1480 ++poll->count; 1481 printf("intr: reported from poller, 0x%x\n", spsr); 1482 #if defined LEVEL2 1483 } else { 1484 printf("intr: miss! 0x%x\n", spsr); 1485 #endif 1486 } 1487 } 1488 splx(s); 1489 } 1490 #endif /* defined CB_PCMCIA_POLL */ 1491 1492 /* 1493 * static int pccbb_detect_card(struct pccbb_softc *sc) 1494 * return value: 0 if no card exists. 1495 * 1 if 16-bit card exists. 1496 * 2 if cardbus card exists. 1497 */ 1498 static int 1499 pccbb_detect_card(sc) 1500 struct pccbb_softc *sc; 1501 { 1502 bus_space_handle_t base_memh = sc->sc_base_memh; 1503 bus_space_tag_t base_memt = sc->sc_base_memt; 1504 u_int32_t sockstat = 1505 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1506 int retval = 0; 1507 1508 /* CD1 and CD2 asserted */ 1509 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1510 /* card must be present */ 1511 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1512 /* NOTACARD DEASSERTED */ 1513 if (CB_SOCKET_STAT_CB & sockstat) { 1514 /* CardBus mode */ 1515 retval = 2; 1516 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1517 /* 16-bit mode */ 1518 retval = 1; 1519 } 1520 } 1521 } 1522 return retval; 1523 } 1524 1525 /* 1526 * STATIC int cb_reset(struct pccbb_softc *sc) 1527 * This function resets CardBus card. 1528 */ 1529 STATIC int 1530 cb_reset(sc) 1531 struct pccbb_softc *sc; 1532 { 1533 /* 1534 * Reset Assert at least 20 ms 1535 * Some machines request longer duration. 1536 */ 1537 int reset_duration = 1538 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1539 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1540 1541 /* Reset bit Assert (bit 6 at 0x3E) */ 1542 bcr |= CB_BCR_RESET_ENABLE; 1543 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1544 DELAY_MS(reset_duration, sc); 1545 1546 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1547 /* Reset bit Deassert (bit 6 at 0x3E) */ 1548 bcr &= ~CB_BCR_RESET_ENABLE; 1549 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1550 DELAY_MS(reset_duration, sc); 1551 } 1552 /* No card found on the slot. Keep Reset. */ 1553 return 1; 1554 } 1555 1556 /* 1557 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1558 * This function detect card Voltage. 1559 */ 1560 STATIC int 1561 cb_detect_voltage(sc) 1562 struct pccbb_softc *sc; 1563 { 1564 u_int32_t psr; /* socket present-state reg */ 1565 bus_space_tag_t iot = sc->sc_base_memt; 1566 bus_space_handle_t ioh = sc->sc_base_memh; 1567 int vol = PCCARD_VCC_UKN; /* set 0 */ 1568 1569 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1570 1571 if (0x400u & psr) { 1572 vol |= PCCARD_VCC_5V; 1573 } 1574 if (0x800u & psr) { 1575 vol |= PCCARD_VCC_3V; 1576 } 1577 1578 return vol; 1579 } 1580 1581 STATIC int 1582 cbbprint(aux, pcic) 1583 void *aux; 1584 const char *pcic; 1585 { 1586 /* 1587 struct cbslot_attach_args *cba = aux; 1588 1589 if (cba->cba_slot >= 0) { 1590 aprint_normal(" slot %d", cba->cba_slot); 1591 } 1592 */ 1593 return UNCONF; 1594 } 1595 1596 /* 1597 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1598 * This function enables and disables the card 1599 */ 1600 STATIC int 1601 pccbb_cardenable(sc, function) 1602 struct pccbb_softc *sc; 1603 int function; 1604 { 1605 u_int32_t command = 1606 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1607 1608 DPRINTF(("pccbb_cardenable:")); 1609 switch (function) { 1610 case CARDBUS_IO_ENABLE: 1611 command |= PCI_COMMAND_IO_ENABLE; 1612 break; 1613 case CARDBUS_IO_DISABLE: 1614 command &= ~PCI_COMMAND_IO_ENABLE; 1615 break; 1616 case CARDBUS_MEM_ENABLE: 1617 command |= PCI_COMMAND_MEM_ENABLE; 1618 break; 1619 case CARDBUS_MEM_DISABLE: 1620 command &= ~PCI_COMMAND_MEM_ENABLE; 1621 break; 1622 case CARDBUS_BM_ENABLE: 1623 command |= PCI_COMMAND_MASTER_ENABLE; 1624 break; 1625 case CARDBUS_BM_DISABLE: 1626 command &= ~PCI_COMMAND_MASTER_ENABLE; 1627 break; 1628 default: 1629 return 0; 1630 } 1631 1632 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1633 DPRINTF((" command reg 0x%x\n", command)); 1634 return 1; 1635 } 1636 1637 #if !rbus 1638 /* 1639 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1640 */ 1641 static int 1642 pccbb_io_open(ct, win, start, end) 1643 cardbus_chipset_tag_t ct; 1644 int win; 1645 u_int32_t start, end; 1646 { 1647 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1648 int basereg; 1649 int limitreg; 1650 1651 if ((win < 0) || (win > 2)) { 1652 #if defined DIAGNOSTIC 1653 printf("cardbus_io_open: window out of range %d\n", win); 1654 #endif 1655 return 0; 1656 } 1657 1658 basereg = win * 8 + 0x2c; 1659 limitreg = win * 8 + 0x30; 1660 1661 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1662 start, basereg, end, limitreg)); 1663 1664 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1665 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1666 return 1; 1667 } 1668 1669 /* 1670 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1671 */ 1672 static int 1673 pccbb_io_close(ct, win) 1674 cardbus_chipset_tag_t ct; 1675 int win; 1676 { 1677 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1678 int basereg; 1679 int limitreg; 1680 1681 if ((win < 0) || (win > 2)) { 1682 #if defined DIAGNOSTIC 1683 printf("cardbus_io_close: window out of range %d\n", win); 1684 #endif 1685 return 0; 1686 } 1687 1688 basereg = win * 8 + 0x2c; 1689 limitreg = win * 8 + 0x30; 1690 1691 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1692 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1693 return 1; 1694 } 1695 1696 /* 1697 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1698 */ 1699 static int 1700 pccbb_mem_open(ct, win, start, end) 1701 cardbus_chipset_tag_t ct; 1702 int win; 1703 u_int32_t start, end; 1704 { 1705 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1706 int basereg; 1707 int limitreg; 1708 1709 if ((win < 0) || (win > 2)) { 1710 #if defined DIAGNOSTIC 1711 printf("cardbus_mem_open: window out of range %d\n", win); 1712 #endif 1713 return 0; 1714 } 1715 1716 basereg = win * 8 + 0x1c; 1717 limitreg = win * 8 + 0x20; 1718 1719 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1720 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1721 return 1; 1722 } 1723 1724 /* 1725 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1726 */ 1727 static int 1728 pccbb_mem_close(ct, win) 1729 cardbus_chipset_tag_t ct; 1730 int win; 1731 { 1732 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1733 int basereg; 1734 int limitreg; 1735 1736 if ((win < 0) || (win > 2)) { 1737 #if defined DIAGNOSTIC 1738 printf("cardbus_mem_close: window out of range %d\n", win); 1739 #endif 1740 return 0; 1741 } 1742 1743 basereg = win * 8 + 0x1c; 1744 limitreg = win * 8 + 0x20; 1745 1746 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1747 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1748 return 1; 1749 } 1750 #endif 1751 1752 /* 1753 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1754 * int irq, 1755 * int level, 1756 * int (* func)(void *), 1757 * void *arg) 1758 * 1759 * This function registers an interrupt handler at the bridge, in 1760 * order not to call the interrupt handlers of child devices when 1761 * a card-deletion interrupt occurs. 1762 * 1763 * The arguments irq and level are not used. 1764 */ 1765 static void * 1766 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1767 cardbus_chipset_tag_t ct; 1768 int irq, level; 1769 int (*func)(void *); 1770 void *arg; 1771 { 1772 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1773 1774 return pccbb_intr_establish(sc, irq, level, func, arg); 1775 } 1776 1777 1778 /* 1779 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1780 * void *ih) 1781 * 1782 * This function removes an interrupt handler pointed by ih. 1783 */ 1784 static void 1785 pccbb_cb_intr_disestablish(ct, ih) 1786 cardbus_chipset_tag_t ct; 1787 void *ih; 1788 { 1789 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1790 1791 pccbb_intr_disestablish(sc, ih); 1792 } 1793 1794 1795 void 1796 pccbb_intr_route(sc) 1797 struct pccbb_softc *sc; 1798 { 1799 pcireg_t reg; 1800 1801 /* initialize bridge intr routing */ 1802 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1803 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1804 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1805 1806 switch (sc->sc_chipset) { 1807 case CB_TI113X: 1808 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1809 /* functional intr enabled */ 1810 reg |= PCI113X_CBCTRL_PCI_INTR; 1811 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1812 break; 1813 default: 1814 break; 1815 } 1816 } 1817 1818 /* 1819 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1820 * int irq, 1821 * int level, 1822 * int (* func)(void *), 1823 * void *arg) 1824 * 1825 * This function registers an interrupt handler at the bridge, in 1826 * order not to call the interrupt handlers of child devices when 1827 * a card-deletion interrupt occurs. 1828 * 1829 * The arguments irq is not used because pccbb selects intr vector. 1830 */ 1831 static void * 1832 pccbb_intr_establish(sc, irq, level, func, arg) 1833 struct pccbb_softc *sc; 1834 int irq, level; 1835 int (*func)(void *); 1836 void *arg; 1837 { 1838 struct pccbb_intrhand_list *pil, *newpil; 1839 1840 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1841 1842 if (LIST_EMPTY(&sc->sc_pil)) { 1843 pccbb_intr_route(sc); 1844 } 1845 1846 /* 1847 * Allocate a room for interrupt handler structure. 1848 */ 1849 if (NULL == (newpil = 1850 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1851 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1852 return NULL; 1853 } 1854 1855 newpil->pil_func = func; 1856 newpil->pil_arg = arg; 1857 newpil->pil_level = level; 1858 1859 if (LIST_EMPTY(&sc->sc_pil)) { 1860 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1861 } else { 1862 for (pil = LIST_FIRST(&sc->sc_pil); 1863 LIST_NEXT(pil, pil_next) != NULL; 1864 pil = LIST_NEXT(pil, pil_next)); 1865 LIST_INSERT_AFTER(pil, newpil, pil_next); 1866 } 1867 1868 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1869 LIST_FIRST(&sc->sc_pil))); 1870 1871 return newpil; 1872 } 1873 1874 /* 1875 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1876 * void *ih) 1877 * 1878 * This function removes an interrupt handler pointed by ih. ih 1879 * should be the value returned by cardbus_intr_establish() or 1880 * NULL. 1881 * 1882 * When ih is NULL, this function will do nothing. 1883 */ 1884 static void 1885 pccbb_intr_disestablish(sc, ih) 1886 struct pccbb_softc *sc; 1887 void *ih; 1888 { 1889 struct pccbb_intrhand_list *pil; 1890 pcireg_t reg; 1891 1892 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1893 LIST_FIRST(&sc->sc_pil))); 1894 1895 if (ih == NULL) { 1896 /* intr handler is not set */ 1897 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1898 return; 1899 } 1900 1901 #ifdef DIAGNOSTIC 1902 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1903 pil = LIST_NEXT(pil, pil_next)) { 1904 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1905 if (pil == ih) { 1906 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1907 break; 1908 } 1909 } 1910 if (pil == NULL) { 1911 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1912 sc->sc_dev.dv_xname, ih); 1913 } 1914 #endif 1915 1916 pil = (struct pccbb_intrhand_list *)ih; 1917 LIST_REMOVE(pil, pil_next); 1918 free(pil, M_DEVBUF); 1919 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1920 1921 if (LIST_EMPTY(&sc->sc_pil)) { 1922 /* No interrupt handlers */ 1923 1924 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1925 1926 /* stop routing PCI intr */ 1927 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1928 reg |= CB_BCR_INTR_IREQ_ENABLE; 1929 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1930 1931 switch (sc->sc_chipset) { 1932 case CB_TI113X: 1933 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1934 /* functional intr disabled */ 1935 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1936 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1937 break; 1938 default: 1939 break; 1940 } 1941 } 1942 } 1943 1944 #if defined SHOW_REGS 1945 static void 1946 cb_show_regs(pc, tag, memt, memh) 1947 pci_chipset_tag_t pc; 1948 pcitag_t tag; 1949 bus_space_tag_t memt; 1950 bus_space_handle_t memh; 1951 { 1952 int i; 1953 printf("PCI config regs:"); 1954 for (i = 0; i < 0x50; i += 4) { 1955 if (i % 16 == 0) { 1956 printf("\n 0x%02x:", i); 1957 } 1958 printf(" %08x", pci_conf_read(pc, tag, i)); 1959 } 1960 for (i = 0x80; i < 0xb0; i += 4) { 1961 if (i % 16 == 0) { 1962 printf("\n 0x%02x:", i); 1963 } 1964 printf(" %08x", pci_conf_read(pc, tag, i)); 1965 } 1966 1967 if (memh == 0) { 1968 printf("\n"); 1969 return; 1970 } 1971 1972 printf("\nsocket regs:"); 1973 for (i = 0; i <= 0x10; i += 0x04) { 1974 printf(" %08x", bus_space_read_4(memt, memh, i)); 1975 } 1976 printf("\nExCA regs:"); 1977 for (i = 0; i < 0x08; ++i) { 1978 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1979 } 1980 printf("\n"); 1981 return; 1982 } 1983 #endif 1984 1985 /* 1986 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1987 * int busno, int function) 1988 * This is the function to make a tag to access config space of 1989 * a CardBus Card. It works same as pci_conf_read. 1990 */ 1991 static cardbustag_t 1992 pccbb_make_tag(cc, busno, function) 1993 cardbus_chipset_tag_t cc; 1994 int busno, function; 1995 { 1996 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1997 1998 return pci_make_tag(sc->sc_pc, busno, 0, function); 1999 } 2000 2001 static void 2002 pccbb_free_tag(cc, tag) 2003 cardbus_chipset_tag_t cc; 2004 cardbustag_t tag; 2005 { 2006 } 2007 2008 /* 2009 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 2010 * cardbustag_t tag, int offset) 2011 * This is the function to read the config space of a CardBus Card. 2012 * It works same as pci_conf_read. 2013 */ 2014 static cardbusreg_t 2015 pccbb_conf_read(cc, tag, offset) 2016 cardbus_chipset_tag_t cc; 2017 cardbustag_t tag; 2018 int offset; /* register offset */ 2019 { 2020 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2021 2022 return pci_conf_read(sc->sc_pc, tag, offset); 2023 } 2024 2025 /* 2026 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 2027 * int offs, cardbusreg_t val) 2028 * This is the function to write the config space of a CardBus Card. 2029 * It works same as pci_conf_write. 2030 */ 2031 static void 2032 pccbb_conf_write(cc, tag, reg, val) 2033 cardbus_chipset_tag_t cc; 2034 cardbustag_t tag; 2035 int reg; /* register offset */ 2036 cardbusreg_t val; 2037 { 2038 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2039 2040 pci_conf_write(sc->sc_pc, tag, reg, val); 2041 } 2042 2043 #if 0 2044 STATIC int 2045 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2046 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2047 int speed, int flags, 2048 bus_space_handle_t * iohp) 2049 #endif 2050 /* 2051 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2052 * bus_addr_t start, bus_size_t size, 2053 * bus_size_t align, 2054 * struct pcmcia_io_handle *pcihp 2055 * 2056 * This function only allocates I/O region for pccard. This function 2057 * never maps the allocated region to pccard I/O area. 2058 * 2059 * XXX: The interface of this function is not very good, I believe. 2060 */ 2061 STATIC int 2062 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2063 pcmcia_chipset_handle_t pch; 2064 bus_addr_t start; /* start address */ 2065 bus_size_t size; 2066 bus_size_t align; 2067 struct pcmcia_io_handle *pcihp; 2068 { 2069 struct pcic_handle *ph = (struct pcic_handle *)pch; 2070 bus_addr_t ioaddr; 2071 int flags = 0; 2072 bus_space_tag_t iot; 2073 bus_space_handle_t ioh; 2074 bus_addr_t mask; 2075 #if rbus 2076 rbus_tag_t rb; 2077 #endif 2078 if (align == 0) { 2079 align = size; /* XXX: funny??? */ 2080 } 2081 2082 if (start != 0) { 2083 /* XXX: assume all card decode lower 10 bits by its hardware */ 2084 mask = 0x3ff; 2085 /* enforce to use only masked address */ 2086 start &= mask; 2087 } else { 2088 /* 2089 * calculate mask: 2090 * 1. get the most significant bit of size (call it msb). 2091 * 2. compare msb with the value of size. 2092 * 3. if size is larger, shift msb left once. 2093 * 4. obtain mask value to decrement msb. 2094 */ 2095 bus_size_t size_tmp = size; 2096 int shifts = 0; 2097 2098 mask = 1; 2099 while (size_tmp) { 2100 ++shifts; 2101 size_tmp >>= 1; 2102 } 2103 mask = (1 << shifts); 2104 if (mask < size) { 2105 mask <<= 1; 2106 } 2107 --mask; 2108 } 2109 2110 /* 2111 * Allocate some arbitrary I/O space. 2112 */ 2113 2114 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2115 2116 #if rbus 2117 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2118 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2119 return 1; 2120 } 2121 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2122 (u_long) ioaddr, (u_long) size)); 2123 #else 2124 if (start) { 2125 ioaddr = start; 2126 if (bus_space_map(iot, start, size, 0, &ioh)) { 2127 return 1; 2128 } 2129 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2130 (u_long) ioaddr, (u_long) size)); 2131 } else { 2132 flags |= PCMCIA_IO_ALLOCATED; 2133 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2134 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2135 size, align, 0, 0, &ioaddr, &ioh)) { 2136 /* No room be able to be get. */ 2137 return 1; 2138 } 2139 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2140 (u_long) ioaddr, (u_long) size)); 2141 } 2142 #endif 2143 2144 pcihp->iot = iot; 2145 pcihp->ioh = ioh; 2146 pcihp->addr = ioaddr; 2147 pcihp->size = size; 2148 pcihp->flags = flags; 2149 2150 return 0; 2151 } 2152 2153 /* 2154 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2155 * struct pcmcia_io_handle *pcihp) 2156 * 2157 * This function only frees I/O region for pccard. 2158 * 2159 * XXX: The interface of this function is not very good, I believe. 2160 */ 2161 void 2162 pccbb_pcmcia_io_free(pch, pcihp) 2163 pcmcia_chipset_handle_t pch; 2164 struct pcmcia_io_handle *pcihp; 2165 { 2166 #if !rbus 2167 bus_space_tag_t iot = pcihp->iot; 2168 #endif 2169 bus_space_handle_t ioh = pcihp->ioh; 2170 bus_size_t size = pcihp->size; 2171 2172 #if rbus 2173 struct pccbb_softc *sc = 2174 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2175 rbus_tag_t rb = sc->sc_rbus_iot; 2176 2177 rbus_space_free(rb, ioh, size, NULL); 2178 #else 2179 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2180 bus_space_free(iot, ioh, size); 2181 else 2182 bus_space_unmap(iot, ioh, size); 2183 #endif 2184 } 2185 2186 /* 2187 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2188 * bus_addr_t offset, bus_size_t size, 2189 * struct pcmcia_io_handle *pcihp, 2190 * int *windowp) 2191 * 2192 * This function maps the allocated I/O region to pccard. This function 2193 * never allocates any I/O region for pccard I/O area. I don't 2194 * understand why the original authors of pcmciabus separated alloc and 2195 * map. I believe the two must be unite. 2196 * 2197 * XXX: no wait timing control? 2198 */ 2199 int 2200 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2201 pcmcia_chipset_handle_t pch; 2202 int width; 2203 bus_addr_t offset; 2204 bus_size_t size; 2205 struct pcmcia_io_handle *pcihp; 2206 int *windowp; 2207 { 2208 struct pcic_handle *ph = (struct pcic_handle *)pch; 2209 bus_addr_t ioaddr = pcihp->addr + offset; 2210 int i, win; 2211 #if defined CBB_DEBUG 2212 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2213 #endif 2214 2215 /* Sanity check I/O handle. */ 2216 2217 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2218 panic("pccbb_pcmcia_io_map iot is bogus"); 2219 } 2220 2221 /* XXX Sanity check offset/size. */ 2222 2223 win = -1; 2224 for (i = 0; i < PCIC_IO_WINS; i++) { 2225 if ((ph->ioalloc & (1 << i)) == 0) { 2226 win = i; 2227 ph->ioalloc |= (1 << i); 2228 break; 2229 } 2230 } 2231 2232 if (win == -1) { 2233 return 1; 2234 } 2235 2236 *windowp = win; 2237 2238 /* XXX this is pretty gross */ 2239 2240 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2241 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2242 2243 /* XXX wtf is this doing here? */ 2244 2245 #if 0 2246 printf(" port 0x%lx", (u_long) ioaddr); 2247 if (size > 1) { 2248 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2249 } 2250 #endif 2251 2252 ph->io[win].addr = ioaddr; 2253 ph->io[win].size = size; 2254 ph->io[win].width = width; 2255 2256 /* actual dirty register-value changing in the function below. */ 2257 pccbb_pcmcia_do_io_map(ph, win); 2258 2259 return 0; 2260 } 2261 2262 /* 2263 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2264 * 2265 * This function changes register-value to map I/O region for pccard. 2266 */ 2267 static void 2268 pccbb_pcmcia_do_io_map(ph, win) 2269 struct pcic_handle *ph; 2270 int win; 2271 { 2272 static u_int8_t pcic_iowidth[3] = { 2273 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2274 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2275 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2276 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2277 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2278 }; 2279 2280 #define PCIC_SIA_START_LOW 0 2281 #define PCIC_SIA_START_HIGH 1 2282 #define PCIC_SIA_STOP_LOW 2 2283 #define PCIC_SIA_STOP_HIGH 3 2284 2285 int regbase_win = 0x8 + win * 0x04; 2286 u_int8_t ioctl, enable; 2287 2288 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2289 "width %d\n", win, (unsigned long)ph->io[win].addr, 2290 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2291 2292 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2293 ph->io[win].addr & 0xff); 2294 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2295 (ph->io[win].addr >> 8) & 0xff); 2296 2297 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2298 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2299 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2300 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2301 2302 ioctl = Pcic_read(ph, PCIC_IOCTL); 2303 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2304 switch (win) { 2305 case 0: 2306 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2307 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2308 PCIC_IOCTL_IO0_DATASIZE_MASK); 2309 ioctl |= pcic_iowidth[ph->io[win].width]; 2310 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2311 break; 2312 case 1: 2313 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2314 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2315 PCIC_IOCTL_IO1_DATASIZE_MASK); 2316 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2317 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2318 break; 2319 } 2320 Pcic_write(ph, PCIC_IOCTL, ioctl); 2321 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2322 #if defined CBB_DEBUG 2323 { 2324 u_int8_t start_low = 2325 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2326 u_int8_t start_high = 2327 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2328 u_int8_t stop_low = 2329 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2330 u_int8_t stop_high = 2331 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2332 printf 2333 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2334 start_low, start_high, stop_low, stop_high, ioctl, enable); 2335 } 2336 #endif 2337 } 2338 2339 /* 2340 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2341 * 2342 * This function unmaps I/O region. No return value. 2343 */ 2344 STATIC void 2345 pccbb_pcmcia_io_unmap(pch, win) 2346 pcmcia_chipset_handle_t pch; 2347 int win; 2348 { 2349 struct pcic_handle *ph = (struct pcic_handle *)pch; 2350 int reg; 2351 2352 if (win >= PCIC_IO_WINS || win < 0) { 2353 panic("pccbb_pcmcia_io_unmap: window out of range"); 2354 } 2355 2356 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2357 switch (win) { 2358 case 0: 2359 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2360 break; 2361 case 1: 2362 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2363 break; 2364 } 2365 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2366 2367 ph->ioalloc &= ~(1 << win); 2368 } 2369 2370 static int 2371 pccbb_pcmcia_wait_ready(ph) 2372 struct pcic_handle *ph; 2373 { 2374 u_int8_t stat; 2375 int i; 2376 2377 /* wait an initial 10ms for quick cards */ 2378 stat = Pcic_read(ph, PCIC_IF_STATUS); 2379 if (stat & PCIC_IF_STATUS_READY) 2380 return (0); 2381 pccbb_pcmcia_delay(ph, 10, "pccwr0"); 2382 for (i = 0; i < 50; i++) { 2383 stat = Pcic_read(ph, PCIC_IF_STATUS); 2384 if (stat & PCIC_IF_STATUS_READY) 2385 return (0); 2386 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2387 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2388 return (ENXIO); 2389 /* wait .1s (100ms) each iteration now */ 2390 pccbb_pcmcia_delay(ph, 100, "pccwr1"); 2391 } 2392 2393 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2394 return (EWOULDBLOCK); 2395 } 2396 2397 /* 2398 * Perform long (msec order) delay. 2399 */ 2400 static void 2401 pccbb_pcmcia_delay(ph, timo, wmesg) 2402 struct pcic_handle *ph; 2403 int timo; /* in ms. must not be zero */ 2404 const char *wmesg; 2405 { 2406 2407 #ifdef DIAGNOSTIC 2408 if (timo <= 0) 2409 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2410 if (!curlwp) 2411 panic("pccbb_pcmcia_delay: called in interrupt context"); 2412 #if 0 2413 if (!ph->event_thread) 2414 panic("pccbb_pcmcia_delay: no event thread"); 2415 #endif 2416 #endif 2417 DPRINTF(("pccbb_pcmcia_delay: \"%s\" %p, sleep %d ms\n", 2418 wmesg, ph->event_thread, timo)); 2419 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2420 } 2421 2422 /* 2423 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2424 * 2425 * This function enables the card. All information is stored in 2426 * the first argument, pcmcia_chipset_handle_t. 2427 */ 2428 STATIC void 2429 pccbb_pcmcia_socket_enable(pch) 2430 pcmcia_chipset_handle_t pch; 2431 { 2432 struct pcic_handle *ph = (struct pcic_handle *)pch; 2433 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2434 pcireg_t spsr; 2435 int voltage; 2436 int win; 2437 u_int8_t power, intr; 2438 #ifdef DIAGNOSTIC 2439 int reg; 2440 #endif 2441 2442 /* this bit is mostly stolen from pcic_attach_card */ 2443 2444 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2445 2446 /* get card Vcc info */ 2447 spsr = 2448 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2449 CB_SOCKET_STAT); 2450 if (spsr & CB_SOCKET_STAT_5VCARD) { 2451 DPRINTF(("5V card\n")); 2452 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2453 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2454 DPRINTF(("3V card\n")); 2455 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2456 } else { 2457 printf("?V card, 0x%x\n", spsr); /* XXX */ 2458 return; 2459 } 2460 2461 /* disable interrupts; assert RESET */ 2462 intr = Pcic_read(ph, PCIC_INTR); 2463 intr &= PCIC_INTR_ENABLE; 2464 Pcic_write(ph, PCIC_INTR, intr); 2465 2466 /* zero out the address windows */ 2467 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2468 2469 /* power down the socket to reset it, clear the card reset pin */ 2470 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2471 2472 /* power off; assert output enable bit */ 2473 power = PCIC_PWRCTL_OE; 2474 Pcic_write(ph, PCIC_PWRCTL, power); 2475 2476 /* power up the socket */ 2477 if (pccbb_power(sc, voltage) == 0) 2478 return; 2479 2480 /* 2481 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2482 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2483 * RESET Width (Th (Hi-z RESET)) = 1ms 2484 * RESET Width (Tw (RESET)) = 10us 2485 */ 2486 pccbb_pcmcia_delay(ph, 1, "pccen1"); 2487 2488 /* negate RESET */ 2489 intr |= PCIC_INTR_RESET; 2490 Pcic_write(ph, PCIC_INTR, intr); 2491 2492 /* 2493 * RESET Setup Time (Tsu (RESET)) = 20ms 2494 */ 2495 pccbb_pcmcia_delay(ph, 20, "pccen2"); 2496 2497 #ifdef DIAGNOSTIC 2498 reg = Pcic_read(ph, PCIC_IF_STATUS); 2499 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2500 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2501 #endif 2502 2503 /* wait for the chip to finish initializing */ 2504 if (pccbb_pcmcia_wait_ready(ph)) { 2505 /* XXX return a failure status?? */ 2506 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2507 Pcic_write(ph, PCIC_PWRCTL, 0); 2508 return; 2509 } 2510 2511 /* reinstall all the memory and io mappings */ 2512 for (win = 0; win < PCIC_MEM_WINS; ++win) 2513 if (ph->memalloc & (1 << win)) 2514 pccbb_pcmcia_do_mem_map(ph, win); 2515 for (win = 0; win < PCIC_IO_WINS; ++win) 2516 if (ph->ioalloc & (1 << win)) 2517 pccbb_pcmcia_do_io_map(ph, win); 2518 } 2519 2520 /* 2521 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2522 * 2523 * This function disables the card. All information is stored in 2524 * the first argument, pcmcia_chipset_handle_t. 2525 */ 2526 STATIC void 2527 pccbb_pcmcia_socket_disable(pch) 2528 pcmcia_chipset_handle_t pch; 2529 { 2530 struct pcic_handle *ph = (struct pcic_handle *)pch; 2531 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2532 u_int8_t intr; 2533 2534 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2535 2536 /* disable interrupts; assert RESET */ 2537 intr = Pcic_read(ph, PCIC_INTR); 2538 intr &= PCIC_INTR_ENABLE; 2539 Pcic_write(ph, PCIC_INTR, intr); 2540 2541 /* zero out the address windows */ 2542 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2543 2544 /* power down the socket to reset it, clear the card reset pin */ 2545 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2546 2547 /* disable socket: negate output enable bit and power off */ 2548 Pcic_write(ph, PCIC_PWRCTL, 0); 2549 2550 /* 2551 * Vcc Falling Time (Tpf) = 300ms 2552 */ 2553 pccbb_pcmcia_delay(ph, 300, "pccwr1"); 2554 } 2555 2556 STATIC void 2557 pccbb_pcmcia_socket_settype(pch, type) 2558 pcmcia_chipset_handle_t pch; 2559 int type; 2560 { 2561 struct pcic_handle *ph = (struct pcic_handle *)pch; 2562 u_int8_t intr; 2563 2564 /* set the card type */ 2565 2566 intr = Pcic_read(ph, PCIC_INTR); 2567 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2568 if (type == PCMCIA_IFTYPE_IO) 2569 intr |= PCIC_INTR_CARDTYPE_IO; 2570 else 2571 intr |= PCIC_INTR_CARDTYPE_MEM; 2572 Pcic_write(ph, PCIC_INTR, intr); 2573 2574 DPRINTF(("%s: pccbb_pcmcia_socket_settype %02x type %s %02x\n", 2575 ph->ph_parent->dv_xname, ph->sock, 2576 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2577 } 2578 2579 /* 2580 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2581 * 2582 * This function detects whether a card is in the slot or not. 2583 * If a card is inserted, return 1. Otherwise, return 0. 2584 */ 2585 STATIC int 2586 pccbb_pcmcia_card_detect(pch) 2587 pcmcia_chipset_handle_t pch; 2588 { 2589 struct pcic_handle *ph = (struct pcic_handle *)pch; 2590 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2591 2592 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2593 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2594 } 2595 2596 #if 0 2597 STATIC int 2598 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2599 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2600 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2601 #endif 2602 /* 2603 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2604 * bus_size_t size, 2605 * struct pcmcia_mem_handle *pcmhp) 2606 * 2607 * This function only allocates memory region for pccard. This 2608 * function never maps the allocated region to pccard memory area. 2609 * 2610 * XXX: Why the argument of start address is not in? 2611 */ 2612 STATIC int 2613 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2614 pcmcia_chipset_handle_t pch; 2615 bus_size_t size; 2616 struct pcmcia_mem_handle *pcmhp; 2617 { 2618 struct pcic_handle *ph = (struct pcic_handle *)pch; 2619 bus_space_handle_t memh; 2620 bus_addr_t addr; 2621 bus_size_t sizepg; 2622 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2623 #if rbus 2624 rbus_tag_t rb; 2625 #endif 2626 2627 /* Check that the card is still there. */ 2628 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2629 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2630 return 1; 2631 2632 /* out of sc->memh, allocate as many pages as necessary */ 2633 2634 /* convert size to PCIC pages */ 2635 /* 2636 * This is not enough; when the requested region is on the page 2637 * boundaries, this may calculate wrong result. 2638 */ 2639 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2640 #if 0 2641 if (sizepg > PCIC_MAX_MEM_PAGES) { 2642 return 1; 2643 } 2644 #endif 2645 2646 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2647 return 1; 2648 } 2649 2650 addr = 0; /* XXX gcc -Wuninitialized */ 2651 2652 #if rbus 2653 rb = sc->sc_rbus_memt; 2654 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2655 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2656 &addr, &memh)) { 2657 return 1; 2658 } 2659 #else 2660 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2661 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2662 0, /* boundary */ 2663 0, /* flags */ 2664 &addr, &memh)) { 2665 return 1; 2666 } 2667 #endif 2668 2669 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2670 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2671 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2672 2673 pcmhp->memt = sc->sc_memt; 2674 pcmhp->memh = memh; 2675 pcmhp->addr = addr; 2676 pcmhp->size = size; 2677 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2678 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2679 pcmhp->mhandle = 0; 2680 /* No offset??? Funny. */ 2681 2682 return 0; 2683 } 2684 2685 /* 2686 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2687 * struct pcmcia_mem_handle *pcmhp) 2688 * 2689 * This function release the memory space allocated by the function 2690 * pccbb_pcmcia_mem_alloc(). 2691 */ 2692 STATIC void 2693 pccbb_pcmcia_mem_free(pch, pcmhp) 2694 pcmcia_chipset_handle_t pch; 2695 struct pcmcia_mem_handle *pcmhp; 2696 { 2697 #if rbus 2698 struct pcic_handle *ph = (struct pcic_handle *)pch; 2699 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2700 2701 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2702 #else 2703 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2704 #endif 2705 } 2706 2707 /* 2708 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2709 * 2710 * This function release the memory space allocated by the function 2711 * pccbb_pcmcia_mem_alloc(). 2712 */ 2713 STATIC void 2714 pccbb_pcmcia_do_mem_map(ph, win) 2715 struct pcic_handle *ph; 2716 int win; 2717 { 2718 int regbase_win; 2719 bus_addr_t phys_addr; 2720 bus_addr_t phys_end; 2721 2722 #define PCIC_SMM_START_LOW 0 2723 #define PCIC_SMM_START_HIGH 1 2724 #define PCIC_SMM_STOP_LOW 2 2725 #define PCIC_SMM_STOP_HIGH 3 2726 #define PCIC_CMA_LOW 4 2727 #define PCIC_CMA_HIGH 5 2728 2729 u_int8_t start_low, start_high = 0; 2730 u_int8_t stop_low, stop_high; 2731 u_int8_t off_low, off_high; 2732 u_int8_t mem_window; 2733 int reg; 2734 2735 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2736 int mem8 = 2737 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2738 || (kind == PCMCIA_MEM_ATTR); 2739 2740 regbase_win = 0x10 + win * 0x08; 2741 2742 phys_addr = ph->mem[win].addr; 2743 phys_end = phys_addr + ph->mem[win].size; 2744 2745 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2746 (unsigned long)phys_addr, (unsigned long)phys_end, 2747 (unsigned long)ph->mem[win].offset)); 2748 2749 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2750 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2751 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2752 2753 /* bit 19:12 */ 2754 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2755 /* bit 23:20 and bit 7 on */ 2756 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2757 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2758 /* bit 31:24, for 32-bit address */ 2759 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2760 2761 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2762 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2763 2764 if (((struct pccbb_softc *)ph-> 2765 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2766 Pcic_write(ph, 0x40 + win, mem_window); 2767 } 2768 2769 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2770 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2771 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2772 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2773 2774 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2775 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2776 2777 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2778 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2779 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2780 | ((kind == PCMCIA_MEM_ATTR) ? 2781 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2782 2783 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2784 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2785 2786 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2787 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2788 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2789 2790 #if defined CBB_DEBUG 2791 { 2792 int r1, r2, r3, r4, r5, r6, r7 = 0; 2793 2794 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2795 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2796 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2797 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2798 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2799 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2800 if (((struct pccbb_softc *)(ph-> 2801 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2802 r7 = Pcic_read(ph, 0x40 + win); 2803 } 2804 2805 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2806 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2807 if (((struct pccbb_softc *)(ph-> 2808 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2809 DPRINTF((" %02x", r7)); 2810 } 2811 DPRINTF(("\n")); 2812 } 2813 #endif 2814 } 2815 2816 /* 2817 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2818 * bus_addr_t card_addr, bus_size_t size, 2819 * struct pcmcia_mem_handle *pcmhp, 2820 * bus_addr_t *offsetp, int *windowp) 2821 * 2822 * This function maps memory space allocated by the function 2823 * pccbb_pcmcia_mem_alloc(). 2824 */ 2825 STATIC int 2826 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2827 pcmcia_chipset_handle_t pch; 2828 int kind; 2829 bus_addr_t card_addr; 2830 bus_size_t size; 2831 struct pcmcia_mem_handle *pcmhp; 2832 bus_addr_t *offsetp; 2833 int *windowp; 2834 { 2835 struct pcic_handle *ph = (struct pcic_handle *)pch; 2836 bus_addr_t busaddr; 2837 long card_offset; 2838 int win; 2839 2840 /* Check that the card is still there. */ 2841 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2842 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2843 return 1; 2844 2845 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2846 if ((ph->memalloc & (1 << win)) == 0) { 2847 ph->memalloc |= (1 << win); 2848 break; 2849 } 2850 } 2851 2852 if (win == PCIC_MEM_WINS) { 2853 return 1; 2854 } 2855 2856 *windowp = win; 2857 2858 /* XXX this is pretty gross */ 2859 2860 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2861 panic("pccbb_pcmcia_mem_map memt is bogus"); 2862 } 2863 2864 busaddr = pcmhp->addr; 2865 2866 /* 2867 * compute the address offset to the pcmcia address space for the 2868 * pcic. this is intentionally signed. The masks and shifts below 2869 * will cause TRT to happen in the pcic registers. Deal with making 2870 * sure the address is aligned, and return the alignment offset. 2871 */ 2872 2873 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2874 card_addr -= *offsetp; 2875 2876 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2877 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2878 (u_long) card_addr)); 2879 2880 /* 2881 * include the offset in the size, and decrement size by one, since 2882 * the hw wants start/stop 2883 */ 2884 size += *offsetp - 1; 2885 2886 card_offset = (((long)card_addr) - ((long)busaddr)); 2887 2888 ph->mem[win].addr = busaddr; 2889 ph->mem[win].size = size; 2890 ph->mem[win].offset = card_offset; 2891 ph->mem[win].kind = kind; 2892 2893 pccbb_pcmcia_do_mem_map(ph, win); 2894 2895 return 0; 2896 } 2897 2898 /* 2899 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2900 * int window) 2901 * 2902 * This function unmaps memory space which mapped by the function 2903 * pccbb_pcmcia_mem_map(). 2904 */ 2905 STATIC void 2906 pccbb_pcmcia_mem_unmap(pch, window) 2907 pcmcia_chipset_handle_t pch; 2908 int window; 2909 { 2910 struct pcic_handle *ph = (struct pcic_handle *)pch; 2911 int reg; 2912 2913 if (window >= PCIC_MEM_WINS) { 2914 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2915 } 2916 2917 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2918 reg &= ~(1 << window); 2919 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2920 2921 ph->memalloc &= ~(1 << window); 2922 } 2923 2924 #if defined PCCBB_PCMCIA_POLL 2925 struct pccbb_poll_str { 2926 void *arg; 2927 int (*func)(void *); 2928 int level; 2929 struct pcic_handle *ph; 2930 int count; 2931 int num; 2932 struct callout poll_ch; 2933 }; 2934 2935 static struct pccbb_poll_str pccbb_poll[10]; 2936 static int pccbb_poll_n = 0; 2937 2938 static void pccbb_pcmcia_poll(void *arg); 2939 2940 static void 2941 pccbb_pcmcia_poll(arg) 2942 void *arg; 2943 { 2944 struct pccbb_poll_str *poll = arg; 2945 struct pcic_handle *ph = poll->ph; 2946 struct pccbb_softc *sc = ph->sc; 2947 int s; 2948 u_int32_t spsr; /* socket present-state reg */ 2949 2950 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2951 switch (poll->level) { 2952 case IPL_NET: 2953 s = splnet(); 2954 break; 2955 case IPL_BIO: 2956 s = splbio(); 2957 break; 2958 case IPL_TTY: /* fallthrough */ 2959 default: 2960 s = spltty(); 2961 break; 2962 } 2963 2964 spsr = 2965 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2966 CB_SOCKET_STAT); 2967 2968 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2969 if (!(spsr & 0x40)) /* CINT low */ 2970 #else 2971 if (1) 2972 #endif 2973 { 2974 if ((*poll->func) (poll->arg) > 0) { 2975 ++poll->count; 2976 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2977 #if defined LEVEL2 2978 } else { 2979 printf("intr: miss! 0x%x\n", spsr); 2980 #endif 2981 } 2982 } 2983 splx(s); 2984 } 2985 #endif /* defined CB_PCMCIA_POLL */ 2986 2987 /* 2988 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2989 * struct pcmcia_function *pf, 2990 * int ipl, 2991 * int (*func)(void *), 2992 * void *arg); 2993 * 2994 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2995 */ 2996 STATIC void * 2997 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2998 pcmcia_chipset_handle_t pch; 2999 struct pcmcia_function *pf; 3000 int ipl; 3001 int (*func)(void *); 3002 void *arg; 3003 { 3004 struct pcic_handle *ph = (struct pcic_handle *)pch; 3005 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3006 3007 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3008 /* what should I do? */ 3009 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3010 DPRINTF(("%s does not provide edge nor pulse " 3011 "interrupt\n", sc->sc_dev.dv_xname)); 3012 return NULL; 3013 } 3014 /* 3015 * XXX Noooooo! The interrupt flag must set properly!! 3016 * dumb pcmcia driver!! 3017 */ 3018 } 3019 3020 return pccbb_intr_establish(sc, 0, ipl, func, arg); 3021 } 3022 3023 /* 3024 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 3025 * void *ih) 3026 * 3027 * This function disables PC-Card interrupt. 3028 */ 3029 STATIC void 3030 pccbb_pcmcia_intr_disestablish(pch, ih) 3031 pcmcia_chipset_handle_t pch; 3032 void *ih; 3033 { 3034 struct pcic_handle *ph = (struct pcic_handle *)pch; 3035 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3036 3037 pccbb_intr_disestablish(sc, ih); 3038 } 3039 3040 #if rbus 3041 /* 3042 * static int 3043 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3044 * bus_addr_t addr, bus_size_t size, 3045 * bus_addr_t mask, bus_size_t align, 3046 * int flags, bus_addr_t *addrp; 3047 * bus_space_handle_t *bshp) 3048 * 3049 * This function allocates a portion of memory or io space for 3050 * clients. This function is called from CardBus card drivers. 3051 */ 3052 static int 3053 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3054 cardbus_chipset_tag_t ct; 3055 rbus_tag_t rb; 3056 bus_addr_t addr; 3057 bus_size_t size; 3058 bus_addr_t mask; 3059 bus_size_t align; 3060 int flags; 3061 bus_addr_t *addrp; 3062 bus_space_handle_t *bshp; 3063 { 3064 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3065 3066 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3067 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3068 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3069 3070 if (align == 0) { 3071 align = size; 3072 } 3073 3074 if (rb->rb_bt == sc->sc_memt) { 3075 if (align < 16) { 3076 return 1; 3077 } 3078 /* 3079 * XXX: align more than 0x1000 to avoid overwrapping 3080 * memory windows for two or more devices. 0x1000 3081 * means memory window's granularity. 3082 * 3083 * Two or more devices should be able to share same 3084 * memory window region. However, overrapping memory 3085 * window is not good because some devices, such as 3086 * 3Com 3C575[BC], have a broken address decoder and 3087 * intrude other's memory region. 3088 */ 3089 if (align < 0x1000) { 3090 align = 0x1000; 3091 } 3092 } else if (rb->rb_bt == sc->sc_iot) { 3093 if (align < 4) { 3094 return 1; 3095 } 3096 /* XXX: hack for avoiding ISA image */ 3097 if (mask < 0x0100) { 3098 mask = 0x3ff; 3099 addr = 0x300; 3100 } 3101 3102 } else { 3103 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3104 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3105 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3106 (unsigned long)sc->sc_memt)); 3107 return 1; 3108 /* XXX: panic here? */ 3109 } 3110 3111 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3112 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3113 return 1; 3114 } 3115 3116 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3117 3118 return 0; 3119 } 3120 3121 /* 3122 * static int 3123 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3124 * bus_space_handle_t *bshp, bus_size_t size); 3125 * 3126 * This function is called from CardBus card drivers. 3127 */ 3128 static int 3129 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3130 cardbus_chipset_tag_t ct; 3131 rbus_tag_t rb; 3132 bus_space_handle_t bsh; 3133 bus_size_t size; 3134 { 3135 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3136 bus_space_tag_t bt = rb->rb_bt; 3137 3138 pccbb_close_win(sc, bt, bsh, size); 3139 3140 if (bt == sc->sc_memt) { 3141 } else if (bt == sc->sc_iot) { 3142 } else { 3143 return 1; 3144 /* XXX: panic here? */ 3145 } 3146 3147 return rbus_space_free(rb, bsh, size, NULL); 3148 } 3149 #endif /* rbus */ 3150 3151 #if rbus 3152 3153 static int 3154 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3155 struct pccbb_softc *sc; 3156 bus_space_tag_t bst; 3157 bus_addr_t addr; 3158 bus_size_t size; 3159 bus_space_handle_t bsh; 3160 int flags; 3161 { 3162 struct pccbb_win_chain_head *head; 3163 bus_addr_t align; 3164 3165 head = &sc->sc_iowindow; 3166 align = 0x04; 3167 if (sc->sc_memt == bst) { 3168 head = &sc->sc_memwindow; 3169 align = 0x1000; 3170 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3171 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3172 (unsigned long)bst)); 3173 } 3174 3175 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3176 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3177 sc->sc_dev.dv_xname, 3178 (head == &sc->sc_memwindow) ? "mem" : "io"); 3179 } 3180 pccbb_winset(align, sc, bst); 3181 3182 return 0; 3183 } 3184 3185 static int 3186 pccbb_close_win(sc, bst, bsh, size) 3187 struct pccbb_softc *sc; 3188 bus_space_tag_t bst; 3189 bus_space_handle_t bsh; 3190 bus_size_t size; 3191 { 3192 struct pccbb_win_chain_head *head; 3193 bus_addr_t align; 3194 3195 head = &sc->sc_iowindow; 3196 align = 0x04; 3197 if (sc->sc_memt == bst) { 3198 head = &sc->sc_memwindow; 3199 align = 0x1000; 3200 } 3201 3202 if (pccbb_winlist_delete(head, bsh, size)) { 3203 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3204 sc->sc_dev.dv_xname, 3205 (head == &sc->sc_memwindow) ? "mem" : "io"); 3206 } 3207 pccbb_winset(align, sc, bst); 3208 3209 return 0; 3210 } 3211 3212 static int 3213 pccbb_winlist_insert(head, start, size, bsh, flags) 3214 struct pccbb_win_chain_head *head; 3215 bus_addr_t start; 3216 bus_size_t size; 3217 bus_space_handle_t bsh; 3218 int flags; 3219 { 3220 struct pccbb_win_chain *chainp, *elem; 3221 3222 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3223 M_NOWAIT)) == NULL) 3224 return (1); /* fail */ 3225 3226 elem->wc_start = start; 3227 elem->wc_end = start + (size - 1); 3228 elem->wc_handle = bsh; 3229 elem->wc_flags = flags; 3230 3231 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3232 chainp = TAILQ_NEXT(chainp, wc_list)) { 3233 if (chainp->wc_end < start) 3234 continue; 3235 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3236 return (0); 3237 } 3238 3239 TAILQ_INSERT_TAIL(head, elem, wc_list); 3240 return (0); 3241 } 3242 3243 static int 3244 pccbb_winlist_delete(head, bsh, size) 3245 struct pccbb_win_chain_head *head; 3246 bus_space_handle_t bsh; 3247 bus_size_t size; 3248 { 3249 struct pccbb_win_chain *chainp; 3250 3251 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3252 chainp = TAILQ_NEXT(chainp, wc_list)) { 3253 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3254 continue; 3255 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3256 printf("pccbb_winlist_delete: window 0x%lx size " 3257 "inconsistent: 0x%lx, 0x%lx\n", 3258 (unsigned long)chainp->wc_start, 3259 (unsigned long)(chainp->wc_end - chainp->wc_start), 3260 (unsigned long)(size - 1)); 3261 return 1; 3262 } 3263 3264 TAILQ_REMOVE(head, chainp, wc_list); 3265 free(chainp, M_DEVBUF); 3266 3267 return 0; 3268 } 3269 3270 return 1; /* fail: no candidate to remove */ 3271 } 3272 3273 static void 3274 pccbb_winset(align, sc, bst) 3275 bus_addr_t align; 3276 struct pccbb_softc *sc; 3277 bus_space_tag_t bst; 3278 { 3279 pci_chipset_tag_t pc; 3280 pcitag_t tag; 3281 bus_addr_t mask = ~(align - 1); 3282 struct { 3283 cardbusreg_t win_start; 3284 cardbusreg_t win_limit; 3285 int win_flags; 3286 } win[2]; 3287 struct pccbb_win_chain *chainp; 3288 int offs; 3289 3290 win[0].win_start = win[1].win_start = 0xffffffff; 3291 win[0].win_limit = win[1].win_limit = 0; 3292 win[0].win_flags = win[1].win_flags = 0; 3293 3294 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3295 offs = 0x2c; 3296 if (sc->sc_memt == bst) { 3297 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3298 offs = 0x1c; 3299 } 3300 3301 if (chainp != NULL) { 3302 win[0].win_start = chainp->wc_start & mask; 3303 win[0].win_limit = chainp->wc_end & mask; 3304 win[0].win_flags = chainp->wc_flags; 3305 chainp = TAILQ_NEXT(chainp, wc_list); 3306 } 3307 3308 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3309 if (win[1].win_start == 0xffffffff) { 3310 /* window 1 is not used */ 3311 if ((win[0].win_flags == chainp->wc_flags) && 3312 (win[0].win_limit + align >= 3313 (chainp->wc_start & mask))) { 3314 /* concatenate */ 3315 win[0].win_limit = chainp->wc_end & mask; 3316 } else { 3317 /* make new window */ 3318 win[1].win_start = chainp->wc_start & mask; 3319 win[1].win_limit = chainp->wc_end & mask; 3320 win[1].win_flags = chainp->wc_flags; 3321 } 3322 continue; 3323 } 3324 3325 /* Both windows are engaged. */ 3326 if (win[0].win_flags == win[1].win_flags) { 3327 /* same flags */ 3328 if (win[0].win_flags == chainp->wc_flags) { 3329 if (win[1].win_start - (win[0].win_limit + 3330 align) < 3331 (chainp->wc_start & mask) - 3332 ((chainp->wc_end & mask) + align)) { 3333 /* 3334 * merge window 0 and 1, and set win1 3335 * to chainp 3336 */ 3337 win[0].win_limit = win[1].win_limit; 3338 win[1].win_start = 3339 chainp->wc_start & mask; 3340 win[1].win_limit = 3341 chainp->wc_end & mask; 3342 } else { 3343 win[1].win_limit = 3344 chainp->wc_end & mask; 3345 } 3346 } else { 3347 /* different flags */ 3348 3349 /* concatenate win0 and win1 */ 3350 win[0].win_limit = win[1].win_limit; 3351 /* allocate win[1] to new space */ 3352 win[1].win_start = chainp->wc_start & mask; 3353 win[1].win_limit = chainp->wc_end & mask; 3354 win[1].win_flags = chainp->wc_flags; 3355 } 3356 } else { 3357 /* the flags of win[0] and win[1] is different */ 3358 if (win[0].win_flags == chainp->wc_flags) { 3359 win[0].win_limit = chainp->wc_end & mask; 3360 /* 3361 * XXX this creates overlapping windows, so 3362 * what should the poor bridge do if one is 3363 * cachable, and the other is not? 3364 */ 3365 printf("%s: overlapping windows\n", 3366 sc->sc_dev.dv_xname); 3367 } else { 3368 win[1].win_limit = chainp->wc_end & mask; 3369 } 3370 } 3371 } 3372 3373 pc = sc->sc_pc; 3374 tag = sc->sc_tag; 3375 pci_conf_write(pc, tag, offs, win[0].win_start); 3376 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3377 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3378 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3379 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3380 (unsigned long)pci_conf_read(pc, tag, offs), 3381 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3382 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3383 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3384 3385 if (bst == sc->sc_memt) { 3386 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3387 3388 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3389 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3390 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3391 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3392 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3393 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3394 } 3395 } 3396 3397 #endif /* rbus */ 3398 3399 static void 3400 pccbb_powerhook(why, arg) 3401 int why; 3402 void *arg; 3403 { 3404 struct pccbb_softc *sc = arg; 3405 pcireg_t reg; 3406 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3407 bus_space_handle_t base_memh = sc->sc_base_memh; 3408 3409 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3410 3411 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3412 DPRINTF(("%s: power: why %d stopping intr\n", 3413 sc->sc_dev.dv_xname, why)); 3414 if (sc->sc_pil_intr_enable) { 3415 (void)pccbbintr_function(sc); 3416 } 3417 sc->sc_pil_intr_enable = 0; 3418 3419 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3420 3421 if (sc->sc_chipset == CB_RX5C47X) 3422 sc->sc_ricoh_misc_ctrl = pci_conf_read(sc->sc_pc, 3423 sc->sc_tag, 3424 RICOH_PCI_MISC_CTRL); 3425 3426 /* ToDo: deactivate or suspend child devices */ 3427 } 3428 3429 if (why == PWR_RESUME) { 3430 if (sc->sc_pwrmgt_offs != 0) { 3431 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3432 sc->sc_pwrmgt_offs + 4); 3433 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3434 reg & 0x100) { 3435 /* powrstate != D0 */ 3436 3437 printf("%s going back to D0 mode\n", 3438 sc->sc_dev.dv_xname); 3439 reg &= ~PCI_PMCSR_STATE_MASK; 3440 reg |= PCI_PMCSR_STATE_D0; 3441 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3442 pci_conf_write(sc->sc_pc, sc->sc_tag, 3443 sc->sc_pwrmgt_offs + 4, reg); 3444 3445 pci_conf_write(sc->sc_pc, sc->sc_tag, 3446 PCI_SOCKBASE, sc->sc_sockbase); 3447 pci_conf_write(sc->sc_pc, sc->sc_tag, 3448 PCI_BUSNUM, sc->sc_busnum); 3449 pccbb_chipinit(sc); 3450 /* setup memory and io space window for CB */ 3451 pccbb_winset(0x1000, sc, sc->sc_memt); 3452 pccbb_winset(0x04, sc, sc->sc_iot); 3453 goto norestore; 3454 } 3455 } 3456 3457 norestore: 3458 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 3459 if (sc->sc_chipset == CB_RX5C47X) { 3460 pci_conf_write(sc->sc_pc, sc->sc_tag, 3461 RICOH_PCI_MISC_CTRL, sc->sc_ricoh_misc_ctrl); 3462 } 3463 3464 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3465 /* BIOS did not recover this register */ 3466 pci_conf_write (sc->sc_pc, sc->sc_tag, 3467 PCI_SOCKBASE, sc->sc_sockbase); 3468 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3469 /* BIOS did not recover this register */ 3470 pci_conf_write (sc->sc_pc, sc->sc_tag, 3471 PCI_BUSNUM, sc->sc_busnum); 3472 /* CSC Interrupt: Card detect interrupt on */ 3473 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3474 /* Card detect intr is turned on. */ 3475 reg |= CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3476 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3477 /* reset interrupt */ 3478 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3479 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3480 3481 /* 3482 * check for card insertion or removal during suspend period. 3483 * XXX: the code can't cope with card swap (remove then 3484 * insert). how can we detect such situation? 3485 */ 3486 (void)pccbbintr(sc); 3487 3488 sc->sc_pil_intr_enable = 1; 3489 DPRINTF(("%s: power: RESUME enabling intr\n", 3490 sc->sc_dev.dv_xname)); 3491 3492 /* ToDo: activate or wakeup child devices */ 3493 } 3494 } 3495
Indexes created Fri Sep 26 08:10:20 GMT 2025